main.c 61 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static u8 parse_mpdudensity(u8 mpdudensity)
  21. {
  22. /*
  23. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  24. * 0 for no restriction
  25. * 1 for 1/4 us
  26. * 2 for 1/2 us
  27. * 3 for 1 us
  28. * 4 for 2 us
  29. * 5 for 4 us
  30. * 6 for 8 us
  31. * 7 for 16 us
  32. */
  33. switch (mpdudensity) {
  34. case 0:
  35. return 0;
  36. case 1:
  37. case 2:
  38. case 3:
  39. /* Our lower layer calculations limit our precision to
  40. 1 microsecond */
  41. return 1;
  42. case 4:
  43. return 2;
  44. case 5:
  45. return 4;
  46. case 6:
  47. return 8;
  48. case 7:
  49. return 16;
  50. default:
  51. return 0;
  52. }
  53. }
  54. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  55. {
  56. bool pending = false;
  57. spin_lock_bh(&txq->axq_lock);
  58. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  59. pending = true;
  60. spin_unlock_bh(&txq->axq_lock);
  61. return pending;
  62. }
  63. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  64. {
  65. unsigned long flags;
  66. bool ret;
  67. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  68. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  69. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  70. return ret;
  71. }
  72. void ath9k_ps_wakeup(struct ath_softc *sc)
  73. {
  74. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  75. unsigned long flags;
  76. enum ath9k_power_mode power_mode;
  77. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  78. if (++sc->ps_usecount != 1)
  79. goto unlock;
  80. power_mode = sc->sc_ah->power_mode;
  81. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  82. /*
  83. * While the hardware is asleep, the cycle counters contain no
  84. * useful data. Better clear them now so that they don't mess up
  85. * survey data results.
  86. */
  87. if (power_mode != ATH9K_PM_AWAKE) {
  88. spin_lock(&common->cc_lock);
  89. ath_hw_cycle_counters_update(common);
  90. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  91. spin_unlock(&common->cc_lock);
  92. }
  93. unlock:
  94. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  95. }
  96. void ath9k_ps_restore(struct ath_softc *sc)
  97. {
  98. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  99. enum ath9k_power_mode mode;
  100. unsigned long flags;
  101. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  102. if (--sc->ps_usecount != 0)
  103. goto unlock;
  104. if (sc->ps_idle)
  105. mode = ATH9K_PM_FULL_SLEEP;
  106. else if (sc->ps_enabled &&
  107. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  108. PS_WAIT_FOR_CAB |
  109. PS_WAIT_FOR_PSPOLL_DATA |
  110. PS_WAIT_FOR_TX_ACK)))
  111. mode = ATH9K_PM_NETWORK_SLEEP;
  112. else
  113. goto unlock;
  114. spin_lock(&common->cc_lock);
  115. ath_hw_cycle_counters_update(common);
  116. spin_unlock(&common->cc_lock);
  117. ath9k_hw_setpower(sc->sc_ah, mode);
  118. unlock:
  119. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  120. }
  121. void ath_start_ani(struct ath_common *common)
  122. {
  123. struct ath_hw *ah = common->ah;
  124. unsigned long timestamp = jiffies_to_msecs(jiffies);
  125. struct ath_softc *sc = (struct ath_softc *) common->priv;
  126. if (!(sc->sc_flags & SC_OP_ANI_RUN))
  127. return;
  128. if (sc->sc_flags & SC_OP_OFFCHANNEL)
  129. return;
  130. common->ani.longcal_timer = timestamp;
  131. common->ani.shortcal_timer = timestamp;
  132. common->ani.checkani_timer = timestamp;
  133. mod_timer(&common->ani.timer,
  134. jiffies +
  135. msecs_to_jiffies((u32)ah->config.ani_poll_interval));
  136. }
  137. static void ath_update_survey_nf(struct ath_softc *sc, int channel)
  138. {
  139. struct ath_hw *ah = sc->sc_ah;
  140. struct ath9k_channel *chan = &ah->channels[channel];
  141. struct survey_info *survey = &sc->survey[channel];
  142. if (chan->noisefloor) {
  143. survey->filled |= SURVEY_INFO_NOISE_DBM;
  144. survey->noise = ath9k_hw_getchan_noise(ah, chan);
  145. }
  146. }
  147. /*
  148. * Updates the survey statistics and returns the busy time since last
  149. * update in %, if the measurement duration was long enough for the
  150. * result to be useful, -1 otherwise.
  151. */
  152. static int ath_update_survey_stats(struct ath_softc *sc)
  153. {
  154. struct ath_hw *ah = sc->sc_ah;
  155. struct ath_common *common = ath9k_hw_common(ah);
  156. int pos = ah->curchan - &ah->channels[0];
  157. struct survey_info *survey = &sc->survey[pos];
  158. struct ath_cycle_counters *cc = &common->cc_survey;
  159. unsigned int div = common->clockrate * 1000;
  160. int ret = 0;
  161. if (!ah->curchan)
  162. return -1;
  163. if (ah->power_mode == ATH9K_PM_AWAKE)
  164. ath_hw_cycle_counters_update(common);
  165. if (cc->cycles > 0) {
  166. survey->filled |= SURVEY_INFO_CHANNEL_TIME |
  167. SURVEY_INFO_CHANNEL_TIME_BUSY |
  168. SURVEY_INFO_CHANNEL_TIME_RX |
  169. SURVEY_INFO_CHANNEL_TIME_TX;
  170. survey->channel_time += cc->cycles / div;
  171. survey->channel_time_busy += cc->rx_busy / div;
  172. survey->channel_time_rx += cc->rx_frame / div;
  173. survey->channel_time_tx += cc->tx_frame / div;
  174. }
  175. if (cc->cycles < div)
  176. return -1;
  177. if (cc->cycles > 0)
  178. ret = cc->rx_busy * 100 / cc->cycles;
  179. memset(cc, 0, sizeof(*cc));
  180. ath_update_survey_nf(sc, pos);
  181. return ret;
  182. }
  183. static void __ath_cancel_work(struct ath_softc *sc)
  184. {
  185. cancel_work_sync(&sc->paprd_work);
  186. cancel_work_sync(&sc->hw_check_work);
  187. cancel_delayed_work_sync(&sc->tx_complete_work);
  188. cancel_delayed_work_sync(&sc->hw_pll_work);
  189. }
  190. static void ath_cancel_work(struct ath_softc *sc)
  191. {
  192. __ath_cancel_work(sc);
  193. cancel_work_sync(&sc->hw_reset_work);
  194. }
  195. static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
  196. {
  197. struct ath_hw *ah = sc->sc_ah;
  198. struct ath_common *common = ath9k_hw_common(ah);
  199. bool ret;
  200. ieee80211_stop_queues(sc->hw);
  201. sc->hw_busy_count = 0;
  202. del_timer_sync(&common->ani.timer);
  203. ath9k_debug_samp_bb_mac(sc);
  204. ath9k_hw_disable_interrupts(ah);
  205. ret = ath_drain_all_txq(sc, retry_tx);
  206. if (!ath_stoprecv(sc))
  207. ret = false;
  208. if (!flush) {
  209. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  210. ath_rx_tasklet(sc, 1, true);
  211. ath_rx_tasklet(sc, 1, false);
  212. } else {
  213. ath_flushrecv(sc);
  214. }
  215. return ret;
  216. }
  217. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  218. {
  219. struct ath_hw *ah = sc->sc_ah;
  220. struct ath_common *common = ath9k_hw_common(ah);
  221. if (ath_startrecv(sc) != 0) {
  222. ath_err(common, "Unable to restart recv logic\n");
  223. return false;
  224. }
  225. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  226. sc->config.txpowlimit, &sc->curtxpow);
  227. ath9k_hw_set_interrupts(ah);
  228. ath9k_hw_enable_interrupts(ah);
  229. if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) && start) {
  230. if (sc->sc_flags & SC_OP_BEACONS)
  231. ath_set_beacon(sc);
  232. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  233. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
  234. if (!common->disable_ani)
  235. ath_start_ani(common);
  236. }
  237. if (ath9k_hw_ops(ah)->antdiv_comb_conf_get && sc->ant_rx != 3) {
  238. struct ath_hw_antcomb_conf div_ant_conf;
  239. u8 lna_conf;
  240. ath9k_hw_antdiv_comb_conf_get(ah, &div_ant_conf);
  241. if (sc->ant_rx == 1)
  242. lna_conf = ATH_ANT_DIV_COMB_LNA1;
  243. else
  244. lna_conf = ATH_ANT_DIV_COMB_LNA2;
  245. div_ant_conf.main_lna_conf = lna_conf;
  246. div_ant_conf.alt_lna_conf = lna_conf;
  247. ath9k_hw_antdiv_comb_conf_set(ah, &div_ant_conf);
  248. }
  249. ieee80211_wake_queues(sc->hw);
  250. return true;
  251. }
  252. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
  253. bool retry_tx)
  254. {
  255. struct ath_hw *ah = sc->sc_ah;
  256. struct ath_common *common = ath9k_hw_common(ah);
  257. struct ath9k_hw_cal_data *caldata = NULL;
  258. bool fastcc = true;
  259. bool flush = false;
  260. int r;
  261. __ath_cancel_work(sc);
  262. spin_lock_bh(&sc->sc_pcu_lock);
  263. if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) {
  264. fastcc = false;
  265. caldata = &sc->caldata;
  266. }
  267. if (!hchan) {
  268. fastcc = false;
  269. flush = true;
  270. hchan = ah->curchan;
  271. }
  272. if (fastcc && !ath9k_hw_check_alive(ah))
  273. fastcc = false;
  274. if (!ath_prepare_reset(sc, retry_tx, flush))
  275. fastcc = false;
  276. ath_dbg(common, ATH_DBG_CONFIG,
  277. "Reset to %u MHz, HT40: %d fastcc: %d\n",
  278. hchan->channel, !!(hchan->channelFlags & (CHANNEL_HT40MINUS |
  279. CHANNEL_HT40PLUS)),
  280. fastcc);
  281. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  282. if (r) {
  283. ath_err(common,
  284. "Unable to reset channel, reset status %d\n", r);
  285. goto out;
  286. }
  287. if (!ath_complete_reset(sc, true))
  288. r = -EIO;
  289. out:
  290. spin_unlock_bh(&sc->sc_pcu_lock);
  291. return r;
  292. }
  293. /*
  294. * Set/change channels. If the channel is really being changed, it's done
  295. * by reseting the chip. To accomplish this we must first cleanup any pending
  296. * DMA, then restart stuff.
  297. */
  298. static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  299. struct ath9k_channel *hchan)
  300. {
  301. int r;
  302. if (sc->sc_flags & SC_OP_INVALID)
  303. return -EIO;
  304. ath9k_ps_wakeup(sc);
  305. r = ath_reset_internal(sc, hchan, false);
  306. ath9k_ps_restore(sc);
  307. return r;
  308. }
  309. static void ath_paprd_activate(struct ath_softc *sc)
  310. {
  311. struct ath_hw *ah = sc->sc_ah;
  312. struct ath9k_hw_cal_data *caldata = ah->caldata;
  313. int chain;
  314. if (!caldata || !caldata->paprd_done)
  315. return;
  316. ath9k_ps_wakeup(sc);
  317. ar9003_paprd_enable(ah, false);
  318. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  319. if (!(ah->txchainmask & BIT(chain)))
  320. continue;
  321. ar9003_paprd_populate_single_table(ah, caldata, chain);
  322. }
  323. ar9003_paprd_enable(ah, true);
  324. ath9k_ps_restore(sc);
  325. }
  326. static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
  327. {
  328. struct ieee80211_hw *hw = sc->hw;
  329. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  330. struct ath_hw *ah = sc->sc_ah;
  331. struct ath_common *common = ath9k_hw_common(ah);
  332. struct ath_tx_control txctl;
  333. int time_left;
  334. memset(&txctl, 0, sizeof(txctl));
  335. txctl.txq = sc->tx.txq_map[WME_AC_BE];
  336. memset(tx_info, 0, sizeof(*tx_info));
  337. tx_info->band = hw->conf.channel->band;
  338. tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
  339. tx_info->control.rates[0].idx = 0;
  340. tx_info->control.rates[0].count = 1;
  341. tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
  342. tx_info->control.rates[1].idx = -1;
  343. init_completion(&sc->paprd_complete);
  344. txctl.paprd = BIT(chain);
  345. if (ath_tx_start(hw, skb, &txctl) != 0) {
  346. ath_dbg(common, ATH_DBG_CALIBRATE, "PAPRD TX failed\n");
  347. dev_kfree_skb_any(skb);
  348. return false;
  349. }
  350. time_left = wait_for_completion_timeout(&sc->paprd_complete,
  351. msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
  352. if (!time_left)
  353. ath_dbg(common, ATH_DBG_CALIBRATE,
  354. "Timeout waiting for paprd training on TX chain %d\n",
  355. chain);
  356. return !!time_left;
  357. }
  358. void ath_paprd_calibrate(struct work_struct *work)
  359. {
  360. struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
  361. struct ieee80211_hw *hw = sc->hw;
  362. struct ath_hw *ah = sc->sc_ah;
  363. struct ieee80211_hdr *hdr;
  364. struct sk_buff *skb = NULL;
  365. struct ath9k_hw_cal_data *caldata = ah->caldata;
  366. struct ath_common *common = ath9k_hw_common(ah);
  367. int ftype;
  368. int chain_ok = 0;
  369. int chain;
  370. int len = 1800;
  371. if (!caldata)
  372. return;
  373. ath9k_ps_wakeup(sc);
  374. if (ar9003_paprd_init_table(ah) < 0)
  375. goto fail_paprd;
  376. skb = alloc_skb(len, GFP_KERNEL);
  377. if (!skb)
  378. goto fail_paprd;
  379. skb_put(skb, len);
  380. memset(skb->data, 0, len);
  381. hdr = (struct ieee80211_hdr *)skb->data;
  382. ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
  383. hdr->frame_control = cpu_to_le16(ftype);
  384. hdr->duration_id = cpu_to_le16(10);
  385. memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
  386. memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
  387. memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
  388. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  389. if (!(ah->txchainmask & BIT(chain)))
  390. continue;
  391. chain_ok = 0;
  392. ath_dbg(common, ATH_DBG_CALIBRATE,
  393. "Sending PAPRD frame for thermal measurement "
  394. "on chain %d\n", chain);
  395. if (!ath_paprd_send_frame(sc, skb, chain))
  396. goto fail_paprd;
  397. ar9003_paprd_setup_gain_table(ah, chain);
  398. ath_dbg(common, ATH_DBG_CALIBRATE,
  399. "Sending PAPRD training frame on chain %d\n", chain);
  400. if (!ath_paprd_send_frame(sc, skb, chain))
  401. goto fail_paprd;
  402. if (!ar9003_paprd_is_done(ah)) {
  403. ath_dbg(common, ATH_DBG_CALIBRATE,
  404. "PAPRD not yet done on chain %d\n", chain);
  405. break;
  406. }
  407. if (ar9003_paprd_create_curve(ah, caldata, chain)) {
  408. ath_dbg(common, ATH_DBG_CALIBRATE,
  409. "PAPRD create curve failed on chain %d\n",
  410. chain);
  411. break;
  412. }
  413. chain_ok = 1;
  414. }
  415. kfree_skb(skb);
  416. if (chain_ok) {
  417. caldata->paprd_done = true;
  418. ath_paprd_activate(sc);
  419. }
  420. fail_paprd:
  421. ath9k_ps_restore(sc);
  422. }
  423. /*
  424. * This routine performs the periodic noise floor calibration function
  425. * that is used to adjust and optimize the chip performance. This
  426. * takes environmental changes (location, temperature) into account.
  427. * When the task is complete, it reschedules itself depending on the
  428. * appropriate interval that was calculated.
  429. */
  430. void ath_ani_calibrate(unsigned long data)
  431. {
  432. struct ath_softc *sc = (struct ath_softc *)data;
  433. struct ath_hw *ah = sc->sc_ah;
  434. struct ath_common *common = ath9k_hw_common(ah);
  435. bool longcal = false;
  436. bool shortcal = false;
  437. bool aniflag = false;
  438. unsigned int timestamp = jiffies_to_msecs(jiffies);
  439. u32 cal_interval, short_cal_interval, long_cal_interval;
  440. unsigned long flags;
  441. if (ah->caldata && ah->caldata->nfcal_interference)
  442. long_cal_interval = ATH_LONG_CALINTERVAL_INT;
  443. else
  444. long_cal_interval = ATH_LONG_CALINTERVAL;
  445. short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
  446. ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
  447. /* Only calibrate if awake */
  448. if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
  449. goto set_timer;
  450. ath9k_ps_wakeup(sc);
  451. /* Long calibration runs independently of short calibration. */
  452. if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
  453. longcal = true;
  454. ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
  455. common->ani.longcal_timer = timestamp;
  456. }
  457. /* Short calibration applies only while caldone is false */
  458. if (!common->ani.caldone) {
  459. if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
  460. shortcal = true;
  461. ath_dbg(common, ATH_DBG_ANI,
  462. "shortcal @%lu\n", jiffies);
  463. common->ani.shortcal_timer = timestamp;
  464. common->ani.resetcal_timer = timestamp;
  465. }
  466. } else {
  467. if ((timestamp - common->ani.resetcal_timer) >=
  468. ATH_RESTART_CALINTERVAL) {
  469. common->ani.caldone = ath9k_hw_reset_calvalid(ah);
  470. if (common->ani.caldone)
  471. common->ani.resetcal_timer = timestamp;
  472. }
  473. }
  474. /* Verify whether we must check ANI */
  475. if ((timestamp - common->ani.checkani_timer) >=
  476. ah->config.ani_poll_interval) {
  477. aniflag = true;
  478. common->ani.checkani_timer = timestamp;
  479. }
  480. /* Call ANI routine if necessary */
  481. if (aniflag) {
  482. spin_lock_irqsave(&common->cc_lock, flags);
  483. ath9k_hw_ani_monitor(ah, ah->curchan);
  484. ath_update_survey_stats(sc);
  485. spin_unlock_irqrestore(&common->cc_lock, flags);
  486. }
  487. /* Perform calibration if necessary */
  488. if (longcal || shortcal) {
  489. common->ani.caldone =
  490. ath9k_hw_calibrate(ah, ah->curchan,
  491. ah->rxchainmask, longcal);
  492. }
  493. ath9k_ps_restore(sc);
  494. set_timer:
  495. /*
  496. * Set timer interval based on previous results.
  497. * The interval must be the shortest necessary to satisfy ANI,
  498. * short calibration and long calibration.
  499. */
  500. ath9k_debug_samp_bb_mac(sc);
  501. cal_interval = ATH_LONG_CALINTERVAL;
  502. if (sc->sc_ah->config.enable_ani)
  503. cal_interval = min(cal_interval,
  504. (u32)ah->config.ani_poll_interval);
  505. if (!common->ani.caldone)
  506. cal_interval = min(cal_interval, (u32)short_cal_interval);
  507. mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
  508. if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
  509. if (!ah->caldata->paprd_done)
  510. ieee80211_queue_work(sc->hw, &sc->paprd_work);
  511. else if (!ah->paprd_table_write_done)
  512. ath_paprd_activate(sc);
  513. }
  514. }
  515. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
  516. {
  517. struct ath_node *an;
  518. an = (struct ath_node *)sta->drv_priv;
  519. #ifdef CONFIG_ATH9K_DEBUGFS
  520. spin_lock(&sc->nodes_lock);
  521. list_add(&an->list, &sc->nodes);
  522. spin_unlock(&sc->nodes_lock);
  523. an->sta = sta;
  524. #endif
  525. if (sc->sc_flags & SC_OP_TXAGGR) {
  526. ath_tx_node_init(sc, an);
  527. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  528. sta->ht_cap.ampdu_factor);
  529. an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
  530. }
  531. }
  532. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  533. {
  534. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  535. #ifdef CONFIG_ATH9K_DEBUGFS
  536. spin_lock(&sc->nodes_lock);
  537. list_del(&an->list);
  538. spin_unlock(&sc->nodes_lock);
  539. an->sta = NULL;
  540. #endif
  541. if (sc->sc_flags & SC_OP_TXAGGR)
  542. ath_tx_node_cleanup(sc, an);
  543. }
  544. void ath9k_tasklet(unsigned long data)
  545. {
  546. struct ath_softc *sc = (struct ath_softc *)data;
  547. struct ath_hw *ah = sc->sc_ah;
  548. struct ath_common *common = ath9k_hw_common(ah);
  549. u32 status = sc->intrstatus;
  550. u32 rxmask;
  551. ath9k_ps_wakeup(sc);
  552. spin_lock(&sc->sc_pcu_lock);
  553. if ((status & ATH9K_INT_FATAL) ||
  554. (status & ATH9K_INT_BB_WATCHDOG)) {
  555. #ifdef CONFIG_ATH9K_DEBUGFS
  556. enum ath_reset_type type;
  557. if (status & ATH9K_INT_FATAL)
  558. type = RESET_TYPE_FATAL_INT;
  559. else
  560. type = RESET_TYPE_BB_WATCHDOG;
  561. RESET_STAT_INC(sc, type);
  562. #endif
  563. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  564. goto out;
  565. }
  566. /*
  567. * Only run the baseband hang check if beacons stop working in AP or
  568. * IBSS mode, because it has a high false positive rate. For station
  569. * mode it should not be necessary, since the upper layers will detect
  570. * this through a beacon miss automatically and the following channel
  571. * change will trigger a hardware reset anyway
  572. */
  573. if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
  574. !ath9k_hw_check_alive(ah))
  575. ieee80211_queue_work(sc->hw, &sc->hw_check_work);
  576. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  577. /*
  578. * TSF sync does not look correct; remain awake to sync with
  579. * the next Beacon.
  580. */
  581. ath_dbg(common, ATH_DBG_PS,
  582. "TSFOOR - Sync with next Beacon\n");
  583. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  584. }
  585. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  586. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  587. ATH9K_INT_RXORN);
  588. else
  589. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  590. if (status & rxmask) {
  591. /* Check for high priority Rx first */
  592. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  593. (status & ATH9K_INT_RXHP))
  594. ath_rx_tasklet(sc, 0, true);
  595. ath_rx_tasklet(sc, 0, false);
  596. }
  597. if (status & ATH9K_INT_TX) {
  598. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  599. ath_tx_edma_tasklet(sc);
  600. else
  601. ath_tx_tasklet(sc);
  602. }
  603. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  604. if (status & ATH9K_INT_GENTIMER)
  605. ath_gen_timer_isr(sc->sc_ah);
  606. out:
  607. /* re-enable hardware interrupt */
  608. ath9k_hw_enable_interrupts(ah);
  609. spin_unlock(&sc->sc_pcu_lock);
  610. ath9k_ps_restore(sc);
  611. }
  612. irqreturn_t ath_isr(int irq, void *dev)
  613. {
  614. #define SCHED_INTR ( \
  615. ATH9K_INT_FATAL | \
  616. ATH9K_INT_BB_WATCHDOG | \
  617. ATH9K_INT_RXORN | \
  618. ATH9K_INT_RXEOL | \
  619. ATH9K_INT_RX | \
  620. ATH9K_INT_RXLP | \
  621. ATH9K_INT_RXHP | \
  622. ATH9K_INT_TX | \
  623. ATH9K_INT_BMISS | \
  624. ATH9K_INT_CST | \
  625. ATH9K_INT_TSFOOR | \
  626. ATH9K_INT_GENTIMER)
  627. struct ath_softc *sc = dev;
  628. struct ath_hw *ah = sc->sc_ah;
  629. struct ath_common *common = ath9k_hw_common(ah);
  630. enum ath9k_int status;
  631. bool sched = false;
  632. /*
  633. * The hardware is not ready/present, don't
  634. * touch anything. Note this can happen early
  635. * on if the IRQ is shared.
  636. */
  637. if (sc->sc_flags & SC_OP_INVALID)
  638. return IRQ_NONE;
  639. /* shared irq, not for us */
  640. if (!ath9k_hw_intrpend(ah))
  641. return IRQ_NONE;
  642. /*
  643. * Figure out the reason(s) for the interrupt. Note
  644. * that the hal returns a pseudo-ISR that may include
  645. * bits we haven't explicitly enabled so we mask the
  646. * value to insure we only process bits we requested.
  647. */
  648. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  649. status &= ah->imask; /* discard unasked-for bits */
  650. /*
  651. * If there are no status bits set, then this interrupt was not
  652. * for me (should have been caught above).
  653. */
  654. if (!status)
  655. return IRQ_NONE;
  656. /* Cache the status */
  657. sc->intrstatus = status;
  658. if (status & SCHED_INTR)
  659. sched = true;
  660. /*
  661. * If a FATAL or RXORN interrupt is received, we have to reset the
  662. * chip immediately.
  663. */
  664. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  665. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  666. goto chip_reset;
  667. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  668. (status & ATH9K_INT_BB_WATCHDOG)) {
  669. spin_lock(&common->cc_lock);
  670. ath_hw_cycle_counters_update(common);
  671. ar9003_hw_bb_watchdog_dbg_info(ah);
  672. spin_unlock(&common->cc_lock);
  673. goto chip_reset;
  674. }
  675. if (status & ATH9K_INT_SWBA)
  676. tasklet_schedule(&sc->bcon_tasklet);
  677. if (status & ATH9K_INT_TXURN)
  678. ath9k_hw_updatetxtriglevel(ah, true);
  679. if (status & ATH9K_INT_RXEOL) {
  680. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  681. ath9k_hw_set_interrupts(ah);
  682. }
  683. if (status & ATH9K_INT_MIB) {
  684. /*
  685. * Disable interrupts until we service the MIB
  686. * interrupt; otherwise it will continue to
  687. * fire.
  688. */
  689. ath9k_hw_disable_interrupts(ah);
  690. /*
  691. * Let the hal handle the event. We assume
  692. * it will clear whatever condition caused
  693. * the interrupt.
  694. */
  695. spin_lock(&common->cc_lock);
  696. ath9k_hw_proc_mib_event(ah);
  697. spin_unlock(&common->cc_lock);
  698. ath9k_hw_enable_interrupts(ah);
  699. }
  700. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  701. if (status & ATH9K_INT_TIM_TIMER) {
  702. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  703. goto chip_reset;
  704. /* Clear RxAbort bit so that we can
  705. * receive frames */
  706. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  707. ath9k_hw_setrxabort(sc->sc_ah, 0);
  708. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  709. }
  710. chip_reset:
  711. ath_debug_stat_interrupt(sc, status);
  712. if (sched) {
  713. /* turn off every interrupt */
  714. ath9k_hw_disable_interrupts(ah);
  715. tasklet_schedule(&sc->intr_tq);
  716. }
  717. return IRQ_HANDLED;
  718. #undef SCHED_INTR
  719. }
  720. static void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
  721. {
  722. struct ath_hw *ah = sc->sc_ah;
  723. struct ath_common *common = ath9k_hw_common(ah);
  724. struct ieee80211_channel *channel = hw->conf.channel;
  725. int r;
  726. ath9k_ps_wakeup(sc);
  727. spin_lock_bh(&sc->sc_pcu_lock);
  728. atomic_set(&ah->intr_ref_cnt, -1);
  729. ath9k_hw_configpcipowersave(ah, false);
  730. if (!ah->curchan)
  731. ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah);
  732. r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  733. if (r) {
  734. ath_err(common,
  735. "Unable to reset channel (%u MHz), reset status %d\n",
  736. channel->center_freq, r);
  737. }
  738. ath_complete_reset(sc, true);
  739. /* Enable LED */
  740. ath9k_hw_cfg_output(ah, ah->led_pin,
  741. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  742. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  743. spin_unlock_bh(&sc->sc_pcu_lock);
  744. ath9k_ps_restore(sc);
  745. }
  746. void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
  747. {
  748. struct ath_hw *ah = sc->sc_ah;
  749. struct ieee80211_channel *channel = hw->conf.channel;
  750. int r;
  751. ath9k_ps_wakeup(sc);
  752. ath_cancel_work(sc);
  753. spin_lock_bh(&sc->sc_pcu_lock);
  754. /*
  755. * Keep the LED on when the radio is disabled
  756. * during idle unassociated state.
  757. */
  758. if (!sc->ps_idle) {
  759. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  760. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  761. }
  762. ath_prepare_reset(sc, false, true);
  763. if (!ah->curchan)
  764. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  765. r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  766. if (r) {
  767. ath_err(ath9k_hw_common(sc->sc_ah),
  768. "Unable to reset channel (%u MHz), reset status %d\n",
  769. channel->center_freq, r);
  770. }
  771. ath9k_hw_phy_disable(ah);
  772. ath9k_hw_configpcipowersave(ah, true);
  773. spin_unlock_bh(&sc->sc_pcu_lock);
  774. ath9k_ps_restore(sc);
  775. }
  776. static int ath_reset(struct ath_softc *sc, bool retry_tx)
  777. {
  778. int r;
  779. ath9k_ps_wakeup(sc);
  780. r = ath_reset_internal(sc, NULL, retry_tx);
  781. if (retry_tx) {
  782. int i;
  783. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  784. if (ATH_TXQ_SETUP(sc, i)) {
  785. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  786. ath_txq_schedule(sc, &sc->tx.txq[i]);
  787. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  788. }
  789. }
  790. }
  791. ath9k_ps_restore(sc);
  792. return r;
  793. }
  794. void ath_reset_work(struct work_struct *work)
  795. {
  796. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  797. ath_reset(sc, true);
  798. }
  799. void ath_hw_check(struct work_struct *work)
  800. {
  801. struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
  802. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  803. unsigned long flags;
  804. int busy;
  805. ath9k_ps_wakeup(sc);
  806. if (ath9k_hw_check_alive(sc->sc_ah))
  807. goto out;
  808. spin_lock_irqsave(&common->cc_lock, flags);
  809. busy = ath_update_survey_stats(sc);
  810. spin_unlock_irqrestore(&common->cc_lock, flags);
  811. ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, "
  812. "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1);
  813. if (busy >= 99) {
  814. if (++sc->hw_busy_count >= 3) {
  815. RESET_STAT_INC(sc, RESET_TYPE_BB_HANG);
  816. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  817. }
  818. } else if (busy >= 0)
  819. sc->hw_busy_count = 0;
  820. out:
  821. ath9k_ps_restore(sc);
  822. }
  823. static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
  824. {
  825. static int count;
  826. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  827. if (pll_sqsum >= 0x40000) {
  828. count++;
  829. if (count == 3) {
  830. /* Rx is hung for more than 500ms. Reset it */
  831. ath_dbg(common, ATH_DBG_RESET,
  832. "Possible RX hang, resetting");
  833. RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG);
  834. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  835. count = 0;
  836. }
  837. } else
  838. count = 0;
  839. }
  840. void ath_hw_pll_work(struct work_struct *work)
  841. {
  842. struct ath_softc *sc = container_of(work, struct ath_softc,
  843. hw_pll_work.work);
  844. u32 pll_sqsum;
  845. if (AR_SREV_9485(sc->sc_ah)) {
  846. ath9k_ps_wakeup(sc);
  847. pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
  848. ath9k_ps_restore(sc);
  849. ath_hw_pll_rx_hang_check(sc, pll_sqsum);
  850. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
  851. }
  852. }
  853. /**********************/
  854. /* mac80211 callbacks */
  855. /**********************/
  856. static int ath9k_start(struct ieee80211_hw *hw)
  857. {
  858. struct ath_softc *sc = hw->priv;
  859. struct ath_hw *ah = sc->sc_ah;
  860. struct ath_common *common = ath9k_hw_common(ah);
  861. struct ieee80211_channel *curchan = hw->conf.channel;
  862. struct ath9k_channel *init_channel;
  863. int r;
  864. ath_dbg(common, ATH_DBG_CONFIG,
  865. "Starting driver with initial channel: %d MHz\n",
  866. curchan->center_freq);
  867. ath9k_ps_wakeup(sc);
  868. mutex_lock(&sc->mutex);
  869. /* setup initial channel */
  870. sc->chan_idx = curchan->hw_value;
  871. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  872. /* Reset SERDES registers */
  873. ath9k_hw_configpcipowersave(ah, false);
  874. /*
  875. * The basic interface to setting the hardware in a good
  876. * state is ``reset''. On return the hardware is known to
  877. * be powered up and with interrupts disabled. This must
  878. * be followed by initialization of the appropriate bits
  879. * and then setup of the interrupt mask.
  880. */
  881. spin_lock_bh(&sc->sc_pcu_lock);
  882. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  883. if (r) {
  884. ath_err(common,
  885. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  886. r, curchan->center_freq);
  887. spin_unlock_bh(&sc->sc_pcu_lock);
  888. goto mutex_unlock;
  889. }
  890. /* Setup our intr mask. */
  891. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  892. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  893. ATH9K_INT_GLOBAL;
  894. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  895. ah->imask |= ATH9K_INT_RXHP |
  896. ATH9K_INT_RXLP |
  897. ATH9K_INT_BB_WATCHDOG;
  898. else
  899. ah->imask |= ATH9K_INT_RX;
  900. ah->imask |= ATH9K_INT_GTT;
  901. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  902. ah->imask |= ATH9K_INT_CST;
  903. sc->sc_flags &= ~SC_OP_INVALID;
  904. sc->sc_ah->is_monitoring = false;
  905. /* Disable BMISS interrupt when we're not associated */
  906. ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  907. if (!ath_complete_reset(sc, false)) {
  908. r = -EIO;
  909. spin_unlock_bh(&sc->sc_pcu_lock);
  910. goto mutex_unlock;
  911. }
  912. spin_unlock_bh(&sc->sc_pcu_lock);
  913. if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
  914. !ah->btcoex_hw.enabled) {
  915. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI))
  916. ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
  917. AR_STOMP_LOW_WLAN_WGHT);
  918. ath9k_hw_btcoex_enable(ah);
  919. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  920. ath9k_btcoex_timer_resume(sc);
  921. }
  922. if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
  923. common->bus_ops->extn_synch_en(common);
  924. mutex_unlock:
  925. mutex_unlock(&sc->mutex);
  926. ath9k_ps_restore(sc);
  927. return r;
  928. }
  929. static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  930. {
  931. struct ath_softc *sc = hw->priv;
  932. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  933. struct ath_tx_control txctl;
  934. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  935. if (sc->ps_enabled) {
  936. /*
  937. * mac80211 does not set PM field for normal data frames, so we
  938. * need to update that based on the current PS mode.
  939. */
  940. if (ieee80211_is_data(hdr->frame_control) &&
  941. !ieee80211_is_nullfunc(hdr->frame_control) &&
  942. !ieee80211_has_pm(hdr->frame_control)) {
  943. ath_dbg(common, ATH_DBG_PS,
  944. "Add PM=1 for a TX frame while in PS mode\n");
  945. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  946. }
  947. }
  948. if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
  949. /*
  950. * We are using PS-Poll and mac80211 can request TX while in
  951. * power save mode. Need to wake up hardware for the TX to be
  952. * completed and if needed, also for RX of buffered frames.
  953. */
  954. ath9k_ps_wakeup(sc);
  955. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  956. ath9k_hw_setrxabort(sc->sc_ah, 0);
  957. if (ieee80211_is_pspoll(hdr->frame_control)) {
  958. ath_dbg(common, ATH_DBG_PS,
  959. "Sending PS-Poll to pick a buffered frame\n");
  960. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  961. } else {
  962. ath_dbg(common, ATH_DBG_PS,
  963. "Wake up to complete TX\n");
  964. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  965. }
  966. /*
  967. * The actual restore operation will happen only after
  968. * the sc_flags bit is cleared. We are just dropping
  969. * the ps_usecount here.
  970. */
  971. ath9k_ps_restore(sc);
  972. }
  973. memset(&txctl, 0, sizeof(struct ath_tx_control));
  974. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  975. ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
  976. if (ath_tx_start(hw, skb, &txctl) != 0) {
  977. ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
  978. goto exit;
  979. }
  980. return;
  981. exit:
  982. dev_kfree_skb_any(skb);
  983. }
  984. static void ath9k_stop(struct ieee80211_hw *hw)
  985. {
  986. struct ath_softc *sc = hw->priv;
  987. struct ath_hw *ah = sc->sc_ah;
  988. struct ath_common *common = ath9k_hw_common(ah);
  989. mutex_lock(&sc->mutex);
  990. ath_cancel_work(sc);
  991. if (sc->sc_flags & SC_OP_INVALID) {
  992. ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
  993. mutex_unlock(&sc->mutex);
  994. return;
  995. }
  996. /* Ensure HW is awake when we try to shut it down. */
  997. ath9k_ps_wakeup(sc);
  998. if (ah->btcoex_hw.enabled) {
  999. ath9k_hw_btcoex_disable(ah);
  1000. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  1001. ath9k_btcoex_timer_pause(sc);
  1002. ath_mci_flush_profile(&sc->btcoex.mci);
  1003. }
  1004. spin_lock_bh(&sc->sc_pcu_lock);
  1005. /* prevent tasklets to enable interrupts once we disable them */
  1006. ah->imask &= ~ATH9K_INT_GLOBAL;
  1007. /* make sure h/w will not generate any interrupt
  1008. * before setting the invalid flag. */
  1009. ath9k_hw_disable_interrupts(ah);
  1010. if (!(sc->sc_flags & SC_OP_INVALID)) {
  1011. ath_drain_all_txq(sc, false);
  1012. ath_stoprecv(sc);
  1013. ath9k_hw_phy_disable(ah);
  1014. } else
  1015. sc->rx.rxlink = NULL;
  1016. if (sc->rx.frag) {
  1017. dev_kfree_skb_any(sc->rx.frag);
  1018. sc->rx.frag = NULL;
  1019. }
  1020. /* disable HAL and put h/w to sleep */
  1021. ath9k_hw_disable(ah);
  1022. spin_unlock_bh(&sc->sc_pcu_lock);
  1023. /* we can now sync irq and kill any running tasklets, since we already
  1024. * disabled interrupts and not holding a spin lock */
  1025. synchronize_irq(sc->irq);
  1026. tasklet_kill(&sc->intr_tq);
  1027. tasklet_kill(&sc->bcon_tasklet);
  1028. ath9k_ps_restore(sc);
  1029. sc->ps_idle = true;
  1030. ath_radio_disable(sc, hw);
  1031. sc->sc_flags |= SC_OP_INVALID;
  1032. mutex_unlock(&sc->mutex);
  1033. ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
  1034. }
  1035. bool ath9k_uses_beacons(int type)
  1036. {
  1037. switch (type) {
  1038. case NL80211_IFTYPE_AP:
  1039. case NL80211_IFTYPE_ADHOC:
  1040. case NL80211_IFTYPE_MESH_POINT:
  1041. return true;
  1042. default:
  1043. return false;
  1044. }
  1045. }
  1046. static void ath9k_reclaim_beacon(struct ath_softc *sc,
  1047. struct ieee80211_vif *vif)
  1048. {
  1049. struct ath_vif *avp = (void *)vif->drv_priv;
  1050. ath9k_set_beaconing_status(sc, false);
  1051. ath_beacon_return(sc, avp);
  1052. ath9k_set_beaconing_status(sc, true);
  1053. sc->sc_flags &= ~SC_OP_BEACONS;
  1054. }
  1055. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1056. {
  1057. struct ath9k_vif_iter_data *iter_data = data;
  1058. int i;
  1059. if (iter_data->hw_macaddr)
  1060. for (i = 0; i < ETH_ALEN; i++)
  1061. iter_data->mask[i] &=
  1062. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  1063. switch (vif->type) {
  1064. case NL80211_IFTYPE_AP:
  1065. iter_data->naps++;
  1066. break;
  1067. case NL80211_IFTYPE_STATION:
  1068. iter_data->nstations++;
  1069. break;
  1070. case NL80211_IFTYPE_ADHOC:
  1071. iter_data->nadhocs++;
  1072. break;
  1073. case NL80211_IFTYPE_MESH_POINT:
  1074. iter_data->nmeshes++;
  1075. break;
  1076. case NL80211_IFTYPE_WDS:
  1077. iter_data->nwds++;
  1078. break;
  1079. default:
  1080. iter_data->nothers++;
  1081. break;
  1082. }
  1083. }
  1084. /* Called with sc->mutex held. */
  1085. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  1086. struct ieee80211_vif *vif,
  1087. struct ath9k_vif_iter_data *iter_data)
  1088. {
  1089. struct ath_softc *sc = hw->priv;
  1090. struct ath_hw *ah = sc->sc_ah;
  1091. struct ath_common *common = ath9k_hw_common(ah);
  1092. /*
  1093. * Use the hardware MAC address as reference, the hardware uses it
  1094. * together with the BSSID mask when matching addresses.
  1095. */
  1096. memset(iter_data, 0, sizeof(*iter_data));
  1097. iter_data->hw_macaddr = common->macaddr;
  1098. memset(&iter_data->mask, 0xff, ETH_ALEN);
  1099. if (vif)
  1100. ath9k_vif_iter(iter_data, vif->addr, vif);
  1101. /* Get list of all active MAC addresses */
  1102. ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
  1103. iter_data);
  1104. }
  1105. /* Called with sc->mutex held. */
  1106. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  1107. struct ieee80211_vif *vif)
  1108. {
  1109. struct ath_softc *sc = hw->priv;
  1110. struct ath_hw *ah = sc->sc_ah;
  1111. struct ath_common *common = ath9k_hw_common(ah);
  1112. struct ath9k_vif_iter_data iter_data;
  1113. ath9k_calculate_iter_data(hw, vif, &iter_data);
  1114. /* Set BSSID mask. */
  1115. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  1116. ath_hw_setbssidmask(common);
  1117. /* Set op-mode & TSF */
  1118. if (iter_data.naps > 0) {
  1119. ath9k_hw_set_tsfadjust(ah, 1);
  1120. sc->sc_flags |= SC_OP_TSF_RESET;
  1121. ah->opmode = NL80211_IFTYPE_AP;
  1122. } else {
  1123. ath9k_hw_set_tsfadjust(ah, 0);
  1124. sc->sc_flags &= ~SC_OP_TSF_RESET;
  1125. if (iter_data.nmeshes)
  1126. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  1127. else if (iter_data.nwds)
  1128. ah->opmode = NL80211_IFTYPE_AP;
  1129. else if (iter_data.nadhocs)
  1130. ah->opmode = NL80211_IFTYPE_ADHOC;
  1131. else
  1132. ah->opmode = NL80211_IFTYPE_STATION;
  1133. }
  1134. /*
  1135. * Enable MIB interrupts when there are hardware phy counters.
  1136. */
  1137. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
  1138. if (ah->config.enable_ani)
  1139. ah->imask |= ATH9K_INT_MIB;
  1140. ah->imask |= ATH9K_INT_TSFOOR;
  1141. } else {
  1142. ah->imask &= ~ATH9K_INT_MIB;
  1143. ah->imask &= ~ATH9K_INT_TSFOOR;
  1144. }
  1145. ath9k_hw_set_interrupts(ah);
  1146. /* Set up ANI */
  1147. if (iter_data.naps > 0) {
  1148. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1149. if (!common->disable_ani) {
  1150. sc->sc_flags |= SC_OP_ANI_RUN;
  1151. ath_start_ani(common);
  1152. }
  1153. } else {
  1154. sc->sc_flags &= ~SC_OP_ANI_RUN;
  1155. del_timer_sync(&common->ani.timer);
  1156. }
  1157. }
  1158. /* Called with sc->mutex held, vif counts set up properly. */
  1159. static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
  1160. struct ieee80211_vif *vif)
  1161. {
  1162. struct ath_softc *sc = hw->priv;
  1163. ath9k_calculate_summary_state(hw, vif);
  1164. if (ath9k_uses_beacons(vif->type)) {
  1165. int error;
  1166. /* This may fail because upper levels do not have beacons
  1167. * properly configured yet. That's OK, we assume it
  1168. * will be properly configured and then we will be notified
  1169. * in the info_changed method and set up beacons properly
  1170. * there.
  1171. */
  1172. ath9k_set_beaconing_status(sc, false);
  1173. error = ath_beacon_alloc(sc, vif);
  1174. if (!error)
  1175. ath_beacon_config(sc, vif);
  1176. ath9k_set_beaconing_status(sc, true);
  1177. }
  1178. }
  1179. static int ath9k_add_interface(struct ieee80211_hw *hw,
  1180. struct ieee80211_vif *vif)
  1181. {
  1182. struct ath_softc *sc = hw->priv;
  1183. struct ath_hw *ah = sc->sc_ah;
  1184. struct ath_common *common = ath9k_hw_common(ah);
  1185. int ret = 0;
  1186. ath9k_ps_wakeup(sc);
  1187. mutex_lock(&sc->mutex);
  1188. switch (vif->type) {
  1189. case NL80211_IFTYPE_STATION:
  1190. case NL80211_IFTYPE_WDS:
  1191. case NL80211_IFTYPE_ADHOC:
  1192. case NL80211_IFTYPE_AP:
  1193. case NL80211_IFTYPE_MESH_POINT:
  1194. break;
  1195. default:
  1196. ath_err(common, "Interface type %d not yet supported\n",
  1197. vif->type);
  1198. ret = -EOPNOTSUPP;
  1199. goto out;
  1200. }
  1201. if (ath9k_uses_beacons(vif->type)) {
  1202. if (sc->nbcnvifs >= ATH_BCBUF) {
  1203. ath_err(common, "Not enough beacon buffers when adding"
  1204. " new interface of type: %i\n",
  1205. vif->type);
  1206. ret = -ENOBUFS;
  1207. goto out;
  1208. }
  1209. }
  1210. if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
  1211. ((vif->type == NL80211_IFTYPE_ADHOC) &&
  1212. sc->nvifs > 0)) {
  1213. ath_err(common, "Cannot create ADHOC interface when other"
  1214. " interfaces already exist.\n");
  1215. ret = -EINVAL;
  1216. goto out;
  1217. }
  1218. ath_dbg(common, ATH_DBG_CONFIG,
  1219. "Attach a VIF of type: %d\n", vif->type);
  1220. sc->nvifs++;
  1221. ath9k_do_vif_add_setup(hw, vif);
  1222. out:
  1223. mutex_unlock(&sc->mutex);
  1224. ath9k_ps_restore(sc);
  1225. return ret;
  1226. }
  1227. static int ath9k_change_interface(struct ieee80211_hw *hw,
  1228. struct ieee80211_vif *vif,
  1229. enum nl80211_iftype new_type,
  1230. bool p2p)
  1231. {
  1232. struct ath_softc *sc = hw->priv;
  1233. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1234. int ret = 0;
  1235. ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n");
  1236. mutex_lock(&sc->mutex);
  1237. ath9k_ps_wakeup(sc);
  1238. /* See if new interface type is valid. */
  1239. if ((new_type == NL80211_IFTYPE_ADHOC) &&
  1240. (sc->nvifs > 1)) {
  1241. ath_err(common, "When using ADHOC, it must be the only"
  1242. " interface.\n");
  1243. ret = -EINVAL;
  1244. goto out;
  1245. }
  1246. if (ath9k_uses_beacons(new_type) &&
  1247. !ath9k_uses_beacons(vif->type)) {
  1248. if (sc->nbcnvifs >= ATH_BCBUF) {
  1249. ath_err(common, "No beacon slot available\n");
  1250. ret = -ENOBUFS;
  1251. goto out;
  1252. }
  1253. }
  1254. /* Clean up old vif stuff */
  1255. if (ath9k_uses_beacons(vif->type))
  1256. ath9k_reclaim_beacon(sc, vif);
  1257. /* Add new settings */
  1258. vif->type = new_type;
  1259. vif->p2p = p2p;
  1260. ath9k_do_vif_add_setup(hw, vif);
  1261. out:
  1262. ath9k_ps_restore(sc);
  1263. mutex_unlock(&sc->mutex);
  1264. return ret;
  1265. }
  1266. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  1267. struct ieee80211_vif *vif)
  1268. {
  1269. struct ath_softc *sc = hw->priv;
  1270. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1271. ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
  1272. ath9k_ps_wakeup(sc);
  1273. mutex_lock(&sc->mutex);
  1274. sc->nvifs--;
  1275. /* Reclaim beacon resources */
  1276. if (ath9k_uses_beacons(vif->type))
  1277. ath9k_reclaim_beacon(sc, vif);
  1278. ath9k_calculate_summary_state(hw, NULL);
  1279. mutex_unlock(&sc->mutex);
  1280. ath9k_ps_restore(sc);
  1281. }
  1282. static void ath9k_enable_ps(struct ath_softc *sc)
  1283. {
  1284. struct ath_hw *ah = sc->sc_ah;
  1285. sc->ps_enabled = true;
  1286. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1287. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  1288. ah->imask |= ATH9K_INT_TIM_TIMER;
  1289. ath9k_hw_set_interrupts(ah);
  1290. }
  1291. ath9k_hw_setrxabort(ah, 1);
  1292. }
  1293. }
  1294. static void ath9k_disable_ps(struct ath_softc *sc)
  1295. {
  1296. struct ath_hw *ah = sc->sc_ah;
  1297. sc->ps_enabled = false;
  1298. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  1299. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1300. ath9k_hw_setrxabort(ah, 0);
  1301. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  1302. PS_WAIT_FOR_CAB |
  1303. PS_WAIT_FOR_PSPOLL_DATA |
  1304. PS_WAIT_FOR_TX_ACK);
  1305. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  1306. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  1307. ath9k_hw_set_interrupts(ah);
  1308. }
  1309. }
  1310. }
  1311. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1312. {
  1313. struct ath_softc *sc = hw->priv;
  1314. struct ath_hw *ah = sc->sc_ah;
  1315. struct ath_common *common = ath9k_hw_common(ah);
  1316. struct ieee80211_conf *conf = &hw->conf;
  1317. bool disable_radio = false;
  1318. mutex_lock(&sc->mutex);
  1319. /*
  1320. * Leave this as the first check because we need to turn on the
  1321. * radio if it was disabled before prior to processing the rest
  1322. * of the changes. Likewise we must only disable the radio towards
  1323. * the end.
  1324. */
  1325. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1326. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1327. if (!sc->ps_idle) {
  1328. ath_radio_enable(sc, hw);
  1329. ath_dbg(common, ATH_DBG_CONFIG,
  1330. "not-idle: enabling radio\n");
  1331. } else {
  1332. disable_radio = true;
  1333. }
  1334. }
  1335. /*
  1336. * We just prepare to enable PS. We have to wait until our AP has
  1337. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1338. * those ACKs and end up retransmitting the same null data frames.
  1339. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1340. */
  1341. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1342. unsigned long flags;
  1343. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1344. if (conf->flags & IEEE80211_CONF_PS)
  1345. ath9k_enable_ps(sc);
  1346. else
  1347. ath9k_disable_ps(sc);
  1348. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1349. }
  1350. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1351. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1352. ath_dbg(common, ATH_DBG_CONFIG,
  1353. "Monitor mode is enabled\n");
  1354. sc->sc_ah->is_monitoring = true;
  1355. } else {
  1356. ath_dbg(common, ATH_DBG_CONFIG,
  1357. "Monitor mode is disabled\n");
  1358. sc->sc_ah->is_monitoring = false;
  1359. }
  1360. }
  1361. if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
  1362. struct ieee80211_channel *curchan = hw->conf.channel;
  1363. struct ath9k_channel old_chan;
  1364. int pos = curchan->hw_value;
  1365. int old_pos = -1;
  1366. unsigned long flags;
  1367. if (ah->curchan)
  1368. old_pos = ah->curchan - &ah->channels[0];
  1369. if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
  1370. sc->sc_flags |= SC_OP_OFFCHANNEL;
  1371. else
  1372. sc->sc_flags &= ~SC_OP_OFFCHANNEL;
  1373. ath_dbg(common, ATH_DBG_CONFIG,
  1374. "Set channel: %d MHz type: %d\n",
  1375. curchan->center_freq, conf->channel_type);
  1376. /* update survey stats for the old channel before switching */
  1377. spin_lock_irqsave(&common->cc_lock, flags);
  1378. ath_update_survey_stats(sc);
  1379. spin_unlock_irqrestore(&common->cc_lock, flags);
  1380. /*
  1381. * Preserve the current channel values, before updating
  1382. * the same channel
  1383. */
  1384. if (old_pos == pos) {
  1385. memcpy(&old_chan, &sc->sc_ah->channels[pos],
  1386. sizeof(struct ath9k_channel));
  1387. ah->curchan = &old_chan;
  1388. }
  1389. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  1390. curchan, conf->channel_type);
  1391. /*
  1392. * If the operating channel changes, change the survey in-use flags
  1393. * along with it.
  1394. * Reset the survey data for the new channel, unless we're switching
  1395. * back to the operating channel from an off-channel operation.
  1396. */
  1397. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  1398. sc->cur_survey != &sc->survey[pos]) {
  1399. if (sc->cur_survey)
  1400. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  1401. sc->cur_survey = &sc->survey[pos];
  1402. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  1403. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  1404. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  1405. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  1406. }
  1407. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1408. ath_err(common, "Unable to set channel\n");
  1409. mutex_unlock(&sc->mutex);
  1410. return -EINVAL;
  1411. }
  1412. /*
  1413. * The most recent snapshot of channel->noisefloor for the old
  1414. * channel is only available after the hardware reset. Copy it to
  1415. * the survey stats now.
  1416. */
  1417. if (old_pos >= 0)
  1418. ath_update_survey_nf(sc, old_pos);
  1419. }
  1420. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1421. ath_dbg(common, ATH_DBG_CONFIG,
  1422. "Set power: %d\n", conf->power_level);
  1423. sc->config.txpowlimit = 2 * conf->power_level;
  1424. ath9k_ps_wakeup(sc);
  1425. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  1426. sc->config.txpowlimit, &sc->curtxpow);
  1427. ath9k_ps_restore(sc);
  1428. }
  1429. if (disable_radio) {
  1430. ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
  1431. ath_radio_disable(sc, hw);
  1432. }
  1433. mutex_unlock(&sc->mutex);
  1434. return 0;
  1435. }
  1436. #define SUPPORTED_FILTERS \
  1437. (FIF_PROMISC_IN_BSS | \
  1438. FIF_ALLMULTI | \
  1439. FIF_CONTROL | \
  1440. FIF_PSPOLL | \
  1441. FIF_OTHER_BSS | \
  1442. FIF_BCN_PRBRESP_PROMISC | \
  1443. FIF_PROBE_REQ | \
  1444. FIF_FCSFAIL)
  1445. /* FIXME: sc->sc_full_reset ? */
  1446. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1447. unsigned int changed_flags,
  1448. unsigned int *total_flags,
  1449. u64 multicast)
  1450. {
  1451. struct ath_softc *sc = hw->priv;
  1452. u32 rfilt;
  1453. changed_flags &= SUPPORTED_FILTERS;
  1454. *total_flags &= SUPPORTED_FILTERS;
  1455. sc->rx.rxfilter = *total_flags;
  1456. ath9k_ps_wakeup(sc);
  1457. rfilt = ath_calcrxfilter(sc);
  1458. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1459. ath9k_ps_restore(sc);
  1460. ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
  1461. "Set HW RX filter: 0x%x\n", rfilt);
  1462. }
  1463. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1464. struct ieee80211_vif *vif,
  1465. struct ieee80211_sta *sta)
  1466. {
  1467. struct ath_softc *sc = hw->priv;
  1468. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1469. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1470. struct ieee80211_key_conf ps_key = { };
  1471. ath_node_attach(sc, sta);
  1472. if (vif->type != NL80211_IFTYPE_AP &&
  1473. vif->type != NL80211_IFTYPE_AP_VLAN)
  1474. return 0;
  1475. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1476. return 0;
  1477. }
  1478. static void ath9k_del_ps_key(struct ath_softc *sc,
  1479. struct ieee80211_vif *vif,
  1480. struct ieee80211_sta *sta)
  1481. {
  1482. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1483. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1484. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1485. if (!an->ps_key)
  1486. return;
  1487. ath_key_delete(common, &ps_key);
  1488. }
  1489. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1490. struct ieee80211_vif *vif,
  1491. struct ieee80211_sta *sta)
  1492. {
  1493. struct ath_softc *sc = hw->priv;
  1494. ath9k_del_ps_key(sc, vif, sta);
  1495. ath_node_detach(sc, sta);
  1496. return 0;
  1497. }
  1498. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1499. struct ieee80211_vif *vif,
  1500. enum sta_notify_cmd cmd,
  1501. struct ieee80211_sta *sta)
  1502. {
  1503. struct ath_softc *sc = hw->priv;
  1504. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1505. switch (cmd) {
  1506. case STA_NOTIFY_SLEEP:
  1507. an->sleeping = true;
  1508. ath_tx_aggr_sleep(sta, sc, an);
  1509. break;
  1510. case STA_NOTIFY_AWAKE:
  1511. an->sleeping = false;
  1512. ath_tx_aggr_wakeup(sc, an);
  1513. break;
  1514. }
  1515. }
  1516. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1517. struct ieee80211_vif *vif, u16 queue,
  1518. const struct ieee80211_tx_queue_params *params)
  1519. {
  1520. struct ath_softc *sc = hw->priv;
  1521. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1522. struct ath_txq *txq;
  1523. struct ath9k_tx_queue_info qi;
  1524. int ret = 0;
  1525. if (queue >= WME_NUM_AC)
  1526. return 0;
  1527. txq = sc->tx.txq_map[queue];
  1528. ath9k_ps_wakeup(sc);
  1529. mutex_lock(&sc->mutex);
  1530. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1531. qi.tqi_aifs = params->aifs;
  1532. qi.tqi_cwmin = params->cw_min;
  1533. qi.tqi_cwmax = params->cw_max;
  1534. qi.tqi_burstTime = params->txop;
  1535. ath_dbg(common, ATH_DBG_CONFIG,
  1536. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1537. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1538. params->cw_max, params->txop);
  1539. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1540. if (ret)
  1541. ath_err(common, "TXQ Update failed\n");
  1542. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1543. if (queue == WME_AC_BE && !ret)
  1544. ath_beaconq_config(sc);
  1545. mutex_unlock(&sc->mutex);
  1546. ath9k_ps_restore(sc);
  1547. return ret;
  1548. }
  1549. static int ath9k_set_key(struct ieee80211_hw *hw,
  1550. enum set_key_cmd cmd,
  1551. struct ieee80211_vif *vif,
  1552. struct ieee80211_sta *sta,
  1553. struct ieee80211_key_conf *key)
  1554. {
  1555. struct ath_softc *sc = hw->priv;
  1556. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1557. int ret = 0;
  1558. if (ath9k_modparam_nohwcrypt)
  1559. return -ENOSPC;
  1560. if (vif->type == NL80211_IFTYPE_ADHOC &&
  1561. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1562. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1563. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1564. /*
  1565. * For now, disable hw crypto for the RSN IBSS group keys. This
  1566. * could be optimized in the future to use a modified key cache
  1567. * design to support per-STA RX GTK, but until that gets
  1568. * implemented, use of software crypto for group addressed
  1569. * frames is a acceptable to allow RSN IBSS to be used.
  1570. */
  1571. return -EOPNOTSUPP;
  1572. }
  1573. mutex_lock(&sc->mutex);
  1574. ath9k_ps_wakeup(sc);
  1575. ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
  1576. switch (cmd) {
  1577. case SET_KEY:
  1578. if (sta)
  1579. ath9k_del_ps_key(sc, vif, sta);
  1580. ret = ath_key_config(common, vif, sta, key);
  1581. if (ret >= 0) {
  1582. key->hw_key_idx = ret;
  1583. /* push IV and Michael MIC generation to stack */
  1584. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1585. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1586. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1587. if (sc->sc_ah->sw_mgmt_crypto &&
  1588. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1589. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1590. ret = 0;
  1591. }
  1592. break;
  1593. case DISABLE_KEY:
  1594. ath_key_delete(common, key);
  1595. break;
  1596. default:
  1597. ret = -EINVAL;
  1598. }
  1599. ath9k_ps_restore(sc);
  1600. mutex_unlock(&sc->mutex);
  1601. return ret;
  1602. }
  1603. static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1604. {
  1605. struct ath_softc *sc = data;
  1606. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1607. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1608. struct ath_vif *avp = (void *)vif->drv_priv;
  1609. /*
  1610. * Skip iteration if primary station vif's bss info
  1611. * was not changed
  1612. */
  1613. if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
  1614. return;
  1615. if (bss_conf->assoc) {
  1616. sc->sc_flags |= SC_OP_PRIM_STA_VIF;
  1617. avp->primary_sta_vif = true;
  1618. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1619. common->curaid = bss_conf->aid;
  1620. ath9k_hw_write_associd(sc->sc_ah);
  1621. ath_dbg(common, ATH_DBG_CONFIG,
  1622. "Bss Info ASSOC %d, bssid: %pM\n",
  1623. bss_conf->aid, common->curbssid);
  1624. ath_beacon_config(sc, vif);
  1625. /*
  1626. * Request a re-configuration of Beacon related timers
  1627. * on the receipt of the first Beacon frame (i.e.,
  1628. * after time sync with the AP).
  1629. */
  1630. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1631. /* Reset rssi stats */
  1632. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1633. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1634. if (!common->disable_ani) {
  1635. sc->sc_flags |= SC_OP_ANI_RUN;
  1636. ath_start_ani(common);
  1637. }
  1638. }
  1639. }
  1640. static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
  1641. {
  1642. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1643. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1644. struct ath_vif *avp = (void *)vif->drv_priv;
  1645. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1646. return;
  1647. /* Reconfigure bss info */
  1648. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1649. ath_dbg(common, ATH_DBG_CONFIG,
  1650. "Bss Info DISASSOC %d, bssid %pM\n",
  1651. common->curaid, common->curbssid);
  1652. sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
  1653. avp->primary_sta_vif = false;
  1654. memset(common->curbssid, 0, ETH_ALEN);
  1655. common->curaid = 0;
  1656. }
  1657. ieee80211_iterate_active_interfaces_atomic(
  1658. sc->hw, ath9k_bss_iter, sc);
  1659. /*
  1660. * None of station vifs are associated.
  1661. * Clear bssid & aid
  1662. */
  1663. if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
  1664. ath9k_hw_write_associd(sc->sc_ah);
  1665. /* Stop ANI */
  1666. sc->sc_flags &= ~SC_OP_ANI_RUN;
  1667. del_timer_sync(&common->ani.timer);
  1668. memset(&sc->caldata, 0, sizeof(sc->caldata));
  1669. }
  1670. }
  1671. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1672. struct ieee80211_vif *vif,
  1673. struct ieee80211_bss_conf *bss_conf,
  1674. u32 changed)
  1675. {
  1676. struct ath_softc *sc = hw->priv;
  1677. struct ath_hw *ah = sc->sc_ah;
  1678. struct ath_common *common = ath9k_hw_common(ah);
  1679. struct ath_vif *avp = (void *)vif->drv_priv;
  1680. int slottime;
  1681. int error;
  1682. ath9k_ps_wakeup(sc);
  1683. mutex_lock(&sc->mutex);
  1684. if (changed & BSS_CHANGED_BSSID) {
  1685. ath9k_config_bss(sc, vif);
  1686. ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
  1687. common->curbssid, common->curaid);
  1688. }
  1689. if (changed & BSS_CHANGED_IBSS) {
  1690. /* There can be only one vif available */
  1691. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1692. common->curaid = bss_conf->aid;
  1693. ath9k_hw_write_associd(sc->sc_ah);
  1694. if (bss_conf->ibss_joined) {
  1695. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1696. if (!common->disable_ani) {
  1697. sc->sc_flags |= SC_OP_ANI_RUN;
  1698. ath_start_ani(common);
  1699. }
  1700. } else {
  1701. sc->sc_flags &= ~SC_OP_ANI_RUN;
  1702. del_timer_sync(&common->ani.timer);
  1703. }
  1704. }
  1705. /* Enable transmission of beacons (AP, IBSS, MESH) */
  1706. if ((changed & BSS_CHANGED_BEACON) ||
  1707. ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
  1708. ath9k_set_beaconing_status(sc, false);
  1709. error = ath_beacon_alloc(sc, vif);
  1710. if (!error)
  1711. ath_beacon_config(sc, vif);
  1712. ath9k_set_beaconing_status(sc, true);
  1713. }
  1714. if (changed & BSS_CHANGED_ERP_SLOT) {
  1715. if (bss_conf->use_short_slot)
  1716. slottime = 9;
  1717. else
  1718. slottime = 20;
  1719. if (vif->type == NL80211_IFTYPE_AP) {
  1720. /*
  1721. * Defer update, so that connected stations can adjust
  1722. * their settings at the same time.
  1723. * See beacon.c for more details
  1724. */
  1725. sc->beacon.slottime = slottime;
  1726. sc->beacon.updateslot = UPDATE;
  1727. } else {
  1728. ah->slottime = slottime;
  1729. ath9k_hw_init_global_settings(ah);
  1730. }
  1731. }
  1732. /* Disable transmission of beacons */
  1733. if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
  1734. !bss_conf->enable_beacon) {
  1735. ath9k_set_beaconing_status(sc, false);
  1736. avp->is_bslot_active = false;
  1737. ath9k_set_beaconing_status(sc, true);
  1738. }
  1739. if (changed & BSS_CHANGED_BEACON_INT) {
  1740. /*
  1741. * In case of AP mode, the HW TSF has to be reset
  1742. * when the beacon interval changes.
  1743. */
  1744. if (vif->type == NL80211_IFTYPE_AP) {
  1745. sc->sc_flags |= SC_OP_TSF_RESET;
  1746. ath9k_set_beaconing_status(sc, false);
  1747. error = ath_beacon_alloc(sc, vif);
  1748. if (!error)
  1749. ath_beacon_config(sc, vif);
  1750. ath9k_set_beaconing_status(sc, true);
  1751. } else
  1752. ath_beacon_config(sc, vif);
  1753. }
  1754. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1755. ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
  1756. bss_conf->use_short_preamble);
  1757. if (bss_conf->use_short_preamble)
  1758. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  1759. else
  1760. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  1761. }
  1762. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1763. ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
  1764. bss_conf->use_cts_prot);
  1765. if (bss_conf->use_cts_prot &&
  1766. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  1767. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  1768. else
  1769. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  1770. }
  1771. mutex_unlock(&sc->mutex);
  1772. ath9k_ps_restore(sc);
  1773. }
  1774. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1775. {
  1776. struct ath_softc *sc = hw->priv;
  1777. u64 tsf;
  1778. mutex_lock(&sc->mutex);
  1779. ath9k_ps_wakeup(sc);
  1780. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1781. ath9k_ps_restore(sc);
  1782. mutex_unlock(&sc->mutex);
  1783. return tsf;
  1784. }
  1785. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1786. struct ieee80211_vif *vif,
  1787. u64 tsf)
  1788. {
  1789. struct ath_softc *sc = hw->priv;
  1790. mutex_lock(&sc->mutex);
  1791. ath9k_ps_wakeup(sc);
  1792. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1793. ath9k_ps_restore(sc);
  1794. mutex_unlock(&sc->mutex);
  1795. }
  1796. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1797. {
  1798. struct ath_softc *sc = hw->priv;
  1799. mutex_lock(&sc->mutex);
  1800. ath9k_ps_wakeup(sc);
  1801. ath9k_hw_reset_tsf(sc->sc_ah);
  1802. ath9k_ps_restore(sc);
  1803. mutex_unlock(&sc->mutex);
  1804. }
  1805. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1806. struct ieee80211_vif *vif,
  1807. enum ieee80211_ampdu_mlme_action action,
  1808. struct ieee80211_sta *sta,
  1809. u16 tid, u16 *ssn, u8 buf_size)
  1810. {
  1811. struct ath_softc *sc = hw->priv;
  1812. int ret = 0;
  1813. local_bh_disable();
  1814. switch (action) {
  1815. case IEEE80211_AMPDU_RX_START:
  1816. if (!(sc->sc_flags & SC_OP_RXAGGR))
  1817. ret = -ENOTSUPP;
  1818. break;
  1819. case IEEE80211_AMPDU_RX_STOP:
  1820. break;
  1821. case IEEE80211_AMPDU_TX_START:
  1822. if (!(sc->sc_flags & SC_OP_TXAGGR))
  1823. return -EOPNOTSUPP;
  1824. ath9k_ps_wakeup(sc);
  1825. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1826. if (!ret)
  1827. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1828. ath9k_ps_restore(sc);
  1829. break;
  1830. case IEEE80211_AMPDU_TX_STOP:
  1831. ath9k_ps_wakeup(sc);
  1832. ath_tx_aggr_stop(sc, sta, tid);
  1833. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1834. ath9k_ps_restore(sc);
  1835. break;
  1836. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1837. ath9k_ps_wakeup(sc);
  1838. ath_tx_aggr_resume(sc, sta, tid);
  1839. ath9k_ps_restore(sc);
  1840. break;
  1841. default:
  1842. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1843. }
  1844. local_bh_enable();
  1845. return ret;
  1846. }
  1847. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1848. struct survey_info *survey)
  1849. {
  1850. struct ath_softc *sc = hw->priv;
  1851. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1852. struct ieee80211_supported_band *sband;
  1853. struct ieee80211_channel *chan;
  1854. unsigned long flags;
  1855. int pos;
  1856. spin_lock_irqsave(&common->cc_lock, flags);
  1857. if (idx == 0)
  1858. ath_update_survey_stats(sc);
  1859. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1860. if (sband && idx >= sband->n_channels) {
  1861. idx -= sband->n_channels;
  1862. sband = NULL;
  1863. }
  1864. if (!sband)
  1865. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1866. if (!sband || idx >= sband->n_channels) {
  1867. spin_unlock_irqrestore(&common->cc_lock, flags);
  1868. return -ENOENT;
  1869. }
  1870. chan = &sband->channels[idx];
  1871. pos = chan->hw_value;
  1872. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1873. survey->channel = chan;
  1874. spin_unlock_irqrestore(&common->cc_lock, flags);
  1875. return 0;
  1876. }
  1877. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1878. {
  1879. struct ath_softc *sc = hw->priv;
  1880. struct ath_hw *ah = sc->sc_ah;
  1881. mutex_lock(&sc->mutex);
  1882. ah->coverage_class = coverage_class;
  1883. ath9k_ps_wakeup(sc);
  1884. ath9k_hw_init_global_settings(ah);
  1885. ath9k_ps_restore(sc);
  1886. mutex_unlock(&sc->mutex);
  1887. }
  1888. static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
  1889. {
  1890. struct ath_softc *sc = hw->priv;
  1891. struct ath_hw *ah = sc->sc_ah;
  1892. struct ath_common *common = ath9k_hw_common(ah);
  1893. int timeout = 200; /* ms */
  1894. int i, j;
  1895. bool drain_txq;
  1896. mutex_lock(&sc->mutex);
  1897. cancel_delayed_work_sync(&sc->tx_complete_work);
  1898. if (ah->ah_flags & AH_UNPLUGGED) {
  1899. ath_dbg(common, ATH_DBG_ANY, "Device has been unplugged!\n");
  1900. mutex_unlock(&sc->mutex);
  1901. return;
  1902. }
  1903. if (sc->sc_flags & SC_OP_INVALID) {
  1904. ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
  1905. mutex_unlock(&sc->mutex);
  1906. return;
  1907. }
  1908. if (drop)
  1909. timeout = 1;
  1910. for (j = 0; j < timeout; j++) {
  1911. bool npend = false;
  1912. if (j)
  1913. usleep_range(1000, 2000);
  1914. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1915. if (!ATH_TXQ_SETUP(sc, i))
  1916. continue;
  1917. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1918. if (npend)
  1919. break;
  1920. }
  1921. if (!npend)
  1922. goto out;
  1923. }
  1924. ath9k_ps_wakeup(sc);
  1925. spin_lock_bh(&sc->sc_pcu_lock);
  1926. drain_txq = ath_drain_all_txq(sc, false);
  1927. spin_unlock_bh(&sc->sc_pcu_lock);
  1928. if (!drain_txq)
  1929. ath_reset(sc, false);
  1930. ath9k_ps_restore(sc);
  1931. ieee80211_wake_queues(hw);
  1932. out:
  1933. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1934. mutex_unlock(&sc->mutex);
  1935. }
  1936. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1937. {
  1938. struct ath_softc *sc = hw->priv;
  1939. int i;
  1940. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1941. if (!ATH_TXQ_SETUP(sc, i))
  1942. continue;
  1943. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1944. return true;
  1945. }
  1946. return false;
  1947. }
  1948. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1949. {
  1950. struct ath_softc *sc = hw->priv;
  1951. struct ath_hw *ah = sc->sc_ah;
  1952. struct ieee80211_vif *vif;
  1953. struct ath_vif *avp;
  1954. struct ath_buf *bf;
  1955. struct ath_tx_status ts;
  1956. int status;
  1957. vif = sc->beacon.bslot[0];
  1958. if (!vif)
  1959. return 0;
  1960. avp = (void *)vif->drv_priv;
  1961. if (!avp->is_bslot_active)
  1962. return 0;
  1963. if (!sc->beacon.tx_processed) {
  1964. tasklet_disable(&sc->bcon_tasklet);
  1965. bf = avp->av_bcbuf;
  1966. if (!bf || !bf->bf_mpdu)
  1967. goto skip;
  1968. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1969. if (status == -EINPROGRESS)
  1970. goto skip;
  1971. sc->beacon.tx_processed = true;
  1972. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1973. skip:
  1974. tasklet_enable(&sc->bcon_tasklet);
  1975. }
  1976. return sc->beacon.tx_last;
  1977. }
  1978. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1979. struct ieee80211_low_level_stats *stats)
  1980. {
  1981. struct ath_softc *sc = hw->priv;
  1982. struct ath_hw *ah = sc->sc_ah;
  1983. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1984. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1985. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1986. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1987. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1988. return 0;
  1989. }
  1990. static u32 fill_chainmask(u32 cap, u32 new)
  1991. {
  1992. u32 filled = 0;
  1993. int i;
  1994. for (i = 0; cap && new; i++, cap >>= 1) {
  1995. if (!(cap & BIT(0)))
  1996. continue;
  1997. if (new & BIT(0))
  1998. filled |= BIT(i);
  1999. new >>= 1;
  2000. }
  2001. return filled;
  2002. }
  2003. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  2004. {
  2005. struct ath_softc *sc = hw->priv;
  2006. struct ath_hw *ah = sc->sc_ah;
  2007. if (!rx_ant || !tx_ant)
  2008. return -EINVAL;
  2009. sc->ant_rx = rx_ant;
  2010. sc->ant_tx = tx_ant;
  2011. if (ah->caps.rx_chainmask == 1)
  2012. return 0;
  2013. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  2014. if (AR_SREV_9100(ah))
  2015. ah->rxchainmask = 0x7;
  2016. else
  2017. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  2018. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  2019. ath9k_reload_chainmask_settings(sc);
  2020. return 0;
  2021. }
  2022. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  2023. {
  2024. struct ath_softc *sc = hw->priv;
  2025. *tx_ant = sc->ant_tx;
  2026. *rx_ant = sc->ant_rx;
  2027. return 0;
  2028. }
  2029. struct ieee80211_ops ath9k_ops = {
  2030. .tx = ath9k_tx,
  2031. .start = ath9k_start,
  2032. .stop = ath9k_stop,
  2033. .add_interface = ath9k_add_interface,
  2034. .change_interface = ath9k_change_interface,
  2035. .remove_interface = ath9k_remove_interface,
  2036. .config = ath9k_config,
  2037. .configure_filter = ath9k_configure_filter,
  2038. .sta_add = ath9k_sta_add,
  2039. .sta_remove = ath9k_sta_remove,
  2040. .sta_notify = ath9k_sta_notify,
  2041. .conf_tx = ath9k_conf_tx,
  2042. .bss_info_changed = ath9k_bss_info_changed,
  2043. .set_key = ath9k_set_key,
  2044. .get_tsf = ath9k_get_tsf,
  2045. .set_tsf = ath9k_set_tsf,
  2046. .reset_tsf = ath9k_reset_tsf,
  2047. .ampdu_action = ath9k_ampdu_action,
  2048. .get_survey = ath9k_get_survey,
  2049. .rfkill_poll = ath9k_rfkill_poll_state,
  2050. .set_coverage_class = ath9k_set_coverage_class,
  2051. .flush = ath9k_flush,
  2052. .tx_frames_pending = ath9k_tx_frames_pending,
  2053. .tx_last_beacon = ath9k_tx_last_beacon,
  2054. .get_stats = ath9k_get_stats,
  2055. .set_antenna = ath9k_set_antenna,
  2056. .get_antenna = ath9k_get_antenna,
  2057. };