ti_hdmi.h 2.3 KB

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  1. /*
  2. * ti_hdmi.h
  3. *
  4. * HDMI driver definition for TI OMAP4, DM81xx, DM38xx Processor.
  5. *
  6. * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License version 2 as published by
  10. * the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program. If not, see <http://www.gnu.org/licenses/>.
  19. */
  20. #ifndef _TI_HDMI_H
  21. #define _TI_HDMI_H
  22. enum hdmi_pll_pwr {
  23. HDMI_PLLPWRCMD_ALLOFF = 0,
  24. HDMI_PLLPWRCMD_PLLONLY = 1,
  25. HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
  26. HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
  27. };
  28. enum hdmi_core_hdmi_dvi {
  29. HDMI_DVI = 0,
  30. HDMI_HDMI = 1
  31. };
  32. enum hdmi_clk_refsel {
  33. HDMI_REFSEL_PCLK = 0,
  34. HDMI_REFSEL_REF1 = 1,
  35. HDMI_REFSEL_REF2 = 2,
  36. HDMI_REFSEL_SYSCLK = 3
  37. };
  38. struct hdmi_video_timings {
  39. u16 x_res;
  40. u16 y_res;
  41. /* Unit: KHz */
  42. u32 pixel_clock;
  43. u16 hsw;
  44. u16 hfp;
  45. u16 hbp;
  46. u16 vsw;
  47. u16 vfp;
  48. u16 vbp;
  49. };
  50. /* HDMI timing structure */
  51. struct hdmi_timings {
  52. struct hdmi_video_timings timings;
  53. int vsync_pol;
  54. int hsync_pol;
  55. };
  56. struct hdmi_cm {
  57. int code;
  58. int mode;
  59. };
  60. struct hdmi_config {
  61. struct hdmi_timings timings;
  62. u16 interlace;
  63. struct hdmi_cm cm;
  64. };
  65. /* HDMI PLL structure */
  66. struct hdmi_pll_info {
  67. u16 regn;
  68. u16 regm;
  69. u32 regmf;
  70. u16 regm2;
  71. u16 regsd;
  72. u16 dcofreq;
  73. enum hdmi_clk_refsel refsel;
  74. };
  75. struct hdmi_ip_data {
  76. void __iomem *base_wp; /* HDMI wrapper */
  77. unsigned long core_sys_offset;
  78. unsigned long core_av_offset;
  79. unsigned long pll_offset;
  80. unsigned long phy_offset;
  81. struct hdmi_config cfg;
  82. struct hdmi_pll_info pll_data;
  83. };
  84. int hdmi_phy_init(struct hdmi_ip_data *ip_data);
  85. void hdmi_phy_off(struct hdmi_ip_data *ip_data);
  86. int read_edid(struct hdmi_ip_data *ip_data, u8 *pedid, u16 max_length);
  87. void hdmi_wp_video_start(struct hdmi_ip_data *ip_data, bool start);
  88. int hdmi_pll_program(struct hdmi_ip_data *ip_data);
  89. int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val);
  90. void hdmi_basic_configure(struct hdmi_ip_data *ip_data);
  91. #endif