nand.h 19 KB

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  1. /*
  2. * linux/include/linux/mtd/nand.h
  3. *
  4. * Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org>
  5. * Steven J. Hill <sjhill@realitydiluted.com>
  6. * Thomas Gleixner <tglx@linutronix.de>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * Info:
  13. * Contains standard defines and IDs for NAND flash devices
  14. *
  15. * Changelog:
  16. * See git changelog.
  17. */
  18. #ifndef __LINUX_MTD_NAND_H
  19. #define __LINUX_MTD_NAND_H
  20. #include <linux/wait.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/mtd/mtd.h>
  23. #include <linux/mtd/flashchip.h>
  24. #include <linux/mtd/bbm.h>
  25. struct mtd_info;
  26. /* Scan and identify a NAND device */
  27. extern int nand_scan (struct mtd_info *mtd, int max_chips);
  28. /* Separate phases of nand_scan(), allowing board driver to intervene
  29. * and override command or ECC setup according to flash type */
  30. extern int nand_scan_ident(struct mtd_info *mtd, int max_chips);
  31. extern int nand_scan_tail(struct mtd_info *mtd);
  32. /* Free resources held by the NAND device */
  33. extern void nand_release (struct mtd_info *mtd);
  34. /* Internal helper for board drivers which need to override command function */
  35. extern void nand_wait_ready(struct mtd_info *mtd);
  36. /* locks all blockes present in the device */
  37. extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  38. /* unlocks specified locked blockes */
  39. extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  40. /* The maximum number of NAND chips in an array */
  41. #define NAND_MAX_CHIPS 8
  42. /* This constant declares the max. oobsize / page, which
  43. * is supported now. If you add a chip with bigger oobsize/page
  44. * adjust this accordingly.
  45. */
  46. #define NAND_MAX_OOBSIZE 128
  47. #define NAND_MAX_PAGESIZE 4096
  48. /*
  49. * Constants for hardware specific CLE/ALE/NCE function
  50. *
  51. * These are bits which can be or'ed to set/clear multiple
  52. * bits in one go.
  53. */
  54. /* Select the chip by setting nCE to low */
  55. #define NAND_NCE 0x01
  56. /* Select the command latch by setting CLE to high */
  57. #define NAND_CLE 0x02
  58. /* Select the address latch by setting ALE to high */
  59. #define NAND_ALE 0x04
  60. #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
  61. #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
  62. #define NAND_CTRL_CHANGE 0x80
  63. /*
  64. * Standard NAND flash commands
  65. */
  66. #define NAND_CMD_READ0 0
  67. #define NAND_CMD_READ1 1
  68. #define NAND_CMD_RNDOUT 5
  69. #define NAND_CMD_PAGEPROG 0x10
  70. #define NAND_CMD_READOOB 0x50
  71. #define NAND_CMD_ERASE1 0x60
  72. #define NAND_CMD_STATUS 0x70
  73. #define NAND_CMD_STATUS_MULTI 0x71
  74. #define NAND_CMD_SEQIN 0x80
  75. #define NAND_CMD_RNDIN 0x85
  76. #define NAND_CMD_READID 0x90
  77. #define NAND_CMD_ERASE2 0xd0
  78. #define NAND_CMD_RESET 0xff
  79. #define NAND_CMD_LOCK 0x2a
  80. #define NAND_CMD_UNLOCK1 0x23
  81. #define NAND_CMD_UNLOCK2 0x24
  82. /* Extended commands for large page devices */
  83. #define NAND_CMD_READSTART 0x30
  84. #define NAND_CMD_RNDOUTSTART 0xE0
  85. #define NAND_CMD_CACHEDPROG 0x15
  86. /* Extended commands for AG-AND device */
  87. /*
  88. * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
  89. * there is no way to distinguish that from NAND_CMD_READ0
  90. * until the remaining sequence of commands has been completed
  91. * so add a high order bit and mask it off in the command.
  92. */
  93. #define NAND_CMD_DEPLETE1 0x100
  94. #define NAND_CMD_DEPLETE2 0x38
  95. #define NAND_CMD_STATUS_MULTI 0x71
  96. #define NAND_CMD_STATUS_ERROR 0x72
  97. /* multi-bank error status (banks 0-3) */
  98. #define NAND_CMD_STATUS_ERROR0 0x73
  99. #define NAND_CMD_STATUS_ERROR1 0x74
  100. #define NAND_CMD_STATUS_ERROR2 0x75
  101. #define NAND_CMD_STATUS_ERROR3 0x76
  102. #define NAND_CMD_STATUS_RESET 0x7f
  103. #define NAND_CMD_STATUS_CLEAR 0xff
  104. #define NAND_CMD_NONE -1
  105. /* Status bits */
  106. #define NAND_STATUS_FAIL 0x01
  107. #define NAND_STATUS_FAIL_N1 0x02
  108. #define NAND_STATUS_TRUE_READY 0x20
  109. #define NAND_STATUS_READY 0x40
  110. #define NAND_STATUS_WP 0x80
  111. /*
  112. * Constants for ECC_MODES
  113. */
  114. typedef enum {
  115. NAND_ECC_NONE,
  116. NAND_ECC_SOFT,
  117. NAND_ECC_HW,
  118. NAND_ECC_HW_SYNDROME,
  119. NAND_ECC_HW_OOB_FIRST,
  120. } nand_ecc_modes_t;
  121. /*
  122. * Constants for Hardware ECC
  123. */
  124. /* Reset Hardware ECC for read */
  125. #define NAND_ECC_READ 0
  126. /* Reset Hardware ECC for write */
  127. #define NAND_ECC_WRITE 1
  128. /* Enable Hardware ECC before syndrom is read back from flash */
  129. #define NAND_ECC_READSYN 2
  130. /* Bit mask for flags passed to do_nand_read_ecc */
  131. #define NAND_GET_DEVICE 0x80
  132. /* Option constants for bizarre disfunctionality and real
  133. * features
  134. */
  135. /* Chip can not auto increment pages */
  136. #define NAND_NO_AUTOINCR 0x00000001
  137. /* Buswitdh is 16 bit */
  138. #define NAND_BUSWIDTH_16 0x00000002
  139. /* Device supports partial programming without padding */
  140. #define NAND_NO_PADDING 0x00000004
  141. /* Chip has cache program function */
  142. #define NAND_CACHEPRG 0x00000008
  143. /* Chip has copy back function */
  144. #define NAND_COPYBACK 0x00000010
  145. /* AND Chip which has 4 banks and a confusing page / block
  146. * assignment. See Renesas datasheet for further information */
  147. #define NAND_IS_AND 0x00000020
  148. /* Chip has a array of 4 pages which can be read without
  149. * additional ready /busy waits */
  150. #define NAND_4PAGE_ARRAY 0x00000040
  151. /* Chip requires that BBT is periodically rewritten to prevent
  152. * bits from adjacent blocks from 'leaking' in altering data.
  153. * This happens with the Renesas AG-AND chips, possibly others. */
  154. #define BBT_AUTO_REFRESH 0x00000080
  155. /* Chip does not require ready check on read. True
  156. * for all large page devices, as they do not support
  157. * autoincrement.*/
  158. #define NAND_NO_READRDY 0x00000100
  159. /* Chip does not allow subpage writes */
  160. #define NAND_NO_SUBPAGE_WRITE 0x00000200
  161. /* Options valid for Samsung large page devices */
  162. #define NAND_SAMSUNG_LP_OPTIONS \
  163. (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
  164. /* Macros to identify the above */
  165. #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
  166. #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
  167. #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
  168. #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
  169. /* Large page NAND with SOFT_ECC should support subpage reads */
  170. #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
  171. && (chip->page_shift > 9))
  172. /* Mask to zero out the chip options, which come from the id table */
  173. #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
  174. /* Non chip related options */
  175. /* Use a flash based bad block table. This option is passed to the
  176. * default bad block table function. */
  177. #define NAND_USE_FLASH_BBT 0x00010000
  178. /* This option skips the bbt scan during initialization. */
  179. #define NAND_SKIP_BBTSCAN 0x00020000
  180. /* This option is defined if the board driver allocates its own buffers
  181. (e.g. because it needs them DMA-coherent */
  182. #define NAND_OWN_BUFFERS 0x00040000
  183. /* Chip may not exist, so silence any errors in scan */
  184. #define NAND_SCAN_SILENT_NODEV 0x00080000
  185. /* Options set by nand scan */
  186. /* Nand scan has allocated controller struct */
  187. #define NAND_CONTROLLER_ALLOC 0x80000000
  188. /* Cell info constants */
  189. #define NAND_CI_CHIPNR_MSK 0x03
  190. #define NAND_CI_CELLTYPE_MSK 0x0C
  191. /* Keep gcc happy */
  192. struct nand_chip;
  193. /**
  194. * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
  195. * @lock: protection lock
  196. * @active: the mtd device which holds the controller currently
  197. * @wq: wait queue to sleep on if a NAND operation is in progress
  198. * used instead of the per chip wait queue when a hw controller is available
  199. */
  200. struct nand_hw_control {
  201. spinlock_t lock;
  202. struct nand_chip *active;
  203. wait_queue_head_t wq;
  204. };
  205. /**
  206. * struct nand_ecc_ctrl - Control structure for ecc
  207. * @mode: ecc mode
  208. * @steps: number of ecc steps per page
  209. * @size: data bytes per ecc step
  210. * @bytes: ecc bytes per step
  211. * @total: total number of ecc bytes per page
  212. * @prepad: padding information for syndrome based ecc generators
  213. * @postpad: padding information for syndrome based ecc generators
  214. * @layout: ECC layout control struct pointer
  215. * @hwctl: function to control hardware ecc generator. Must only
  216. * be provided if an hardware ECC is available
  217. * @calculate: function for ecc calculation or readback from ecc hardware
  218. * @correct: function for ecc correction, matching to ecc generator (sw/hw)
  219. * @read_page_raw: function to read a raw page without ECC
  220. * @write_page_raw: function to write a raw page without ECC
  221. * @read_page: function to read a page according to the ecc generator requirements
  222. * @read_subpage: function to read parts of the page covered by ECC.
  223. * @write_page: function to write a page according to the ecc generator requirements
  224. * @read_oob: function to read chip OOB data
  225. * @write_oob: function to write chip OOB data
  226. */
  227. struct nand_ecc_ctrl {
  228. nand_ecc_modes_t mode;
  229. int steps;
  230. int size;
  231. int bytes;
  232. int total;
  233. int prepad;
  234. int postpad;
  235. struct nand_ecclayout *layout;
  236. void (*hwctl)(struct mtd_info *mtd, int mode);
  237. int (*calculate)(struct mtd_info *mtd,
  238. const uint8_t *dat,
  239. uint8_t *ecc_code);
  240. int (*correct)(struct mtd_info *mtd, uint8_t *dat,
  241. uint8_t *read_ecc,
  242. uint8_t *calc_ecc);
  243. int (*read_page_raw)(struct mtd_info *mtd,
  244. struct nand_chip *chip,
  245. uint8_t *buf, int page);
  246. void (*write_page_raw)(struct mtd_info *mtd,
  247. struct nand_chip *chip,
  248. const uint8_t *buf);
  249. int (*read_page)(struct mtd_info *mtd,
  250. struct nand_chip *chip,
  251. uint8_t *buf, int page);
  252. int (*read_subpage)(struct mtd_info *mtd,
  253. struct nand_chip *chip,
  254. uint32_t offs, uint32_t len,
  255. uint8_t *buf);
  256. void (*write_page)(struct mtd_info *mtd,
  257. struct nand_chip *chip,
  258. const uint8_t *buf);
  259. int (*read_oob)(struct mtd_info *mtd,
  260. struct nand_chip *chip,
  261. int page,
  262. int sndcmd);
  263. int (*write_oob)(struct mtd_info *mtd,
  264. struct nand_chip *chip,
  265. int page);
  266. };
  267. /**
  268. * struct nand_buffers - buffer structure for read/write
  269. * @ecccalc: buffer for calculated ecc
  270. * @ecccode: buffer for ecc read from flash
  271. * @databuf: buffer for data - dynamically sized
  272. *
  273. * Do not change the order of buffers. databuf and oobrbuf must be in
  274. * consecutive order.
  275. */
  276. struct nand_buffers {
  277. uint8_t ecccalc[NAND_MAX_OOBSIZE];
  278. uint8_t ecccode[NAND_MAX_OOBSIZE];
  279. uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
  280. };
  281. /**
  282. * struct nand_chip - NAND Private Flash Chip Data
  283. * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
  284. * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
  285. * @read_byte: [REPLACEABLE] read one byte from the chip
  286. * @read_word: [REPLACEABLE] read one word from the chip
  287. * @write_buf: [REPLACEABLE] write data from the buffer to the chip
  288. * @read_buf: [REPLACEABLE] read data from the chip into the buffer
  289. * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
  290. * @select_chip: [REPLACEABLE] select chip nr
  291. * @block_bad: [REPLACEABLE] check, if the block is bad
  292. * @block_markbad: [REPLACEABLE] mark the block bad
  293. * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
  294. * ALE/CLE/nCE. Also used to write command and address
  295. * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
  296. * If set to NULL no access to ready/busy is available and the ready/busy information
  297. * is read from the chip status register
  298. * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
  299. * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
  300. * @ecc: [BOARDSPECIFIC] ecc control ctructure
  301. * @buffers: buffer structure for read/write
  302. * @hwcontrol: platform-specific hardware control structure
  303. * @ops: oob operation operands
  304. * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
  305. * @scan_bbt: [REPLACEABLE] function to scan bad block table
  306. * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
  307. * @state: [INTERN] the current state of the NAND device
  308. * @oob_poi: poison value buffer
  309. * @page_shift: [INTERN] number of address bits in a page (column address bits)
  310. * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
  311. * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
  312. * @chip_shift: [INTERN] number of address bits in one chip
  313. * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
  314. * special functionality. See the defines for further explanation
  315. * @badblockpos: [INTERN] position of the bad block marker in the oob area
  316. * @cellinfo: [INTERN] MLC/multichip data from chip ident
  317. * @numchips: [INTERN] number of physical chips
  318. * @chipsize: [INTERN] the size of one chip for multichip arrays
  319. * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
  320. * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
  321. * @subpagesize: [INTERN] holds the subpagesize
  322. * @ecclayout: [REPLACEABLE] the default ecc placement scheme
  323. * @bbt: [INTERN] bad block table pointer
  324. * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
  325. * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
  326. * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
  327. * @controller: [REPLACEABLE] a pointer to a hardware controller structure
  328. * which is shared among multiple independend devices
  329. * @priv: [OPTIONAL] pointer to private chip date
  330. * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
  331. * (determine if errors are correctable)
  332. * @write_page: [REPLACEABLE] High-level page write function
  333. */
  334. struct nand_chip {
  335. void __iomem *IO_ADDR_R;
  336. void __iomem *IO_ADDR_W;
  337. uint8_t (*read_byte)(struct mtd_info *mtd);
  338. u16 (*read_word)(struct mtd_info *mtd);
  339. void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
  340. void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
  341. int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
  342. void (*select_chip)(struct mtd_info *mtd, int chip);
  343. int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
  344. int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
  345. void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
  346. unsigned int ctrl);
  347. int (*dev_ready)(struct mtd_info *mtd);
  348. void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
  349. int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
  350. void (*erase_cmd)(struct mtd_info *mtd, int page);
  351. int (*scan_bbt)(struct mtd_info *mtd);
  352. int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
  353. int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
  354. const uint8_t *buf, int page, int cached, int raw);
  355. int chip_delay;
  356. unsigned int options;
  357. int page_shift;
  358. int phys_erase_shift;
  359. int bbt_erase_shift;
  360. int chip_shift;
  361. int numchips;
  362. uint64_t chipsize;
  363. int pagemask;
  364. int pagebuf;
  365. int subpagesize;
  366. uint8_t cellinfo;
  367. int badblockpos;
  368. flstate_t state;
  369. uint8_t *oob_poi;
  370. struct nand_hw_control *controller;
  371. struct nand_ecclayout *ecclayout;
  372. struct nand_ecc_ctrl ecc;
  373. struct nand_buffers *buffers;
  374. struct nand_hw_control hwcontrol;
  375. struct mtd_oob_ops ops;
  376. uint8_t *bbt;
  377. struct nand_bbt_descr *bbt_td;
  378. struct nand_bbt_descr *bbt_md;
  379. struct nand_bbt_descr *badblock_pattern;
  380. void *priv;
  381. };
  382. /*
  383. * NAND Flash Manufacturer ID Codes
  384. */
  385. #define NAND_MFR_TOSHIBA 0x98
  386. #define NAND_MFR_SAMSUNG 0xec
  387. #define NAND_MFR_FUJITSU 0x04
  388. #define NAND_MFR_NATIONAL 0x8f
  389. #define NAND_MFR_RENESAS 0x07
  390. #define NAND_MFR_STMICRO 0x20
  391. #define NAND_MFR_HYNIX 0xad
  392. #define NAND_MFR_MICRON 0x2c
  393. #define NAND_MFR_AMD 0x01
  394. /**
  395. * struct nand_flash_dev - NAND Flash Device ID Structure
  396. * @name: Identify the device type
  397. * @id: device ID code
  398. * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
  399. * If the pagesize is 0, then the real pagesize
  400. * and the eraseize are determined from the
  401. * extended id bytes in the chip
  402. * @erasesize: Size of an erase block in the flash device.
  403. * @chipsize: Total chipsize in Mega Bytes
  404. * @options: Bitfield to store chip relevant options
  405. */
  406. struct nand_flash_dev {
  407. char *name;
  408. int id;
  409. unsigned long pagesize;
  410. unsigned long chipsize;
  411. unsigned long erasesize;
  412. unsigned long options;
  413. };
  414. /**
  415. * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
  416. * @name: Manufacturer name
  417. * @id: manufacturer ID code of device.
  418. */
  419. struct nand_manufacturers {
  420. int id;
  421. char * name;
  422. };
  423. extern struct nand_flash_dev nand_flash_ids[];
  424. extern struct nand_manufacturers nand_manuf_ids[];
  425. extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
  426. extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
  427. extern int nand_default_bbt(struct mtd_info *mtd);
  428. extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
  429. extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
  430. int allowbbt);
  431. extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
  432. size_t * retlen, uint8_t * buf);
  433. /**
  434. * struct platform_nand_chip - chip level device structure
  435. * @nr_chips: max. number of chips to scan for
  436. * @chip_offset: chip number offset
  437. * @nr_partitions: number of partitions pointed to by partitions (or zero)
  438. * @partitions: mtd partition list
  439. * @chip_delay: R/B delay value in us
  440. * @options: Option flags, e.g. 16bit buswidth
  441. * @ecclayout: ecc layout info structure
  442. * @part_probe_types: NULL-terminated array of probe types
  443. * @set_parts: platform specific function to set partitions
  444. * @priv: hardware controller specific settings
  445. */
  446. struct platform_nand_chip {
  447. int nr_chips;
  448. int chip_offset;
  449. int nr_partitions;
  450. struct mtd_partition *partitions;
  451. struct nand_ecclayout *ecclayout;
  452. int chip_delay;
  453. unsigned int options;
  454. const char **part_probe_types;
  455. void (*set_parts)(uint64_t size,
  456. struct platform_nand_chip *chip);
  457. void *priv;
  458. };
  459. /* Keep gcc happy */
  460. struct platform_device;
  461. /**
  462. * struct platform_nand_ctrl - controller level device structure
  463. * @probe: platform specific function to probe/setup hardware
  464. * @remove: platform specific function to remove/teardown hardware
  465. * @hwcontrol: platform specific hardware control structure
  466. * @dev_ready: platform specific function to read ready/busy pin
  467. * @select_chip: platform specific chip select function
  468. * @cmd_ctrl: platform specific function for controlling
  469. * ALE/CLE/nCE. Also used to write command and address
  470. * @write_buf: platform specific function for write buffer
  471. * @read_buf: platform specific function for read buffer
  472. * @priv: private data to transport driver specific settings
  473. *
  474. * All fields are optional and depend on the hardware driver requirements
  475. */
  476. struct platform_nand_ctrl {
  477. int (*probe)(struct platform_device *pdev);
  478. void (*remove)(struct platform_device *pdev);
  479. void (*hwcontrol)(struct mtd_info *mtd, int cmd);
  480. int (*dev_ready)(struct mtd_info *mtd);
  481. void (*select_chip)(struct mtd_info *mtd, int chip);
  482. void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
  483. unsigned int ctrl);
  484. void (*write_buf)(struct mtd_info *mtd,
  485. const uint8_t *buf, int len);
  486. void (*read_buf)(struct mtd_info *mtd,
  487. uint8_t *buf, int len);
  488. void *priv;
  489. };
  490. /**
  491. * struct platform_nand_data - container structure for platform-specific data
  492. * @chip: chip level chip structure
  493. * @ctrl: controller level device structure
  494. */
  495. struct platform_nand_data {
  496. struct platform_nand_chip chip;
  497. struct platform_nand_ctrl ctrl;
  498. };
  499. /* Some helpers to access the data structures */
  500. static inline
  501. struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
  502. {
  503. struct nand_chip *chip = mtd->priv;
  504. return chip->priv;
  505. }
  506. #endif /* __LINUX_MTD_NAND_H */