intel_crt.c 19 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/dmi.h>
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include "drmP.h"
  30. #include "drm.h"
  31. #include "drm_crtc.h"
  32. #include "drm_crtc_helper.h"
  33. #include "drm_edid.h"
  34. #include "intel_drv.h"
  35. #include "i915_drm.h"
  36. #include "i915_drv.h"
  37. /* Here's the desired hotplug mode */
  38. #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
  39. ADPA_CRT_HOTPLUG_WARMUP_10MS | \
  40. ADPA_CRT_HOTPLUG_SAMPLE_4S | \
  41. ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
  42. ADPA_CRT_HOTPLUG_VOLREF_325MV | \
  43. ADPA_CRT_HOTPLUG_ENABLE)
  44. struct intel_crt {
  45. struct intel_encoder base;
  46. bool force_hotplug_required;
  47. };
  48. static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  49. {
  50. return container_of(intel_attached_encoder(connector),
  51. struct intel_crt, base);
  52. }
  53. static void pch_crt_dpms(struct drm_encoder *encoder, int mode)
  54. {
  55. struct drm_device *dev = encoder->dev;
  56. struct drm_i915_private *dev_priv = dev->dev_private;
  57. u32 temp;
  58. temp = I915_READ(PCH_ADPA);
  59. temp &= ~ADPA_DAC_ENABLE;
  60. switch (mode) {
  61. case DRM_MODE_DPMS_ON:
  62. temp |= ADPA_DAC_ENABLE;
  63. break;
  64. case DRM_MODE_DPMS_STANDBY:
  65. case DRM_MODE_DPMS_SUSPEND:
  66. case DRM_MODE_DPMS_OFF:
  67. /* Just leave port enable cleared */
  68. break;
  69. }
  70. I915_WRITE(PCH_ADPA, temp);
  71. }
  72. static void gmch_crt_dpms(struct drm_encoder *encoder, int mode)
  73. {
  74. struct drm_device *dev = encoder->dev;
  75. struct drm_i915_private *dev_priv = dev->dev_private;
  76. u32 temp;
  77. temp = I915_READ(ADPA);
  78. temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  79. temp &= ~ADPA_DAC_ENABLE;
  80. switch (mode) {
  81. case DRM_MODE_DPMS_ON:
  82. temp |= ADPA_DAC_ENABLE;
  83. break;
  84. case DRM_MODE_DPMS_STANDBY:
  85. temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
  86. break;
  87. case DRM_MODE_DPMS_SUSPEND:
  88. temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
  89. break;
  90. case DRM_MODE_DPMS_OFF:
  91. temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
  92. break;
  93. }
  94. I915_WRITE(ADPA, temp);
  95. }
  96. static int intel_crt_mode_valid(struct drm_connector *connector,
  97. struct drm_display_mode *mode)
  98. {
  99. struct drm_device *dev = connector->dev;
  100. int max_clock = 0;
  101. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  102. return MODE_NO_DBLESCAN;
  103. if (mode->clock < 25000)
  104. return MODE_CLOCK_LOW;
  105. if (IS_GEN2(dev))
  106. max_clock = 350000;
  107. else
  108. max_clock = 400000;
  109. if (mode->clock > max_clock)
  110. return MODE_CLOCK_HIGH;
  111. return MODE_OK;
  112. }
  113. static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
  114. struct drm_display_mode *mode,
  115. struct drm_display_mode *adjusted_mode)
  116. {
  117. return true;
  118. }
  119. static void intel_crt_mode_set(struct drm_encoder *encoder,
  120. struct drm_display_mode *mode,
  121. struct drm_display_mode *adjusted_mode)
  122. {
  123. struct drm_device *dev = encoder->dev;
  124. struct drm_crtc *crtc = encoder->crtc;
  125. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  126. struct drm_i915_private *dev_priv = dev->dev_private;
  127. int dpll_md_reg;
  128. u32 adpa, dpll_md;
  129. u32 adpa_reg;
  130. dpll_md_reg = DPLL_MD(intel_crtc->pipe);
  131. if (HAS_PCH_SPLIT(dev))
  132. adpa_reg = PCH_ADPA;
  133. else
  134. adpa_reg = ADPA;
  135. /*
  136. * Disable separate mode multiplier used when cloning SDVO to CRT
  137. * XXX this needs to be adjusted when we really are cloning
  138. */
  139. if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
  140. dpll_md = I915_READ(dpll_md_reg);
  141. I915_WRITE(dpll_md_reg,
  142. dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
  143. }
  144. adpa = ADPA_HOTPLUG_BITS;
  145. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  146. adpa |= ADPA_HSYNC_ACTIVE_HIGH;
  147. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  148. adpa |= ADPA_VSYNC_ACTIVE_HIGH;
  149. /* For CPT allow 3 pipe config, for others just use A or B */
  150. if (HAS_PCH_CPT(dev))
  151. adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
  152. else if (intel_crtc->pipe == 0)
  153. adpa |= ADPA_PIPE_A_SELECT;
  154. else
  155. adpa |= ADPA_PIPE_B_SELECT;
  156. if (!HAS_PCH_SPLIT(dev))
  157. I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
  158. I915_WRITE(adpa_reg, adpa);
  159. }
  160. static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
  161. {
  162. struct drm_device *dev = connector->dev;
  163. struct intel_crt *crt = intel_attached_crt(connector);
  164. struct drm_i915_private *dev_priv = dev->dev_private;
  165. u32 adpa;
  166. bool ret;
  167. /* The first time through, trigger an explicit detection cycle */
  168. if (crt->force_hotplug_required) {
  169. bool turn_off_dac = HAS_PCH_SPLIT(dev);
  170. u32 save_adpa;
  171. crt->force_hotplug_required = 0;
  172. save_adpa = adpa = I915_READ(PCH_ADPA);
  173. DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  174. adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  175. if (turn_off_dac)
  176. adpa &= ~ADPA_DAC_ENABLE;
  177. I915_WRITE(PCH_ADPA, adpa);
  178. if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  179. 1000))
  180. DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  181. if (turn_off_dac) {
  182. I915_WRITE(PCH_ADPA, save_adpa);
  183. POSTING_READ(PCH_ADPA);
  184. }
  185. }
  186. /* Check the status to see if both blue and green are on now */
  187. adpa = I915_READ(PCH_ADPA);
  188. if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  189. ret = true;
  190. else
  191. ret = false;
  192. DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
  193. return ret;
  194. }
  195. static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
  196. {
  197. struct drm_device *dev = connector->dev;
  198. struct drm_i915_private *dev_priv = dev->dev_private;
  199. u32 adpa;
  200. bool ret;
  201. u32 save_adpa;
  202. save_adpa = adpa = I915_READ(ADPA);
  203. DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  204. adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  205. I915_WRITE(ADPA, adpa);
  206. if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  207. 1000)) {
  208. DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  209. I915_WRITE(ADPA, save_adpa);
  210. }
  211. /* Check the status to see if both blue and green are on now */
  212. adpa = I915_READ(ADPA);
  213. if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  214. ret = true;
  215. else
  216. ret = false;
  217. DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
  218. /* FIXME: debug force function and remove */
  219. ret = true;
  220. return ret;
  221. }
  222. /**
  223. * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  224. *
  225. * Not for i915G/i915GM
  226. *
  227. * \return true if CRT is connected.
  228. * \return false if CRT is disconnected.
  229. */
  230. static bool intel_crt_detect_hotplug(struct drm_connector *connector)
  231. {
  232. struct drm_device *dev = connector->dev;
  233. struct drm_i915_private *dev_priv = dev->dev_private;
  234. u32 hotplug_en, orig, stat;
  235. bool ret = false;
  236. int i, tries = 0;
  237. if (HAS_PCH_SPLIT(dev))
  238. return intel_ironlake_crt_detect_hotplug(connector);
  239. if (IS_VALLEYVIEW(dev))
  240. return valleyview_crt_detect_hotplug(connector);
  241. /*
  242. * On 4 series desktop, CRT detect sequence need to be done twice
  243. * to get a reliable result.
  244. */
  245. if (IS_G4X(dev) && !IS_GM45(dev))
  246. tries = 2;
  247. else
  248. tries = 1;
  249. hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
  250. hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
  251. for (i = 0; i < tries ; i++) {
  252. /* turn on the FORCE_DETECT */
  253. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  254. /* wait for FORCE_DETECT to go off */
  255. if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
  256. CRT_HOTPLUG_FORCE_DETECT) == 0,
  257. 1000))
  258. DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
  259. }
  260. stat = I915_READ(PORT_HOTPLUG_STAT);
  261. if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
  262. ret = true;
  263. /* clear the interrupt we just generated, if any */
  264. I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
  265. /* and put the bits back */
  266. I915_WRITE(PORT_HOTPLUG_EN, orig);
  267. return ret;
  268. }
  269. static bool intel_crt_detect_ddc(struct drm_connector *connector)
  270. {
  271. struct intel_crt *crt = intel_attached_crt(connector);
  272. struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
  273. /* CRT should always be at 0, but check anyway */
  274. if (crt->base.type != INTEL_OUTPUT_ANALOG)
  275. return false;
  276. if (intel_ddc_probe(&crt->base, dev_priv->crt_ddc_pin)) {
  277. struct edid *edid;
  278. bool is_digital = false;
  279. struct i2c_adapter *i2c;
  280. i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
  281. edid = drm_get_edid(connector, i2c);
  282. /*
  283. * This may be a DVI-I connector with a shared DDC
  284. * link between analog and digital outputs, so we
  285. * have to check the EDID input spec of the attached device.
  286. *
  287. * On the other hand, what should we do if it is a broken EDID?
  288. */
  289. if (edid != NULL) {
  290. is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
  291. connector->display_info.raw_edid = NULL;
  292. kfree(edid);
  293. }
  294. if (!is_digital) {
  295. DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
  296. return true;
  297. } else {
  298. DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
  299. }
  300. }
  301. return false;
  302. }
  303. static enum drm_connector_status
  304. intel_crt_load_detect(struct intel_crt *crt)
  305. {
  306. struct drm_device *dev = crt->base.base.dev;
  307. struct drm_i915_private *dev_priv = dev->dev_private;
  308. uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
  309. uint32_t save_bclrpat;
  310. uint32_t save_vtotal;
  311. uint32_t vtotal, vactive;
  312. uint32_t vsample;
  313. uint32_t vblank, vblank_start, vblank_end;
  314. uint32_t dsl;
  315. uint32_t bclrpat_reg;
  316. uint32_t vtotal_reg;
  317. uint32_t vblank_reg;
  318. uint32_t vsync_reg;
  319. uint32_t pipeconf_reg;
  320. uint32_t pipe_dsl_reg;
  321. uint8_t st00;
  322. enum drm_connector_status status;
  323. DRM_DEBUG_KMS("starting load-detect on CRT\n");
  324. bclrpat_reg = BCLRPAT(pipe);
  325. vtotal_reg = VTOTAL(pipe);
  326. vblank_reg = VBLANK(pipe);
  327. vsync_reg = VSYNC(pipe);
  328. pipeconf_reg = PIPECONF(pipe);
  329. pipe_dsl_reg = PIPEDSL(pipe);
  330. save_bclrpat = I915_READ(bclrpat_reg);
  331. save_vtotal = I915_READ(vtotal_reg);
  332. vblank = I915_READ(vblank_reg);
  333. vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
  334. vactive = (save_vtotal & 0x7ff) + 1;
  335. vblank_start = (vblank & 0xfff) + 1;
  336. vblank_end = ((vblank >> 16) & 0xfff) + 1;
  337. /* Set the border color to purple. */
  338. I915_WRITE(bclrpat_reg, 0x500050);
  339. if (!IS_GEN2(dev)) {
  340. uint32_t pipeconf = I915_READ(pipeconf_reg);
  341. I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
  342. POSTING_READ(pipeconf_reg);
  343. /* Wait for next Vblank to substitue
  344. * border color for Color info */
  345. intel_wait_for_vblank(dev, pipe);
  346. st00 = I915_READ8(VGA_MSR_WRITE);
  347. status = ((st00 & (1 << 4)) != 0) ?
  348. connector_status_connected :
  349. connector_status_disconnected;
  350. I915_WRITE(pipeconf_reg, pipeconf);
  351. } else {
  352. bool restore_vblank = false;
  353. int count, detect;
  354. /*
  355. * If there isn't any border, add some.
  356. * Yes, this will flicker
  357. */
  358. if (vblank_start <= vactive && vblank_end >= vtotal) {
  359. uint32_t vsync = I915_READ(vsync_reg);
  360. uint32_t vsync_start = (vsync & 0xffff) + 1;
  361. vblank_start = vsync_start;
  362. I915_WRITE(vblank_reg,
  363. (vblank_start - 1) |
  364. ((vblank_end - 1) << 16));
  365. restore_vblank = true;
  366. }
  367. /* sample in the vertical border, selecting the larger one */
  368. if (vblank_start - vactive >= vtotal - vblank_end)
  369. vsample = (vblank_start + vactive) >> 1;
  370. else
  371. vsample = (vtotal + vblank_end) >> 1;
  372. /*
  373. * Wait for the border to be displayed
  374. */
  375. while (I915_READ(pipe_dsl_reg) >= vactive)
  376. ;
  377. while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
  378. ;
  379. /*
  380. * Watch ST00 for an entire scanline
  381. */
  382. detect = 0;
  383. count = 0;
  384. do {
  385. count++;
  386. /* Read the ST00 VGA status register */
  387. st00 = I915_READ8(VGA_MSR_WRITE);
  388. if (st00 & (1 << 4))
  389. detect++;
  390. } while ((I915_READ(pipe_dsl_reg) == dsl));
  391. /* restore vblank if necessary */
  392. if (restore_vblank)
  393. I915_WRITE(vblank_reg, vblank);
  394. /*
  395. * If more than 3/4 of the scanline detected a monitor,
  396. * then it is assumed to be present. This works even on i830,
  397. * where there isn't any way to force the border color across
  398. * the screen
  399. */
  400. status = detect * 4 > count * 3 ?
  401. connector_status_connected :
  402. connector_status_disconnected;
  403. }
  404. /* Restore previous settings */
  405. I915_WRITE(bclrpat_reg, save_bclrpat);
  406. return status;
  407. }
  408. static enum drm_connector_status
  409. intel_crt_detect(struct drm_connector *connector, bool force)
  410. {
  411. struct drm_device *dev = connector->dev;
  412. struct intel_crt *crt = intel_attached_crt(connector);
  413. enum drm_connector_status status;
  414. struct intel_load_detect_pipe tmp;
  415. if (I915_HAS_HOTPLUG(dev)) {
  416. /* We can not rely on the HPD pin always being correctly wired
  417. * up, for example many KVM do not pass it through, and so
  418. * only trust an assertion that the monitor is connected.
  419. */
  420. if (intel_crt_detect_hotplug(connector)) {
  421. DRM_DEBUG_KMS("CRT detected via hotplug\n");
  422. return connector_status_connected;
  423. } else
  424. DRM_DEBUG_KMS("CRT not detected via hotplug\n");
  425. }
  426. if (intel_crt_detect_ddc(connector))
  427. return connector_status_connected;
  428. /* Load detection is broken on HPD capable machines. Whoever wants a
  429. * broken monitor (without edid) to work behind a broken kvm (that fails
  430. * to have the right resistors for HP detection) needs to fix this up.
  431. * For now just bail out. */
  432. if (I915_HAS_HOTPLUG(dev))
  433. return connector_status_disconnected;
  434. if (!force)
  435. return connector->status;
  436. /* for pre-945g platforms use load detect */
  437. if (intel_get_load_detect_pipe(&crt->base, connector, NULL,
  438. &tmp)) {
  439. if (intel_crt_detect_ddc(connector))
  440. status = connector_status_connected;
  441. else
  442. status = intel_crt_load_detect(crt);
  443. intel_release_load_detect_pipe(&crt->base, connector,
  444. &tmp);
  445. } else
  446. status = connector_status_unknown;
  447. return status;
  448. }
  449. static void intel_crt_destroy(struct drm_connector *connector)
  450. {
  451. drm_sysfs_connector_remove(connector);
  452. drm_connector_cleanup(connector);
  453. kfree(connector);
  454. }
  455. static int intel_crt_get_modes(struct drm_connector *connector)
  456. {
  457. struct drm_device *dev = connector->dev;
  458. struct drm_i915_private *dev_priv = dev->dev_private;
  459. int ret;
  460. struct i2c_adapter *i2c;
  461. i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
  462. ret = intel_ddc_get_modes(connector, i2c);
  463. if (ret || !IS_G4X(dev))
  464. return ret;
  465. /* Try to probe digital port for output in DVI-I -> VGA mode. */
  466. i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
  467. return intel_ddc_get_modes(connector, i2c);
  468. }
  469. static int intel_crt_set_property(struct drm_connector *connector,
  470. struct drm_property *property,
  471. uint64_t value)
  472. {
  473. return 0;
  474. }
  475. static void intel_crt_reset(struct drm_connector *connector)
  476. {
  477. struct drm_device *dev = connector->dev;
  478. struct intel_crt *crt = intel_attached_crt(connector);
  479. if (HAS_PCH_SPLIT(dev))
  480. crt->force_hotplug_required = 1;
  481. }
  482. /*
  483. * Routines for controlling stuff on the analog port
  484. */
  485. static const struct drm_encoder_helper_funcs pch_encoder_funcs = {
  486. .mode_fixup = intel_crt_mode_fixup,
  487. .prepare = intel_encoder_prepare,
  488. .commit = intel_encoder_commit,
  489. .mode_set = intel_crt_mode_set,
  490. .dpms = pch_crt_dpms,
  491. };
  492. static const struct drm_encoder_helper_funcs gmch_encoder_funcs = {
  493. .mode_fixup = intel_crt_mode_fixup,
  494. .prepare = intel_encoder_prepare,
  495. .commit = intel_encoder_commit,
  496. .mode_set = intel_crt_mode_set,
  497. .dpms = gmch_crt_dpms,
  498. };
  499. static const struct drm_connector_funcs intel_crt_connector_funcs = {
  500. .reset = intel_crt_reset,
  501. .dpms = drm_helper_connector_dpms,
  502. .detect = intel_crt_detect,
  503. .fill_modes = drm_helper_probe_single_connector_modes,
  504. .destroy = intel_crt_destroy,
  505. .set_property = intel_crt_set_property,
  506. };
  507. static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
  508. .mode_valid = intel_crt_mode_valid,
  509. .get_modes = intel_crt_get_modes,
  510. .best_encoder = intel_best_encoder,
  511. };
  512. static const struct drm_encoder_funcs intel_crt_enc_funcs = {
  513. .destroy = intel_encoder_destroy,
  514. };
  515. static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id)
  516. {
  517. DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
  518. return 1;
  519. }
  520. static const struct dmi_system_id intel_no_crt[] = {
  521. {
  522. .callback = intel_no_crt_dmi_callback,
  523. .ident = "ACER ZGB",
  524. .matches = {
  525. DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
  526. DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
  527. },
  528. },
  529. { }
  530. };
  531. void intel_crt_init(struct drm_device *dev)
  532. {
  533. struct drm_connector *connector;
  534. struct intel_crt *crt;
  535. struct intel_connector *intel_connector;
  536. struct drm_i915_private *dev_priv = dev->dev_private;
  537. const struct drm_encoder_helper_funcs *encoder_helper_funcs;
  538. /* Skip machines without VGA that falsely report hotplug events */
  539. if (dmi_check_system(intel_no_crt))
  540. return;
  541. crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
  542. if (!crt)
  543. return;
  544. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  545. if (!intel_connector) {
  546. kfree(crt);
  547. return;
  548. }
  549. connector = &intel_connector->base;
  550. drm_connector_init(dev, &intel_connector->base,
  551. &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  552. drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
  553. DRM_MODE_ENCODER_DAC);
  554. intel_connector_attach_encoder(intel_connector, &crt->base);
  555. crt->base.type = INTEL_OUTPUT_ANALOG;
  556. crt->base.clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT |
  557. 1 << INTEL_ANALOG_CLONE_BIT |
  558. 1 << INTEL_SDVO_LVDS_CLONE_BIT);
  559. if (IS_HASWELL(dev))
  560. crt->base.crtc_mask = (1 << 0);
  561. else
  562. crt->base.crtc_mask = (1 << 0) | (1 << 1);
  563. if (IS_GEN2(dev))
  564. connector->interlace_allowed = 0;
  565. else
  566. connector->interlace_allowed = 1;
  567. connector->doublescan_allowed = 0;
  568. if (HAS_PCH_SPLIT(dev))
  569. encoder_helper_funcs = &pch_encoder_funcs;
  570. else
  571. encoder_helper_funcs = &gmch_encoder_funcs;
  572. drm_encoder_helper_add(&crt->base.base, encoder_helper_funcs);
  573. drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
  574. drm_sysfs_connector_add(connector);
  575. if (I915_HAS_HOTPLUG(dev))
  576. connector->polled = DRM_CONNECTOR_POLL_HPD;
  577. else
  578. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  579. /*
  580. * Configure the automatic hotplug detection stuff
  581. */
  582. crt->force_hotplug_required = 0;
  583. if (HAS_PCH_SPLIT(dev)) {
  584. u32 adpa;
  585. adpa = I915_READ(PCH_ADPA);
  586. adpa &= ~ADPA_CRT_HOTPLUG_MASK;
  587. adpa |= ADPA_HOTPLUG_BITS;
  588. I915_WRITE(PCH_ADPA, adpa);
  589. POSTING_READ(PCH_ADPA);
  590. DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
  591. crt->force_hotplug_required = 1;
  592. }
  593. dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
  594. }