spi_s3c24xx.c 10 KB

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  1. /* linux/drivers/spi/spi_s3c24xx.c
  2. *
  3. * Copyright (c) 2006 Ben Dooks
  4. * Copyright (c) 2006 Simtec Electronics
  5. * Ben Dooks <ben@simtec.co.uk>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. */
  12. #include <linux/init.h>
  13. #include <linux/spinlock.h>
  14. #include <linux/workqueue.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/delay.h>
  17. #include <linux/errno.h>
  18. #include <linux/err.h>
  19. #include <linux/clk.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/gpio.h>
  22. #include <linux/spi/spi.h>
  23. #include <linux/spi/spi_bitbang.h>
  24. #include <asm/io.h>
  25. #include <asm/dma.h>
  26. #include <mach/hardware.h>
  27. #include <plat/regs-spi.h>
  28. #include <mach/spi.h>
  29. struct s3c24xx_spi {
  30. /* bitbang has to be first */
  31. struct spi_bitbang bitbang;
  32. struct completion done;
  33. void __iomem *regs;
  34. int irq;
  35. int len;
  36. int count;
  37. void (*set_cs)(struct s3c2410_spi_info *spi,
  38. int cs, int pol);
  39. /* data buffers */
  40. const unsigned char *tx;
  41. unsigned char *rx;
  42. struct clk *clk;
  43. struct resource *ioarea;
  44. struct spi_master *master;
  45. struct spi_device *curdev;
  46. struct device *dev;
  47. struct s3c2410_spi_info *pdata;
  48. };
  49. #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
  50. #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
  51. static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
  52. {
  53. return spi_master_get_devdata(sdev->master);
  54. }
  55. static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
  56. {
  57. gpio_set_value(spi->pin_cs, pol);
  58. }
  59. static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
  60. {
  61. struct s3c24xx_spi *hw = to_hw(spi);
  62. unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
  63. unsigned int spcon;
  64. switch (value) {
  65. case BITBANG_CS_INACTIVE:
  66. hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
  67. break;
  68. case BITBANG_CS_ACTIVE:
  69. spcon = readb(hw->regs + S3C2410_SPCON);
  70. if (spi->mode & SPI_CPHA)
  71. spcon |= S3C2410_SPCON_CPHA_FMTB;
  72. else
  73. spcon &= ~S3C2410_SPCON_CPHA_FMTB;
  74. if (spi->mode & SPI_CPOL)
  75. spcon |= S3C2410_SPCON_CPOL_HIGH;
  76. else
  77. spcon &= ~S3C2410_SPCON_CPOL_HIGH;
  78. spcon |= S3C2410_SPCON_ENSCK;
  79. /* write new configration */
  80. writeb(spcon, hw->regs + S3C2410_SPCON);
  81. hw->set_cs(hw->pdata, spi->chip_select, cspol);
  82. break;
  83. }
  84. }
  85. static int s3c24xx_spi_setupxfer(struct spi_device *spi,
  86. struct spi_transfer *t)
  87. {
  88. struct s3c24xx_spi *hw = to_hw(spi);
  89. unsigned int bpw;
  90. unsigned int hz;
  91. unsigned int div;
  92. bpw = t ? t->bits_per_word : spi->bits_per_word;
  93. hz = t ? t->speed_hz : spi->max_speed_hz;
  94. if (bpw != 8) {
  95. dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
  96. return -EINVAL;
  97. }
  98. div = clk_get_rate(hw->clk) / hz;
  99. /* is clk = pclk / (2 * (pre+1)), or is it
  100. * clk = (pclk * 2) / ( pre + 1) */
  101. div /= 2;
  102. if (div > 0)
  103. div -= 1;
  104. if (div > 255)
  105. div = 255;
  106. dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", div, hz);
  107. writeb(div, hw->regs + S3C2410_SPPRE);
  108. spin_lock(&hw->bitbang.lock);
  109. if (!hw->bitbang.busy) {
  110. hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
  111. /* need to ndelay for 0.5 clocktick ? */
  112. }
  113. spin_unlock(&hw->bitbang.lock);
  114. return 0;
  115. }
  116. /* the spi->mode bits understood by this driver: */
  117. #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
  118. static int s3c24xx_spi_setup(struct spi_device *spi)
  119. {
  120. int ret;
  121. if (spi->mode & ~MODEBITS) {
  122. dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
  123. spi->mode & ~MODEBITS);
  124. return -EINVAL;
  125. }
  126. ret = s3c24xx_spi_setupxfer(spi, NULL);
  127. if (ret < 0) {
  128. dev_err(&spi->dev, "setupxfer returned %d\n", ret);
  129. return ret;
  130. }
  131. return 0;
  132. }
  133. static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
  134. {
  135. return hw->tx ? hw->tx[count] : 0;
  136. }
  137. static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
  138. {
  139. struct s3c24xx_spi *hw = to_hw(spi);
  140. dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
  141. t->tx_buf, t->rx_buf, t->len);
  142. hw->tx = t->tx_buf;
  143. hw->rx = t->rx_buf;
  144. hw->len = t->len;
  145. hw->count = 0;
  146. init_completion(&hw->done);
  147. /* send the first byte */
  148. writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
  149. wait_for_completion(&hw->done);
  150. return hw->count;
  151. }
  152. static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
  153. {
  154. struct s3c24xx_spi *hw = dev;
  155. unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
  156. unsigned int count = hw->count;
  157. if (spsta & S3C2410_SPSTA_DCOL) {
  158. dev_dbg(hw->dev, "data-collision\n");
  159. complete(&hw->done);
  160. goto irq_done;
  161. }
  162. if (!(spsta & S3C2410_SPSTA_READY)) {
  163. dev_dbg(hw->dev, "spi not ready for tx?\n");
  164. complete(&hw->done);
  165. goto irq_done;
  166. }
  167. hw->count++;
  168. if (hw->rx)
  169. hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
  170. count++;
  171. if (count < hw->len)
  172. writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
  173. else
  174. complete(&hw->done);
  175. irq_done:
  176. return IRQ_HANDLED;
  177. }
  178. static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
  179. {
  180. /* for the moment, permanently enable the clock */
  181. clk_enable(hw->clk);
  182. /* program defaults into the registers */
  183. writeb(0xff, hw->regs + S3C2410_SPPRE);
  184. writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
  185. writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
  186. if (hw->pdata) {
  187. if (hw->set_cs == s3c24xx_spi_gpiocs)
  188. gpio_direction_output(hw->pdata->pin_cs, 1);
  189. if (hw->pdata->gpio_setup)
  190. hw->pdata->gpio_setup(hw->pdata, 1);
  191. }
  192. }
  193. static int __init s3c24xx_spi_probe(struct platform_device *pdev)
  194. {
  195. struct s3c2410_spi_info *pdata;
  196. struct s3c24xx_spi *hw;
  197. struct spi_master *master;
  198. struct resource *res;
  199. int err = 0;
  200. master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
  201. if (master == NULL) {
  202. dev_err(&pdev->dev, "No memory for spi_master\n");
  203. err = -ENOMEM;
  204. goto err_nomem;
  205. }
  206. hw = spi_master_get_devdata(master);
  207. memset(hw, 0, sizeof(struct s3c24xx_spi));
  208. hw->master = spi_master_get(master);
  209. hw->pdata = pdata = pdev->dev.platform_data;
  210. hw->dev = &pdev->dev;
  211. if (pdata == NULL) {
  212. dev_err(&pdev->dev, "No platform data supplied\n");
  213. err = -ENOENT;
  214. goto err_no_pdata;
  215. }
  216. platform_set_drvdata(pdev, hw);
  217. init_completion(&hw->done);
  218. /* setup the master state. */
  219. master->num_chipselect = hw->pdata->num_cs;
  220. master->bus_num = pdata->bus_num;
  221. /* setup the state for the bitbang driver */
  222. hw->bitbang.master = hw->master;
  223. hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
  224. hw->bitbang.chipselect = s3c24xx_spi_chipsel;
  225. hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
  226. hw->bitbang.master->setup = s3c24xx_spi_setup;
  227. dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
  228. /* find and map our resources */
  229. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  230. if (res == NULL) {
  231. dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
  232. err = -ENOENT;
  233. goto err_no_iores;
  234. }
  235. hw->ioarea = request_mem_region(res->start, (res->end - res->start)+1,
  236. pdev->name);
  237. if (hw->ioarea == NULL) {
  238. dev_err(&pdev->dev, "Cannot reserve region\n");
  239. err = -ENXIO;
  240. goto err_no_iores;
  241. }
  242. hw->regs = ioremap(res->start, (res->end - res->start)+1);
  243. if (hw->regs == NULL) {
  244. dev_err(&pdev->dev, "Cannot map IO\n");
  245. err = -ENXIO;
  246. goto err_no_iomap;
  247. }
  248. hw->irq = platform_get_irq(pdev, 0);
  249. if (hw->irq < 0) {
  250. dev_err(&pdev->dev, "No IRQ specified\n");
  251. err = -ENOENT;
  252. goto err_no_irq;
  253. }
  254. err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
  255. if (err) {
  256. dev_err(&pdev->dev, "Cannot claim IRQ\n");
  257. goto err_no_irq;
  258. }
  259. hw->clk = clk_get(&pdev->dev, "spi");
  260. if (IS_ERR(hw->clk)) {
  261. dev_err(&pdev->dev, "No clock for device\n");
  262. err = PTR_ERR(hw->clk);
  263. goto err_no_clk;
  264. }
  265. /* setup any gpio we can */
  266. if (!pdata->set_cs) {
  267. if (pdata->pin_cs < 0) {
  268. dev_err(&pdev->dev, "No chipselect pin\n");
  269. goto err_register;
  270. }
  271. err = gpio_request(pdata->pin_cs, dev_name(&pdev->dev));
  272. if (err) {
  273. dev_err(&pdev->dev, "Failed to get gpio for cs\n");
  274. goto err_register;
  275. }
  276. hw->set_cs = s3c24xx_spi_gpiocs;
  277. gpio_direction_output(pdata->pin_cs, 1);
  278. } else
  279. hw->set_cs = pdata->set_cs;
  280. s3c24xx_spi_initialsetup(hw);
  281. /* register our spi controller */
  282. err = spi_bitbang_start(&hw->bitbang);
  283. if (err) {
  284. dev_err(&pdev->dev, "Failed to register SPI master\n");
  285. goto err_register;
  286. }
  287. return 0;
  288. err_register:
  289. if (hw->set_cs == s3c24xx_spi_gpiocs)
  290. gpio_free(pdata->pin_cs);
  291. clk_disable(hw->clk);
  292. clk_put(hw->clk);
  293. err_no_clk:
  294. free_irq(hw->irq, hw);
  295. err_no_irq:
  296. iounmap(hw->regs);
  297. err_no_iomap:
  298. release_resource(hw->ioarea);
  299. kfree(hw->ioarea);
  300. err_no_iores:
  301. err_no_pdata:
  302. spi_master_put(hw->master);;
  303. err_nomem:
  304. return err;
  305. }
  306. static int __exit s3c24xx_spi_remove(struct platform_device *dev)
  307. {
  308. struct s3c24xx_spi *hw = platform_get_drvdata(dev);
  309. platform_set_drvdata(dev, NULL);
  310. spi_unregister_master(hw->master);
  311. clk_disable(hw->clk);
  312. clk_put(hw->clk);
  313. free_irq(hw->irq, hw);
  314. iounmap(hw->regs);
  315. if (hw->set_cs == s3c24xx_spi_gpiocs)
  316. gpio_free(hw->pdata->pin_cs);
  317. release_resource(hw->ioarea);
  318. kfree(hw->ioarea);
  319. spi_master_put(hw->master);
  320. return 0;
  321. }
  322. #ifdef CONFIG_PM
  323. static int s3c24xx_spi_suspend(struct platform_device *pdev, pm_message_t msg)
  324. {
  325. struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
  326. if (hw->pdata && hw->pdata->gpio_setup)
  327. hw->pdata->gpio_setup(hw->pdata, 0);
  328. clk_disable(hw->clk);
  329. return 0;
  330. }
  331. static int s3c24xx_spi_resume(struct platform_device *pdev)
  332. {
  333. struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
  334. s3c24xx_spi_initialsetup(hw);
  335. return 0;
  336. }
  337. #else
  338. #define s3c24xx_spi_suspend NULL
  339. #define s3c24xx_spi_resume NULL
  340. #endif
  341. MODULE_ALIAS("platform:s3c2410-spi");
  342. static struct platform_driver s3c24xx_spi_driver = {
  343. .remove = __exit_p(s3c24xx_spi_remove),
  344. .suspend = s3c24xx_spi_suspend,
  345. .resume = s3c24xx_spi_resume,
  346. .driver = {
  347. .name = "s3c2410-spi",
  348. .owner = THIS_MODULE,
  349. },
  350. };
  351. static int __init s3c24xx_spi_init(void)
  352. {
  353. return platform_driver_probe(&s3c24xx_spi_driver, s3c24xx_spi_probe);
  354. }
  355. static void __exit s3c24xx_spi_exit(void)
  356. {
  357. platform_driver_unregister(&s3c24xx_spi_driver);
  358. }
  359. module_init(s3c24xx_spi_init);
  360. module_exit(s3c24xx_spi_exit);
  361. MODULE_DESCRIPTION("S3C24XX SPI Driver");
  362. MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
  363. MODULE_LICENSE("GPL");