smp.c 8.4 KB

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  1. /*
  2. * Intel SMP support routines.
  3. *
  4. * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
  5. * (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com>
  6. * (c) 2002,2003 Andi Kleen, SuSE Labs.
  7. *
  8. * i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com>
  9. *
  10. * This code is released under the GNU General Public License version 2 or
  11. * later.
  12. */
  13. #include <linux/init.h>
  14. #include <linux/mm.h>
  15. #include <linux/delay.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/export.h>
  18. #include <linux/kernel_stat.h>
  19. #include <linux/mc146818rtc.h>
  20. #include <linux/cache.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/cpu.h>
  23. #include <linux/gfp.h>
  24. #include <asm/mtrr.h>
  25. #include <asm/tlbflush.h>
  26. #include <asm/mmu_context.h>
  27. #include <asm/proto.h>
  28. #include <asm/apic.h>
  29. #include <asm/nmi.h>
  30. /*
  31. * Some notes on x86 processor bugs affecting SMP operation:
  32. *
  33. * Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
  34. * The Linux implications for SMP are handled as follows:
  35. *
  36. * Pentium III / [Xeon]
  37. * None of the E1AP-E3AP errata are visible to the user.
  38. *
  39. * E1AP. see PII A1AP
  40. * E2AP. see PII A2AP
  41. * E3AP. see PII A3AP
  42. *
  43. * Pentium II / [Xeon]
  44. * None of the A1AP-A3AP errata are visible to the user.
  45. *
  46. * A1AP. see PPro 1AP
  47. * A2AP. see PPro 2AP
  48. * A3AP. see PPro 7AP
  49. *
  50. * Pentium Pro
  51. * None of 1AP-9AP errata are visible to the normal user,
  52. * except occasional delivery of 'spurious interrupt' as trap #15.
  53. * This is very rare and a non-problem.
  54. *
  55. * 1AP. Linux maps APIC as non-cacheable
  56. * 2AP. worked around in hardware
  57. * 3AP. fixed in C0 and above steppings microcode update.
  58. * Linux does not use excessive STARTUP_IPIs.
  59. * 4AP. worked around in hardware
  60. * 5AP. symmetric IO mode (normal Linux operation) not affected.
  61. * 'noapic' mode has vector 0xf filled out properly.
  62. * 6AP. 'noapic' mode might be affected - fixed in later steppings
  63. * 7AP. We do not assume writes to the LVT deassering IRQs
  64. * 8AP. We do not enable low power mode (deep sleep) during MP bootup
  65. * 9AP. We do not use mixed mode
  66. *
  67. * Pentium
  68. * There is a marginal case where REP MOVS on 100MHz SMP
  69. * machines with B stepping processors can fail. XXX should provide
  70. * an L1cache=Writethrough or L1cache=off option.
  71. *
  72. * B stepping CPUs may hang. There are hardware work arounds
  73. * for this. We warn about it in case your board doesn't have the work
  74. * arounds. Basically that's so I can tell anyone with a B stepping
  75. * CPU and SMP problems "tough".
  76. *
  77. * Specific items [From Pentium Processor Specification Update]
  78. *
  79. * 1AP. Linux doesn't use remote read
  80. * 2AP. Linux doesn't trust APIC errors
  81. * 3AP. We work around this
  82. * 4AP. Linux never generated 3 interrupts of the same priority
  83. * to cause a lost local interrupt.
  84. * 5AP. Remote read is never used
  85. * 6AP. not affected - worked around in hardware
  86. * 7AP. not affected - worked around in hardware
  87. * 8AP. worked around in hardware - we get explicit CS errors if not
  88. * 9AP. only 'noapic' mode affected. Might generate spurious
  89. * interrupts, we log only the first one and count the
  90. * rest silently.
  91. * 10AP. not affected - worked around in hardware
  92. * 11AP. Linux reads the APIC between writes to avoid this, as per
  93. * the documentation. Make sure you preserve this as it affects
  94. * the C stepping chips too.
  95. * 12AP. not affected - worked around in hardware
  96. * 13AP. not affected - worked around in hardware
  97. * 14AP. we always deassert INIT during bootup
  98. * 15AP. not affected - worked around in hardware
  99. * 16AP. not affected - worked around in hardware
  100. * 17AP. not affected - worked around in hardware
  101. * 18AP. not affected - worked around in hardware
  102. * 19AP. not affected - worked around in BIOS
  103. *
  104. * If this sounds worrying believe me these bugs are either ___RARE___,
  105. * or are signal timing bugs worked around in hardware and there's
  106. * about nothing of note with C stepping upwards.
  107. */
  108. static atomic_t stopping_cpu = ATOMIC_INIT(-1);
  109. /*
  110. * this function sends a 'reschedule' IPI to another CPU.
  111. * it goes straight through and wastes no time serializing
  112. * anything. Worst case is that we lose a reschedule ...
  113. */
  114. static void native_smp_send_reschedule(int cpu)
  115. {
  116. if (unlikely(cpu_is_offline(cpu))) {
  117. WARN_ON(1);
  118. return;
  119. }
  120. apic->send_IPI_mask(cpumask_of(cpu), RESCHEDULE_VECTOR);
  121. }
  122. void native_send_call_func_single_ipi(int cpu)
  123. {
  124. apic->send_IPI_mask(cpumask_of(cpu), CALL_FUNCTION_SINGLE_VECTOR);
  125. }
  126. void native_send_call_func_ipi(const struct cpumask *mask)
  127. {
  128. cpumask_var_t allbutself;
  129. if (!alloc_cpumask_var(&allbutself, GFP_ATOMIC)) {
  130. apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
  131. return;
  132. }
  133. cpumask_copy(allbutself, cpu_online_mask);
  134. cpumask_clear_cpu(smp_processor_id(), allbutself);
  135. if (cpumask_equal(mask, allbutself) &&
  136. cpumask_equal(cpu_online_mask, cpu_callout_mask))
  137. apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR);
  138. else
  139. apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
  140. free_cpumask_var(allbutself);
  141. }
  142. static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs)
  143. {
  144. /* We are registered on stopping cpu too, avoid spurious NMI */
  145. if (raw_smp_processor_id() == atomic_read(&stopping_cpu))
  146. return NMI_HANDLED;
  147. stop_this_cpu(NULL);
  148. return NMI_HANDLED;
  149. }
  150. /*
  151. * this function calls the 'stop' function on all other CPUs in the system.
  152. */
  153. asmlinkage void smp_reboot_interrupt(void)
  154. {
  155. ack_APIC_irq();
  156. irq_enter();
  157. stop_this_cpu(NULL);
  158. irq_exit();
  159. }
  160. static void native_stop_other_cpus(int wait)
  161. {
  162. unsigned long flags;
  163. unsigned long timeout;
  164. if (reboot_force)
  165. return;
  166. /*
  167. * Use an own vector here because smp_call_function
  168. * does lots of things not suitable in a panic situation.
  169. */
  170. /*
  171. * We start by using the REBOOT_VECTOR irq.
  172. * The irq is treated as a sync point to allow critical
  173. * regions of code on other cpus to release their spin locks
  174. * and re-enable irqs. Jumping straight to an NMI might
  175. * accidentally cause deadlocks with further shutdown/panic
  176. * code. By syncing, we give the cpus up to one second to
  177. * finish their work before we force them off with the NMI.
  178. */
  179. if (num_online_cpus() > 1) {
  180. /* did someone beat us here? */
  181. if (atomic_cmpxchg(&stopping_cpu, -1, safe_smp_processor_id()) != -1)
  182. return;
  183. /* sync above data before sending IRQ */
  184. wmb();
  185. apic->send_IPI_allbutself(REBOOT_VECTOR);
  186. /*
  187. * Don't wait longer than a second if the caller
  188. * didn't ask us to wait.
  189. */
  190. timeout = USEC_PER_SEC;
  191. while (num_online_cpus() > 1 && (wait || timeout--))
  192. udelay(1);
  193. }
  194. /* if the REBOOT_VECTOR didn't work, try with the NMI */
  195. if ((num_online_cpus() > 1)) {
  196. if (register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback,
  197. NMI_FLAG_FIRST, "smp_stop"))
  198. /* Note: we ignore failures here */
  199. /* Hope the REBOOT_IRQ is good enough */
  200. goto finish;
  201. /* sync above data before sending IRQ */
  202. wmb();
  203. pr_emerg("Shutting down cpus with NMI\n");
  204. apic->send_IPI_allbutself(NMI_VECTOR);
  205. /*
  206. * Don't wait longer than a 10 ms if the caller
  207. * didn't ask us to wait.
  208. */
  209. timeout = USEC_PER_MSEC * 10;
  210. while (num_online_cpus() > 1 && (wait || timeout--))
  211. udelay(1);
  212. }
  213. finish:
  214. local_irq_save(flags);
  215. disable_local_APIC();
  216. local_irq_restore(flags);
  217. }
  218. static void native_smp_disable_nmi_ipi(void)
  219. {
  220. smp_ops.stop_other_cpus = native_irq_stop_other_cpus;
  221. }
  222. /*
  223. * Reschedule call back.
  224. */
  225. void smp_reschedule_interrupt(struct pt_regs *regs)
  226. {
  227. ack_APIC_irq();
  228. inc_irq_stat(irq_resched_count);
  229. scheduler_ipi();
  230. /*
  231. * KVM uses this interrupt to force a cpu out of guest mode
  232. */
  233. }
  234. void smp_call_function_interrupt(struct pt_regs *regs)
  235. {
  236. ack_APIC_irq();
  237. irq_enter();
  238. generic_smp_call_function_interrupt();
  239. inc_irq_stat(irq_call_count);
  240. irq_exit();
  241. }
  242. void smp_call_function_single_interrupt(struct pt_regs *regs)
  243. {
  244. ack_APIC_irq();
  245. irq_enter();
  246. generic_smp_call_function_single_interrupt();
  247. inc_irq_stat(irq_call_count);
  248. irq_exit();
  249. }
  250. static int __init nonmi_ipi_setup(char *str)
  251. {
  252. native_smp_disable_nmi_ipi();
  253. return 1;
  254. }
  255. __setup("nonmi_ipi", nonmi_ipi_setup);
  256. struct smp_ops smp_ops = {
  257. .smp_prepare_boot_cpu = native_smp_prepare_boot_cpu,
  258. .smp_prepare_cpus = native_smp_prepare_cpus,
  259. .smp_cpus_done = native_smp_cpus_done,
  260. .stop_other_cpus = native_stop_other_cpus,
  261. .smp_send_reschedule = native_smp_send_reschedule,
  262. .cpu_up = native_cpu_up,
  263. .cpu_die = native_cpu_die,
  264. .cpu_disable = native_cpu_disable,
  265. .play_dead = native_play_dead,
  266. .send_call_func_ipi = native_send_call_func_ipi,
  267. .send_call_func_single_ipi = native_send_call_func_single_ipi,
  268. };
  269. EXPORT_SYMBOL_GPL(smp_ops);