fault.c 4.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159
  1. /*
  2. * Low-level SPU handling
  3. *
  4. * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
  5. *
  6. * Author: Arnd Bergmann <arndb@de.ibm.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2, or (at your option)
  11. * any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/sched.h>
  23. #include <linux/mm.h>
  24. #include <linux/module.h>
  25. #include <asm/spu.h>
  26. #include <asm/spu_csa.h>
  27. #include "spufs.h"
  28. static void spufs_handle_dma_error(struct spu_context *ctx,
  29. unsigned long ea, int type)
  30. {
  31. if (ctx->flags & SPU_CREATE_EVENTS_ENABLED) {
  32. ctx->event_return |= type;
  33. wake_up_all(&ctx->stop_wq);
  34. } else {
  35. siginfo_t info;
  36. memset(&info, 0, sizeof(info));
  37. switch (type) {
  38. case SPE_EVENT_INVALID_DMA:
  39. info.si_signo = SIGBUS;
  40. info.si_code = BUS_OBJERR;
  41. break;
  42. case SPE_EVENT_SPE_DATA_STORAGE:
  43. info.si_signo = SIGBUS;
  44. info.si_addr = (void __user *)ea;
  45. info.si_code = BUS_ADRERR;
  46. break;
  47. case SPE_EVENT_DMA_ALIGNMENT:
  48. info.si_signo = SIGBUS;
  49. /* DAR isn't set for an alignment fault :( */
  50. info.si_code = BUS_ADRALN;
  51. break;
  52. case SPE_EVENT_SPE_ERROR:
  53. info.si_signo = SIGILL;
  54. info.si_addr = (void __user *)(unsigned long)
  55. ctx->ops->npc_read(ctx) - 4;
  56. info.si_code = ILL_ILLOPC;
  57. break;
  58. }
  59. if (info.si_signo)
  60. force_sig_info(info.si_signo, &info, current);
  61. }
  62. }
  63. void spufs_dma_callback(struct spu *spu, int type)
  64. {
  65. spufs_handle_dma_error(spu->ctx, spu->dar, type);
  66. }
  67. /*
  68. * bottom half handler for page faults, we can't do this from
  69. * interrupt context, since we might need to sleep.
  70. * we also need to give up the mutex so we can get scheduled
  71. * out while waiting for the backing store.
  72. *
  73. * TODO: try calling hash_page from the interrupt handler first
  74. * in order to speed up the easy case.
  75. */
  76. int spufs_handle_class1(struct spu_context *ctx)
  77. {
  78. u64 ea, dsisr, access;
  79. unsigned long flags;
  80. unsigned flt = 0;
  81. int ret;
  82. /*
  83. * dar and dsisr get passed from the registers
  84. * to the spu_context, to this function, but not
  85. * back to the spu if it gets scheduled again.
  86. *
  87. * if we don't handle the fault for a saved context
  88. * in time, we can still expect to get the same fault
  89. * the immediately after the context restore.
  90. */
  91. if (ctx->state == SPU_STATE_RUNNABLE) {
  92. ea = ctx->spu->dar;
  93. dsisr = ctx->spu->dsisr;
  94. ctx->spu->dar= ctx->spu->dsisr = 0;
  95. } else {
  96. ea = ctx->csa.priv1.mfc_dar_RW;
  97. dsisr = ctx->csa.priv1.mfc_dsisr_RW;
  98. ctx->csa.priv1.mfc_dar_RW = 0;
  99. ctx->csa.priv1.mfc_dsisr_RW = 0;
  100. }
  101. if (!(dsisr & (MFC_DSISR_PTE_NOT_FOUND | MFC_DSISR_ACCESS_DENIED)))
  102. return 0;
  103. spuctx_switch_state(ctx, SPU_UTIL_IOWAIT);
  104. pr_debug("ctx %p: ea %016lx, dsisr %016lx state %d\n", ctx, ea,
  105. dsisr, ctx->state);
  106. ctx->stats.hash_flt++;
  107. if (ctx->state == SPU_STATE_RUNNABLE)
  108. ctx->spu->stats.hash_flt++;
  109. /* we must not hold the lock when entering spu_handle_mm_fault */
  110. spu_release(ctx);
  111. access = (_PAGE_PRESENT | _PAGE_USER);
  112. access |= (dsisr & MFC_DSISR_ACCESS_PUT) ? _PAGE_RW : 0UL;
  113. local_irq_save(flags);
  114. ret = hash_page(ea, access, 0x300);
  115. local_irq_restore(flags);
  116. /* hashing failed, so try the actual fault handler */
  117. if (ret)
  118. ret = spu_handle_mm_fault(current->mm, ea, dsisr, &flt);
  119. spu_acquire(ctx);
  120. /*
  121. * If we handled the fault successfully and are in runnable
  122. * state, restart the DMA.
  123. * In case of unhandled error report the problem to user space.
  124. */
  125. if (!ret) {
  126. if (flt & VM_FAULT_MAJOR)
  127. ctx->stats.maj_flt++;
  128. else
  129. ctx->stats.min_flt++;
  130. if (ctx->state == SPU_STATE_RUNNABLE) {
  131. if (flt & VM_FAULT_MAJOR)
  132. ctx->spu->stats.maj_flt++;
  133. else
  134. ctx->spu->stats.min_flt++;
  135. }
  136. if (ctx->spu)
  137. ctx->ops->restart_dma(ctx);
  138. } else
  139. spufs_handle_dma_error(ctx, ea, SPE_EVENT_SPE_DATA_STORAGE);
  140. spuctx_switch_state(ctx, SPU_UTIL_SYSTEM);
  141. return ret;
  142. }