au1000_eth.c 34 KB

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  1. /*
  2. *
  3. * Alchemy Au1x00 ethernet driver
  4. *
  5. * Copyright 2001-2003, 2006 MontaVista Software Inc.
  6. * Copyright 2002 TimeSys Corp.
  7. * Added ethtool/mii-tool support,
  8. * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
  9. * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
  10. * or riemer@riemer-nt.de: fixed the link beat detection with
  11. * ioctls (SIOCGMIIPHY)
  12. * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
  13. * converted to use linux-2.6.x's PHY framework
  14. *
  15. * Author: MontaVista Software, Inc.
  16. * ppopov@mvista.com or source@mvista.com
  17. *
  18. * ########################################################################
  19. *
  20. * This program is free software; you can distribute it and/or modify it
  21. * under the terms of the GNU General Public License (Version 2) as
  22. * published by the Free Software Foundation.
  23. *
  24. * This program is distributed in the hope it will be useful, but WITHOUT
  25. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  26. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  27. * for more details.
  28. *
  29. * You should have received a copy of the GNU General Public License along
  30. * with this program; if not, write to the Free Software Foundation, Inc.,
  31. * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  32. *
  33. * ########################################################################
  34. *
  35. *
  36. */
  37. #include <linux/capability.h>
  38. #include <linux/dma-mapping.h>
  39. #include <linux/module.h>
  40. #include <linux/kernel.h>
  41. #include <linux/string.h>
  42. #include <linux/timer.h>
  43. #include <linux/errno.h>
  44. #include <linux/in.h>
  45. #include <linux/ioport.h>
  46. #include <linux/bitops.h>
  47. #include <linux/slab.h>
  48. #include <linux/interrupt.h>
  49. #include <linux/init.h>
  50. #include <linux/netdevice.h>
  51. #include <linux/etherdevice.h>
  52. #include <linux/ethtool.h>
  53. #include <linux/mii.h>
  54. #include <linux/skbuff.h>
  55. #include <linux/delay.h>
  56. #include <linux/crc32.h>
  57. #include <linux/phy.h>
  58. #include <linux/platform_device.h>
  59. #include <asm/cpu.h>
  60. #include <asm/mipsregs.h>
  61. #include <asm/irq.h>
  62. #include <asm/io.h>
  63. #include <asm/processor.h>
  64. #include <au1000.h>
  65. #include <au1xxx_eth.h>
  66. #include <prom.h>
  67. #include "au1000_eth.h"
  68. #ifdef AU1000_ETH_DEBUG
  69. static int au1000_debug = 5;
  70. #else
  71. static int au1000_debug = 3;
  72. #endif
  73. #define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
  74. NETIF_MSG_PROBE | \
  75. NETIF_MSG_LINK)
  76. #define DRV_NAME "au1000_eth"
  77. #define DRV_VERSION "1.6"
  78. #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
  79. #define DRV_DESC "Au1xxx on-chip Ethernet driver"
  80. MODULE_AUTHOR(DRV_AUTHOR);
  81. MODULE_DESCRIPTION(DRV_DESC);
  82. MODULE_LICENSE("GPL");
  83. MODULE_VERSION(DRV_VERSION);
  84. /*
  85. * Theory of operation
  86. *
  87. * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
  88. * There are four receive and four transmit descriptors. These
  89. * descriptors are not in memory; rather, they are just a set of
  90. * hardware registers.
  91. *
  92. * Since the Au1000 has a coherent data cache, the receive and
  93. * transmit buffers are allocated from the KSEG0 segment. The
  94. * hardware registers, however, are still mapped at KSEG1 to
  95. * make sure there's no out-of-order writes, and that all writes
  96. * complete immediately.
  97. */
  98. /* These addresses are only used if yamon doesn't tell us what
  99. * the mac address is, and the mac address is not passed on the
  100. * command line.
  101. */
  102. static unsigned char au1000_mac_addr[6] __devinitdata = {
  103. 0x00, 0x50, 0xc2, 0x0c, 0x30, 0x00
  104. };
  105. struct au1000_private *au_macs[NUM_ETH_INTERFACES];
  106. /*
  107. * board-specific configurations
  108. *
  109. * PHY detection algorithm
  110. *
  111. * If phy_static_config is undefined, the PHY setup is
  112. * autodetected:
  113. *
  114. * mii_probe() first searches the current MAC's MII bus for a PHY,
  115. * selecting the first (or last, if phy_search_highest_addr is
  116. * defined) PHY address not already claimed by another netdev.
  117. *
  118. * If nothing was found that way when searching for the 2nd ethernet
  119. * controller's PHY and phy1_search_mac0 is defined, then
  120. * the first MII bus is searched as well for an unclaimed PHY; this is
  121. * needed in case of a dual-PHY accessible only through the MAC0's MII
  122. * bus.
  123. *
  124. * Finally, if no PHY is found, then the corresponding ethernet
  125. * controller is not registered to the network subsystem.
  126. */
  127. /* autodetection defaults: phy1_search_mac0 */
  128. /* static PHY setup
  129. *
  130. * most boards PHY setup should be detectable properly with the
  131. * autodetection algorithm in mii_probe(), but in some cases (e.g. if
  132. * you have a switch attached, or want to use the PHY's interrupt
  133. * notification capabilities) you can provide a static PHY
  134. * configuration here
  135. *
  136. * IRQs may only be set, if a PHY address was configured
  137. * If a PHY address is given, also a bus id is required to be set
  138. *
  139. * ps: make sure the used irqs are configured properly in the board
  140. * specific irq-map
  141. */
  142. static void au1000_enable_mac(struct net_device *dev, int force_reset)
  143. {
  144. unsigned long flags;
  145. struct au1000_private *aup = netdev_priv(dev);
  146. spin_lock_irqsave(&aup->lock, flags);
  147. if(force_reset || (!aup->mac_enabled)) {
  148. *aup->enable = MAC_EN_CLOCK_ENABLE;
  149. au_sync_delay(2);
  150. *aup->enable = (MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
  151. | MAC_EN_CLOCK_ENABLE);
  152. au_sync_delay(2);
  153. aup->mac_enabled = 1;
  154. }
  155. spin_unlock_irqrestore(&aup->lock, flags);
  156. }
  157. /*
  158. * MII operations
  159. */
  160. static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
  161. {
  162. struct au1000_private *aup = netdev_priv(dev);
  163. volatile u32 *const mii_control_reg = &aup->mac->mii_control;
  164. volatile u32 *const mii_data_reg = &aup->mac->mii_data;
  165. u32 timedout = 20;
  166. u32 mii_control;
  167. while (*mii_control_reg & MAC_MII_BUSY) {
  168. mdelay(1);
  169. if (--timedout == 0) {
  170. printk(KERN_ERR "%s: read_MII busy timeout!!\n",
  171. dev->name);
  172. return -1;
  173. }
  174. }
  175. mii_control = MAC_SET_MII_SELECT_REG(reg) |
  176. MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
  177. *mii_control_reg = mii_control;
  178. timedout = 20;
  179. while (*mii_control_reg & MAC_MII_BUSY) {
  180. mdelay(1);
  181. if (--timedout == 0) {
  182. printk(KERN_ERR "%s: mdio_read busy timeout!!\n",
  183. dev->name);
  184. return -1;
  185. }
  186. }
  187. return (int)*mii_data_reg;
  188. }
  189. static void au1000_mdio_write(struct net_device *dev, int phy_addr,
  190. int reg, u16 value)
  191. {
  192. struct au1000_private *aup = netdev_priv(dev);
  193. volatile u32 *const mii_control_reg = &aup->mac->mii_control;
  194. volatile u32 *const mii_data_reg = &aup->mac->mii_data;
  195. u32 timedout = 20;
  196. u32 mii_control;
  197. while (*mii_control_reg & MAC_MII_BUSY) {
  198. mdelay(1);
  199. if (--timedout == 0) {
  200. printk(KERN_ERR "%s: mdio_write busy timeout!!\n",
  201. dev->name);
  202. return;
  203. }
  204. }
  205. mii_control = MAC_SET_MII_SELECT_REG(reg) |
  206. MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
  207. *mii_data_reg = value;
  208. *mii_control_reg = mii_control;
  209. }
  210. static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
  211. {
  212. /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does
  213. * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus) */
  214. struct net_device *const dev = bus->priv;
  215. au1000_enable_mac(dev, 0); /* make sure the MAC associated with this
  216. * mii_bus is enabled */
  217. return au1000_mdio_read(dev, phy_addr, regnum);
  218. }
  219. static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
  220. u16 value)
  221. {
  222. struct net_device *const dev = bus->priv;
  223. au1000_enable_mac(dev, 0); /* make sure the MAC associated with this
  224. * mii_bus is enabled */
  225. au1000_mdio_write(dev, phy_addr, regnum, value);
  226. return 0;
  227. }
  228. static int au1000_mdiobus_reset(struct mii_bus *bus)
  229. {
  230. struct net_device *const dev = bus->priv;
  231. au1000_enable_mac(dev, 0); /* make sure the MAC associated with this
  232. * mii_bus is enabled */
  233. return 0;
  234. }
  235. static void au1000_hard_stop(struct net_device *dev)
  236. {
  237. struct au1000_private *aup = netdev_priv(dev);
  238. if (au1000_debug > 4)
  239. printk(KERN_INFO "%s: hard stop\n", dev->name);
  240. aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
  241. au_sync_delay(10);
  242. }
  243. static void au1000_enable_rx_tx(struct net_device *dev)
  244. {
  245. struct au1000_private *aup = netdev_priv(dev);
  246. if (au1000_debug > 4)
  247. printk(KERN_INFO "%s: enable_rx_tx\n", dev->name);
  248. aup->mac->control |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
  249. au_sync_delay(10);
  250. }
  251. static void
  252. au1000_adjust_link(struct net_device *dev)
  253. {
  254. struct au1000_private *aup = netdev_priv(dev);
  255. struct phy_device *phydev = aup->phy_dev;
  256. unsigned long flags;
  257. int status_change = 0;
  258. BUG_ON(!aup->phy_dev);
  259. spin_lock_irqsave(&aup->lock, flags);
  260. if (phydev->link && (aup->old_speed != phydev->speed)) {
  261. /* speed changed */
  262. switch (phydev->speed) {
  263. case SPEED_10:
  264. case SPEED_100:
  265. break;
  266. default:
  267. printk(KERN_WARNING
  268. "%s: Speed (%d) is not 10/100 ???\n",
  269. dev->name, phydev->speed);
  270. break;
  271. }
  272. aup->old_speed = phydev->speed;
  273. status_change = 1;
  274. }
  275. if (phydev->link && (aup->old_duplex != phydev->duplex)) {
  276. /* duplex mode changed */
  277. /* switching duplex mode requires to disable rx and tx! */
  278. au1000_hard_stop(dev);
  279. if (DUPLEX_FULL == phydev->duplex)
  280. aup->mac->control = ((aup->mac->control
  281. | MAC_FULL_DUPLEX)
  282. & ~MAC_DISABLE_RX_OWN);
  283. else
  284. aup->mac->control = ((aup->mac->control
  285. & ~MAC_FULL_DUPLEX)
  286. | MAC_DISABLE_RX_OWN);
  287. au_sync_delay(1);
  288. au1000_enable_rx_tx(dev);
  289. aup->old_duplex = phydev->duplex;
  290. status_change = 1;
  291. }
  292. if (phydev->link != aup->old_link) {
  293. /* link state changed */
  294. if (!phydev->link) {
  295. /* link went down */
  296. aup->old_speed = 0;
  297. aup->old_duplex = -1;
  298. }
  299. aup->old_link = phydev->link;
  300. status_change = 1;
  301. }
  302. spin_unlock_irqrestore(&aup->lock, flags);
  303. if (status_change) {
  304. if (phydev->link)
  305. printk(KERN_INFO "%s: link up (%d/%s)\n",
  306. dev->name, phydev->speed,
  307. DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
  308. else
  309. printk(KERN_INFO "%s: link down\n", dev->name);
  310. }
  311. }
  312. static int au1000_mii_probe (struct net_device *dev)
  313. {
  314. struct au1000_private *const aup = netdev_priv(dev);
  315. struct phy_device *phydev = NULL;
  316. if (aup->phy_static_config) {
  317. BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
  318. if (aup->phy_addr)
  319. phydev = aup->mii_bus->phy_map[aup->phy_addr];
  320. else
  321. printk (KERN_INFO DRV_NAME ":%s: using PHY-less setup\n",
  322. dev->name);
  323. return 0;
  324. } else {
  325. int phy_addr;
  326. /* find the first (lowest address) PHY on the current MAC's MII bus */
  327. for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
  328. if (aup->mii_bus->phy_map[phy_addr]) {
  329. phydev = aup->mii_bus->phy_map[phy_addr];
  330. if (!aup->phy_search_highest_addr)
  331. break; /* break out with first one found */
  332. }
  333. if (aup->phy1_search_mac0) {
  334. /* try harder to find a PHY */
  335. if (!phydev && (aup->mac_id == 1)) {
  336. /* no PHY found, maybe we have a dual PHY? */
  337. printk (KERN_INFO DRV_NAME ": no PHY found on MAC1, "
  338. "let's see if it's attached to MAC0...\n");
  339. /* find the first (lowest address) non-attached PHY on
  340. * the MAC0 MII bus */
  341. for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
  342. struct phy_device *const tmp_phydev =
  343. aup->mii_bus->phy_map[phy_addr];
  344. if (aup->mac_id == 1)
  345. break;
  346. if (!tmp_phydev)
  347. continue; /* no PHY here... */
  348. if (tmp_phydev->attached_dev)
  349. continue; /* already claimed by MAC0 */
  350. phydev = tmp_phydev;
  351. break; /* found it */
  352. }
  353. }
  354. }
  355. }
  356. if (!phydev) {
  357. printk (KERN_ERR DRV_NAME ":%s: no PHY found\n", dev->name);
  358. return -1;
  359. }
  360. /* now we are supposed to have a proper phydev, to attach to... */
  361. BUG_ON(phydev->attached_dev);
  362. phydev = phy_connect(dev, dev_name(&phydev->dev), &au1000_adjust_link,
  363. 0, PHY_INTERFACE_MODE_MII);
  364. if (IS_ERR(phydev)) {
  365. printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
  366. return PTR_ERR(phydev);
  367. }
  368. /* mask with MAC supported features */
  369. phydev->supported &= (SUPPORTED_10baseT_Half
  370. | SUPPORTED_10baseT_Full
  371. | SUPPORTED_100baseT_Half
  372. | SUPPORTED_100baseT_Full
  373. | SUPPORTED_Autoneg
  374. /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
  375. | SUPPORTED_MII
  376. | SUPPORTED_TP);
  377. phydev->advertising = phydev->supported;
  378. aup->old_link = 0;
  379. aup->old_speed = 0;
  380. aup->old_duplex = -1;
  381. aup->phy_dev = phydev;
  382. printk(KERN_INFO "%s: attached PHY driver [%s] "
  383. "(mii_bus:phy_addr=%s, irq=%d)\n", dev->name,
  384. phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
  385. return 0;
  386. }
  387. /*
  388. * Buffer allocation/deallocation routines. The buffer descriptor returned
  389. * has the virtual and dma address of a buffer suitable for
  390. * both, receive and transmit operations.
  391. */
  392. static db_dest_t *au1000_GetFreeDB(struct au1000_private *aup)
  393. {
  394. db_dest_t *pDB;
  395. pDB = aup->pDBfree;
  396. if (pDB) {
  397. aup->pDBfree = pDB->pnext;
  398. }
  399. return pDB;
  400. }
  401. void au1000_ReleaseDB(struct au1000_private *aup, db_dest_t *pDB)
  402. {
  403. db_dest_t *pDBfree = aup->pDBfree;
  404. if (pDBfree)
  405. pDBfree->pnext = pDB;
  406. aup->pDBfree = pDB;
  407. }
  408. static void au1000_reset_mac_unlocked(struct net_device *dev)
  409. {
  410. struct au1000_private *const aup = netdev_priv(dev);
  411. int i;
  412. au1000_hard_stop(dev);
  413. *aup->enable = MAC_EN_CLOCK_ENABLE;
  414. au_sync_delay(2);
  415. *aup->enable = 0;
  416. au_sync_delay(2);
  417. aup->tx_full = 0;
  418. for (i = 0; i < NUM_RX_DMA; i++) {
  419. /* reset control bits */
  420. aup->rx_dma_ring[i]->buff_stat &= ~0xf;
  421. }
  422. for (i = 0; i < NUM_TX_DMA; i++) {
  423. /* reset control bits */
  424. aup->tx_dma_ring[i]->buff_stat &= ~0xf;
  425. }
  426. aup->mac_enabled = 0;
  427. }
  428. static void au1000_reset_mac(struct net_device *dev)
  429. {
  430. struct au1000_private *const aup = netdev_priv(dev);
  431. unsigned long flags;
  432. if (au1000_debug > 4)
  433. printk(KERN_INFO "%s: reset mac, aup %x\n",
  434. dev->name, (unsigned)aup);
  435. spin_lock_irqsave(&aup->lock, flags);
  436. au1000_reset_mac_unlocked (dev);
  437. spin_unlock_irqrestore(&aup->lock, flags);
  438. }
  439. /*
  440. * Setup the receive and transmit "rings". These pointers are the addresses
  441. * of the rx and tx MAC DMA registers so they are fixed by the hardware --
  442. * these are not descriptors sitting in memory.
  443. */
  444. static void
  445. au1000_setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base)
  446. {
  447. int i;
  448. for (i = 0; i < NUM_RX_DMA; i++) {
  449. aup->rx_dma_ring[i] =
  450. (volatile rx_dma_t *) (rx_base + sizeof(rx_dma_t)*i);
  451. }
  452. for (i = 0; i < NUM_TX_DMA; i++) {
  453. aup->tx_dma_ring[i] =
  454. (volatile tx_dma_t *) (tx_base + sizeof(tx_dma_t)*i);
  455. }
  456. }
  457. /*
  458. * ethtool operations
  459. */
  460. static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  461. {
  462. struct au1000_private *aup = netdev_priv(dev);
  463. if (aup->phy_dev)
  464. return phy_ethtool_gset(aup->phy_dev, cmd);
  465. return -EINVAL;
  466. }
  467. static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  468. {
  469. struct au1000_private *aup = netdev_priv(dev);
  470. if (!capable(CAP_NET_ADMIN))
  471. return -EPERM;
  472. if (aup->phy_dev)
  473. return phy_ethtool_sset(aup->phy_dev, cmd);
  474. return -EINVAL;
  475. }
  476. static void
  477. au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  478. {
  479. struct au1000_private *aup = netdev_priv(dev);
  480. strcpy(info->driver, DRV_NAME);
  481. strcpy(info->version, DRV_VERSION);
  482. info->fw_version[0] = '\0';
  483. sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id);
  484. info->regdump_len = 0;
  485. }
  486. static void au1000_set_msglevel(struct net_device *dev, u32 value)
  487. {
  488. struct au1000_private *aup = netdev_priv(dev);
  489. aup->msg_enable = value;
  490. }
  491. static u32 au1000_get_msglevel(struct net_device *dev)
  492. {
  493. struct au1000_private *aup = netdev_priv(dev);
  494. return aup->msg_enable;
  495. }
  496. static const struct ethtool_ops au1000_ethtool_ops = {
  497. .get_settings = au1000_get_settings,
  498. .set_settings = au1000_set_settings,
  499. .get_drvinfo = au1000_get_drvinfo,
  500. .get_link = ethtool_op_get_link,
  501. .get_msglevel = au1000_get_msglevel,
  502. .set_msglevel = au1000_set_msglevel,
  503. };
  504. /*
  505. * Initialize the interface.
  506. *
  507. * When the device powers up, the clocks are disabled and the
  508. * mac is in reset state. When the interface is closed, we
  509. * do the same -- reset the device and disable the clocks to
  510. * conserve power. Thus, whenever au1000_init() is called,
  511. * the device should already be in reset state.
  512. */
  513. static int au1000_init(struct net_device *dev)
  514. {
  515. struct au1000_private *aup = netdev_priv(dev);
  516. unsigned long flags;
  517. int i;
  518. u32 control;
  519. if (au1000_debug > 4)
  520. printk("%s: au1000_init\n", dev->name);
  521. /* bring the device out of reset */
  522. au1000_enable_mac(dev, 1);
  523. spin_lock_irqsave(&aup->lock, flags);
  524. aup->mac->control = 0;
  525. aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
  526. aup->tx_tail = aup->tx_head;
  527. aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
  528. aup->mac->mac_addr_high = dev->dev_addr[5]<<8 | dev->dev_addr[4];
  529. aup->mac->mac_addr_low = dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
  530. dev->dev_addr[1]<<8 | dev->dev_addr[0];
  531. for (i = 0; i < NUM_RX_DMA; i++) {
  532. aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
  533. }
  534. au_sync();
  535. control = MAC_RX_ENABLE | MAC_TX_ENABLE;
  536. #ifndef CONFIG_CPU_LITTLE_ENDIAN
  537. control |= MAC_BIG_ENDIAN;
  538. #endif
  539. if (aup->phy_dev) {
  540. if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
  541. control |= MAC_FULL_DUPLEX;
  542. else
  543. control |= MAC_DISABLE_RX_OWN;
  544. } else { /* PHY-less op, assume full-duplex */
  545. control |= MAC_FULL_DUPLEX;
  546. }
  547. aup->mac->control = control;
  548. aup->mac->vlan1_tag = 0x8100; /* activate vlan support */
  549. au_sync();
  550. spin_unlock_irqrestore(&aup->lock, flags);
  551. return 0;
  552. }
  553. static inline void au1000_update_rx_stats(struct net_device *dev, u32 status)
  554. {
  555. struct net_device_stats *ps = &dev->stats;
  556. ps->rx_packets++;
  557. if (status & RX_MCAST_FRAME)
  558. ps->multicast++;
  559. if (status & RX_ERROR) {
  560. ps->rx_errors++;
  561. if (status & RX_MISSED_FRAME)
  562. ps->rx_missed_errors++;
  563. if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR))
  564. ps->rx_length_errors++;
  565. if (status & RX_CRC_ERROR)
  566. ps->rx_crc_errors++;
  567. if (status & RX_COLL)
  568. ps->collisions++;
  569. } else
  570. ps->rx_bytes += status & RX_FRAME_LEN_MASK;
  571. }
  572. /*
  573. * Au1000 receive routine.
  574. */
  575. static int au1000_rx(struct net_device *dev)
  576. {
  577. struct au1000_private *aup = netdev_priv(dev);
  578. struct sk_buff *skb;
  579. volatile rx_dma_t *prxd;
  580. u32 buff_stat, status;
  581. db_dest_t *pDB;
  582. u32 frmlen;
  583. if (au1000_debug > 5)
  584. printk("%s: au1000_rx head %d\n", dev->name, aup->rx_head);
  585. prxd = aup->rx_dma_ring[aup->rx_head];
  586. buff_stat = prxd->buff_stat;
  587. while (buff_stat & RX_T_DONE) {
  588. status = prxd->status;
  589. pDB = aup->rx_db_inuse[aup->rx_head];
  590. au1000_update_rx_stats(dev, status);
  591. if (!(status & RX_ERROR)) {
  592. /* good frame */
  593. frmlen = (status & RX_FRAME_LEN_MASK);
  594. frmlen -= 4; /* Remove FCS */
  595. skb = dev_alloc_skb(frmlen + 2);
  596. if (skb == NULL) {
  597. printk(KERN_ERR
  598. "%s: Memory squeeze, dropping packet.\n",
  599. dev->name);
  600. dev->stats.rx_dropped++;
  601. continue;
  602. }
  603. skb_reserve(skb, 2); /* 16 byte IP header align */
  604. skb_copy_to_linear_data(skb,
  605. (unsigned char *)pDB->vaddr, frmlen);
  606. skb_put(skb, frmlen);
  607. skb->protocol = eth_type_trans(skb, dev);
  608. netif_rx(skb); /* pass the packet to upper layers */
  609. } else {
  610. if (au1000_debug > 4) {
  611. if (status & RX_MISSED_FRAME)
  612. printk("rx miss\n");
  613. if (status & RX_WDOG_TIMER)
  614. printk("rx wdog\n");
  615. if (status & RX_RUNT)
  616. printk("rx runt\n");
  617. if (status & RX_OVERLEN)
  618. printk("rx overlen\n");
  619. if (status & RX_COLL)
  620. printk("rx coll\n");
  621. if (status & RX_MII_ERROR)
  622. printk("rx mii error\n");
  623. if (status & RX_CRC_ERROR)
  624. printk("rx crc error\n");
  625. if (status & RX_LEN_ERROR)
  626. printk("rx len error\n");
  627. if (status & RX_U_CNTRL_FRAME)
  628. printk("rx u control frame\n");
  629. }
  630. }
  631. prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
  632. aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
  633. au_sync();
  634. /* next descriptor */
  635. prxd = aup->rx_dma_ring[aup->rx_head];
  636. buff_stat = prxd->buff_stat;
  637. }
  638. return 0;
  639. }
  640. static void au1000_update_tx_stats(struct net_device *dev, u32 status)
  641. {
  642. struct au1000_private *aup = netdev_priv(dev);
  643. struct net_device_stats *ps = &dev->stats;
  644. if (status & TX_FRAME_ABORTED) {
  645. if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
  646. if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
  647. /* any other tx errors are only valid
  648. * in half duplex mode */
  649. ps->tx_errors++;
  650. ps->tx_aborted_errors++;
  651. }
  652. } else {
  653. ps->tx_errors++;
  654. ps->tx_aborted_errors++;
  655. if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
  656. ps->tx_carrier_errors++;
  657. }
  658. }
  659. }
  660. /*
  661. * Called from the interrupt service routine to acknowledge
  662. * the TX DONE bits. This is a must if the irq is setup as
  663. * edge triggered.
  664. */
  665. static void au1000_tx_ack(struct net_device *dev)
  666. {
  667. struct au1000_private *aup = netdev_priv(dev);
  668. volatile tx_dma_t *ptxd;
  669. ptxd = aup->tx_dma_ring[aup->tx_tail];
  670. while (ptxd->buff_stat & TX_T_DONE) {
  671. au1000_update_tx_stats(dev, ptxd->status);
  672. ptxd->buff_stat &= ~TX_T_DONE;
  673. ptxd->len = 0;
  674. au_sync();
  675. aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
  676. ptxd = aup->tx_dma_ring[aup->tx_tail];
  677. if (aup->tx_full) {
  678. aup->tx_full = 0;
  679. netif_wake_queue(dev);
  680. }
  681. }
  682. }
  683. /*
  684. * Au1000 interrupt service routine.
  685. */
  686. static irqreturn_t au1000_interrupt(int irq, void *dev_id)
  687. {
  688. struct net_device *dev = dev_id;
  689. /* Handle RX interrupts first to minimize chance of overrun */
  690. au1000_rx(dev);
  691. au1000_tx_ack(dev);
  692. return IRQ_RETVAL(1);
  693. }
  694. static int au1000_open(struct net_device *dev)
  695. {
  696. int retval;
  697. struct au1000_private *aup = netdev_priv(dev);
  698. if (au1000_debug > 4)
  699. printk("%s: open: dev=%p\n", dev->name, dev);
  700. retval = request_irq(dev->irq, au1000_interrupt, 0,
  701. dev->name, dev);
  702. if (retval) {
  703. printk(KERN_ERR "%s: unable to get IRQ %d\n",
  704. dev->name, dev->irq);
  705. return retval;
  706. }
  707. retval = au1000_init(dev);
  708. if (retval) {
  709. printk(KERN_ERR "%s: error in au1000_init\n", dev->name);
  710. free_irq(dev->irq, dev);
  711. return retval;
  712. }
  713. if (aup->phy_dev) {
  714. /* cause the PHY state machine to schedule a link state check */
  715. aup->phy_dev->state = PHY_CHANGELINK;
  716. phy_start(aup->phy_dev);
  717. }
  718. netif_start_queue(dev);
  719. if (au1000_debug > 4)
  720. printk("%s: open: Initialization done.\n", dev->name);
  721. return 0;
  722. }
  723. static int au1000_close(struct net_device *dev)
  724. {
  725. unsigned long flags;
  726. struct au1000_private *const aup = netdev_priv(dev);
  727. if (au1000_debug > 4)
  728. printk("%s: close: dev=%p\n", dev->name, dev);
  729. if (aup->phy_dev)
  730. phy_stop(aup->phy_dev);
  731. spin_lock_irqsave(&aup->lock, flags);
  732. au1000_reset_mac_unlocked (dev);
  733. /* stop the device */
  734. netif_stop_queue(dev);
  735. /* disable the interrupt */
  736. free_irq(dev->irq, dev);
  737. spin_unlock_irqrestore(&aup->lock, flags);
  738. return 0;
  739. }
  740. /*
  741. * Au1000 transmit routine.
  742. */
  743. static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
  744. {
  745. struct au1000_private *aup = netdev_priv(dev);
  746. struct net_device_stats *ps = &dev->stats;
  747. volatile tx_dma_t *ptxd;
  748. u32 buff_stat;
  749. db_dest_t *pDB;
  750. int i;
  751. if (au1000_debug > 5)
  752. printk("%s: tx: aup %x len=%d, data=%p, head %d\n",
  753. dev->name, (unsigned)aup, skb->len,
  754. skb->data, aup->tx_head);
  755. ptxd = aup->tx_dma_ring[aup->tx_head];
  756. buff_stat = ptxd->buff_stat;
  757. if (buff_stat & TX_DMA_ENABLE) {
  758. /* We've wrapped around and the transmitter is still busy */
  759. netif_stop_queue(dev);
  760. aup->tx_full = 1;
  761. return NETDEV_TX_BUSY;
  762. } else if (buff_stat & TX_T_DONE) {
  763. au1000_update_tx_stats(dev, ptxd->status);
  764. ptxd->len = 0;
  765. }
  766. if (aup->tx_full) {
  767. aup->tx_full = 0;
  768. netif_wake_queue(dev);
  769. }
  770. pDB = aup->tx_db_inuse[aup->tx_head];
  771. skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
  772. if (skb->len < ETH_ZLEN) {
  773. for (i = skb->len; i < ETH_ZLEN; i++) {
  774. ((char *)pDB->vaddr)[i] = 0;
  775. }
  776. ptxd->len = ETH_ZLEN;
  777. } else
  778. ptxd->len = skb->len;
  779. ps->tx_packets++;
  780. ps->tx_bytes += ptxd->len;
  781. ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
  782. au_sync();
  783. dev_kfree_skb(skb);
  784. aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
  785. dev->trans_start = jiffies;
  786. return NETDEV_TX_OK;
  787. }
  788. /*
  789. * The Tx ring has been full longer than the watchdog timeout
  790. * value. The transmitter must be hung?
  791. */
  792. static void au1000_tx_timeout(struct net_device *dev)
  793. {
  794. printk(KERN_ERR "%s: au1000_tx_timeout: dev=%p\n", dev->name, dev);
  795. au1000_reset_mac(dev);
  796. au1000_init(dev);
  797. dev->trans_start = jiffies;
  798. netif_wake_queue(dev);
  799. }
  800. static void au1000_multicast_list(struct net_device *dev)
  801. {
  802. struct au1000_private *aup = netdev_priv(dev);
  803. if (au1000_debug > 4)
  804. printk("%s: au1000_multicast_list: flags=%x\n", dev->name, dev->flags);
  805. if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
  806. aup->mac->control |= MAC_PROMISCUOUS;
  807. } else if ((dev->flags & IFF_ALLMULTI) ||
  808. netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) {
  809. aup->mac->control |= MAC_PASS_ALL_MULTI;
  810. aup->mac->control &= ~MAC_PROMISCUOUS;
  811. printk(KERN_INFO "%s: Pass all multicast\n", dev->name);
  812. } else {
  813. struct netdev_hw_addr *ha;
  814. u32 mc_filter[2]; /* Multicast hash filter */
  815. mc_filter[1] = mc_filter[0] = 0;
  816. netdev_for_each_mc_addr(ha, dev)
  817. set_bit(ether_crc(ETH_ALEN, ha->addr)>>26,
  818. (long *)mc_filter);
  819. aup->mac->multi_hash_high = mc_filter[1];
  820. aup->mac->multi_hash_low = mc_filter[0];
  821. aup->mac->control &= ~MAC_PROMISCUOUS;
  822. aup->mac->control |= MAC_HASH_MODE;
  823. }
  824. }
  825. static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  826. {
  827. struct au1000_private *aup = netdev_priv(dev);
  828. if (!netif_running(dev))
  829. return -EINVAL;
  830. if (!aup->phy_dev)
  831. return -EINVAL; /* PHY not controllable */
  832. return phy_mii_ioctl(aup->phy_dev, if_mii(rq), cmd);
  833. }
  834. static const struct net_device_ops au1000_netdev_ops = {
  835. .ndo_open = au1000_open,
  836. .ndo_stop = au1000_close,
  837. .ndo_start_xmit = au1000_tx,
  838. .ndo_set_multicast_list = au1000_multicast_list,
  839. .ndo_do_ioctl = au1000_ioctl,
  840. .ndo_tx_timeout = au1000_tx_timeout,
  841. .ndo_set_mac_address = eth_mac_addr,
  842. .ndo_validate_addr = eth_validate_addr,
  843. .ndo_change_mtu = eth_change_mtu,
  844. };
  845. static int __devinit au1000_probe(struct platform_device *pdev)
  846. {
  847. static unsigned version_printed;
  848. struct au1000_private *aup = NULL;
  849. struct au1000_eth_platform_data *pd;
  850. struct net_device *dev = NULL;
  851. db_dest_t *pDB, *pDBfree;
  852. int irq, i, err = 0;
  853. struct resource *base, *macen;
  854. char ethaddr[6];
  855. base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  856. if (!base) {
  857. printk(KERN_ERR DRV_NAME ": failed to retrieve base register\n");
  858. err = -ENODEV;
  859. goto out;
  860. }
  861. macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  862. if (!macen) {
  863. printk(KERN_ERR DRV_NAME ": failed to retrieve MAC Enable register\n");
  864. err = -ENODEV;
  865. goto out;
  866. }
  867. irq = platform_get_irq(pdev, 0);
  868. if (irq < 0) {
  869. printk(KERN_ERR DRV_NAME ": failed to retrieve IRQ\n");
  870. err = -ENODEV;
  871. goto out;
  872. }
  873. if (!request_mem_region(base->start, resource_size(base), pdev->name)) {
  874. printk(KERN_ERR DRV_NAME ": failed to request memory region for base registers\n");
  875. err = -ENXIO;
  876. goto out;
  877. }
  878. if (!request_mem_region(macen->start, resource_size(macen), pdev->name)) {
  879. printk(KERN_ERR DRV_NAME ": failed to request memory region for MAC enable register\n");
  880. err = -ENXIO;
  881. goto err_request;
  882. }
  883. dev = alloc_etherdev(sizeof(struct au1000_private));
  884. if (!dev) {
  885. printk(KERN_ERR "%s: alloc_etherdev failed\n", DRV_NAME);
  886. err = -ENOMEM;
  887. goto err_alloc;
  888. }
  889. SET_NETDEV_DEV(dev, &pdev->dev);
  890. platform_set_drvdata(pdev, dev);
  891. aup = netdev_priv(dev);
  892. spin_lock_init(&aup->lock);
  893. aup->msg_enable = (au1000_debug < 4 ? AU1000_DEF_MSG_ENABLE : au1000_debug);
  894. /* Allocate the data buffers */
  895. /* Snooping works fine with eth on all au1xxx */
  896. aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
  897. (NUM_TX_BUFFS + NUM_RX_BUFFS),
  898. &aup->dma_addr, 0);
  899. if (!aup->vaddr) {
  900. printk(KERN_ERR DRV_NAME ": failed to allocate data buffers\n");
  901. err = -ENOMEM;
  902. goto err_vaddr;
  903. }
  904. /* aup->mac is the base address of the MAC's registers */
  905. aup->mac = (volatile mac_reg_t *)ioremap_nocache(base->start, resource_size(base));
  906. if (!aup->mac) {
  907. printk(KERN_ERR DRV_NAME ": failed to ioremap MAC registers\n");
  908. err = -ENXIO;
  909. goto err_remap1;
  910. }
  911. /* Setup some variables for quick register address access */
  912. aup->enable = (volatile u32 *)ioremap_nocache(macen->start, resource_size(macen));
  913. if (!aup->enable) {
  914. printk(KERN_ERR DRV_NAME ": failed to ioremap MAC enable register\n");
  915. err = -ENXIO;
  916. goto err_remap2;
  917. }
  918. aup->mac_id = pdev->id;
  919. if (pdev->id == 0) {
  920. if (prom_get_ethernet_addr(ethaddr) == 0)
  921. memcpy(au1000_mac_addr, ethaddr, sizeof(au1000_mac_addr));
  922. else {
  923. printk(KERN_INFO "%s: No MAC address found\n",
  924. dev->name);
  925. /* Use the hard coded MAC addresses */
  926. }
  927. au1000_setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
  928. } else if (pdev->id == 1)
  929. au1000_setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
  930. /*
  931. * Assign to the Ethernet ports two consecutive MAC addresses
  932. * to match those that are printed on their stickers
  933. */
  934. memcpy(dev->dev_addr, au1000_mac_addr, sizeof(au1000_mac_addr));
  935. dev->dev_addr[5] += pdev->id;
  936. *aup->enable = 0;
  937. aup->mac_enabled = 0;
  938. pd = pdev->dev.platform_data;
  939. if (!pd) {
  940. printk(KERN_INFO DRV_NAME ": no platform_data passed, PHY search on MAC0\n");
  941. aup->phy1_search_mac0 = 1;
  942. } else {
  943. aup->phy_static_config = pd->phy_static_config;
  944. aup->phy_search_highest_addr = pd->phy_search_highest_addr;
  945. aup->phy1_search_mac0 = pd->phy1_search_mac0;
  946. aup->phy_addr = pd->phy_addr;
  947. aup->phy_busid = pd->phy_busid;
  948. aup->phy_irq = pd->phy_irq;
  949. }
  950. if (aup->phy_busid && aup->phy_busid > 0) {
  951. printk(KERN_ERR DRV_NAME ": MAC0-associated PHY attached 2nd MACs MII"
  952. "bus not supported yet\n");
  953. err = -ENODEV;
  954. goto err_mdiobus_alloc;
  955. }
  956. aup->mii_bus = mdiobus_alloc();
  957. if (aup->mii_bus == NULL) {
  958. printk(KERN_ERR DRV_NAME ": failed to allocate mdiobus structure\n");
  959. err = -ENOMEM;
  960. goto err_mdiobus_alloc;
  961. }
  962. aup->mii_bus->priv = dev;
  963. aup->mii_bus->read = au1000_mdiobus_read;
  964. aup->mii_bus->write = au1000_mdiobus_write;
  965. aup->mii_bus->reset = au1000_mdiobus_reset;
  966. aup->mii_bus->name = "au1000_eth_mii";
  967. snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%x", aup->mac_id);
  968. aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
  969. if (aup->mii_bus->irq == NULL)
  970. goto err_out;
  971. for (i = 0; i < PHY_MAX_ADDR; ++i)
  972. aup->mii_bus->irq[i] = PHY_POLL;
  973. /* if known, set corresponding PHY IRQs */
  974. if (aup->phy_static_config)
  975. if (aup->phy_irq && aup->phy_busid == aup->mac_id)
  976. aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq;
  977. err = mdiobus_register(aup->mii_bus);
  978. if (err) {
  979. printk(KERN_ERR DRV_NAME " failed to register MDIO bus\n");
  980. goto err_mdiobus_reg;
  981. }
  982. if (au1000_mii_probe(dev) != 0)
  983. goto err_out;
  984. pDBfree = NULL;
  985. /* setup the data buffer descriptors and attach a buffer to each one */
  986. pDB = aup->db;
  987. for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
  988. pDB->pnext = pDBfree;
  989. pDBfree = pDB;
  990. pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
  991. pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
  992. pDB++;
  993. }
  994. aup->pDBfree = pDBfree;
  995. for (i = 0; i < NUM_RX_DMA; i++) {
  996. pDB = au1000_GetFreeDB(aup);
  997. if (!pDB) {
  998. goto err_out;
  999. }
  1000. aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
  1001. aup->rx_db_inuse[i] = pDB;
  1002. }
  1003. for (i = 0; i < NUM_TX_DMA; i++) {
  1004. pDB = au1000_GetFreeDB(aup);
  1005. if (!pDB) {
  1006. goto err_out;
  1007. }
  1008. aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
  1009. aup->tx_dma_ring[i]->len = 0;
  1010. aup->tx_db_inuse[i] = pDB;
  1011. }
  1012. dev->base_addr = base->start;
  1013. dev->irq = irq;
  1014. dev->netdev_ops = &au1000_netdev_ops;
  1015. SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
  1016. dev->watchdog_timeo = ETH_TX_TIMEOUT;
  1017. /*
  1018. * The boot code uses the ethernet controller, so reset it to start
  1019. * fresh. au1000_init() expects that the device is in reset state.
  1020. */
  1021. au1000_reset_mac(dev);
  1022. err = register_netdev(dev);
  1023. if (err) {
  1024. printk(KERN_ERR DRV_NAME "%s: Cannot register net device, aborting.\n",
  1025. dev->name);
  1026. goto err_out;
  1027. }
  1028. printk("%s: Au1xx0 Ethernet found at 0x%lx, irq %d\n",
  1029. dev->name, (unsigned long)base->start, irq);
  1030. if (version_printed++ == 0)
  1031. printk("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR);
  1032. return 0;
  1033. err_out:
  1034. if (aup->mii_bus != NULL)
  1035. mdiobus_unregister(aup->mii_bus);
  1036. /* here we should have a valid dev plus aup-> register addresses
  1037. * so we can reset the mac properly.*/
  1038. au1000_reset_mac(dev);
  1039. for (i = 0; i < NUM_RX_DMA; i++) {
  1040. if (aup->rx_db_inuse[i])
  1041. au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
  1042. }
  1043. for (i = 0; i < NUM_TX_DMA; i++) {
  1044. if (aup->tx_db_inuse[i])
  1045. au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
  1046. }
  1047. err_mdiobus_reg:
  1048. mdiobus_free(aup->mii_bus);
  1049. err_mdiobus_alloc:
  1050. iounmap(aup->enable);
  1051. err_remap2:
  1052. iounmap(aup->mac);
  1053. err_remap1:
  1054. dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
  1055. (void *)aup->vaddr, aup->dma_addr);
  1056. err_vaddr:
  1057. free_netdev(dev);
  1058. err_alloc:
  1059. release_mem_region(macen->start, resource_size(macen));
  1060. err_request:
  1061. release_mem_region(base->start, resource_size(base));
  1062. out:
  1063. return err;
  1064. }
  1065. static int __devexit au1000_remove(struct platform_device *pdev)
  1066. {
  1067. struct net_device *dev = platform_get_drvdata(pdev);
  1068. struct au1000_private *aup = netdev_priv(dev);
  1069. int i;
  1070. struct resource *base, *macen;
  1071. platform_set_drvdata(pdev, NULL);
  1072. unregister_netdev(dev);
  1073. mdiobus_unregister(aup->mii_bus);
  1074. mdiobus_free(aup->mii_bus);
  1075. for (i = 0; i < NUM_RX_DMA; i++)
  1076. if (aup->rx_db_inuse[i])
  1077. au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
  1078. for (i = 0; i < NUM_TX_DMA; i++)
  1079. if (aup->tx_db_inuse[i])
  1080. au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
  1081. dma_free_noncoherent(NULL, MAX_BUF_SIZE *
  1082. (NUM_TX_BUFFS + NUM_RX_BUFFS),
  1083. (void *)aup->vaddr, aup->dma_addr);
  1084. iounmap(aup->mac);
  1085. iounmap(aup->enable);
  1086. base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1087. release_mem_region(base->start, resource_size(base));
  1088. macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1089. release_mem_region(macen->start, resource_size(macen));
  1090. free_netdev(dev);
  1091. return 0;
  1092. }
  1093. static struct platform_driver au1000_eth_driver = {
  1094. .probe = au1000_probe,
  1095. .remove = __devexit_p(au1000_remove),
  1096. .driver = {
  1097. .name = "au1000-eth",
  1098. .owner = THIS_MODULE,
  1099. },
  1100. };
  1101. MODULE_ALIAS("platform:au1000-eth");
  1102. static int __init au1000_init_module(void)
  1103. {
  1104. return platform_driver_register(&au1000_eth_driver);
  1105. }
  1106. static void __exit au1000_exit_module(void)
  1107. {
  1108. platform_driver_unregister(&au1000_eth_driver);
  1109. }
  1110. module_init(au1000_init_module);
  1111. module_exit(au1000_exit_module);