sdhci.c 32 KB

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  1. /*
  2. * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
  3. *
  4. * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. /*
  11. * Note that PIO transfer is rather crappy atm. The buffer full/empty
  12. * interrupts aren't reliable so we currently transfer the entire buffer
  13. * directly. Patches to solve the problem are welcome.
  14. */
  15. #include <linux/delay.h>
  16. #include <linux/highmem.h>
  17. #include <linux/pci.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/mmc/host.h>
  20. #include <linux/mmc/protocol.h>
  21. #include <asm/scatterlist.h>
  22. #include "sdhci.h"
  23. #define DRIVER_NAME "sdhci"
  24. #define DRIVER_VERSION "0.11"
  25. #define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
  26. #define DBG(f, x...) \
  27. pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  28. static const struct pci_device_id pci_ids[] __devinitdata = {
  29. /* handle any SD host controller */
  30. {PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)},
  31. { /* end: all zeroes */ },
  32. };
  33. MODULE_DEVICE_TABLE(pci, pci_ids);
  34. static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
  35. static void sdhci_finish_data(struct sdhci_host *);
  36. static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  37. static void sdhci_finish_command(struct sdhci_host *);
  38. static void sdhci_dumpregs(struct sdhci_host *host)
  39. {
  40. printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
  41. printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
  42. readl(host->ioaddr + SDHCI_DMA_ADDRESS),
  43. readw(host->ioaddr + SDHCI_HOST_VERSION));
  44. printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
  45. readw(host->ioaddr + SDHCI_BLOCK_SIZE),
  46. readw(host->ioaddr + SDHCI_BLOCK_COUNT));
  47. printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  48. readl(host->ioaddr + SDHCI_ARGUMENT),
  49. readw(host->ioaddr + SDHCI_TRANSFER_MODE));
  50. printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
  51. readl(host->ioaddr + SDHCI_PRESENT_STATE),
  52. readb(host->ioaddr + SDHCI_HOST_CONTROL));
  53. printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
  54. readb(host->ioaddr + SDHCI_POWER_CONTROL),
  55. readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
  56. printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
  57. readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
  58. readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
  59. printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
  60. readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
  61. readl(host->ioaddr + SDHCI_INT_STATUS));
  62. printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  63. readl(host->ioaddr + SDHCI_INT_ENABLE),
  64. readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
  65. printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  66. readw(host->ioaddr + SDHCI_ACMD12_ERR),
  67. readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
  68. printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
  69. readl(host->ioaddr + SDHCI_CAPABILITIES),
  70. readl(host->ioaddr + SDHCI_MAX_CURRENT));
  71. printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  72. }
  73. /*****************************************************************************\
  74. * *
  75. * Low level functions *
  76. * *
  77. \*****************************************************************************/
  78. static void sdhci_reset(struct sdhci_host *host, u8 mask)
  79. {
  80. writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
  81. if (mask & SDHCI_RESET_ALL) {
  82. host->clock = 0;
  83. mdelay(50);
  84. }
  85. }
  86. static void sdhci_init(struct sdhci_host *host)
  87. {
  88. u32 intmask;
  89. sdhci_reset(host, SDHCI_RESET_ALL);
  90. intmask = ~(SDHCI_INT_CARD_INT | SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
  91. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  92. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  93. /* This is unknown magic. */
  94. writeb(0xE, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
  95. }
  96. static void sdhci_activate_led(struct sdhci_host *host)
  97. {
  98. u8 ctrl;
  99. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  100. ctrl |= SDHCI_CTRL_LED;
  101. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  102. }
  103. static void sdhci_deactivate_led(struct sdhci_host *host)
  104. {
  105. u8 ctrl;
  106. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  107. ctrl &= ~SDHCI_CTRL_LED;
  108. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  109. }
  110. /*****************************************************************************\
  111. * *
  112. * Core functions *
  113. * *
  114. \*****************************************************************************/
  115. static inline char* sdhci_kmap_sg(struct sdhci_host* host)
  116. {
  117. host->mapped_sg = kmap_atomic(host->cur_sg->page, KM_BIO_SRC_IRQ);
  118. return host->mapped_sg + host->cur_sg->offset;
  119. }
  120. static inline void sdhci_kunmap_sg(struct sdhci_host* host)
  121. {
  122. kunmap_atomic(host->mapped_sg, KM_BIO_SRC_IRQ);
  123. }
  124. static inline int sdhci_next_sg(struct sdhci_host* host)
  125. {
  126. /*
  127. * Skip to next SG entry.
  128. */
  129. host->cur_sg++;
  130. host->num_sg--;
  131. /*
  132. * Any entries left?
  133. */
  134. if (host->num_sg > 0) {
  135. host->offset = 0;
  136. host->remain = host->cur_sg->length;
  137. }
  138. return host->num_sg;
  139. }
  140. static void sdhci_transfer_pio(struct sdhci_host *host)
  141. {
  142. char *buffer;
  143. u32 mask;
  144. int bytes, size;
  145. unsigned long max_jiffies;
  146. BUG_ON(!host->data);
  147. if (host->num_sg == 0)
  148. return;
  149. bytes = 0;
  150. if (host->data->flags & MMC_DATA_READ)
  151. mask = SDHCI_DATA_AVAILABLE;
  152. else
  153. mask = SDHCI_SPACE_AVAILABLE;
  154. buffer = sdhci_kmap_sg(host) + host->offset;
  155. /* Transfer shouldn't take more than 5 s */
  156. max_jiffies = jiffies + HZ * 5;
  157. while (host->size > 0) {
  158. if (time_after(jiffies, max_jiffies)) {
  159. printk(KERN_ERR "%s: PIO transfer stalled. "
  160. "Please report this to "
  161. BUGMAIL ".\n", mmc_hostname(host->mmc));
  162. sdhci_dumpregs(host);
  163. sdhci_kunmap_sg(host);
  164. host->data->error = MMC_ERR_FAILED;
  165. sdhci_finish_data(host);
  166. return;
  167. }
  168. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask))
  169. continue;
  170. size = min(host->size, host->remain);
  171. if (size >= 4) {
  172. if (host->data->flags & MMC_DATA_READ)
  173. *(u32*)buffer = readl(host->ioaddr + SDHCI_BUFFER);
  174. else
  175. writel(*(u32*)buffer, host->ioaddr + SDHCI_BUFFER);
  176. size = 4;
  177. } else if (size >= 2) {
  178. if (host->data->flags & MMC_DATA_READ)
  179. *(u16*)buffer = readw(host->ioaddr + SDHCI_BUFFER);
  180. else
  181. writew(*(u16*)buffer, host->ioaddr + SDHCI_BUFFER);
  182. size = 2;
  183. } else {
  184. if (host->data->flags & MMC_DATA_READ)
  185. *(u8*)buffer = readb(host->ioaddr + SDHCI_BUFFER);
  186. else
  187. writeb(*(u8*)buffer, host->ioaddr + SDHCI_BUFFER);
  188. size = 1;
  189. }
  190. buffer += size;
  191. host->offset += size;
  192. host->remain -= size;
  193. bytes += size;
  194. host->size -= size;
  195. if (host->remain == 0) {
  196. sdhci_kunmap_sg(host);
  197. if (sdhci_next_sg(host) == 0) {
  198. DBG("PIO transfer: %d bytes\n", bytes);
  199. return;
  200. }
  201. buffer = sdhci_kmap_sg(host);
  202. }
  203. }
  204. sdhci_kunmap_sg(host);
  205. DBG("PIO transfer: %d bytes\n", bytes);
  206. }
  207. static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
  208. {
  209. u16 mode;
  210. WARN_ON(host->data);
  211. if (data == NULL) {
  212. writew(0, host->ioaddr + SDHCI_TRANSFER_MODE);
  213. return;
  214. }
  215. DBG("blksz %04x blks %04x flags %08x\n",
  216. data->blksz, data->blocks, data->flags);
  217. DBG("tsac %d ms nsac %d clk\n",
  218. data->timeout_ns / 1000000, data->timeout_clks);
  219. mode = SDHCI_TRNS_BLK_CNT_EN;
  220. if (data->blocks > 1)
  221. mode |= SDHCI_TRNS_MULTI;
  222. if (data->flags & MMC_DATA_READ)
  223. mode |= SDHCI_TRNS_READ;
  224. if (host->flags & SDHCI_USE_DMA)
  225. mode |= SDHCI_TRNS_DMA;
  226. writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
  227. writew(data->blksz, host->ioaddr + SDHCI_BLOCK_SIZE);
  228. writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
  229. if (host->flags & SDHCI_USE_DMA) {
  230. int count;
  231. count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
  232. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  233. BUG_ON(count != 1);
  234. writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
  235. } else {
  236. host->size = data->blksz * data->blocks;
  237. host->cur_sg = data->sg;
  238. host->num_sg = data->sg_len;
  239. host->offset = 0;
  240. host->remain = host->cur_sg->length;
  241. }
  242. }
  243. static void sdhci_finish_data(struct sdhci_host *host)
  244. {
  245. struct mmc_data *data;
  246. u32 intmask;
  247. u16 blocks;
  248. BUG_ON(!host->data);
  249. data = host->data;
  250. host->data = NULL;
  251. if (host->flags & SDHCI_USE_DMA) {
  252. pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
  253. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  254. } else {
  255. intmask = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
  256. intmask &= ~(SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
  257. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  258. intmask = readl(host->ioaddr + SDHCI_INT_ENABLE);
  259. intmask &= ~(SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
  260. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  261. }
  262. /*
  263. * Controller doesn't count down when in single block mode.
  264. */
  265. if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
  266. blocks = 0;
  267. else
  268. blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
  269. data->bytes_xfered = data->blksz * (data->blocks - blocks);
  270. if ((data->error == MMC_ERR_NONE) && blocks) {
  271. printk(KERN_ERR "%s: Controller signalled completion even "
  272. "though there were blocks left. Please report this "
  273. "to " BUGMAIL ".\n", mmc_hostname(host->mmc));
  274. data->error = MMC_ERR_FAILED;
  275. }
  276. if (host->size != 0) {
  277. printk(KERN_ERR "%s: %d bytes were left untransferred. "
  278. "Please report this to " BUGMAIL ".\n",
  279. mmc_hostname(host->mmc), host->size);
  280. data->error = MMC_ERR_FAILED;
  281. }
  282. DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
  283. if (data->stop) {
  284. /*
  285. * The controller needs a reset of internal state machines
  286. * upon error conditions.
  287. */
  288. if (data->error != MMC_ERR_NONE) {
  289. sdhci_reset(host, SDHCI_RESET_CMD);
  290. sdhci_reset(host, SDHCI_RESET_DATA);
  291. }
  292. sdhci_send_command(host, data->stop);
  293. } else
  294. tasklet_schedule(&host->finish_tasklet);
  295. }
  296. static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
  297. {
  298. int flags;
  299. unsigned long timeout;
  300. WARN_ON(host->cmd);
  301. DBG("Sending cmd (%x)\n", cmd->opcode);
  302. /* Wait max 10 ms */
  303. timeout = 10;
  304. while (readl(host->ioaddr + SDHCI_PRESENT_STATE) &
  305. (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
  306. if (timeout == 0) {
  307. printk(KERN_ERR "%s: Controller never released "
  308. "inhibit bits. Please report this to "
  309. BUGMAIL ".\n", mmc_hostname(host->mmc));
  310. sdhci_dumpregs(host);
  311. cmd->error = MMC_ERR_FAILED;
  312. tasklet_schedule(&host->finish_tasklet);
  313. return;
  314. }
  315. timeout--;
  316. mdelay(1);
  317. }
  318. mod_timer(&host->timer, jiffies + 10 * HZ);
  319. host->cmd = cmd;
  320. sdhci_prepare_data(host, cmd->data);
  321. writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
  322. if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
  323. printk(KERN_ERR "%s: Unsupported response type! "
  324. "Please report this to " BUGMAIL ".\n",
  325. mmc_hostname(host->mmc));
  326. cmd->error = MMC_ERR_INVALID;
  327. tasklet_schedule(&host->finish_tasklet);
  328. return;
  329. }
  330. if (!(cmd->flags & MMC_RSP_PRESENT))
  331. flags = SDHCI_CMD_RESP_NONE;
  332. else if (cmd->flags & MMC_RSP_136)
  333. flags = SDHCI_CMD_RESP_LONG;
  334. else if (cmd->flags & MMC_RSP_BUSY)
  335. flags = SDHCI_CMD_RESP_SHORT_BUSY;
  336. else
  337. flags = SDHCI_CMD_RESP_SHORT;
  338. if (cmd->flags & MMC_RSP_CRC)
  339. flags |= SDHCI_CMD_CRC;
  340. if (cmd->flags & MMC_RSP_OPCODE)
  341. flags |= SDHCI_CMD_INDEX;
  342. if (cmd->data)
  343. flags |= SDHCI_CMD_DATA;
  344. writel(SDHCI_MAKE_CMD(cmd->opcode, flags),
  345. host->ioaddr + SDHCI_COMMAND);
  346. }
  347. static void sdhci_finish_command(struct sdhci_host *host)
  348. {
  349. int i;
  350. BUG_ON(host->cmd == NULL);
  351. if (host->cmd->flags & MMC_RSP_PRESENT) {
  352. if (host->cmd->flags & MMC_RSP_136) {
  353. /* CRC is stripped so we need to do some shifting. */
  354. for (i = 0;i < 4;i++) {
  355. host->cmd->resp[i] = readl(host->ioaddr +
  356. SDHCI_RESPONSE + (3-i)*4) << 8;
  357. if (i != 3)
  358. host->cmd->resp[i] |=
  359. readb(host->ioaddr +
  360. SDHCI_RESPONSE + (3-i)*4-1);
  361. }
  362. } else {
  363. host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
  364. }
  365. }
  366. host->cmd->error = MMC_ERR_NONE;
  367. DBG("Ending cmd (%x)\n", host->cmd->opcode);
  368. if (host->cmd->data) {
  369. u32 intmask;
  370. host->data = host->cmd->data;
  371. if (!(host->flags & SDHCI_USE_DMA)) {
  372. /*
  373. * Don't enable the interrupts until now to make sure we
  374. * get stable handling of the FIFO.
  375. */
  376. intmask = readl(host->ioaddr + SDHCI_INT_ENABLE);
  377. intmask |= SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL;
  378. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  379. intmask = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
  380. intmask |= SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL;
  381. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  382. /*
  383. * The buffer interrupts are to unreliable so we
  384. * start the transfer immediatly.
  385. */
  386. sdhci_transfer_pio(host);
  387. }
  388. } else
  389. tasklet_schedule(&host->finish_tasklet);
  390. host->cmd = NULL;
  391. }
  392. static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
  393. {
  394. int div;
  395. u16 clk;
  396. unsigned long timeout;
  397. if (clock == host->clock)
  398. return;
  399. writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
  400. if (clock == 0)
  401. goto out;
  402. for (div = 1;div < 256;div *= 2) {
  403. if ((host->max_clk / div) <= clock)
  404. break;
  405. }
  406. div >>= 1;
  407. clk = div << SDHCI_DIVIDER_SHIFT;
  408. clk |= SDHCI_CLOCK_INT_EN;
  409. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  410. /* Wait max 10 ms */
  411. timeout = 10;
  412. while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
  413. & SDHCI_CLOCK_INT_STABLE)) {
  414. if (timeout == 0) {
  415. printk(KERN_ERR "%s: Internal clock never stabilised. "
  416. "Please report this to " BUGMAIL ".\n",
  417. mmc_hostname(host->mmc));
  418. sdhci_dumpregs(host);
  419. return;
  420. }
  421. timeout--;
  422. mdelay(1);
  423. }
  424. clk |= SDHCI_CLOCK_CARD_EN;
  425. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  426. out:
  427. host->clock = clock;
  428. }
  429. static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
  430. {
  431. u8 pwr;
  432. if (host->power == power)
  433. return;
  434. writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
  435. if (power == (unsigned short)-1)
  436. goto out;
  437. pwr = SDHCI_POWER_ON;
  438. switch (power) {
  439. case MMC_VDD_170:
  440. case MMC_VDD_180:
  441. case MMC_VDD_190:
  442. pwr |= SDHCI_POWER_180;
  443. break;
  444. case MMC_VDD_290:
  445. case MMC_VDD_300:
  446. case MMC_VDD_310:
  447. pwr |= SDHCI_POWER_300;
  448. break;
  449. case MMC_VDD_320:
  450. case MMC_VDD_330:
  451. case MMC_VDD_340:
  452. pwr |= SDHCI_POWER_330;
  453. break;
  454. default:
  455. BUG();
  456. }
  457. writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
  458. out:
  459. host->power = power;
  460. }
  461. /*****************************************************************************\
  462. * *
  463. * MMC callbacks *
  464. * *
  465. \*****************************************************************************/
  466. static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  467. {
  468. struct sdhci_host *host;
  469. unsigned long flags;
  470. host = mmc_priv(mmc);
  471. spin_lock_irqsave(&host->lock, flags);
  472. WARN_ON(host->mrq != NULL);
  473. sdhci_activate_led(host);
  474. host->mrq = mrq;
  475. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  476. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  477. tasklet_schedule(&host->finish_tasklet);
  478. } else
  479. sdhci_send_command(host, mrq->cmd);
  480. spin_unlock_irqrestore(&host->lock, flags);
  481. }
  482. static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  483. {
  484. struct sdhci_host *host;
  485. unsigned long flags;
  486. u8 ctrl;
  487. host = mmc_priv(mmc);
  488. spin_lock_irqsave(&host->lock, flags);
  489. /*
  490. * Reset the chip on each power off.
  491. * Should clear out any weird states.
  492. */
  493. if (ios->power_mode == MMC_POWER_OFF) {
  494. writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  495. spin_unlock_irqrestore(&host->lock, flags);
  496. sdhci_init(host);
  497. spin_lock_irqsave(&host->lock, flags);
  498. }
  499. sdhci_set_clock(host, ios->clock);
  500. if (ios->power_mode == MMC_POWER_OFF)
  501. sdhci_set_power(host, -1);
  502. else
  503. sdhci_set_power(host, ios->vdd);
  504. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  505. if (ios->bus_width == MMC_BUS_WIDTH_4)
  506. ctrl |= SDHCI_CTRL_4BITBUS;
  507. else
  508. ctrl &= ~SDHCI_CTRL_4BITBUS;
  509. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  510. spin_unlock_irqrestore(&host->lock, flags);
  511. }
  512. static int sdhci_get_ro(struct mmc_host *mmc)
  513. {
  514. struct sdhci_host *host;
  515. unsigned long flags;
  516. int present;
  517. host = mmc_priv(mmc);
  518. spin_lock_irqsave(&host->lock, flags);
  519. present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
  520. spin_unlock_irqrestore(&host->lock, flags);
  521. return !(present & SDHCI_WRITE_PROTECT);
  522. }
  523. static struct mmc_host_ops sdhci_ops = {
  524. .request = sdhci_request,
  525. .set_ios = sdhci_set_ios,
  526. .get_ro = sdhci_get_ro,
  527. };
  528. /*****************************************************************************\
  529. * *
  530. * Tasklets *
  531. * *
  532. \*****************************************************************************/
  533. static void sdhci_tasklet_card(unsigned long param)
  534. {
  535. struct sdhci_host *host;
  536. unsigned long flags;
  537. host = (struct sdhci_host*)param;
  538. spin_lock_irqsave(&host->lock, flags);
  539. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  540. if (host->mrq) {
  541. printk(KERN_ERR "%s: Card removed during transfer!\n",
  542. mmc_hostname(host->mmc));
  543. printk(KERN_ERR "%s: Resetting controller.\n",
  544. mmc_hostname(host->mmc));
  545. sdhci_reset(host, SDHCI_RESET_CMD);
  546. sdhci_reset(host, SDHCI_RESET_DATA);
  547. host->mrq->cmd->error = MMC_ERR_FAILED;
  548. tasklet_schedule(&host->finish_tasklet);
  549. }
  550. }
  551. spin_unlock_irqrestore(&host->lock, flags);
  552. mmc_detect_change(host->mmc, msecs_to_jiffies(500));
  553. }
  554. static void sdhci_tasklet_finish(unsigned long param)
  555. {
  556. struct sdhci_host *host;
  557. unsigned long flags;
  558. struct mmc_request *mrq;
  559. host = (struct sdhci_host*)param;
  560. spin_lock_irqsave(&host->lock, flags);
  561. del_timer(&host->timer);
  562. mrq = host->mrq;
  563. DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
  564. /*
  565. * The controller needs a reset of internal state machines
  566. * upon error conditions.
  567. */
  568. if ((mrq->cmd->error != MMC_ERR_NONE) ||
  569. (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
  570. (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
  571. sdhci_reset(host, SDHCI_RESET_CMD);
  572. sdhci_reset(host, SDHCI_RESET_DATA);
  573. }
  574. host->mrq = NULL;
  575. host->cmd = NULL;
  576. host->data = NULL;
  577. sdhci_deactivate_led(host);
  578. spin_unlock_irqrestore(&host->lock, flags);
  579. mmc_request_done(host->mmc, mrq);
  580. }
  581. static void sdhci_timeout_timer(unsigned long data)
  582. {
  583. struct sdhci_host *host;
  584. unsigned long flags;
  585. host = (struct sdhci_host*)data;
  586. spin_lock_irqsave(&host->lock, flags);
  587. if (host->mrq) {
  588. printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. "
  589. "Please report this to " BUGMAIL ".\n",
  590. mmc_hostname(host->mmc));
  591. sdhci_dumpregs(host);
  592. if (host->data) {
  593. host->data->error = MMC_ERR_TIMEOUT;
  594. sdhci_finish_data(host);
  595. } else {
  596. if (host->cmd)
  597. host->cmd->error = MMC_ERR_TIMEOUT;
  598. else
  599. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  600. tasklet_schedule(&host->finish_tasklet);
  601. }
  602. }
  603. spin_unlock_irqrestore(&host->lock, flags);
  604. }
  605. /*****************************************************************************\
  606. * *
  607. * Interrupt handling *
  608. * *
  609. \*****************************************************************************/
  610. static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
  611. {
  612. BUG_ON(intmask == 0);
  613. if (!host->cmd) {
  614. printk(KERN_ERR "%s: Got command interrupt even though no "
  615. "command operation was in progress.\n",
  616. mmc_hostname(host->mmc));
  617. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  618. mmc_hostname(host->mmc));
  619. sdhci_dumpregs(host);
  620. return;
  621. }
  622. if (intmask & SDHCI_INT_RESPONSE)
  623. sdhci_finish_command(host);
  624. else {
  625. if (intmask & SDHCI_INT_TIMEOUT)
  626. host->cmd->error = MMC_ERR_TIMEOUT;
  627. else if (intmask & SDHCI_INT_CRC)
  628. host->cmd->error = MMC_ERR_BADCRC;
  629. else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
  630. host->cmd->error = MMC_ERR_FAILED;
  631. else
  632. host->cmd->error = MMC_ERR_INVALID;
  633. tasklet_schedule(&host->finish_tasklet);
  634. }
  635. }
  636. static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
  637. {
  638. BUG_ON(intmask == 0);
  639. if (!host->data) {
  640. /*
  641. * A data end interrupt is sent together with the response
  642. * for the stop command.
  643. */
  644. if (intmask & SDHCI_INT_DATA_END)
  645. return;
  646. printk(KERN_ERR "%s: Got data interrupt even though no "
  647. "data operation was in progress.\n",
  648. mmc_hostname(host->mmc));
  649. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  650. mmc_hostname(host->mmc));
  651. sdhci_dumpregs(host);
  652. return;
  653. }
  654. if (intmask & SDHCI_INT_DATA_TIMEOUT)
  655. host->data->error = MMC_ERR_TIMEOUT;
  656. else if (intmask & SDHCI_INT_DATA_CRC)
  657. host->data->error = MMC_ERR_BADCRC;
  658. else if (intmask & SDHCI_INT_DATA_END_BIT)
  659. host->data->error = MMC_ERR_FAILED;
  660. if (host->data->error != MMC_ERR_NONE)
  661. sdhci_finish_data(host);
  662. else {
  663. if (intmask & (SDHCI_INT_BUF_FULL | SDHCI_INT_BUF_EMPTY))
  664. sdhci_transfer_pio(host);
  665. if (intmask & SDHCI_INT_DATA_END)
  666. sdhci_finish_data(host);
  667. }
  668. }
  669. static irqreturn_t sdhci_irq(int irq, void *dev_id, struct pt_regs *regs)
  670. {
  671. irqreturn_t result;
  672. struct sdhci_host* host = dev_id;
  673. u32 intmask;
  674. spin_lock(&host->lock);
  675. intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
  676. if (!intmask) {
  677. result = IRQ_NONE;
  678. goto out;
  679. }
  680. DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
  681. if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE))
  682. tasklet_schedule(&host->card_tasklet);
  683. if (intmask & SDHCI_INT_CMD_MASK) {
  684. sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
  685. writel(intmask & SDHCI_INT_CMD_MASK,
  686. host->ioaddr + SDHCI_INT_STATUS);
  687. }
  688. if (intmask & SDHCI_INT_DATA_MASK) {
  689. sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
  690. writel(intmask & SDHCI_INT_DATA_MASK,
  691. host->ioaddr + SDHCI_INT_STATUS);
  692. }
  693. intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
  694. if (intmask & SDHCI_INT_CARD_INT) {
  695. printk(KERN_ERR "%s: Unexpected card interrupt. Please "
  696. "report this to " BUGMAIL ".\n",
  697. mmc_hostname(host->mmc));
  698. sdhci_dumpregs(host);
  699. }
  700. if (intmask & SDHCI_INT_BUS_POWER) {
  701. printk(KERN_ERR "%s: Unexpected bus power interrupt. Please "
  702. "report this to " BUGMAIL ".\n",
  703. mmc_hostname(host->mmc));
  704. sdhci_dumpregs(host);
  705. }
  706. if (intmask & SDHCI_INT_ACMD12ERR) {
  707. printk(KERN_ERR "%s: Unexpected auto CMD12 error. Please "
  708. "report this to " BUGMAIL ".\n",
  709. mmc_hostname(host->mmc));
  710. sdhci_dumpregs(host);
  711. writew(~0, host->ioaddr + SDHCI_ACMD12_ERR);
  712. }
  713. if (intmask)
  714. writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
  715. result = IRQ_HANDLED;
  716. out:
  717. spin_unlock(&host->lock);
  718. return result;
  719. }
  720. /*****************************************************************************\
  721. * *
  722. * Suspend/resume *
  723. * *
  724. \*****************************************************************************/
  725. #ifdef CONFIG_PM
  726. static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
  727. {
  728. struct sdhci_chip *chip;
  729. int i, ret;
  730. chip = pci_get_drvdata(pdev);
  731. if (!chip)
  732. return 0;
  733. DBG("Suspending...\n");
  734. for (i = 0;i < chip->num_slots;i++) {
  735. if (!chip->hosts[i])
  736. continue;
  737. ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
  738. if (ret) {
  739. for (i--;i >= 0;i--)
  740. mmc_resume_host(chip->hosts[i]->mmc);
  741. return ret;
  742. }
  743. }
  744. pci_save_state(pdev);
  745. pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
  746. pci_disable_device(pdev);
  747. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  748. return 0;
  749. }
  750. static int sdhci_resume (struct pci_dev *pdev)
  751. {
  752. struct sdhci_chip *chip;
  753. int i, ret;
  754. chip = pci_get_drvdata(pdev);
  755. if (!chip)
  756. return 0;
  757. DBG("Resuming...\n");
  758. pci_set_power_state(pdev, PCI_D0);
  759. pci_restore_state(pdev);
  760. pci_enable_device(pdev);
  761. for (i = 0;i < chip->num_slots;i++) {
  762. if (!chip->hosts[i])
  763. continue;
  764. if (chip->hosts[i]->flags & SDHCI_USE_DMA)
  765. pci_set_master(pdev);
  766. sdhci_init(chip->hosts[i]);
  767. ret = mmc_resume_host(chip->hosts[i]->mmc);
  768. if (ret)
  769. return ret;
  770. }
  771. return 0;
  772. }
  773. #else /* CONFIG_PM */
  774. #define sdhci_suspend NULL
  775. #define sdhci_resume NULL
  776. #endif /* CONFIG_PM */
  777. /*****************************************************************************\
  778. * *
  779. * Device probing/removal *
  780. * *
  781. \*****************************************************************************/
  782. static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
  783. {
  784. int ret;
  785. struct sdhci_chip *chip;
  786. struct mmc_host *mmc;
  787. struct sdhci_host *host;
  788. u8 first_bar;
  789. unsigned int caps;
  790. chip = pci_get_drvdata(pdev);
  791. BUG_ON(!chip);
  792. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
  793. if (ret)
  794. return ret;
  795. first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
  796. if (first_bar > 5) {
  797. printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
  798. return -ENODEV;
  799. }
  800. if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
  801. printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
  802. return -ENODEV;
  803. }
  804. if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
  805. printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. Aborting.\n");
  806. return -ENODEV;
  807. }
  808. mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
  809. if (!mmc)
  810. return -ENOMEM;
  811. host = mmc_priv(mmc);
  812. host->mmc = mmc;
  813. host->bar = first_bar + slot;
  814. host->addr = pci_resource_start(pdev, host->bar);
  815. host->irq = pdev->irq;
  816. DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
  817. snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
  818. ret = pci_request_region(pdev, host->bar, host->slot_descr);
  819. if (ret)
  820. goto free;
  821. host->ioaddr = ioremap_nocache(host->addr,
  822. pci_resource_len(pdev, host->bar));
  823. if (!host->ioaddr) {
  824. ret = -ENOMEM;
  825. goto release;
  826. }
  827. caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
  828. if ((caps & SDHCI_CAN_DO_DMA) && ((pdev->class & 0x0000FF) == 0x01))
  829. host->flags |= SDHCI_USE_DMA;
  830. if (host->flags & SDHCI_USE_DMA) {
  831. if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  832. printk(KERN_WARNING "%s: No suitable DMA available. "
  833. "Falling back to PIO.\n", host->slot_descr);
  834. host->flags &= ~SDHCI_USE_DMA;
  835. }
  836. }
  837. if (host->flags & SDHCI_USE_DMA)
  838. pci_set_master(pdev);
  839. else /* XXX: Hack to get MMC layer to avoid highmem */
  840. pdev->dma_mask = 0;
  841. host->max_clk =
  842. (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
  843. if (host->max_clk == 0) {
  844. printk(KERN_ERR "%s: Hardware doesn't specify base clock "
  845. "frequency.\n", host->slot_descr);
  846. ret = -ENODEV;
  847. goto unmap;
  848. }
  849. host->max_clk *= 1000000;
  850. /*
  851. * Set host parameters.
  852. */
  853. mmc->ops = &sdhci_ops;
  854. mmc->f_min = host->max_clk / 256;
  855. mmc->f_max = host->max_clk;
  856. mmc->caps = MMC_CAP_4_BIT_DATA;
  857. mmc->ocr_avail = 0;
  858. if (caps & SDHCI_CAN_VDD_330)
  859. mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
  860. else if (caps & SDHCI_CAN_VDD_300)
  861. mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
  862. else if (caps & SDHCI_CAN_VDD_180)
  863. mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
  864. if (mmc->ocr_avail == 0) {
  865. printk(KERN_ERR "%s: Hardware doesn't report any "
  866. "support voltages.\n", host->slot_descr);
  867. ret = -ENODEV;
  868. goto unmap;
  869. }
  870. spin_lock_init(&host->lock);
  871. /*
  872. * Maximum number of segments. Hardware cannot do scatter lists.
  873. */
  874. if (host->flags & SDHCI_USE_DMA)
  875. mmc->max_hw_segs = 1;
  876. else
  877. mmc->max_hw_segs = 16;
  878. mmc->max_phys_segs = 16;
  879. /*
  880. * Maximum number of sectors in one transfer. Limited by sector
  881. * count register.
  882. */
  883. mmc->max_sectors = 0x3FFF;
  884. /*
  885. * Maximum segment size. Could be one segment with the maximum number
  886. * of sectors.
  887. */
  888. mmc->max_seg_size = mmc->max_sectors * 512;
  889. /*
  890. * Init tasklets.
  891. */
  892. tasklet_init(&host->card_tasklet,
  893. sdhci_tasklet_card, (unsigned long)host);
  894. tasklet_init(&host->finish_tasklet,
  895. sdhci_tasklet_finish, (unsigned long)host);
  896. setup_timer(&host->timer, sdhci_timeout_timer, (long)host);
  897. ret = request_irq(host->irq, sdhci_irq, SA_SHIRQ,
  898. host->slot_descr, host);
  899. if (ret)
  900. goto untasklet;
  901. sdhci_init(host);
  902. #ifdef CONFIG_MMC_DEBUG
  903. sdhci_dumpregs(host);
  904. #endif
  905. host->chip = chip;
  906. chip->hosts[slot] = host;
  907. mmc_add_host(mmc);
  908. printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
  909. host->addr, host->irq,
  910. (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
  911. return 0;
  912. untasklet:
  913. tasklet_kill(&host->card_tasklet);
  914. tasklet_kill(&host->finish_tasklet);
  915. unmap:
  916. iounmap(host->ioaddr);
  917. release:
  918. pci_release_region(pdev, host->bar);
  919. free:
  920. mmc_free_host(mmc);
  921. return ret;
  922. }
  923. static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
  924. {
  925. struct sdhci_chip *chip;
  926. struct mmc_host *mmc;
  927. struct sdhci_host *host;
  928. chip = pci_get_drvdata(pdev);
  929. host = chip->hosts[slot];
  930. mmc = host->mmc;
  931. chip->hosts[slot] = NULL;
  932. mmc_remove_host(mmc);
  933. sdhci_reset(host, SDHCI_RESET_ALL);
  934. free_irq(host->irq, host);
  935. del_timer_sync(&host->timer);
  936. tasklet_kill(&host->card_tasklet);
  937. tasklet_kill(&host->finish_tasklet);
  938. iounmap(host->ioaddr);
  939. pci_release_region(pdev, host->bar);
  940. mmc_free_host(mmc);
  941. }
  942. static int __devinit sdhci_probe(struct pci_dev *pdev,
  943. const struct pci_device_id *ent)
  944. {
  945. int ret, i;
  946. u8 slots, rev;
  947. struct sdhci_chip *chip;
  948. BUG_ON(pdev == NULL);
  949. BUG_ON(ent == NULL);
  950. pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
  951. printk(KERN_INFO DRIVER_NAME
  952. ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
  953. pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
  954. (int)rev);
  955. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
  956. if (ret)
  957. return ret;
  958. slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
  959. DBG("found %d slot(s)\n", slots);
  960. if (slots == 0)
  961. return -ENODEV;
  962. ret = pci_enable_device(pdev);
  963. if (ret)
  964. return ret;
  965. chip = kzalloc(sizeof(struct sdhci_chip) +
  966. sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
  967. if (!chip) {
  968. ret = -ENOMEM;
  969. goto err;
  970. }
  971. chip->pdev = pdev;
  972. chip->num_slots = slots;
  973. pci_set_drvdata(pdev, chip);
  974. for (i = 0;i < slots;i++) {
  975. ret = sdhci_probe_slot(pdev, i);
  976. if (ret) {
  977. for (i--;i >= 0;i--)
  978. sdhci_remove_slot(pdev, i);
  979. goto free;
  980. }
  981. }
  982. return 0;
  983. free:
  984. pci_set_drvdata(pdev, NULL);
  985. kfree(chip);
  986. err:
  987. pci_disable_device(pdev);
  988. return ret;
  989. }
  990. static void __devexit sdhci_remove(struct pci_dev *pdev)
  991. {
  992. int i;
  993. struct sdhci_chip *chip;
  994. chip = pci_get_drvdata(pdev);
  995. if (chip) {
  996. for (i = 0;i < chip->num_slots;i++)
  997. sdhci_remove_slot(pdev, i);
  998. pci_set_drvdata(pdev, NULL);
  999. kfree(chip);
  1000. }
  1001. pci_disable_device(pdev);
  1002. }
  1003. static struct pci_driver sdhci_driver = {
  1004. .name = DRIVER_NAME,
  1005. .id_table = pci_ids,
  1006. .probe = sdhci_probe,
  1007. .remove = __devexit_p(sdhci_remove),
  1008. .suspend = sdhci_suspend,
  1009. .resume = sdhci_resume,
  1010. };
  1011. /*****************************************************************************\
  1012. * *
  1013. * Driver init/exit *
  1014. * *
  1015. \*****************************************************************************/
  1016. static int __init sdhci_drv_init(void)
  1017. {
  1018. printk(KERN_INFO DRIVER_NAME
  1019. ": Secure Digital Host Controller Interface driver, "
  1020. DRIVER_VERSION "\n");
  1021. printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
  1022. return pci_register_driver(&sdhci_driver);
  1023. }
  1024. static void __exit sdhci_drv_exit(void)
  1025. {
  1026. DBG("Exiting\n");
  1027. pci_unregister_driver(&sdhci_driver);
  1028. }
  1029. module_init(sdhci_drv_init);
  1030. module_exit(sdhci_drv_exit);
  1031. MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
  1032. MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
  1033. MODULE_VERSION(DRIVER_VERSION);
  1034. MODULE_LICENSE("GPL");