cx23885-cards.c 48 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/init.h>
  22. #include <linux/module.h>
  23. #include <linux/pci.h>
  24. #include <linux/delay.h>
  25. #include <media/cx25840.h>
  26. #include <linux/firmware.h>
  27. #include <misc/altera.h>
  28. #include "cx23885.h"
  29. #include "tuner-xc2028.h"
  30. #include "netup-eeprom.h"
  31. #include "netup-init.h"
  32. #include "altera-ci.h"
  33. #include "xc4000.h"
  34. #include "xc5000.h"
  35. #include "cx23888-ir.h"
  36. static unsigned int netup_card_rev = 4;
  37. module_param(netup_card_rev, int, 0644);
  38. MODULE_PARM_DESC(netup_card_rev,
  39. "NetUP Dual DVB-T/C CI card revision");
  40. static unsigned int enable_885_ir;
  41. module_param(enable_885_ir, int, 0644);
  42. MODULE_PARM_DESC(enable_885_ir,
  43. "Enable integrated IR controller for supported\n"
  44. "\t\t CX2388[57] boards that are wired for it:\n"
  45. "\t\t\tHVR-1250 (reported safe)\n"
  46. "\t\t\tTerraTec Cinergy T PCIe Dual (not well tested, appears to be safe)\n"
  47. "\t\t\tTeVii S470 (reported unsafe)\n"
  48. "\t\t This can cause an interrupt storm with some cards.\n"
  49. "\t\t Default: 0 [Disabled]");
  50. /* ------------------------------------------------------------------ */
  51. /* board config info */
  52. struct cx23885_board cx23885_boards[] = {
  53. [CX23885_BOARD_UNKNOWN] = {
  54. .name = "UNKNOWN/GENERIC",
  55. /* Ensure safe default for unknown boards */
  56. .clk_freq = 0,
  57. .input = {{
  58. .type = CX23885_VMUX_COMPOSITE1,
  59. .vmux = 0,
  60. }, {
  61. .type = CX23885_VMUX_COMPOSITE2,
  62. .vmux = 1,
  63. }, {
  64. .type = CX23885_VMUX_COMPOSITE3,
  65. .vmux = 2,
  66. }, {
  67. .type = CX23885_VMUX_COMPOSITE4,
  68. .vmux = 3,
  69. } },
  70. },
  71. [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
  72. .name = "Hauppauge WinTV-HVR1800lp",
  73. .portc = CX23885_MPEG_DVB,
  74. .input = {{
  75. .type = CX23885_VMUX_TELEVISION,
  76. .vmux = 0,
  77. .gpio0 = 0xff00,
  78. }, {
  79. .type = CX23885_VMUX_DEBUG,
  80. .vmux = 0,
  81. .gpio0 = 0xff01,
  82. }, {
  83. .type = CX23885_VMUX_COMPOSITE1,
  84. .vmux = 1,
  85. .gpio0 = 0xff02,
  86. }, {
  87. .type = CX23885_VMUX_SVIDEO,
  88. .vmux = 2,
  89. .gpio0 = 0xff02,
  90. } },
  91. },
  92. [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
  93. .name = "Hauppauge WinTV-HVR1800",
  94. .porta = CX23885_ANALOG_VIDEO,
  95. .portb = CX23885_MPEG_ENCODER,
  96. .portc = CX23885_MPEG_DVB,
  97. .tuner_type = TUNER_PHILIPS_TDA8290,
  98. .tuner_addr = 0x42, /* 0x84 >> 1 */
  99. .tuner_bus = 1,
  100. .input = {{
  101. .type = CX23885_VMUX_TELEVISION,
  102. .vmux = CX25840_VIN7_CH3 |
  103. CX25840_VIN5_CH2 |
  104. CX25840_VIN2_CH1,
  105. .amux = CX25840_AUDIO8,
  106. .gpio0 = 0,
  107. }, {
  108. .type = CX23885_VMUX_COMPOSITE1,
  109. .vmux = CX25840_VIN7_CH3 |
  110. CX25840_VIN4_CH2 |
  111. CX25840_VIN6_CH1,
  112. .amux = CX25840_AUDIO7,
  113. .gpio0 = 0,
  114. }, {
  115. .type = CX23885_VMUX_SVIDEO,
  116. .vmux = CX25840_VIN7_CH3 |
  117. CX25840_VIN4_CH2 |
  118. CX25840_VIN8_CH1 |
  119. CX25840_SVIDEO_ON,
  120. .amux = CX25840_AUDIO7,
  121. .gpio0 = 0,
  122. } },
  123. },
  124. [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
  125. .name = "Hauppauge WinTV-HVR1250",
  126. .porta = CX23885_ANALOG_VIDEO,
  127. .portc = CX23885_MPEG_DVB,
  128. #ifdef MT2131_NO_ANALOG_SUPPORT_YET
  129. .tuner_type = TUNER_PHILIPS_TDA8290,
  130. .tuner_addr = 0x42, /* 0x84 >> 1 */
  131. .tuner_bus = 1,
  132. #endif
  133. .force_bff = 1,
  134. .input = {{
  135. #ifdef MT2131_NO_ANALOG_SUPPORT_YET
  136. .type = CX23885_VMUX_TELEVISION,
  137. .vmux = CX25840_VIN7_CH3 |
  138. CX25840_VIN5_CH2 |
  139. CX25840_VIN2_CH1,
  140. .amux = CX25840_AUDIO8,
  141. .gpio0 = 0xff00,
  142. }, {
  143. #endif
  144. .type = CX23885_VMUX_COMPOSITE1,
  145. .vmux = CX25840_VIN7_CH3 |
  146. CX25840_VIN4_CH2 |
  147. CX25840_VIN6_CH1,
  148. .amux = CX25840_AUDIO7,
  149. .gpio0 = 0xff02,
  150. }, {
  151. .type = CX23885_VMUX_SVIDEO,
  152. .vmux = CX25840_VIN7_CH3 |
  153. CX25840_VIN4_CH2 |
  154. CX25840_VIN8_CH1 |
  155. CX25840_SVIDEO_ON,
  156. .amux = CX25840_AUDIO7,
  157. .gpio0 = 0xff02,
  158. } },
  159. },
  160. [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
  161. .name = "DViCO FusionHDTV5 Express",
  162. .portb = CX23885_MPEG_DVB,
  163. },
  164. [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
  165. .name = "Hauppauge WinTV-HVR1500Q",
  166. .portc = CX23885_MPEG_DVB,
  167. },
  168. [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
  169. .name = "Hauppauge WinTV-HVR1500",
  170. .porta = CX23885_ANALOG_VIDEO,
  171. .portc = CX23885_MPEG_DVB,
  172. .tuner_type = TUNER_XC2028,
  173. .tuner_addr = 0x61, /* 0xc2 >> 1 */
  174. .input = {{
  175. .type = CX23885_VMUX_TELEVISION,
  176. .vmux = CX25840_VIN7_CH3 |
  177. CX25840_VIN5_CH2 |
  178. CX25840_VIN2_CH1,
  179. .gpio0 = 0,
  180. }, {
  181. .type = CX23885_VMUX_COMPOSITE1,
  182. .vmux = CX25840_VIN7_CH3 |
  183. CX25840_VIN4_CH2 |
  184. CX25840_VIN6_CH1,
  185. .gpio0 = 0,
  186. }, {
  187. .type = CX23885_VMUX_SVIDEO,
  188. .vmux = CX25840_VIN7_CH3 |
  189. CX25840_VIN4_CH2 |
  190. CX25840_VIN8_CH1 |
  191. CX25840_SVIDEO_ON,
  192. .gpio0 = 0,
  193. } },
  194. },
  195. [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
  196. .name = "Hauppauge WinTV-HVR1200",
  197. .portc = CX23885_MPEG_DVB,
  198. },
  199. [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
  200. .name = "Hauppauge WinTV-HVR1700",
  201. .portc = CX23885_MPEG_DVB,
  202. },
  203. [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
  204. .name = "Hauppauge WinTV-HVR1400",
  205. .portc = CX23885_MPEG_DVB,
  206. },
  207. [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
  208. .name = "DViCO FusionHDTV7 Dual Express",
  209. .portb = CX23885_MPEG_DVB,
  210. .portc = CX23885_MPEG_DVB,
  211. },
  212. [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
  213. .name = "DViCO FusionHDTV DVB-T Dual Express",
  214. .portb = CX23885_MPEG_DVB,
  215. .portc = CX23885_MPEG_DVB,
  216. },
  217. [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
  218. .name = "Leadtek Winfast PxDVR3200 H",
  219. .portc = CX23885_MPEG_DVB,
  220. },
  221. [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = {
  222. .name = "Leadtek Winfast PxDVR3200 H XC4000",
  223. .porta = CX23885_ANALOG_VIDEO,
  224. .portc = CX23885_MPEG_DVB,
  225. .tuner_type = TUNER_XC4000,
  226. .tuner_addr = 0x61,
  227. .radio_type = UNSET,
  228. .radio_addr = ADDR_UNSET,
  229. .input = {{
  230. .type = CX23885_VMUX_TELEVISION,
  231. .vmux = CX25840_VIN2_CH1 |
  232. CX25840_VIN5_CH2 |
  233. CX25840_NONE0_CH3,
  234. }, {
  235. .type = CX23885_VMUX_COMPOSITE1,
  236. .vmux = CX25840_COMPOSITE1,
  237. }, {
  238. .type = CX23885_VMUX_SVIDEO,
  239. .vmux = CX25840_SVIDEO_LUMA3 |
  240. CX25840_SVIDEO_CHROMA4,
  241. }, {
  242. .type = CX23885_VMUX_COMPONENT,
  243. .vmux = CX25840_VIN7_CH1 |
  244. CX25840_VIN6_CH2 |
  245. CX25840_VIN8_CH3 |
  246. CX25840_COMPONENT_ON,
  247. } },
  248. },
  249. [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
  250. .name = "Compro VideoMate E650F",
  251. .portc = CX23885_MPEG_DVB,
  252. },
  253. [CX23885_BOARD_TBS_6920] = {
  254. .name = "TurboSight TBS 6920",
  255. .portb = CX23885_MPEG_DVB,
  256. },
  257. [CX23885_BOARD_TEVII_S470] = {
  258. .name = "TeVii S470",
  259. .portb = CX23885_MPEG_DVB,
  260. },
  261. [CX23885_BOARD_DVBWORLD_2005] = {
  262. .name = "DVBWorld DVB-S2 2005",
  263. .portb = CX23885_MPEG_DVB,
  264. },
  265. [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
  266. .ci_type = 1,
  267. .name = "NetUP Dual DVB-S2 CI",
  268. .portb = CX23885_MPEG_DVB,
  269. .portc = CX23885_MPEG_DVB,
  270. },
  271. [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
  272. .name = "Hauppauge WinTV-HVR1270",
  273. .portc = CX23885_MPEG_DVB,
  274. },
  275. [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
  276. .name = "Hauppauge WinTV-HVR1275",
  277. .portc = CX23885_MPEG_DVB,
  278. },
  279. [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
  280. .name = "Hauppauge WinTV-HVR1255",
  281. .porta = CX23885_ANALOG_VIDEO,
  282. .portc = CX23885_MPEG_DVB,
  283. .tuner_type = TUNER_ABSENT,
  284. .tuner_addr = 0x42, /* 0x84 >> 1 */
  285. .force_bff = 1,
  286. .input = {{
  287. .type = CX23885_VMUX_TELEVISION,
  288. .vmux = CX25840_VIN7_CH3 |
  289. CX25840_VIN5_CH2 |
  290. CX25840_VIN2_CH1 |
  291. CX25840_DIF_ON,
  292. .amux = CX25840_AUDIO8,
  293. }, {
  294. .type = CX23885_VMUX_COMPOSITE1,
  295. .vmux = CX25840_VIN7_CH3 |
  296. CX25840_VIN4_CH2 |
  297. CX25840_VIN6_CH1,
  298. .amux = CX25840_AUDIO7,
  299. }, {
  300. .type = CX23885_VMUX_SVIDEO,
  301. .vmux = CX25840_VIN7_CH3 |
  302. CX25840_VIN4_CH2 |
  303. CX25840_VIN8_CH1 |
  304. CX25840_SVIDEO_ON,
  305. .amux = CX25840_AUDIO7,
  306. } },
  307. },
  308. [CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = {
  309. .name = "Hauppauge WinTV-HVR1255",
  310. .porta = CX23885_ANALOG_VIDEO,
  311. .portc = CX23885_MPEG_DVB,
  312. .tuner_type = TUNER_ABSENT,
  313. .tuner_addr = 0x42, /* 0x84 >> 1 */
  314. .force_bff = 1,
  315. .input = {{
  316. .type = CX23885_VMUX_TELEVISION,
  317. .vmux = CX25840_VIN7_CH3 |
  318. CX25840_VIN5_CH2 |
  319. CX25840_VIN2_CH1 |
  320. CX25840_DIF_ON,
  321. .amux = CX25840_AUDIO8,
  322. }, {
  323. .type = CX23885_VMUX_SVIDEO,
  324. .vmux = CX25840_VIN7_CH3 |
  325. CX25840_VIN4_CH2 |
  326. CX25840_VIN8_CH1 |
  327. CX25840_SVIDEO_ON,
  328. .amux = CX25840_AUDIO7,
  329. } },
  330. },
  331. [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
  332. .name = "Hauppauge WinTV-HVR1210",
  333. .portc = CX23885_MPEG_DVB,
  334. },
  335. [CX23885_BOARD_MYGICA_X8506] = {
  336. .name = "Mygica X8506 DMB-TH",
  337. .tuner_type = TUNER_XC5000,
  338. .tuner_addr = 0x61,
  339. .tuner_bus = 1,
  340. .porta = CX23885_ANALOG_VIDEO,
  341. .portb = CX23885_MPEG_DVB,
  342. .input = {
  343. {
  344. .type = CX23885_VMUX_TELEVISION,
  345. .vmux = CX25840_COMPOSITE2,
  346. },
  347. {
  348. .type = CX23885_VMUX_COMPOSITE1,
  349. .vmux = CX25840_COMPOSITE8,
  350. },
  351. {
  352. .type = CX23885_VMUX_SVIDEO,
  353. .vmux = CX25840_SVIDEO_LUMA3 |
  354. CX25840_SVIDEO_CHROMA4,
  355. },
  356. {
  357. .type = CX23885_VMUX_COMPONENT,
  358. .vmux = CX25840_COMPONENT_ON |
  359. CX25840_VIN1_CH1 |
  360. CX25840_VIN6_CH2 |
  361. CX25840_VIN7_CH3,
  362. },
  363. },
  364. },
  365. [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
  366. .name = "Magic-Pro ProHDTV Extreme 2",
  367. .tuner_type = TUNER_XC5000,
  368. .tuner_addr = 0x61,
  369. .tuner_bus = 1,
  370. .porta = CX23885_ANALOG_VIDEO,
  371. .portb = CX23885_MPEG_DVB,
  372. .input = {
  373. {
  374. .type = CX23885_VMUX_TELEVISION,
  375. .vmux = CX25840_COMPOSITE2,
  376. },
  377. {
  378. .type = CX23885_VMUX_COMPOSITE1,
  379. .vmux = CX25840_COMPOSITE8,
  380. },
  381. {
  382. .type = CX23885_VMUX_SVIDEO,
  383. .vmux = CX25840_SVIDEO_LUMA3 |
  384. CX25840_SVIDEO_CHROMA4,
  385. },
  386. {
  387. .type = CX23885_VMUX_COMPONENT,
  388. .vmux = CX25840_COMPONENT_ON |
  389. CX25840_VIN1_CH1 |
  390. CX25840_VIN6_CH2 |
  391. CX25840_VIN7_CH3,
  392. },
  393. },
  394. },
  395. [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
  396. .name = "Hauppauge WinTV-HVR1850",
  397. .porta = CX23885_ANALOG_VIDEO,
  398. .portb = CX23885_MPEG_ENCODER,
  399. .portc = CX23885_MPEG_DVB,
  400. .tuner_type = TUNER_ABSENT,
  401. .tuner_addr = 0x42, /* 0x84 >> 1 */
  402. .force_bff = 1,
  403. .input = {{
  404. .type = CX23885_VMUX_TELEVISION,
  405. .vmux = CX25840_VIN7_CH3 |
  406. CX25840_VIN5_CH2 |
  407. CX25840_VIN2_CH1 |
  408. CX25840_DIF_ON,
  409. .amux = CX25840_AUDIO8,
  410. }, {
  411. .type = CX23885_VMUX_COMPOSITE1,
  412. .vmux = CX25840_VIN7_CH3 |
  413. CX25840_VIN4_CH2 |
  414. CX25840_VIN6_CH1,
  415. .amux = CX25840_AUDIO7,
  416. }, {
  417. .type = CX23885_VMUX_SVIDEO,
  418. .vmux = CX25840_VIN7_CH3 |
  419. CX25840_VIN4_CH2 |
  420. CX25840_VIN8_CH1 |
  421. CX25840_SVIDEO_ON,
  422. .amux = CX25840_AUDIO7,
  423. } },
  424. },
  425. [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
  426. .name = "Compro VideoMate E800",
  427. .portc = CX23885_MPEG_DVB,
  428. },
  429. [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
  430. .name = "Hauppauge WinTV-HVR1290",
  431. .portc = CX23885_MPEG_DVB,
  432. },
  433. [CX23885_BOARD_MYGICA_X8558PRO] = {
  434. .name = "Mygica X8558 PRO DMB-TH",
  435. .portb = CX23885_MPEG_DVB,
  436. .portc = CX23885_MPEG_DVB,
  437. },
  438. [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
  439. .name = "LEADTEK WinFast PxTV1200",
  440. .porta = CX23885_ANALOG_VIDEO,
  441. .tuner_type = TUNER_XC2028,
  442. .tuner_addr = 0x61,
  443. .tuner_bus = 1,
  444. .input = {{
  445. .type = CX23885_VMUX_TELEVISION,
  446. .vmux = CX25840_VIN2_CH1 |
  447. CX25840_VIN5_CH2 |
  448. CX25840_NONE0_CH3,
  449. }, {
  450. .type = CX23885_VMUX_COMPOSITE1,
  451. .vmux = CX25840_COMPOSITE1,
  452. }, {
  453. .type = CX23885_VMUX_SVIDEO,
  454. .vmux = CX25840_SVIDEO_LUMA3 |
  455. CX25840_SVIDEO_CHROMA4,
  456. }, {
  457. .type = CX23885_VMUX_COMPONENT,
  458. .vmux = CX25840_VIN7_CH1 |
  459. CX25840_VIN6_CH2 |
  460. CX25840_VIN8_CH3 |
  461. CX25840_COMPONENT_ON,
  462. } },
  463. },
  464. [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
  465. .name = "GoTView X5 3D Hybrid",
  466. .tuner_type = TUNER_XC5000,
  467. .tuner_addr = 0x64,
  468. .tuner_bus = 1,
  469. .porta = CX23885_ANALOG_VIDEO,
  470. .portb = CX23885_MPEG_DVB,
  471. .input = {{
  472. .type = CX23885_VMUX_TELEVISION,
  473. .vmux = CX25840_VIN2_CH1 |
  474. CX25840_VIN5_CH2,
  475. .gpio0 = 0x02,
  476. }, {
  477. .type = CX23885_VMUX_COMPOSITE1,
  478. .vmux = CX23885_VMUX_COMPOSITE1,
  479. }, {
  480. .type = CX23885_VMUX_SVIDEO,
  481. .vmux = CX25840_SVIDEO_LUMA3 |
  482. CX25840_SVIDEO_CHROMA4,
  483. } },
  484. },
  485. [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = {
  486. .ci_type = 2,
  487. .name = "NetUP Dual DVB-T/C-CI RF",
  488. .porta = CX23885_ANALOG_VIDEO,
  489. .portb = CX23885_MPEG_DVB,
  490. .portc = CX23885_MPEG_DVB,
  491. .num_fds_portb = 2,
  492. .num_fds_portc = 2,
  493. .tuner_type = TUNER_XC5000,
  494. .tuner_addr = 0x64,
  495. .input = { {
  496. .type = CX23885_VMUX_TELEVISION,
  497. .vmux = CX25840_COMPOSITE1,
  498. } },
  499. },
  500. [CX23885_BOARD_MPX885] = {
  501. .name = "MPX-885",
  502. .porta = CX23885_ANALOG_VIDEO,
  503. .input = {{
  504. .type = CX23885_VMUX_COMPOSITE1,
  505. .vmux = CX25840_COMPOSITE1,
  506. .amux = CX25840_AUDIO6,
  507. .gpio0 = 0,
  508. }, {
  509. .type = CX23885_VMUX_COMPOSITE2,
  510. .vmux = CX25840_COMPOSITE2,
  511. .amux = CX25840_AUDIO6,
  512. .gpio0 = 0,
  513. }, {
  514. .type = CX23885_VMUX_COMPOSITE3,
  515. .vmux = CX25840_COMPOSITE3,
  516. .amux = CX25840_AUDIO7,
  517. .gpio0 = 0,
  518. }, {
  519. .type = CX23885_VMUX_COMPOSITE4,
  520. .vmux = CX25840_COMPOSITE4,
  521. .amux = CX25840_AUDIO7,
  522. .gpio0 = 0,
  523. } },
  524. },
  525. [CX23885_BOARD_MYGICA_X8507] = {
  526. .name = "Mygica X8507",
  527. .tuner_type = TUNER_XC5000,
  528. .tuner_addr = 0x61,
  529. .tuner_bus = 1,
  530. .porta = CX23885_ANALOG_VIDEO,
  531. .input = {
  532. {
  533. .type = CX23885_VMUX_TELEVISION,
  534. .vmux = CX25840_COMPOSITE2,
  535. .amux = CX25840_AUDIO8,
  536. },
  537. {
  538. .type = CX23885_VMUX_COMPOSITE1,
  539. .vmux = CX25840_COMPOSITE8,
  540. .amux = CX25840_AUDIO7,
  541. },
  542. {
  543. .type = CX23885_VMUX_SVIDEO,
  544. .vmux = CX25840_SVIDEO_LUMA3 |
  545. CX25840_SVIDEO_CHROMA4,
  546. .amux = CX25840_AUDIO7,
  547. },
  548. {
  549. .type = CX23885_VMUX_COMPONENT,
  550. .vmux = CX25840_COMPONENT_ON |
  551. CX25840_VIN1_CH1 |
  552. CX25840_VIN6_CH2 |
  553. CX25840_VIN7_CH3,
  554. .amux = CX25840_AUDIO7,
  555. },
  556. },
  557. },
  558. [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = {
  559. .name = "TerraTec Cinergy T PCIe Dual",
  560. .portb = CX23885_MPEG_DVB,
  561. .portc = CX23885_MPEG_DVB,
  562. },
  563. [CX23885_BOARD_TEVII_S471] = {
  564. .name = "TeVii S471",
  565. .portb = CX23885_MPEG_DVB,
  566. },
  567. [CX23885_BOARD_PROF_8000] = {
  568. .name = "Prof Revolution DVB-S2 8000",
  569. .portb = CX23885_MPEG_DVB,
  570. },
  571. [CX23885_BOARD_HAUPPAUGE_HVR4400] = {
  572. .name = "Hauppauge WinTV-HVR4400",
  573. .portb = CX23885_MPEG_DVB,
  574. },
  575. };
  576. const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
  577. /* ------------------------------------------------------------------ */
  578. /* PCI subsystem IDs */
  579. struct cx23885_subid cx23885_subids[] = {
  580. {
  581. .subvendor = 0x0070,
  582. .subdevice = 0x3400,
  583. .card = CX23885_BOARD_UNKNOWN,
  584. }, {
  585. .subvendor = 0x0070,
  586. .subdevice = 0x7600,
  587. .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
  588. }, {
  589. .subvendor = 0x0070,
  590. .subdevice = 0x7800,
  591. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  592. }, {
  593. .subvendor = 0x0070,
  594. .subdevice = 0x7801,
  595. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  596. }, {
  597. .subvendor = 0x0070,
  598. .subdevice = 0x7809,
  599. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  600. }, {
  601. .subvendor = 0x0070,
  602. .subdevice = 0x7911,
  603. .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
  604. }, {
  605. .subvendor = 0x18ac,
  606. .subdevice = 0xd500,
  607. .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
  608. }, {
  609. .subvendor = 0x0070,
  610. .subdevice = 0x7790,
  611. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  612. }, {
  613. .subvendor = 0x0070,
  614. .subdevice = 0x7797,
  615. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  616. }, {
  617. .subvendor = 0x0070,
  618. .subdevice = 0x7710,
  619. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  620. }, {
  621. .subvendor = 0x0070,
  622. .subdevice = 0x7717,
  623. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  624. }, {
  625. .subvendor = 0x0070,
  626. .subdevice = 0x71d1,
  627. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  628. }, {
  629. .subvendor = 0x0070,
  630. .subdevice = 0x71d3,
  631. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  632. }, {
  633. .subvendor = 0x0070,
  634. .subdevice = 0x8101,
  635. .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
  636. }, {
  637. .subvendor = 0x0070,
  638. .subdevice = 0x8010,
  639. .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
  640. }, {
  641. .subvendor = 0x18ac,
  642. .subdevice = 0xd618,
  643. .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
  644. }, {
  645. .subvendor = 0x18ac,
  646. .subdevice = 0xdb78,
  647. .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
  648. }, {
  649. .subvendor = 0x107d,
  650. .subdevice = 0x6681,
  651. .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
  652. }, {
  653. .subvendor = 0x107d,
  654. .subdevice = 0x6f39,
  655. .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000,
  656. }, {
  657. .subvendor = 0x185b,
  658. .subdevice = 0xe800,
  659. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
  660. }, {
  661. .subvendor = 0x6920,
  662. .subdevice = 0x8888,
  663. .card = CX23885_BOARD_TBS_6920,
  664. }, {
  665. .subvendor = 0xd470,
  666. .subdevice = 0x9022,
  667. .card = CX23885_BOARD_TEVII_S470,
  668. }, {
  669. .subvendor = 0x0001,
  670. .subdevice = 0x2005,
  671. .card = CX23885_BOARD_DVBWORLD_2005,
  672. }, {
  673. .subvendor = 0x1b55,
  674. .subdevice = 0x2a2c,
  675. .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
  676. }, {
  677. .subvendor = 0x0070,
  678. .subdevice = 0x2211,
  679. .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
  680. }, {
  681. .subvendor = 0x0070,
  682. .subdevice = 0x2215,
  683. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  684. }, {
  685. .subvendor = 0x0070,
  686. .subdevice = 0x221d,
  687. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  688. }, {
  689. .subvendor = 0x0070,
  690. .subdevice = 0x2251,
  691. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  692. }, {
  693. .subvendor = 0x0070,
  694. .subdevice = 0x2259,
  695. .card = CX23885_BOARD_HAUPPAUGE_HVR1255_22111,
  696. }, {
  697. .subvendor = 0x0070,
  698. .subdevice = 0x2291,
  699. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  700. }, {
  701. .subvendor = 0x0070,
  702. .subdevice = 0x2295,
  703. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  704. }, {
  705. .subvendor = 0x0070,
  706. .subdevice = 0x2299,
  707. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  708. }, {
  709. .subvendor = 0x0070,
  710. .subdevice = 0x229d,
  711. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  712. }, {
  713. .subvendor = 0x0070,
  714. .subdevice = 0x22f0,
  715. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  716. }, {
  717. .subvendor = 0x0070,
  718. .subdevice = 0x22f1,
  719. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  720. }, {
  721. .subvendor = 0x0070,
  722. .subdevice = 0x22f2,
  723. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  724. }, {
  725. .subvendor = 0x0070,
  726. .subdevice = 0x22f3,
  727. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  728. }, {
  729. .subvendor = 0x0070,
  730. .subdevice = 0x22f4,
  731. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  732. }, {
  733. .subvendor = 0x0070,
  734. .subdevice = 0x22f5,
  735. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  736. }, {
  737. .subvendor = 0x14f1,
  738. .subdevice = 0x8651,
  739. .card = CX23885_BOARD_MYGICA_X8506,
  740. }, {
  741. .subvendor = 0x14f1,
  742. .subdevice = 0x8657,
  743. .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
  744. }, {
  745. .subvendor = 0x0070,
  746. .subdevice = 0x8541,
  747. .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
  748. }, {
  749. .subvendor = 0x1858,
  750. .subdevice = 0xe800,
  751. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
  752. }, {
  753. .subvendor = 0x0070,
  754. .subdevice = 0x8551,
  755. .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
  756. }, {
  757. .subvendor = 0x14f1,
  758. .subdevice = 0x8578,
  759. .card = CX23885_BOARD_MYGICA_X8558PRO,
  760. }, {
  761. .subvendor = 0x107d,
  762. .subdevice = 0x6f22,
  763. .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
  764. }, {
  765. .subvendor = 0x5654,
  766. .subdevice = 0x2390,
  767. .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
  768. }, {
  769. .subvendor = 0x1b55,
  770. .subdevice = 0xe2e4,
  771. .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF,
  772. }, {
  773. .subvendor = 0x14f1,
  774. .subdevice = 0x8502,
  775. .card = CX23885_BOARD_MYGICA_X8507,
  776. }, {
  777. .subvendor = 0x153b,
  778. .subdevice = 0x117e,
  779. .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL,
  780. }, {
  781. .subvendor = 0xd471,
  782. .subdevice = 0x9022,
  783. .card = CX23885_BOARD_TEVII_S471,
  784. }, {
  785. .subvendor = 0x8000,
  786. .subdevice = 0x3034,
  787. .card = CX23885_BOARD_PROF_8000,
  788. }, {
  789. .subvendor = 0x0070,
  790. .subdevice = 0xc108,
  791. .card = CX23885_BOARD_HAUPPAUGE_HVR4400,
  792. }, {
  793. .subvendor = 0x0070,
  794. .subdevice = 0xc138,
  795. .card = CX23885_BOARD_HAUPPAUGE_HVR4400,
  796. }, {
  797. .subvendor = 0x0070,
  798. .subdevice = 0xc12a,
  799. .card = CX23885_BOARD_HAUPPAUGE_HVR4400,
  800. }, {
  801. .subvendor = 0x0070,
  802. .subdevice = 0xc1f8,
  803. .card = CX23885_BOARD_HAUPPAUGE_HVR4400,
  804. },
  805. };
  806. const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
  807. void cx23885_card_list(struct cx23885_dev *dev)
  808. {
  809. int i;
  810. if (0 == dev->pci->subsystem_vendor &&
  811. 0 == dev->pci->subsystem_device) {
  812. printk(KERN_INFO
  813. "%s: Board has no valid PCIe Subsystem ID and can't\n"
  814. "%s: be autodetected. Pass card=<n> insmod option\n"
  815. "%s: to workaround that. Redirect complaints to the\n"
  816. "%s: vendor of the TV card. Best regards,\n"
  817. "%s: -- tux\n",
  818. dev->name, dev->name, dev->name, dev->name, dev->name);
  819. } else {
  820. printk(KERN_INFO
  821. "%s: Your board isn't known (yet) to the driver.\n"
  822. "%s: Try to pick one of the existing card configs via\n"
  823. "%s: card=<n> insmod option. Updating to the latest\n"
  824. "%s: version might help as well.\n",
  825. dev->name, dev->name, dev->name, dev->name);
  826. }
  827. printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
  828. dev->name);
  829. for (i = 0; i < cx23885_bcount; i++)
  830. printk(KERN_INFO "%s: card=%d -> %s\n",
  831. dev->name, i, cx23885_boards[i].name);
  832. }
  833. static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
  834. {
  835. struct tveeprom tv;
  836. tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
  837. eeprom_data);
  838. /* Make sure we support the board model */
  839. switch (tv.model) {
  840. case 22001:
  841. /* WinTV-HVR1270 (PCIe, Retail, half height)
  842. * ATSC/QAM and basic analog, IR Blast */
  843. case 22009:
  844. /* WinTV-HVR1210 (PCIe, Retail, half height)
  845. * DVB-T and basic analog, IR Blast */
  846. case 22011:
  847. /* WinTV-HVR1270 (PCIe, Retail, half height)
  848. * ATSC/QAM and basic analog, IR Recv */
  849. case 22019:
  850. /* WinTV-HVR1210 (PCIe, Retail, half height)
  851. * DVB-T and basic analog, IR Recv */
  852. case 22021:
  853. /* WinTV-HVR1275 (PCIe, Retail, half height)
  854. * ATSC/QAM and basic analog, IR Recv */
  855. case 22029:
  856. /* WinTV-HVR1210 (PCIe, Retail, half height)
  857. * DVB-T and basic analog, IR Recv */
  858. case 22101:
  859. /* WinTV-HVR1270 (PCIe, Retail, full height)
  860. * ATSC/QAM and basic analog, IR Blast */
  861. case 22109:
  862. /* WinTV-HVR1210 (PCIe, Retail, full height)
  863. * DVB-T and basic analog, IR Blast */
  864. case 22111:
  865. /* WinTV-HVR1270 (PCIe, Retail, full height)
  866. * ATSC/QAM and basic analog, IR Recv */
  867. case 22119:
  868. /* WinTV-HVR1210 (PCIe, Retail, full height)
  869. * DVB-T and basic analog, IR Recv */
  870. case 22121:
  871. /* WinTV-HVR1275 (PCIe, Retail, full height)
  872. * ATSC/QAM and basic analog, IR Recv */
  873. case 22129:
  874. /* WinTV-HVR1210 (PCIe, Retail, full height)
  875. * DVB-T and basic analog, IR Recv */
  876. case 71009:
  877. /* WinTV-HVR1200 (PCIe, Retail, full height)
  878. * DVB-T and basic analog */
  879. case 71359:
  880. /* WinTV-HVR1200 (PCIe, OEM, half height)
  881. * DVB-T and basic analog */
  882. case 71439:
  883. /* WinTV-HVR1200 (PCIe, OEM, half height)
  884. * DVB-T and basic analog */
  885. case 71449:
  886. /* WinTV-HVR1200 (PCIe, OEM, full height)
  887. * DVB-T and basic analog */
  888. case 71939:
  889. /* WinTV-HVR1200 (PCIe, OEM, half height)
  890. * DVB-T and basic analog */
  891. case 71949:
  892. /* WinTV-HVR1200 (PCIe, OEM, full height)
  893. * DVB-T and basic analog */
  894. case 71959:
  895. /* WinTV-HVR1200 (PCIe, OEM, full height)
  896. * DVB-T and basic analog */
  897. case 71979:
  898. /* WinTV-HVR1200 (PCIe, OEM, half height)
  899. * DVB-T and basic analog */
  900. case 71999:
  901. /* WinTV-HVR1200 (PCIe, OEM, full height)
  902. * DVB-T and basic analog */
  903. case 76601:
  904. /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
  905. channel ATSC and MPEG2 HW Encoder */
  906. case 77001:
  907. /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
  908. and Basic analog */
  909. case 77011:
  910. /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
  911. and Basic analog */
  912. case 77041:
  913. /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
  914. and Basic analog */
  915. case 77051:
  916. /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
  917. and Basic analog */
  918. case 78011:
  919. /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
  920. Dual channel ATSC and MPEG2 HW Encoder */
  921. case 78501:
  922. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  923. Dual channel ATSC and MPEG2 HW Encoder */
  924. case 78521:
  925. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  926. Dual channel ATSC and MPEG2 HW Encoder */
  927. case 78531:
  928. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
  929. Dual channel ATSC and MPEG2 HW Encoder */
  930. case 78631:
  931. /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
  932. Dual channel ATSC and MPEG2 HW Encoder */
  933. case 79001:
  934. /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
  935. ATSC and Basic analog */
  936. case 79101:
  937. /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
  938. ATSC and Basic analog */
  939. case 79501:
  940. /* WinTV-HVR1250 (PCIe, No IR, half height,
  941. ATSC [at least] and Basic analog) */
  942. case 79561:
  943. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  944. ATSC and Basic analog */
  945. case 79571:
  946. /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
  947. ATSC and Basic analog */
  948. case 79671:
  949. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  950. ATSC and Basic analog */
  951. case 80019:
  952. /* WinTV-HVR1400 (Express Card, Retail, IR,
  953. * DVB-T and Basic analog */
  954. case 81509:
  955. /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
  956. * DVB-T and MPEG2 HW Encoder */
  957. case 81519:
  958. /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
  959. * DVB-T and MPEG2 HW Encoder */
  960. break;
  961. case 85021:
  962. /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
  963. Dual channel ATSC and MPEG2 HW Encoder */
  964. break;
  965. case 85721:
  966. /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
  967. Dual channel ATSC and Basic analog */
  968. break;
  969. default:
  970. printk(KERN_WARNING "%s: warning: "
  971. "unknown hauppauge model #%d\n",
  972. dev->name, tv.model);
  973. break;
  974. }
  975. printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
  976. dev->name, tv.model);
  977. }
  978. int cx23885_tuner_callback(void *priv, int component, int command, int arg)
  979. {
  980. struct cx23885_tsport *port = priv;
  981. struct cx23885_dev *dev = port->dev;
  982. u32 bitmask = 0;
  983. if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH))
  984. return 0;
  985. if (command != 0) {
  986. printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
  987. __func__, command);
  988. return -EINVAL;
  989. }
  990. switch (dev->board) {
  991. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  992. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  993. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  994. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  995. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  996. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  997. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  998. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  999. /* Tuner Reset Command */
  1000. bitmask = 0x04;
  1001. break;
  1002. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  1003. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1004. /* Two identical tuners on two different i2c buses,
  1005. * we need to reset the correct gpio. */
  1006. if (port->nr == 1)
  1007. bitmask = 0x01;
  1008. else if (port->nr == 2)
  1009. bitmask = 0x04;
  1010. break;
  1011. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1012. /* Tuner Reset Command */
  1013. bitmask = 0x02;
  1014. break;
  1015. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1016. altera_ci_tuner_reset(dev, port->nr);
  1017. break;
  1018. }
  1019. if (bitmask) {
  1020. /* Drive the tuner into reset and back out */
  1021. cx_clear(GP0_IO, bitmask);
  1022. mdelay(200);
  1023. cx_set(GP0_IO, bitmask);
  1024. }
  1025. return 0;
  1026. }
  1027. void cx23885_gpio_setup(struct cx23885_dev *dev)
  1028. {
  1029. switch (dev->board) {
  1030. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1031. /* GPIO-0 cx24227 demodulator reset */
  1032. cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
  1033. break;
  1034. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1035. /* GPIO-0 cx24227 demodulator */
  1036. /* GPIO-2 xc3028 tuner */
  1037. /* Put the parts into reset */
  1038. cx_set(GP0_IO, 0x00050000);
  1039. cx_clear(GP0_IO, 0x00000005);
  1040. msleep(5);
  1041. /* Bring the parts out of reset */
  1042. cx_set(GP0_IO, 0x00050005);
  1043. break;
  1044. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1045. /* GPIO-0 cx24227 demodulator reset */
  1046. /* GPIO-2 xc5000 tuner reset */
  1047. cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
  1048. break;
  1049. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1050. /* GPIO-0 656_CLK */
  1051. /* GPIO-1 656_D0 */
  1052. /* GPIO-2 8295A Reset */
  1053. /* GPIO-3-10 cx23417 data0-7 */
  1054. /* GPIO-11-14 cx23417 addr0-3 */
  1055. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  1056. /* GPIO-19 IR_RX */
  1057. /* CX23417 GPIO's */
  1058. /* EIO15 Zilog Reset */
  1059. /* EIO14 S5H1409/CX24227 Reset */
  1060. mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
  1061. /* Put the demod into reset and protect the eeprom */
  1062. mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
  1063. mdelay(100);
  1064. /* Bring the demod and blaster out of reset */
  1065. mc417_gpio_set(dev, GPIO_15 | GPIO_14);
  1066. mdelay(100);
  1067. /* Force the TDA8295A into reset and back */
  1068. cx23885_gpio_enable(dev, GPIO_2, 1);
  1069. cx23885_gpio_set(dev, GPIO_2);
  1070. mdelay(20);
  1071. cx23885_gpio_clear(dev, GPIO_2);
  1072. mdelay(20);
  1073. cx23885_gpio_set(dev, GPIO_2);
  1074. mdelay(20);
  1075. break;
  1076. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1077. /* GPIO-0 tda10048 demodulator reset */
  1078. /* GPIO-2 tda18271 tuner reset */
  1079. /* Put the parts into reset and back */
  1080. cx_set(GP0_IO, 0x00050000);
  1081. mdelay(20);
  1082. cx_clear(GP0_IO, 0x00000005);
  1083. mdelay(20);
  1084. cx_set(GP0_IO, 0x00050005);
  1085. break;
  1086. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1087. /* GPIO-0 TDA10048 demodulator reset */
  1088. /* GPIO-2 TDA8295A Reset */
  1089. /* GPIO-3-10 cx23417 data0-7 */
  1090. /* GPIO-11-14 cx23417 addr0-3 */
  1091. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  1092. /* The following GPIO's are on the interna AVCore (cx25840) */
  1093. /* GPIO-19 IR_RX */
  1094. /* GPIO-20 IR_TX 416/DVBT Select */
  1095. /* GPIO-21 IIS DAT */
  1096. /* GPIO-22 IIS WCLK */
  1097. /* GPIO-23 IIS BCLK */
  1098. /* Put the parts into reset and back */
  1099. cx_set(GP0_IO, 0x00050000);
  1100. mdelay(20);
  1101. cx_clear(GP0_IO, 0x00000005);
  1102. mdelay(20);
  1103. cx_set(GP0_IO, 0x00050005);
  1104. break;
  1105. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1106. /* GPIO-0 Dibcom7000p demodulator reset */
  1107. /* GPIO-2 xc3028L tuner reset */
  1108. /* GPIO-13 LED */
  1109. /* Put the parts into reset and back */
  1110. cx_set(GP0_IO, 0x00050000);
  1111. mdelay(20);
  1112. cx_clear(GP0_IO, 0x00000005);
  1113. mdelay(20);
  1114. cx_set(GP0_IO, 0x00050005);
  1115. break;
  1116. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  1117. /* GPIO-0 xc5000 tuner reset i2c bus 0 */
  1118. /* GPIO-1 s5h1409 demod reset i2c bus 0 */
  1119. /* GPIO-2 xc5000 tuner reset i2c bus 1 */
  1120. /* GPIO-3 s5h1409 demod reset i2c bus 0 */
  1121. /* Put the parts into reset and back */
  1122. cx_set(GP0_IO, 0x000f0000);
  1123. mdelay(20);
  1124. cx_clear(GP0_IO, 0x0000000f);
  1125. mdelay(20);
  1126. cx_set(GP0_IO, 0x000f000f);
  1127. break;
  1128. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1129. /* GPIO-0 portb xc3028 reset */
  1130. /* GPIO-1 portb zl10353 reset */
  1131. /* GPIO-2 portc xc3028 reset */
  1132. /* GPIO-3 portc zl10353 reset */
  1133. /* Put the parts into reset and back */
  1134. cx_set(GP0_IO, 0x000f0000);
  1135. mdelay(20);
  1136. cx_clear(GP0_IO, 0x0000000f);
  1137. mdelay(20);
  1138. cx_set(GP0_IO, 0x000f000f);
  1139. break;
  1140. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1141. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  1142. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1143. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1144. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  1145. /* GPIO-2 xc3028 tuner reset */
  1146. /* The following GPIO's are on the internal AVCore (cx25840) */
  1147. /* GPIO-? zl10353 demod reset */
  1148. /* Put the parts into reset and back */
  1149. cx_set(GP0_IO, 0x00040000);
  1150. mdelay(20);
  1151. cx_clear(GP0_IO, 0x00000004);
  1152. mdelay(20);
  1153. cx_set(GP0_IO, 0x00040004);
  1154. break;
  1155. case CX23885_BOARD_TBS_6920:
  1156. case CX23885_BOARD_PROF_8000:
  1157. cx_write(MC417_CTL, 0x00000036);
  1158. cx_write(MC417_OEN, 0x00001000);
  1159. cx_set(MC417_RWD, 0x00000002);
  1160. mdelay(200);
  1161. cx_clear(MC417_RWD, 0x00000800);
  1162. mdelay(200);
  1163. cx_set(MC417_RWD, 0x00000800);
  1164. mdelay(200);
  1165. break;
  1166. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1167. /* GPIO-0 INTA from CiMax1
  1168. GPIO-1 INTB from CiMax2
  1169. GPIO-2 reset chips
  1170. GPIO-3 to GPIO-10 data/addr for CA
  1171. GPIO-11 ~CS0 to CiMax1
  1172. GPIO-12 ~CS1 to CiMax2
  1173. GPIO-13 ADL0 load LSB addr
  1174. GPIO-14 ADL1 load MSB addr
  1175. GPIO-15 ~RDY from CiMax
  1176. GPIO-17 ~RD to CiMax
  1177. GPIO-18 ~WR to CiMax
  1178. */
  1179. cx_set(GP0_IO, 0x00040000); /* GPIO as out */
  1180. /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
  1181. cx_clear(GP0_IO, 0x00030004);
  1182. mdelay(100);/* reset delay */
  1183. cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
  1184. cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
  1185. /* GPIO-15 IN as ~ACK, rest as OUT */
  1186. cx_write(MC417_OEN, 0x00001000);
  1187. /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
  1188. cx_write(MC417_RWD, 0x0000c300);
  1189. /* enable irq */
  1190. cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
  1191. break;
  1192. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1193. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1194. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1195. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  1196. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1197. /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
  1198. /* GPIO-6 I2C Gate which can isolate the demod from the bus */
  1199. /* GPIO-9 Demod reset */
  1200. /* Put the parts into reset and back */
  1201. cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
  1202. cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
  1203. cx23885_gpio_clear(dev, GPIO_9);
  1204. mdelay(20);
  1205. cx23885_gpio_set(dev, GPIO_9);
  1206. break;
  1207. case CX23885_BOARD_MYGICA_X8506:
  1208. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1209. case CX23885_BOARD_MYGICA_X8507:
  1210. /* GPIO-0 (0)Analog / (1)Digital TV */
  1211. /* GPIO-1 reset XC5000 */
  1212. /* GPIO-2 reset LGS8GL5 / LGS8G75 */
  1213. cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
  1214. cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
  1215. mdelay(100);
  1216. cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
  1217. mdelay(100);
  1218. break;
  1219. case CX23885_BOARD_MYGICA_X8558PRO:
  1220. /* GPIO-0 reset first ATBM8830 */
  1221. /* GPIO-1 reset second ATBM8830 */
  1222. cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
  1223. cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
  1224. mdelay(100);
  1225. cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
  1226. mdelay(100);
  1227. break;
  1228. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1229. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1230. /* GPIO-0 656_CLK */
  1231. /* GPIO-1 656_D0 */
  1232. /* GPIO-2 Wake# */
  1233. /* GPIO-3-10 cx23417 data0-7 */
  1234. /* GPIO-11-14 cx23417 addr0-3 */
  1235. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  1236. /* GPIO-19 IR_RX */
  1237. /* GPIO-20 C_IR_TX */
  1238. /* GPIO-21 I2S DAT */
  1239. /* GPIO-22 I2S WCLK */
  1240. /* GPIO-23 I2S BCLK */
  1241. /* ALT GPIO: EXP GPIO LATCH */
  1242. /* CX23417 GPIO's */
  1243. /* GPIO-14 S5H1411/CX24228 Reset */
  1244. /* GPIO-13 EEPROM write protect */
  1245. mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
  1246. /* Put the demod into reset and protect the eeprom */
  1247. mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
  1248. mdelay(100);
  1249. /* Bring the demod out of reset */
  1250. mc417_gpio_set(dev, GPIO_14);
  1251. mdelay(100);
  1252. /* CX24228 GPIO */
  1253. /* Connected to IF / Mux */
  1254. break;
  1255. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1256. cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
  1257. break;
  1258. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1259. /* GPIO-0 ~INT in
  1260. GPIO-1 TMS out
  1261. GPIO-2 ~reset chips out
  1262. GPIO-3 to GPIO-10 data/addr for CA in/out
  1263. GPIO-11 ~CS out
  1264. GPIO-12 ADDR out
  1265. GPIO-13 ~WR out
  1266. GPIO-14 ~RD out
  1267. GPIO-15 ~RDY in
  1268. GPIO-16 TCK out
  1269. GPIO-17 TDO in
  1270. GPIO-18 TDI out
  1271. */
  1272. cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
  1273. /* GPIO-0 as INT, reset & TMS low */
  1274. cx_clear(GP0_IO, 0x00010006);
  1275. mdelay(100);/* reset delay */
  1276. cx_set(GP0_IO, 0x00000004); /* reset high */
  1277. cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */
  1278. /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */
  1279. cx_write(MC417_OEN, 0x00005000);
  1280. /* ~RD, ~WR high; ADDR low; ~CS high */
  1281. cx_write(MC417_RWD, 0x00000d00);
  1282. /* enable irq */
  1283. cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
  1284. break;
  1285. case CX23885_BOARD_HAUPPAUGE_HVR4400:
  1286. /* GPIO-8 tda10071 demod reset */
  1287. /* Put the parts into reset and back */
  1288. cx23885_gpio_enable(dev, GPIO_8, 1);
  1289. cx23885_gpio_clear(dev, GPIO_8);
  1290. mdelay(100);
  1291. cx23885_gpio_set(dev, GPIO_8);
  1292. mdelay(100);
  1293. break;
  1294. }
  1295. }
  1296. int cx23885_ir_init(struct cx23885_dev *dev)
  1297. {
  1298. static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
  1299. {
  1300. .flags = V4L2_SUBDEV_IO_PIN_INPUT,
  1301. .pin = CX23885_PIN_IR_RX_GPIO19,
  1302. .function = CX23885_PAD_IR_RX,
  1303. .value = 0,
  1304. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1305. }, {
  1306. .flags = V4L2_SUBDEV_IO_PIN_OUTPUT,
  1307. .pin = CX23885_PIN_IR_TX_GPIO20,
  1308. .function = CX23885_PAD_IR_TX,
  1309. .value = 0,
  1310. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1311. }
  1312. };
  1313. const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
  1314. static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
  1315. {
  1316. .flags = V4L2_SUBDEV_IO_PIN_INPUT,
  1317. .pin = CX23885_PIN_IR_RX_GPIO19,
  1318. .function = CX23885_PAD_IR_RX,
  1319. .value = 0,
  1320. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1321. }
  1322. };
  1323. const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
  1324. struct v4l2_subdev_ir_parameters params;
  1325. int ret = 0;
  1326. switch (dev->board) {
  1327. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1328. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1329. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1330. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1331. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1332. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1333. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1334. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  1335. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1336. /* FIXME: Implement me */
  1337. break;
  1338. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1339. ret = cx23888_ir_probe(dev);
  1340. if (ret)
  1341. break;
  1342. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
  1343. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1344. ir_rx_pin_cfg_count, ir_rx_pin_cfg);
  1345. break;
  1346. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1347. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1348. ret = cx23888_ir_probe(dev);
  1349. if (ret)
  1350. break;
  1351. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
  1352. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1353. ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
  1354. /*
  1355. * For these boards we need to invert the Tx output via the
  1356. * IR controller to have the LED off while idle
  1357. */
  1358. v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, &params);
  1359. params.enable = false;
  1360. params.shutdown = false;
  1361. params.invert_level = true;
  1362. v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
  1363. params.shutdown = true;
  1364. v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
  1365. break;
  1366. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1367. case CX23885_BOARD_TEVII_S470:
  1368. if (!enable_885_ir)
  1369. break;
  1370. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
  1371. if (dev->sd_ir == NULL) {
  1372. ret = -ENODEV;
  1373. break;
  1374. }
  1375. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1376. ir_rx_pin_cfg_count, ir_rx_pin_cfg);
  1377. break;
  1378. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1379. if (!enable_885_ir)
  1380. break;
  1381. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
  1382. if (dev->sd_ir == NULL) {
  1383. ret = -ENODEV;
  1384. break;
  1385. }
  1386. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1387. ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
  1388. break;
  1389. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1390. request_module("ir-kbd-i2c");
  1391. break;
  1392. }
  1393. return ret;
  1394. }
  1395. void cx23885_ir_fini(struct cx23885_dev *dev)
  1396. {
  1397. switch (dev->board) {
  1398. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1399. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1400. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1401. cx23885_irq_remove(dev, PCI_MSK_IR);
  1402. cx23888_ir_remove(dev);
  1403. dev->sd_ir = NULL;
  1404. break;
  1405. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1406. case CX23885_BOARD_TEVII_S470:
  1407. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1408. cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
  1409. /* sd_ir is a duplicate pointer to the AV Core, just clear it */
  1410. dev->sd_ir = NULL;
  1411. break;
  1412. }
  1413. }
  1414. static int netup_jtag_io(void *device, int tms, int tdi, int read_tdo)
  1415. {
  1416. int data;
  1417. int tdo = 0;
  1418. struct cx23885_dev *dev = (struct cx23885_dev *)device;
  1419. /*TMS*/
  1420. data = ((cx_read(GP0_IO)) & (~0x00000002));
  1421. data |= (tms ? 0x00020002 : 0x00020000);
  1422. cx_write(GP0_IO, data);
  1423. /*TDI*/
  1424. data = ((cx_read(MC417_RWD)) & (~0x0000a000));
  1425. data |= (tdi ? 0x00008000 : 0);
  1426. cx_write(MC417_RWD, data);
  1427. if (read_tdo)
  1428. tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/
  1429. cx_write(MC417_RWD, data | 0x00002000);
  1430. udelay(1);
  1431. /*TCK*/
  1432. cx_write(MC417_RWD, data);
  1433. return tdo;
  1434. }
  1435. void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
  1436. {
  1437. switch (dev->board) {
  1438. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1439. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1440. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1441. if (dev->sd_ir)
  1442. cx23885_irq_add_enable(dev, PCI_MSK_IR);
  1443. break;
  1444. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1445. case CX23885_BOARD_TEVII_S470:
  1446. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1447. if (dev->sd_ir)
  1448. cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
  1449. break;
  1450. }
  1451. }
  1452. void cx23885_card_setup(struct cx23885_dev *dev)
  1453. {
  1454. struct cx23885_tsport *ts1 = &dev->ts1;
  1455. struct cx23885_tsport *ts2 = &dev->ts2;
  1456. static u8 eeprom[256];
  1457. if (dev->i2c_bus[0].i2c_rc == 0) {
  1458. dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
  1459. tveeprom_read(&dev->i2c_bus[0].i2c_client,
  1460. eeprom, sizeof(eeprom));
  1461. }
  1462. switch (dev->board) {
  1463. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1464. if (dev->i2c_bus[0].i2c_rc == 0) {
  1465. if (eeprom[0x80] != 0x84)
  1466. hauppauge_eeprom(dev, eeprom+0xc0);
  1467. else
  1468. hauppauge_eeprom(dev, eeprom+0x80);
  1469. }
  1470. break;
  1471. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1472. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1473. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1474. if (dev->i2c_bus[0].i2c_rc == 0)
  1475. hauppauge_eeprom(dev, eeprom+0x80);
  1476. break;
  1477. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1478. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1479. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1480. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1481. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1482. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1483. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1484. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  1485. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1486. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1487. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1488. case CX23885_BOARD_HAUPPAUGE_HVR4400:
  1489. if (dev->i2c_bus[0].i2c_rc == 0)
  1490. hauppauge_eeprom(dev, eeprom+0xc0);
  1491. break;
  1492. }
  1493. switch (dev->board) {
  1494. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  1495. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1496. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1497. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1498. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1499. /* break omitted intentionally */
  1500. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  1501. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1502. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1503. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1504. break;
  1505. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1506. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1507. /* Defaults for VID B - Analog encoder */
  1508. /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
  1509. ts1->gen_ctrl_val = 0x10e;
  1510. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1511. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1512. /* APB_TSVALERR_POL (active low)*/
  1513. ts1->vld_misc_val = 0x2000;
  1514. ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
  1515. cx_write(0x130184, 0xc);
  1516. /* Defaults for VID C */
  1517. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1518. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1519. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1520. break;
  1521. case CX23885_BOARD_TBS_6920:
  1522. ts1->gen_ctrl_val = 0x4; /* Parallel */
  1523. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1524. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1525. break;
  1526. case CX23885_BOARD_TEVII_S470:
  1527. case CX23885_BOARD_TEVII_S471:
  1528. case CX23885_BOARD_DVBWORLD_2005:
  1529. case CX23885_BOARD_PROF_8000:
  1530. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1531. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1532. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1533. break;
  1534. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1535. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1536. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1537. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1538. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1539. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1540. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1541. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1542. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1543. break;
  1544. case CX23885_BOARD_MYGICA_X8506:
  1545. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1546. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1547. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1548. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1549. break;
  1550. case CX23885_BOARD_MYGICA_X8558PRO:
  1551. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1552. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1553. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1554. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1555. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1556. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1557. break;
  1558. case CX23885_BOARD_HAUPPAUGE_HVR4400:
  1559. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1560. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1561. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1562. break;
  1563. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1564. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1565. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1566. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1567. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1568. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1569. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1570. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1571. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  1572. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1573. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1574. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1575. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1576. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  1577. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1578. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1579. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1580. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1581. default:
  1582. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1583. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1584. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1585. }
  1586. /* Certain boards support analog, or require the avcore to be
  1587. * loaded, ensure this happens.
  1588. */
  1589. switch (dev->board) {
  1590. case CX23885_BOARD_TEVII_S470:
  1591. /* Currently only enabled for the integrated IR controller */
  1592. if (!enable_885_ir)
  1593. break;
  1594. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1595. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1596. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1597. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1598. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1599. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  1600. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1601. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1602. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1603. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1604. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1605. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  1606. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1607. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1608. case CX23885_BOARD_MYGICA_X8506:
  1609. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1610. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1611. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  1612. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1613. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1614. case CX23885_BOARD_MPX885:
  1615. case CX23885_BOARD_MYGICA_X8507:
  1616. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1617. dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
  1618. &dev->i2c_bus[2].i2c_adap,
  1619. "cx25840", 0x88 >> 1, NULL);
  1620. if (dev->sd_cx25840) {
  1621. dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
  1622. v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
  1623. }
  1624. break;
  1625. }
  1626. /* AUX-PLL 27MHz CLK */
  1627. switch (dev->board) {
  1628. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1629. netup_initialize(dev);
  1630. break;
  1631. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
  1632. int ret;
  1633. const struct firmware *fw;
  1634. const char *filename = "dvb-netup-altera-01.fw";
  1635. char *action = "configure";
  1636. static struct netup_card_info cinfo;
  1637. struct altera_config netup_config = {
  1638. .dev = dev,
  1639. .action = action,
  1640. .jtag_io = netup_jtag_io,
  1641. };
  1642. netup_initialize(dev);
  1643. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  1644. if (netup_card_rev)
  1645. cinfo.rev = netup_card_rev;
  1646. switch (cinfo.rev) {
  1647. case 0x4:
  1648. filename = "dvb-netup-altera-04.fw";
  1649. break;
  1650. default:
  1651. filename = "dvb-netup-altera-01.fw";
  1652. break;
  1653. }
  1654. printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n",
  1655. cinfo.rev, filename);
  1656. ret = request_firmware(&fw, filename, &dev->pci->dev);
  1657. if (ret != 0)
  1658. printk(KERN_ERR "did not find the firmware file. (%s) "
  1659. "Please see linux/Documentation/dvb/ for more details "
  1660. "on firmware-problems.", filename);
  1661. else
  1662. altera_init(&netup_config, fw);
  1663. release_firmware(fw);
  1664. break;
  1665. }
  1666. }
  1667. }
  1668. /* ------------------------------------------------------------------ */