radeon_ring.c 18 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <linux/seq_file.h>
  29. #include <linux/slab.h>
  30. #include "drmP.h"
  31. #include "radeon_drm.h"
  32. #include "radeon_reg.h"
  33. #include "radeon.h"
  34. #include "atom.h"
  35. int radeon_debugfs_ib_init(struct radeon_device *rdev);
  36. int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);
  37. u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
  38. {
  39. struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
  40. u32 pg_idx, pg_offset;
  41. u32 idx_value = 0;
  42. int new_page;
  43. pg_idx = (idx * 4) / PAGE_SIZE;
  44. pg_offset = (idx * 4) % PAGE_SIZE;
  45. if (ibc->kpage_idx[0] == pg_idx)
  46. return ibc->kpage[0][pg_offset/4];
  47. if (ibc->kpage_idx[1] == pg_idx)
  48. return ibc->kpage[1][pg_offset/4];
  49. new_page = radeon_cs_update_pages(p, pg_idx);
  50. if (new_page < 0) {
  51. p->parser_error = new_page;
  52. return 0;
  53. }
  54. idx_value = ibc->kpage[new_page][pg_offset/4];
  55. return idx_value;
  56. }
  57. void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
  58. {
  59. #if DRM_DEBUG_CODE
  60. if (ring->count_dw <= 0) {
  61. DRM_ERROR("radeon: writting more dword to ring than expected !\n");
  62. }
  63. #endif
  64. ring->ring[ring->wptr++] = v;
  65. ring->wptr &= ring->ptr_mask;
  66. ring->count_dw--;
  67. ring->ring_free_dw--;
  68. }
  69. /*
  70. * IB.
  71. */
  72. bool radeon_ib_try_free(struct radeon_device *rdev, struct radeon_ib *ib)
  73. {
  74. bool done = false;
  75. /* only free ib which have been emited */
  76. if (ib->fence && ib->fence->emitted) {
  77. if (radeon_fence_signaled(ib->fence)) {
  78. radeon_fence_unref(&ib->fence);
  79. radeon_sa_bo_free(rdev, &ib->sa_bo);
  80. done = true;
  81. }
  82. }
  83. return done;
  84. }
  85. int radeon_ib_get(struct radeon_device *rdev, int ring,
  86. struct radeon_ib **ib, unsigned size)
  87. {
  88. struct radeon_fence *fence;
  89. unsigned cretry = 0;
  90. int r = 0, i, idx;
  91. *ib = NULL;
  92. /* align size on 256 bytes */
  93. size = ALIGN(size, 256);
  94. r = radeon_fence_create(rdev, &fence, ring);
  95. if (r) {
  96. dev_err(rdev->dev, "failed to create fence for new IB\n");
  97. return r;
  98. }
  99. radeon_mutex_lock(&rdev->ib_pool.mutex);
  100. idx = rdev->ib_pool.head_id;
  101. retry:
  102. if (cretry > 5) {
  103. dev_err(rdev->dev, "failed to get an ib after 5 retry\n");
  104. radeon_mutex_unlock(&rdev->ib_pool.mutex);
  105. radeon_fence_unref(&fence);
  106. return -ENOMEM;
  107. }
  108. cretry++;
  109. for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
  110. radeon_ib_try_free(rdev, &rdev->ib_pool.ibs[idx]);
  111. if (rdev->ib_pool.ibs[idx].fence == NULL) {
  112. r = radeon_sa_bo_new(rdev, &rdev->ib_pool.sa_manager,
  113. &rdev->ib_pool.ibs[idx].sa_bo,
  114. size, 256);
  115. if (!r) {
  116. *ib = &rdev->ib_pool.ibs[idx];
  117. (*ib)->ptr = rdev->ib_pool.sa_manager.cpu_ptr;
  118. (*ib)->ptr += ((*ib)->sa_bo.offset >> 2);
  119. (*ib)->gpu_addr = rdev->ib_pool.sa_manager.gpu_addr;
  120. (*ib)->gpu_addr += (*ib)->sa_bo.offset;
  121. (*ib)->fence = fence;
  122. (*ib)->vm_id = 0;
  123. (*ib)->is_const_ib = false;
  124. /* ib are most likely to be allocated in a ring fashion
  125. * thus rdev->ib_pool.head_id should be the id of the
  126. * oldest ib
  127. */
  128. rdev->ib_pool.head_id = (1 + idx);
  129. rdev->ib_pool.head_id &= (RADEON_IB_POOL_SIZE - 1);
  130. radeon_mutex_unlock(&rdev->ib_pool.mutex);
  131. return 0;
  132. }
  133. }
  134. idx = (idx + 1) & (RADEON_IB_POOL_SIZE - 1);
  135. }
  136. /* this should be rare event, ie all ib scheduled none signaled yet.
  137. */
  138. for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
  139. if (rdev->ib_pool.ibs[idx].fence && rdev->ib_pool.ibs[idx].fence->emitted) {
  140. r = radeon_fence_wait(rdev->ib_pool.ibs[idx].fence, false);
  141. if (!r) {
  142. goto retry;
  143. }
  144. /* an error happened */
  145. break;
  146. }
  147. idx = (idx + 1) & (RADEON_IB_POOL_SIZE - 1);
  148. }
  149. radeon_mutex_unlock(&rdev->ib_pool.mutex);
  150. radeon_fence_unref(&fence);
  151. return r;
  152. }
  153. void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
  154. {
  155. struct radeon_ib *tmp = *ib;
  156. *ib = NULL;
  157. if (tmp == NULL) {
  158. return;
  159. }
  160. radeon_mutex_lock(&rdev->ib_pool.mutex);
  161. if (tmp->fence && !tmp->fence->emitted) {
  162. radeon_sa_bo_free(rdev, &tmp->sa_bo);
  163. radeon_fence_unref(&tmp->fence);
  164. }
  165. radeon_mutex_unlock(&rdev->ib_pool.mutex);
  166. }
  167. int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
  168. {
  169. struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
  170. int r = 0;
  171. if (!ib->length_dw || !ring->ready) {
  172. /* TODO: Nothings in the ib we should report. */
  173. DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx);
  174. return -EINVAL;
  175. }
  176. /* 64 dwords should be enough for fence too */
  177. r = radeon_ring_lock(rdev, ring, 64);
  178. if (r) {
  179. DRM_ERROR("radeon: scheduling IB failed (%d).\n", r);
  180. return r;
  181. }
  182. radeon_ring_ib_execute(rdev, ib->fence->ring, ib);
  183. radeon_fence_emit(rdev, ib->fence);
  184. radeon_ring_unlock_commit(rdev, ring);
  185. return 0;
  186. }
  187. int radeon_ib_pool_init(struct radeon_device *rdev)
  188. {
  189. struct radeon_sa_manager tmp;
  190. int i, r;
  191. r = radeon_sa_bo_manager_init(rdev, &tmp,
  192. RADEON_IB_POOL_SIZE*64*1024,
  193. RADEON_GEM_DOMAIN_GTT);
  194. if (r) {
  195. return r;
  196. }
  197. radeon_mutex_lock(&rdev->ib_pool.mutex);
  198. if (rdev->ib_pool.ready) {
  199. radeon_mutex_unlock(&rdev->ib_pool.mutex);
  200. radeon_sa_bo_manager_fini(rdev, &tmp);
  201. return 0;
  202. }
  203. rdev->ib_pool.sa_manager = tmp;
  204. INIT_LIST_HEAD(&rdev->ib_pool.sa_manager.sa_bo);
  205. for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
  206. rdev->ib_pool.ibs[i].fence = NULL;
  207. rdev->ib_pool.ibs[i].idx = i;
  208. rdev->ib_pool.ibs[i].length_dw = 0;
  209. INIT_LIST_HEAD(&rdev->ib_pool.ibs[i].sa_bo.list);
  210. }
  211. rdev->ib_pool.head_id = 0;
  212. rdev->ib_pool.ready = true;
  213. DRM_INFO("radeon: ib pool ready.\n");
  214. if (radeon_debugfs_ib_init(rdev)) {
  215. DRM_ERROR("Failed to register debugfs file for IB !\n");
  216. }
  217. radeon_mutex_unlock(&rdev->ib_pool.mutex);
  218. return 0;
  219. }
  220. void radeon_ib_pool_fini(struct radeon_device *rdev)
  221. {
  222. unsigned i;
  223. radeon_mutex_lock(&rdev->ib_pool.mutex);
  224. if (rdev->ib_pool.ready) {
  225. for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
  226. radeon_sa_bo_free(rdev, &rdev->ib_pool.ibs[i].sa_bo);
  227. radeon_fence_unref(&rdev->ib_pool.ibs[i].fence);
  228. }
  229. radeon_sa_bo_manager_fini(rdev, &rdev->ib_pool.sa_manager);
  230. rdev->ib_pool.ready = false;
  231. }
  232. radeon_mutex_unlock(&rdev->ib_pool.mutex);
  233. }
  234. int radeon_ib_pool_start(struct radeon_device *rdev)
  235. {
  236. return radeon_sa_bo_manager_start(rdev, &rdev->ib_pool.sa_manager);
  237. }
  238. int radeon_ib_pool_suspend(struct radeon_device *rdev)
  239. {
  240. return radeon_sa_bo_manager_suspend(rdev, &rdev->ib_pool.sa_manager);
  241. }
  242. int radeon_ib_ring_tests(struct radeon_device *rdev)
  243. {
  244. unsigned i;
  245. int r;
  246. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  247. struct radeon_ring *ring = &rdev->ring[i];
  248. if (!ring->ready)
  249. continue;
  250. r = radeon_ib_test(rdev, i, ring);
  251. if (r) {
  252. ring->ready = false;
  253. if (i == RADEON_RING_TYPE_GFX_INDEX) {
  254. /* oh, oh, that's really bad */
  255. DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r);
  256. rdev->accel_working = false;
  257. return r;
  258. } else {
  259. /* still not good, but we can live with it */
  260. DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r);
  261. }
  262. }
  263. }
  264. return 0;
  265. }
  266. /*
  267. * Ring.
  268. */
  269. int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *ring)
  270. {
  271. /* r1xx-r5xx only has CP ring */
  272. if (rdev->family < CHIP_R600)
  273. return RADEON_RING_TYPE_GFX_INDEX;
  274. if (rdev->family >= CHIP_CAYMAN) {
  275. if (ring == &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX])
  276. return CAYMAN_RING_TYPE_CP1_INDEX;
  277. else if (ring == &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX])
  278. return CAYMAN_RING_TYPE_CP2_INDEX;
  279. }
  280. return RADEON_RING_TYPE_GFX_INDEX;
  281. }
  282. void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
  283. {
  284. u32 rptr;
  285. if (rdev->wb.enabled)
  286. rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
  287. else
  288. rptr = RREG32(ring->rptr_reg);
  289. ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
  290. /* This works because ring_size is a power of 2 */
  291. ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4));
  292. ring->ring_free_dw -= ring->wptr;
  293. ring->ring_free_dw &= ring->ptr_mask;
  294. if (!ring->ring_free_dw) {
  295. ring->ring_free_dw = ring->ring_size / 4;
  296. }
  297. }
  298. int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
  299. {
  300. int r;
  301. /* Align requested size with padding so unlock_commit can
  302. * pad safely */
  303. ndw = (ndw + ring->align_mask) & ~ring->align_mask;
  304. while (ndw > (ring->ring_free_dw - 1)) {
  305. radeon_ring_free_size(rdev, ring);
  306. if (ndw < ring->ring_free_dw) {
  307. break;
  308. }
  309. mutex_unlock(&ring->mutex);
  310. r = radeon_fence_wait_next(rdev, radeon_ring_index(rdev, ring));
  311. mutex_lock(&ring->mutex);
  312. if (r)
  313. return r;
  314. }
  315. ring->count_dw = ndw;
  316. ring->wptr_old = ring->wptr;
  317. return 0;
  318. }
  319. int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
  320. {
  321. int r;
  322. mutex_lock(&ring->mutex);
  323. r = radeon_ring_alloc(rdev, ring, ndw);
  324. if (r) {
  325. mutex_unlock(&ring->mutex);
  326. return r;
  327. }
  328. return 0;
  329. }
  330. void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)
  331. {
  332. unsigned count_dw_pad;
  333. unsigned i;
  334. /* We pad to match fetch size */
  335. count_dw_pad = (ring->align_mask + 1) -
  336. (ring->wptr & ring->align_mask);
  337. for (i = 0; i < count_dw_pad; i++) {
  338. radeon_ring_write(ring, ring->nop);
  339. }
  340. DRM_MEMORYBARRIER();
  341. WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask);
  342. (void)RREG32(ring->wptr_reg);
  343. }
  344. void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring)
  345. {
  346. radeon_ring_commit(rdev, ring);
  347. mutex_unlock(&ring->mutex);
  348. }
  349. void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)
  350. {
  351. ring->wptr = ring->wptr_old;
  352. mutex_unlock(&ring->mutex);
  353. }
  354. void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring)
  355. {
  356. int r;
  357. mutex_lock(&ring->mutex);
  358. radeon_ring_free_size(rdev, ring);
  359. if (ring->rptr == ring->wptr) {
  360. r = radeon_ring_alloc(rdev, ring, 1);
  361. if (!r) {
  362. radeon_ring_write(ring, ring->nop);
  363. radeon_ring_commit(rdev, ring);
  364. }
  365. }
  366. mutex_unlock(&ring->mutex);
  367. }
  368. void radeon_ring_lockup_update(struct radeon_ring *ring)
  369. {
  370. ring->last_rptr = ring->rptr;
  371. ring->last_activity = jiffies;
  372. }
  373. /**
  374. * radeon_ring_test_lockup() - check if ring is lockedup by recording information
  375. * @rdev: radeon device structure
  376. * @ring: radeon_ring structure holding ring information
  377. *
  378. * We don't need to initialize the lockup tracking information as we will either
  379. * have CP rptr to a different value of jiffies wrap around which will force
  380. * initialization of the lockup tracking informations.
  381. *
  382. * A possible false positivie is if we get call after while and last_cp_rptr ==
  383. * the current CP rptr, even if it's unlikely it might happen. To avoid this
  384. * if the elapsed time since last call is bigger than 2 second than we return
  385. * false and update the tracking information. Due to this the caller must call
  386. * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported
  387. * the fencing code should be cautious about that.
  388. *
  389. * Caller should write to the ring to force CP to do something so we don't get
  390. * false positive when CP is just gived nothing to do.
  391. *
  392. **/
  393. bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
  394. {
  395. unsigned long cjiffies, elapsed;
  396. uint32_t rptr;
  397. cjiffies = jiffies;
  398. if (!time_after(cjiffies, ring->last_activity)) {
  399. /* likely a wrap around */
  400. radeon_ring_lockup_update(ring);
  401. return false;
  402. }
  403. rptr = RREG32(ring->rptr_reg);
  404. ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
  405. if (ring->rptr != ring->last_rptr) {
  406. /* CP is still working no lockup */
  407. radeon_ring_lockup_update(ring);
  408. return false;
  409. }
  410. elapsed = jiffies_to_msecs(cjiffies - ring->last_activity);
  411. if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) {
  412. dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
  413. return true;
  414. }
  415. /* give a chance to the GPU ... */
  416. return false;
  417. }
  418. int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
  419. unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
  420. u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop)
  421. {
  422. int r;
  423. ring->ring_size = ring_size;
  424. ring->rptr_offs = rptr_offs;
  425. ring->rptr_reg = rptr_reg;
  426. ring->wptr_reg = wptr_reg;
  427. ring->ptr_reg_shift = ptr_reg_shift;
  428. ring->ptr_reg_mask = ptr_reg_mask;
  429. ring->nop = nop;
  430. /* Allocate ring buffer */
  431. if (ring->ring_obj == NULL) {
  432. r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
  433. RADEON_GEM_DOMAIN_GTT,
  434. &ring->ring_obj);
  435. if (r) {
  436. dev_err(rdev->dev, "(%d) ring create failed\n", r);
  437. return r;
  438. }
  439. r = radeon_bo_reserve(ring->ring_obj, false);
  440. if (unlikely(r != 0))
  441. return r;
  442. r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
  443. &ring->gpu_addr);
  444. if (r) {
  445. radeon_bo_unreserve(ring->ring_obj);
  446. dev_err(rdev->dev, "(%d) ring pin failed\n", r);
  447. return r;
  448. }
  449. r = radeon_bo_kmap(ring->ring_obj,
  450. (void **)&ring->ring);
  451. radeon_bo_unreserve(ring->ring_obj);
  452. if (r) {
  453. dev_err(rdev->dev, "(%d) ring map failed\n", r);
  454. return r;
  455. }
  456. }
  457. ring->ptr_mask = (ring->ring_size / 4) - 1;
  458. ring->ring_free_dw = ring->ring_size / 4;
  459. if (radeon_debugfs_ring_init(rdev, ring)) {
  460. DRM_ERROR("Failed to register debugfs file for rings !\n");
  461. }
  462. return 0;
  463. }
  464. void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)
  465. {
  466. int r;
  467. struct radeon_bo *ring_obj;
  468. mutex_lock(&ring->mutex);
  469. ring_obj = ring->ring_obj;
  470. ring->ring = NULL;
  471. ring->ring_obj = NULL;
  472. mutex_unlock(&ring->mutex);
  473. if (ring_obj) {
  474. r = radeon_bo_reserve(ring_obj, false);
  475. if (likely(r == 0)) {
  476. radeon_bo_kunmap(ring_obj);
  477. radeon_bo_unpin(ring_obj);
  478. radeon_bo_unreserve(ring_obj);
  479. }
  480. radeon_bo_unref(&ring_obj);
  481. }
  482. }
  483. /*
  484. * Debugfs info
  485. */
  486. #if defined(CONFIG_DEBUG_FS)
  487. static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
  488. {
  489. struct drm_info_node *node = (struct drm_info_node *) m->private;
  490. struct drm_device *dev = node->minor->dev;
  491. struct radeon_device *rdev = dev->dev_private;
  492. int ridx = *(int*)node->info_ent->data;
  493. struct radeon_ring *ring = &rdev->ring[ridx];
  494. unsigned count, i, j;
  495. radeon_ring_free_size(rdev, ring);
  496. count = (ring->ring_size / 4) - ring->ring_free_dw;
  497. seq_printf(m, "wptr(0x%04x): 0x%08x\n", ring->wptr_reg, RREG32(ring->wptr_reg));
  498. seq_printf(m, "rptr(0x%04x): 0x%08x\n", ring->rptr_reg, RREG32(ring->rptr_reg));
  499. seq_printf(m, "driver's copy of the wptr: 0x%08x\n", ring->wptr);
  500. seq_printf(m, "driver's copy of the rptr: 0x%08x\n", ring->rptr);
  501. seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
  502. seq_printf(m, "%u dwords in ring\n", count);
  503. i = ring->rptr;
  504. for (j = 0; j <= count; j++) {
  505. seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
  506. i = (i + 1) & ring->ptr_mask;
  507. }
  508. return 0;
  509. }
  510. static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
  511. static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
  512. static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
  513. static struct drm_info_list radeon_debugfs_ring_info_list[] = {
  514. {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index},
  515. {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index},
  516. {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index},
  517. };
  518. static int radeon_debugfs_ib_info(struct seq_file *m, void *data)
  519. {
  520. struct drm_info_node *node = (struct drm_info_node *) m->private;
  521. struct drm_device *dev = node->minor->dev;
  522. struct radeon_device *rdev = dev->dev_private;
  523. struct radeon_ib *ib = &rdev->ib_pool.ibs[*((unsigned*)node->info_ent->data)];
  524. unsigned i;
  525. if (ib == NULL) {
  526. return 0;
  527. }
  528. seq_printf(m, "IB %04u\n", ib->idx);
  529. seq_printf(m, "IB fence %p\n", ib->fence);
  530. seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
  531. for (i = 0; i < ib->length_dw; i++) {
  532. seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
  533. }
  534. return 0;
  535. }
  536. static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE];
  537. static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32];
  538. static unsigned radeon_debugfs_ib_idx[RADEON_IB_POOL_SIZE];
  539. #endif
  540. int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring)
  541. {
  542. #if defined(CONFIG_DEBUG_FS)
  543. unsigned i;
  544. for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) {
  545. struct drm_info_list *info = &radeon_debugfs_ring_info_list[i];
  546. int ridx = *(int*)radeon_debugfs_ring_info_list[i].data;
  547. unsigned r;
  548. if (&rdev->ring[ridx] != ring)
  549. continue;
  550. r = radeon_debugfs_add_files(rdev, info, 1);
  551. if (r)
  552. return r;
  553. }
  554. #endif
  555. return 0;
  556. }
  557. int radeon_debugfs_ib_init(struct radeon_device *rdev)
  558. {
  559. #if defined(CONFIG_DEBUG_FS)
  560. unsigned i;
  561. for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
  562. sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i);
  563. radeon_debugfs_ib_idx[i] = i;
  564. radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i];
  565. radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info;
  566. radeon_debugfs_ib_list[i].driver_features = 0;
  567. radeon_debugfs_ib_list[i].data = &radeon_debugfs_ib_idx[i];
  568. }
  569. return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list,
  570. RADEON_IB_POOL_SIZE);
  571. #else
  572. return 0;
  573. #endif
  574. }