cs4231.c 62 KB

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  1. /*
  2. * Driver for CS4231 sound chips found on Sparcs.
  3. * Copyright (C) 2002 David S. Miller <davem@redhat.com>
  4. *
  5. * Based entirely upon drivers/sbus/audio/cs4231.c which is:
  6. * Copyright (C) 1996, 1997, 1998, 1998 Derrick J Brashear (shadow@andrew.cmu.edu)
  7. * and also sound/isa/cs423x/cs4231_lib.c which is:
  8. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/slab.h>
  13. #include <linux/delay.h>
  14. #include <linux/init.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/moduleparam.h>
  17. #include <sound/driver.h>
  18. #include <sound/core.h>
  19. #include <sound/pcm.h>
  20. #include <sound/info.h>
  21. #include <sound/control.h>
  22. #include <sound/timer.h>
  23. #include <sound/initval.h>
  24. #include <sound/pcm_params.h>
  25. #include <asm/io.h>
  26. #include <asm/irq.h>
  27. #ifdef CONFIG_SBUS
  28. #define SBUS_SUPPORT
  29. #include <asm/sbus.h>
  30. #endif
  31. #if defined(CONFIG_PCI) && defined(CONFIG_SPARC64)
  32. #define EBUS_SUPPORT
  33. #include <linux/pci.h>
  34. #include <asm/ebus.h>
  35. #endif
  36. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  37. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  38. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  39. module_param_array(index, int, NULL, 0444);
  40. MODULE_PARM_DESC(index, "Index value for Sun CS4231 soundcard.");
  41. module_param_array(id, charp, NULL, 0444);
  42. MODULE_PARM_DESC(id, "ID string for Sun CS4231 soundcard.");
  43. module_param_array(enable, bool, NULL, 0444);
  44. MODULE_PARM_DESC(enable, "Enable Sun CS4231 soundcard.");
  45. MODULE_AUTHOR("Jaroslav Kysela, Derrick J. Brashear and David S. Miller");
  46. MODULE_DESCRIPTION("Sun CS4231");
  47. MODULE_LICENSE("GPL");
  48. MODULE_SUPPORTED_DEVICE("{{Sun,CS4231}}");
  49. #ifdef SBUS_SUPPORT
  50. struct sbus_dma_info {
  51. spinlock_t lock;
  52. int dir;
  53. void __iomem *regs;
  54. };
  55. #endif
  56. struct snd_cs4231;
  57. struct cs4231_dma_control {
  58. void (*prepare)(struct cs4231_dma_control *dma_cont, int dir);
  59. void (*enable)(struct cs4231_dma_control *dma_cont, int on);
  60. int (*request)(struct cs4231_dma_control *dma_cont, dma_addr_t bus_addr, size_t len);
  61. unsigned int (*address)(struct cs4231_dma_control *dma_cont);
  62. void (*preallocate)(struct snd_cs4231 *chip, struct snd_pcm *pcm);
  63. #ifdef EBUS_SUPPORT
  64. struct ebus_dma_info ebus_info;
  65. #endif
  66. #ifdef SBUS_SUPPORT
  67. struct sbus_dma_info sbus_info;
  68. #endif
  69. };
  70. struct snd_cs4231 {
  71. spinlock_t lock;
  72. void __iomem *port;
  73. struct cs4231_dma_control p_dma;
  74. struct cs4231_dma_control c_dma;
  75. u32 flags;
  76. #define CS4231_FLAG_EBUS 0x00000001
  77. #define CS4231_FLAG_PLAYBACK 0x00000002
  78. #define CS4231_FLAG_CAPTURE 0x00000004
  79. struct snd_card *card;
  80. struct snd_pcm *pcm;
  81. struct snd_pcm_substream *playback_substream;
  82. unsigned int p_periods_sent;
  83. struct snd_pcm_substream *capture_substream;
  84. unsigned int c_periods_sent;
  85. struct snd_timer *timer;
  86. unsigned short mode;
  87. #define CS4231_MODE_NONE 0x0000
  88. #define CS4231_MODE_PLAY 0x0001
  89. #define CS4231_MODE_RECORD 0x0002
  90. #define CS4231_MODE_TIMER 0x0004
  91. #define CS4231_MODE_OPEN (CS4231_MODE_PLAY|CS4231_MODE_RECORD|CS4231_MODE_TIMER)
  92. unsigned char image[32]; /* registers image */
  93. int mce_bit;
  94. int calibrate_mute;
  95. struct mutex mce_mutex;
  96. struct mutex open_mutex;
  97. union {
  98. #ifdef SBUS_SUPPORT
  99. struct sbus_dev *sdev;
  100. #endif
  101. #ifdef EBUS_SUPPORT
  102. struct pci_dev *pdev;
  103. #endif
  104. } dev_u;
  105. unsigned int irq[2];
  106. unsigned int regs_size;
  107. struct snd_cs4231 *next;
  108. };
  109. static struct snd_cs4231 *cs4231_list;
  110. /* Eventually we can use sound/isa/cs423x/cs4231_lib.c directly, but for
  111. * now.... -DaveM
  112. */
  113. /* IO ports */
  114. #define CS4231P(chip, x) ((chip)->port + c_d_c_CS4231##x)
  115. /* XXX offsets are different than PC ISA chips... */
  116. #define c_d_c_CS4231REGSEL 0x0
  117. #define c_d_c_CS4231REG 0x4
  118. #define c_d_c_CS4231STATUS 0x8
  119. #define c_d_c_CS4231PIO 0xc
  120. /* codec registers */
  121. #define CS4231_LEFT_INPUT 0x00 /* left input control */
  122. #define CS4231_RIGHT_INPUT 0x01 /* right input control */
  123. #define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */
  124. #define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */
  125. #define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */
  126. #define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */
  127. #define CS4231_LEFT_OUTPUT 0x06 /* left output control register */
  128. #define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */
  129. #define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */
  130. #define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */
  131. #define CS4231_PIN_CTRL 0x0a /* pin control */
  132. #define CS4231_TEST_INIT 0x0b /* test and initialization */
  133. #define CS4231_MISC_INFO 0x0c /* miscellaneaous information */
  134. #define CS4231_LOOPBACK 0x0d /* loopback control */
  135. #define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */
  136. #define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */
  137. #define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */
  138. #define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */
  139. #define CS4231_LEFT_LINE_IN 0x12 /* left line input control */
  140. #define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */
  141. #define CS4231_TIMER_LOW 0x14 /* timer low byte */
  142. #define CS4231_TIMER_HIGH 0x15 /* timer high byte */
  143. #define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */
  144. #define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */
  145. #define CS4236_EXT_REG 0x17 /* extended register access */
  146. #define CS4231_IRQ_STATUS 0x18 /* irq status register */
  147. #define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */
  148. #define CS4231_VERSION 0x19 /* CS4231(A) - version values */
  149. #define CS4231_MONO_CTRL 0x1a /* mono input/output control */
  150. #define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */
  151. #define CS4235_LEFT_MASTER 0x1b /* left master output control */
  152. #define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */
  153. #define CS4231_PLY_VAR_FREQ 0x1d /* playback variable frequency */
  154. #define CS4235_RIGHT_MASTER 0x1d /* right master output control */
  155. #define CS4231_REC_UPR_CNT 0x1e /* record upper count */
  156. #define CS4231_REC_LWR_CNT 0x1f /* record lower count */
  157. /* definitions for codec register select port - CODECP( REGSEL ) */
  158. #define CS4231_INIT 0x80 /* CODEC is initializing */
  159. #define CS4231_MCE 0x40 /* mode change enable */
  160. #define CS4231_TRD 0x20 /* transfer request disable */
  161. /* definitions for codec status register - CODECP( STATUS ) */
  162. #define CS4231_GLOBALIRQ 0x01 /* IRQ is active */
  163. /* definitions for codec irq status - CS4231_IRQ_STATUS */
  164. #define CS4231_PLAYBACK_IRQ 0x10
  165. #define CS4231_RECORD_IRQ 0x20
  166. #define CS4231_TIMER_IRQ 0x40
  167. #define CS4231_ALL_IRQS 0x70
  168. #define CS4231_REC_UNDERRUN 0x08
  169. #define CS4231_REC_OVERRUN 0x04
  170. #define CS4231_PLY_OVERRUN 0x02
  171. #define CS4231_PLY_UNDERRUN 0x01
  172. /* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */
  173. #define CS4231_ENABLE_MIC_GAIN 0x20
  174. #define CS4231_MIXS_LINE 0x00
  175. #define CS4231_MIXS_AUX1 0x40
  176. #define CS4231_MIXS_MIC 0x80
  177. #define CS4231_MIXS_ALL 0xc0
  178. /* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */
  179. #define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */
  180. #define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */
  181. #define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */
  182. #define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */
  183. #define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */
  184. #define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */
  185. #define CS4231_STEREO 0x10 /* stereo mode */
  186. /* bits 3-1 define frequency divisor */
  187. #define CS4231_XTAL1 0x00 /* 24.576 crystal */
  188. #define CS4231_XTAL2 0x01 /* 16.9344 crystal */
  189. /* definitions for interface control register - CS4231_IFACE_CTRL */
  190. #define CS4231_RECORD_PIO 0x80 /* record PIO enable */
  191. #define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */
  192. #define CS4231_CALIB_MODE 0x18 /* calibration mode bits */
  193. #define CS4231_AUTOCALIB 0x08 /* auto calibrate */
  194. #define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */
  195. #define CS4231_RECORD_ENABLE 0x02 /* record enable */
  196. #define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */
  197. /* definitions for pin control register - CS4231_PIN_CTRL */
  198. #define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */
  199. #define CS4231_XCTL1 0x40 /* external control #1 */
  200. #define CS4231_XCTL0 0x80 /* external control #0 */
  201. /* definitions for test and init register - CS4231_TEST_INIT */
  202. #define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */
  203. #define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */
  204. /* definitions for misc control register - CS4231_MISC_INFO */
  205. #define CS4231_MODE2 0x40 /* MODE 2 */
  206. #define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */
  207. #define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */
  208. /* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */
  209. #define CS4231_DACZ 0x01 /* zero DAC when underrun */
  210. #define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */
  211. #define CS4231_OLB 0x80 /* output level bit */
  212. /* SBUS DMA register defines. */
  213. #define APCCSR 0x10UL /* APC DMA CSR */
  214. #define APCCVA 0x20UL /* APC Capture DMA Address */
  215. #define APCCC 0x24UL /* APC Capture Count */
  216. #define APCCNVA 0x28UL /* APC Capture DMA Next Address */
  217. #define APCCNC 0x2cUL /* APC Capture Next Count */
  218. #define APCPVA 0x30UL /* APC Play DMA Address */
  219. #define APCPC 0x34UL /* APC Play Count */
  220. #define APCPNVA 0x38UL /* APC Play DMA Next Address */
  221. #define APCPNC 0x3cUL /* APC Play Next Count */
  222. /* Defines for SBUS DMA-routines */
  223. #define APCVA 0x0UL /* APC DMA Address */
  224. #define APCC 0x4UL /* APC Count */
  225. #define APCNVA 0x8UL /* APC DMA Next Address */
  226. #define APCNC 0xcUL /* APC Next Count */
  227. #define APC_PLAY 0x30UL /* Play registers start at 0x30 */
  228. #define APC_RECORD 0x20UL /* Record registers start at 0x20 */
  229. /* APCCSR bits */
  230. #define APC_INT_PENDING 0x800000 /* Interrupt Pending */
  231. #define APC_PLAY_INT 0x400000 /* Playback interrupt */
  232. #define APC_CAPT_INT 0x200000 /* Capture interrupt */
  233. #define APC_GENL_INT 0x100000 /* General interrupt */
  234. #define APC_XINT_ENA 0x80000 /* General ext int. enable */
  235. #define APC_XINT_PLAY 0x40000 /* Playback ext intr */
  236. #define APC_XINT_CAPT 0x20000 /* Capture ext intr */
  237. #define APC_XINT_GENL 0x10000 /* Error ext intr */
  238. #define APC_XINT_EMPT 0x8000 /* Pipe empty interrupt (0 write to pva) */
  239. #define APC_XINT_PEMP 0x4000 /* Play pipe empty (pva and pnva not set) */
  240. #define APC_XINT_PNVA 0x2000 /* Playback NVA dirty */
  241. #define APC_XINT_PENA 0x1000 /* play pipe empty Int enable */
  242. #define APC_XINT_COVF 0x800 /* Cap data dropped on floor */
  243. #define APC_XINT_CNVA 0x400 /* Capture NVA dirty */
  244. #define APC_XINT_CEMP 0x200 /* Capture pipe empty (cva and cnva not set) */
  245. #define APC_XINT_CENA 0x100 /* Cap. pipe empty int enable */
  246. #define APC_PPAUSE 0x80 /* Pause the play DMA */
  247. #define APC_CPAUSE 0x40 /* Pause the capture DMA */
  248. #define APC_CDC_RESET 0x20 /* CODEC RESET */
  249. #define APC_PDMA_READY 0x08 /* Play DMA Go */
  250. #define APC_CDMA_READY 0x04 /* Capture DMA Go */
  251. #define APC_CHIP_RESET 0x01 /* Reset the chip */
  252. /* EBUS DMA register offsets */
  253. #define EBDMA_CSR 0x00UL /* Control/Status */
  254. #define EBDMA_ADDR 0x04UL /* DMA Address */
  255. #define EBDMA_COUNT 0x08UL /* DMA Count */
  256. /*
  257. * Some variables
  258. */
  259. static unsigned char freq_bits[14] = {
  260. /* 5510 */ 0x00 | CS4231_XTAL2,
  261. /* 6620 */ 0x0E | CS4231_XTAL2,
  262. /* 8000 */ 0x00 | CS4231_XTAL1,
  263. /* 9600 */ 0x0E | CS4231_XTAL1,
  264. /* 11025 */ 0x02 | CS4231_XTAL2,
  265. /* 16000 */ 0x02 | CS4231_XTAL1,
  266. /* 18900 */ 0x04 | CS4231_XTAL2,
  267. /* 22050 */ 0x06 | CS4231_XTAL2,
  268. /* 27042 */ 0x04 | CS4231_XTAL1,
  269. /* 32000 */ 0x06 | CS4231_XTAL1,
  270. /* 33075 */ 0x0C | CS4231_XTAL2,
  271. /* 37800 */ 0x08 | CS4231_XTAL2,
  272. /* 44100 */ 0x0A | CS4231_XTAL2,
  273. /* 48000 */ 0x0C | CS4231_XTAL1
  274. };
  275. static unsigned int rates[14] = {
  276. 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
  277. 27042, 32000, 33075, 37800, 44100, 48000
  278. };
  279. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  280. .count = ARRAY_SIZE(rates),
  281. .list = rates,
  282. };
  283. static int snd_cs4231_xrate(struct snd_pcm_runtime *runtime)
  284. {
  285. return snd_pcm_hw_constraint_list(runtime, 0,
  286. SNDRV_PCM_HW_PARAM_RATE,
  287. &hw_constraints_rates);
  288. }
  289. static unsigned char snd_cs4231_original_image[32] =
  290. {
  291. 0x00, /* 00/00 - lic */
  292. 0x00, /* 01/01 - ric */
  293. 0x9f, /* 02/02 - la1ic */
  294. 0x9f, /* 03/03 - ra1ic */
  295. 0x9f, /* 04/04 - la2ic */
  296. 0x9f, /* 05/05 - ra2ic */
  297. 0xbf, /* 06/06 - loc */
  298. 0xbf, /* 07/07 - roc */
  299. 0x20, /* 08/08 - pdfr */
  300. CS4231_AUTOCALIB, /* 09/09 - ic */
  301. 0x00, /* 0a/10 - pc */
  302. 0x00, /* 0b/11 - ti */
  303. CS4231_MODE2, /* 0c/12 - mi */
  304. 0x00, /* 0d/13 - lbc */
  305. 0x00, /* 0e/14 - pbru */
  306. 0x00, /* 0f/15 - pbrl */
  307. 0x80, /* 10/16 - afei */
  308. 0x01, /* 11/17 - afeii */
  309. 0x9f, /* 12/18 - llic */
  310. 0x9f, /* 13/19 - rlic */
  311. 0x00, /* 14/20 - tlb */
  312. 0x00, /* 15/21 - thb */
  313. 0x00, /* 16/22 - la3mic/reserved */
  314. 0x00, /* 17/23 - ra3mic/reserved */
  315. 0x00, /* 18/24 - afs */
  316. 0x00, /* 19/25 - lamoc/version */
  317. 0x00, /* 1a/26 - mioc */
  318. 0x00, /* 1b/27 - ramoc/reserved */
  319. 0x20, /* 1c/28 - cdfr */
  320. 0x00, /* 1d/29 - res4 */
  321. 0x00, /* 1e/30 - cbru */
  322. 0x00, /* 1f/31 - cbrl */
  323. };
  324. static u8 __cs4231_readb(struct snd_cs4231 *cp, void __iomem *reg_addr)
  325. {
  326. #ifdef EBUS_SUPPORT
  327. if (cp->flags & CS4231_FLAG_EBUS)
  328. return readb(reg_addr);
  329. else
  330. #endif
  331. #ifdef SBUS_SUPPORT
  332. return sbus_readb(reg_addr);
  333. #endif
  334. }
  335. static void __cs4231_writeb(struct snd_cs4231 *cp, u8 val, void __iomem *reg_addr)
  336. {
  337. #ifdef EBUS_SUPPORT
  338. if (cp->flags & CS4231_FLAG_EBUS)
  339. return writeb(val, reg_addr);
  340. else
  341. #endif
  342. #ifdef SBUS_SUPPORT
  343. return sbus_writeb(val, reg_addr);
  344. #endif
  345. }
  346. /*
  347. * Basic I/O functions
  348. */
  349. static void snd_cs4231_ready(struct snd_cs4231 *chip)
  350. {
  351. int timeout;
  352. for (timeout = 250;
  353. timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
  354. timeout--)
  355. udelay(100);
  356. }
  357. static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg, unsigned char value)
  358. {
  359. snd_cs4231_ready(chip);
  360. #ifdef CONFIG_SND_DEBUG
  361. if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
  362. snd_printdd("out: auto calibration time out - reg = 0x%x, "
  363. "value = 0x%x\n",
  364. reg, value);
  365. #endif
  366. __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
  367. wmb();
  368. __cs4231_writeb(chip, value, CS4231P(chip, REG));
  369. mb();
  370. }
  371. static inline void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg,
  372. unsigned char mask, unsigned char value)
  373. {
  374. unsigned char tmp = (chip->image[reg] & mask) | value;
  375. chip->image[reg] = tmp;
  376. if (!chip->calibrate_mute)
  377. snd_cs4231_dout(chip, reg, tmp);
  378. }
  379. static void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg,
  380. unsigned char value)
  381. {
  382. snd_cs4231_dout(chip, reg, value);
  383. chip->image[reg] = value;
  384. mb();
  385. }
  386. static unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg)
  387. {
  388. snd_cs4231_ready(chip);
  389. #ifdef CONFIG_SND_DEBUG
  390. if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
  391. snd_printdd("in: auto calibration time out - reg = 0x%x\n",
  392. reg);
  393. #endif
  394. __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
  395. mb();
  396. return __cs4231_readb(chip, CS4231P(chip, REG));
  397. }
  398. /*
  399. * CS4231 detection / MCE routines
  400. */
  401. static void snd_cs4231_busy_wait(struct snd_cs4231 *chip)
  402. {
  403. int timeout;
  404. /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
  405. for (timeout = 5; timeout > 0; timeout--)
  406. __cs4231_readb(chip, CS4231P(chip, REGSEL));
  407. /* end of cleanup sequence */
  408. for (timeout = 500;
  409. timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
  410. timeout--)
  411. msleep(1);
  412. }
  413. static void snd_cs4231_mce_up(struct snd_cs4231 *chip)
  414. {
  415. unsigned long flags;
  416. int timeout;
  417. spin_lock_irqsave(&chip->lock, flags);
  418. snd_cs4231_ready(chip);
  419. #ifdef CONFIG_SND_DEBUG
  420. if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
  421. snd_printdd("mce_up - auto calibration time out (0)\n");
  422. #endif
  423. chip->mce_bit |= CS4231_MCE;
  424. timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL));
  425. if (timeout == 0x80)
  426. snd_printdd("mce_up [%p]: serious init problem - codec still busy\n", chip->port);
  427. if (!(timeout & CS4231_MCE))
  428. __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL));
  429. spin_unlock_irqrestore(&chip->lock, flags);
  430. }
  431. static void snd_cs4231_mce_down(struct snd_cs4231 *chip)
  432. {
  433. unsigned long flags;
  434. int timeout;
  435. spin_lock_irqsave(&chip->lock, flags);
  436. snd_cs4231_busy_wait(chip);
  437. #ifdef CONFIG_SND_DEBUG
  438. if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
  439. snd_printdd("mce_down [%p] - auto calibration time out (0)\n", CS4231P(chip, REGSEL));
  440. #endif
  441. chip->mce_bit &= ~CS4231_MCE;
  442. timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL));
  443. __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL));
  444. if (timeout == 0x80)
  445. snd_printdd("mce_down [%p]: serious init problem - codec still busy\n", chip->port);
  446. if ((timeout & CS4231_MCE) == 0) {
  447. spin_unlock_irqrestore(&chip->lock, flags);
  448. return;
  449. }
  450. snd_cs4231_busy_wait(chip);
  451. /* calibration process */
  452. snd_cs4231_ready(chip);
  453. snd_cs4231_ready(chip);
  454. if ((snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) == 0) {
  455. snd_printd("cs4231_mce_down - auto calibration time out (1)\n");
  456. spin_unlock_irqrestore(&chip->lock, flags);
  457. return;
  458. }
  459. /* in 10ms increments, check condition, up to 250ms */
  460. timeout = 25;
  461. while (snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) {
  462. spin_unlock_irqrestore(&chip->lock, flags);
  463. if (--timeout < 0) {
  464. snd_printk("mce_down - auto calibration time out (2)\n");
  465. return;
  466. }
  467. msleep(10);
  468. spin_lock_irqsave(&chip->lock, flags);
  469. }
  470. /* in 10ms increments, check condition, up to 100ms */
  471. timeout = 10;
  472. while (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) {
  473. spin_unlock_irqrestore(&chip->lock, flags);
  474. if (--timeout < 0) {
  475. snd_printk("mce_down - auto calibration time out (3)\n");
  476. return;
  477. }
  478. msleep(10);
  479. spin_lock_irqsave(&chip->lock, flags);
  480. }
  481. spin_unlock_irqrestore(&chip->lock, flags);
  482. }
  483. static void snd_cs4231_advance_dma(struct cs4231_dma_control *dma_cont,
  484. struct snd_pcm_substream *substream,
  485. unsigned int *periods_sent)
  486. {
  487. struct snd_pcm_runtime *runtime = substream->runtime;
  488. while (1) {
  489. unsigned int period_size = snd_pcm_lib_period_bytes(substream);
  490. unsigned int offset = period_size * (*periods_sent);
  491. BUG_ON(period_size >= (1 << 24));
  492. if (dma_cont->request(dma_cont, runtime->dma_addr + offset, period_size))
  493. return;
  494. (*periods_sent) = ((*periods_sent) + 1) % runtime->periods;
  495. }
  496. }
  497. static void cs4231_dma_trigger(struct snd_pcm_substream *substream,
  498. unsigned int what, int on)
  499. {
  500. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  501. struct cs4231_dma_control *dma_cont;
  502. if (what & CS4231_PLAYBACK_ENABLE) {
  503. dma_cont = &chip->p_dma;
  504. if (on) {
  505. dma_cont->prepare(dma_cont, 0);
  506. dma_cont->enable(dma_cont, 1);
  507. snd_cs4231_advance_dma(dma_cont,
  508. chip->playback_substream,
  509. &chip->p_periods_sent);
  510. } else {
  511. dma_cont->enable(dma_cont, 0);
  512. }
  513. }
  514. if (what & CS4231_RECORD_ENABLE) {
  515. dma_cont = &chip->c_dma;
  516. if (on) {
  517. dma_cont->prepare(dma_cont, 1);
  518. dma_cont->enable(dma_cont, 1);
  519. snd_cs4231_advance_dma(dma_cont,
  520. chip->capture_substream,
  521. &chip->c_periods_sent);
  522. } else {
  523. dma_cont->enable(dma_cont, 0);
  524. }
  525. }
  526. }
  527. static int snd_cs4231_trigger(struct snd_pcm_substream *substream, int cmd)
  528. {
  529. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  530. int result = 0;
  531. switch (cmd) {
  532. case SNDRV_PCM_TRIGGER_START:
  533. case SNDRV_PCM_TRIGGER_STOP:
  534. {
  535. unsigned int what = 0;
  536. struct snd_pcm_substream *s;
  537. unsigned long flags;
  538. snd_pcm_group_for_each_entry(s, substream) {
  539. if (s == chip->playback_substream) {
  540. what |= CS4231_PLAYBACK_ENABLE;
  541. snd_pcm_trigger_done(s, substream);
  542. } else if (s == chip->capture_substream) {
  543. what |= CS4231_RECORD_ENABLE;
  544. snd_pcm_trigger_done(s, substream);
  545. }
  546. }
  547. spin_lock_irqsave(&chip->lock, flags);
  548. if (cmd == SNDRV_PCM_TRIGGER_START) {
  549. cs4231_dma_trigger(substream, what, 1);
  550. chip->image[CS4231_IFACE_CTRL] |= what;
  551. } else {
  552. cs4231_dma_trigger(substream, what, 0);
  553. chip->image[CS4231_IFACE_CTRL] &= ~what;
  554. }
  555. snd_cs4231_out(chip, CS4231_IFACE_CTRL,
  556. chip->image[CS4231_IFACE_CTRL]);
  557. spin_unlock_irqrestore(&chip->lock, flags);
  558. break;
  559. }
  560. default:
  561. result = -EINVAL;
  562. break;
  563. }
  564. return result;
  565. }
  566. /*
  567. * CODEC I/O
  568. */
  569. static unsigned char snd_cs4231_get_rate(unsigned int rate)
  570. {
  571. int i;
  572. for (i = 0; i < 14; i++)
  573. if (rate == rates[i])
  574. return freq_bits[i];
  575. // snd_BUG();
  576. return freq_bits[13];
  577. }
  578. static unsigned char snd_cs4231_get_format(struct snd_cs4231 *chip, int format, int channels)
  579. {
  580. unsigned char rformat;
  581. rformat = CS4231_LINEAR_8;
  582. switch (format) {
  583. case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break;
  584. case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break;
  585. case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break;
  586. case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break;
  587. case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break;
  588. }
  589. if (channels > 1)
  590. rformat |= CS4231_STEREO;
  591. return rformat;
  592. }
  593. static void snd_cs4231_calibrate_mute(struct snd_cs4231 *chip, int mute)
  594. {
  595. unsigned long flags;
  596. mute = mute ? 1 : 0;
  597. spin_lock_irqsave(&chip->lock, flags);
  598. if (chip->calibrate_mute == mute) {
  599. spin_unlock_irqrestore(&chip->lock, flags);
  600. return;
  601. }
  602. if (!mute) {
  603. snd_cs4231_dout(chip, CS4231_LEFT_INPUT,
  604. chip->image[CS4231_LEFT_INPUT]);
  605. snd_cs4231_dout(chip, CS4231_RIGHT_INPUT,
  606. chip->image[CS4231_RIGHT_INPUT]);
  607. snd_cs4231_dout(chip, CS4231_LOOPBACK,
  608. chip->image[CS4231_LOOPBACK]);
  609. }
  610. snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT,
  611. mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
  612. snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT,
  613. mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
  614. snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT,
  615. mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
  616. snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT,
  617. mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
  618. snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT,
  619. mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
  620. snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT,
  621. mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
  622. snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN,
  623. mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
  624. snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN,
  625. mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
  626. snd_cs4231_dout(chip, CS4231_MONO_CTRL,
  627. mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
  628. chip->calibrate_mute = mute;
  629. spin_unlock_irqrestore(&chip->lock, flags);
  630. }
  631. static void snd_cs4231_playback_format(struct snd_cs4231 *chip, struct snd_pcm_hw_params *params,
  632. unsigned char pdfr)
  633. {
  634. unsigned long flags;
  635. mutex_lock(&chip->mce_mutex);
  636. snd_cs4231_calibrate_mute(chip, 1);
  637. snd_cs4231_mce_up(chip);
  638. spin_lock_irqsave(&chip->lock, flags);
  639. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  640. (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
  641. (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
  642. pdfr);
  643. spin_unlock_irqrestore(&chip->lock, flags);
  644. snd_cs4231_mce_down(chip);
  645. snd_cs4231_calibrate_mute(chip, 0);
  646. mutex_unlock(&chip->mce_mutex);
  647. }
  648. static void snd_cs4231_capture_format(struct snd_cs4231 *chip, struct snd_pcm_hw_params *params,
  649. unsigned char cdfr)
  650. {
  651. unsigned long flags;
  652. mutex_lock(&chip->mce_mutex);
  653. snd_cs4231_calibrate_mute(chip, 1);
  654. snd_cs4231_mce_up(chip);
  655. spin_lock_irqsave(&chip->lock, flags);
  656. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
  657. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  658. ((chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
  659. (cdfr & 0x0f));
  660. spin_unlock_irqrestore(&chip->lock, flags);
  661. snd_cs4231_mce_down(chip);
  662. snd_cs4231_mce_up(chip);
  663. spin_lock_irqsave(&chip->lock, flags);
  664. }
  665. snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
  666. spin_unlock_irqrestore(&chip->lock, flags);
  667. snd_cs4231_mce_down(chip);
  668. snd_cs4231_calibrate_mute(chip, 0);
  669. mutex_unlock(&chip->mce_mutex);
  670. }
  671. /*
  672. * Timer interface
  673. */
  674. static unsigned long snd_cs4231_timer_resolution(struct snd_timer *timer)
  675. {
  676. struct snd_cs4231 *chip = snd_timer_chip(timer);
  677. return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
  678. }
  679. static int snd_cs4231_timer_start(struct snd_timer *timer)
  680. {
  681. unsigned long flags;
  682. unsigned int ticks;
  683. struct snd_cs4231 *chip = snd_timer_chip(timer);
  684. spin_lock_irqsave(&chip->lock, flags);
  685. ticks = timer->sticks;
  686. if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
  687. (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
  688. (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
  689. snd_cs4231_out(chip, CS4231_TIMER_HIGH,
  690. chip->image[CS4231_TIMER_HIGH] =
  691. (unsigned char) (ticks >> 8));
  692. snd_cs4231_out(chip, CS4231_TIMER_LOW,
  693. chip->image[CS4231_TIMER_LOW] =
  694. (unsigned char) ticks);
  695. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
  696. chip->image[CS4231_ALT_FEATURE_1] | CS4231_TIMER_ENABLE);
  697. }
  698. spin_unlock_irqrestore(&chip->lock, flags);
  699. return 0;
  700. }
  701. static int snd_cs4231_timer_stop(struct snd_timer *timer)
  702. {
  703. unsigned long flags;
  704. struct snd_cs4231 *chip = snd_timer_chip(timer);
  705. spin_lock_irqsave(&chip->lock, flags);
  706. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
  707. chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE);
  708. spin_unlock_irqrestore(&chip->lock, flags);
  709. return 0;
  710. }
  711. static void __init snd_cs4231_init(struct snd_cs4231 *chip)
  712. {
  713. unsigned long flags;
  714. snd_cs4231_mce_down(chip);
  715. #ifdef SNDRV_DEBUG_MCE
  716. snd_printdd("init: (1)\n");
  717. #endif
  718. snd_cs4231_mce_up(chip);
  719. spin_lock_irqsave(&chip->lock, flags);
  720. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  721. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO |
  722. CS4231_CALIB_MODE);
  723. chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
  724. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  725. spin_unlock_irqrestore(&chip->lock, flags);
  726. snd_cs4231_mce_down(chip);
  727. #ifdef SNDRV_DEBUG_MCE
  728. snd_printdd("init: (2)\n");
  729. #endif
  730. snd_cs4231_mce_up(chip);
  731. spin_lock_irqsave(&chip->lock, flags);
  732. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
  733. spin_unlock_irqrestore(&chip->lock, flags);
  734. snd_cs4231_mce_down(chip);
  735. #ifdef SNDRV_DEBUG_MCE
  736. snd_printdd("init: (3) - afei = 0x%x\n", chip->image[CS4231_ALT_FEATURE_1]);
  737. #endif
  738. spin_lock_irqsave(&chip->lock, flags);
  739. snd_cs4231_out(chip, CS4231_ALT_FEATURE_2, chip->image[CS4231_ALT_FEATURE_2]);
  740. spin_unlock_irqrestore(&chip->lock, flags);
  741. snd_cs4231_mce_up(chip);
  742. spin_lock_irqsave(&chip->lock, flags);
  743. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT]);
  744. spin_unlock_irqrestore(&chip->lock, flags);
  745. snd_cs4231_mce_down(chip);
  746. #ifdef SNDRV_DEBUG_MCE
  747. snd_printdd("init: (4)\n");
  748. #endif
  749. snd_cs4231_mce_up(chip);
  750. spin_lock_irqsave(&chip->lock, flags);
  751. snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
  752. spin_unlock_irqrestore(&chip->lock, flags);
  753. snd_cs4231_mce_down(chip);
  754. #ifdef SNDRV_DEBUG_MCE
  755. snd_printdd("init: (5)\n");
  756. #endif
  757. }
  758. static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode)
  759. {
  760. unsigned long flags;
  761. mutex_lock(&chip->open_mutex);
  762. if ((chip->mode & mode)) {
  763. mutex_unlock(&chip->open_mutex);
  764. return -EAGAIN;
  765. }
  766. if (chip->mode & CS4231_MODE_OPEN) {
  767. chip->mode |= mode;
  768. mutex_unlock(&chip->open_mutex);
  769. return 0;
  770. }
  771. /* ok. now enable and ack CODEC IRQ */
  772. spin_lock_irqsave(&chip->lock, flags);
  773. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  774. CS4231_RECORD_IRQ |
  775. CS4231_TIMER_IRQ);
  776. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  777. __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
  778. __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
  779. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  780. CS4231_RECORD_IRQ |
  781. CS4231_TIMER_IRQ);
  782. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  783. spin_unlock_irqrestore(&chip->lock, flags);
  784. chip->mode = mode;
  785. mutex_unlock(&chip->open_mutex);
  786. return 0;
  787. }
  788. static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode)
  789. {
  790. unsigned long flags;
  791. mutex_lock(&chip->open_mutex);
  792. chip->mode &= ~mode;
  793. if (chip->mode & CS4231_MODE_OPEN) {
  794. mutex_unlock(&chip->open_mutex);
  795. return;
  796. }
  797. snd_cs4231_calibrate_mute(chip, 1);
  798. /* disable IRQ */
  799. spin_lock_irqsave(&chip->lock, flags);
  800. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  801. __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
  802. __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
  803. /* now disable record & playback */
  804. if (chip->image[CS4231_IFACE_CTRL] &
  805. (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  806. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
  807. spin_unlock_irqrestore(&chip->lock, flags);
  808. snd_cs4231_mce_up(chip);
  809. spin_lock_irqsave(&chip->lock, flags);
  810. chip->image[CS4231_IFACE_CTRL] &=
  811. ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  812. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
  813. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  814. spin_unlock_irqrestore(&chip->lock, flags);
  815. snd_cs4231_mce_down(chip);
  816. spin_lock_irqsave(&chip->lock, flags);
  817. }
  818. /* clear IRQ again */
  819. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  820. __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
  821. __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
  822. spin_unlock_irqrestore(&chip->lock, flags);
  823. snd_cs4231_calibrate_mute(chip, 0);
  824. chip->mode = 0;
  825. mutex_unlock(&chip->open_mutex);
  826. }
  827. /*
  828. * timer open/close
  829. */
  830. static int snd_cs4231_timer_open(struct snd_timer *timer)
  831. {
  832. struct snd_cs4231 *chip = snd_timer_chip(timer);
  833. snd_cs4231_open(chip, CS4231_MODE_TIMER);
  834. return 0;
  835. }
  836. static int snd_cs4231_timer_close(struct snd_timer * timer)
  837. {
  838. struct snd_cs4231 *chip = snd_timer_chip(timer);
  839. snd_cs4231_close(chip, CS4231_MODE_TIMER);
  840. return 0;
  841. }
  842. static struct snd_timer_hardware snd_cs4231_timer_table =
  843. {
  844. .flags = SNDRV_TIMER_HW_AUTO,
  845. .resolution = 9945,
  846. .ticks = 65535,
  847. .open = snd_cs4231_timer_open,
  848. .close = snd_cs4231_timer_close,
  849. .c_resolution = snd_cs4231_timer_resolution,
  850. .start = snd_cs4231_timer_start,
  851. .stop = snd_cs4231_timer_stop,
  852. };
  853. /*
  854. * ok.. exported functions..
  855. */
  856. static int snd_cs4231_playback_hw_params(struct snd_pcm_substream *substream,
  857. struct snd_pcm_hw_params *hw_params)
  858. {
  859. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  860. unsigned char new_pdfr;
  861. int err;
  862. if ((err = snd_pcm_lib_malloc_pages(substream,
  863. params_buffer_bytes(hw_params))) < 0)
  864. return err;
  865. new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params),
  866. params_channels(hw_params)) |
  867. snd_cs4231_get_rate(params_rate(hw_params));
  868. snd_cs4231_playback_format(chip, hw_params, new_pdfr);
  869. return 0;
  870. }
  871. static int snd_cs4231_playback_prepare(struct snd_pcm_substream *substream)
  872. {
  873. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  874. struct snd_pcm_runtime *runtime = substream->runtime;
  875. unsigned long flags;
  876. spin_lock_irqsave(&chip->lock, flags);
  877. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
  878. CS4231_PLAYBACK_PIO);
  879. BUG_ON(runtime->period_size > 0xffff + 1);
  880. chip->p_periods_sent = 0;
  881. spin_unlock_irqrestore(&chip->lock, flags);
  882. return 0;
  883. }
  884. static int snd_cs4231_capture_hw_params(struct snd_pcm_substream *substream,
  885. struct snd_pcm_hw_params *hw_params)
  886. {
  887. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  888. unsigned char new_cdfr;
  889. int err;
  890. if ((err = snd_pcm_lib_malloc_pages(substream,
  891. params_buffer_bytes(hw_params))) < 0)
  892. return err;
  893. new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params),
  894. params_channels(hw_params)) |
  895. snd_cs4231_get_rate(params_rate(hw_params));
  896. snd_cs4231_capture_format(chip, hw_params, new_cdfr);
  897. return 0;
  898. }
  899. static int snd_cs4231_capture_prepare(struct snd_pcm_substream *substream)
  900. {
  901. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  902. unsigned long flags;
  903. spin_lock_irqsave(&chip->lock, flags);
  904. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE |
  905. CS4231_RECORD_PIO);
  906. chip->c_periods_sent = 0;
  907. spin_unlock_irqrestore(&chip->lock, flags);
  908. return 0;
  909. }
  910. static void snd_cs4231_overrange(struct snd_cs4231 *chip)
  911. {
  912. unsigned long flags;
  913. unsigned char res;
  914. spin_lock_irqsave(&chip->lock, flags);
  915. res = snd_cs4231_in(chip, CS4231_TEST_INIT);
  916. spin_unlock_irqrestore(&chip->lock, flags);
  917. if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */
  918. chip->capture_substream->runtime->overrange++;
  919. }
  920. static void snd_cs4231_play_callback(struct snd_cs4231 *chip)
  921. {
  922. if (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) {
  923. snd_pcm_period_elapsed(chip->playback_substream);
  924. snd_cs4231_advance_dma(&chip->p_dma, chip->playback_substream,
  925. &chip->p_periods_sent);
  926. }
  927. }
  928. static void snd_cs4231_capture_callback(struct snd_cs4231 *chip)
  929. {
  930. if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) {
  931. snd_pcm_period_elapsed(chip->capture_substream);
  932. snd_cs4231_advance_dma(&chip->c_dma, chip->capture_substream,
  933. &chip->c_periods_sent);
  934. }
  935. }
  936. static snd_pcm_uframes_t snd_cs4231_playback_pointer(struct snd_pcm_substream *substream)
  937. {
  938. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  939. struct cs4231_dma_control *dma_cont = &chip->p_dma;
  940. size_t ptr;
  941. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
  942. return 0;
  943. ptr = dma_cont->address(dma_cont);
  944. if (ptr != 0)
  945. ptr -= substream->runtime->dma_addr;
  946. return bytes_to_frames(substream->runtime, ptr);
  947. }
  948. static snd_pcm_uframes_t snd_cs4231_capture_pointer(struct snd_pcm_substream *substream)
  949. {
  950. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  951. struct cs4231_dma_control *dma_cont = &chip->c_dma;
  952. size_t ptr;
  953. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
  954. return 0;
  955. ptr = dma_cont->address(dma_cont);
  956. if (ptr != 0)
  957. ptr -= substream->runtime->dma_addr;
  958. return bytes_to_frames(substream->runtime, ptr);
  959. }
  960. static int __init snd_cs4231_probe(struct snd_cs4231 *chip)
  961. {
  962. unsigned long flags;
  963. int i, id, vers;
  964. unsigned char *ptr;
  965. id = vers = 0;
  966. for (i = 0; i < 50; i++) {
  967. mb();
  968. if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
  969. udelay(2000);
  970. else {
  971. spin_lock_irqsave(&chip->lock, flags);
  972. snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
  973. id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
  974. vers = snd_cs4231_in(chip, CS4231_VERSION);
  975. spin_unlock_irqrestore(&chip->lock, flags);
  976. if (id == 0x0a)
  977. break; /* this is valid value */
  978. }
  979. }
  980. snd_printdd("cs4231: port = %p, id = 0x%x\n", chip->port, id);
  981. if (id != 0x0a)
  982. return -ENODEV; /* no valid device found */
  983. spin_lock_irqsave(&chip->lock, flags);
  984. __cs4231_readb(chip, CS4231P(chip, STATUS)); /* clear any pendings IRQ */
  985. __cs4231_writeb(chip, 0, CS4231P(chip, STATUS));
  986. mb();
  987. spin_unlock_irqrestore(&chip->lock, flags);
  988. chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
  989. chip->image[CS4231_IFACE_CTRL] =
  990. chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA;
  991. chip->image[CS4231_ALT_FEATURE_1] = 0x80;
  992. chip->image[CS4231_ALT_FEATURE_2] = 0x01;
  993. if (vers & 0x20)
  994. chip->image[CS4231_ALT_FEATURE_2] |= 0x02;
  995. ptr = (unsigned char *) &chip->image;
  996. snd_cs4231_mce_down(chip);
  997. spin_lock_irqsave(&chip->lock, flags);
  998. for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */
  999. snd_cs4231_out(chip, i, *ptr++);
  1000. spin_unlock_irqrestore(&chip->lock, flags);
  1001. snd_cs4231_mce_up(chip);
  1002. snd_cs4231_mce_down(chip);
  1003. mdelay(2);
  1004. return 0; /* all things are ok.. */
  1005. }
  1006. static struct snd_pcm_hardware snd_cs4231_playback =
  1007. {
  1008. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1009. SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
  1010. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
  1011. SNDRV_PCM_FMTBIT_IMA_ADPCM |
  1012. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |
  1013. SNDRV_PCM_FMTBIT_S16_BE),
  1014. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  1015. .rate_min = 5510,
  1016. .rate_max = 48000,
  1017. .channels_min = 1,
  1018. .channels_max = 2,
  1019. .buffer_bytes_max = (32*1024),
  1020. .period_bytes_min = 64,
  1021. .period_bytes_max = (32*1024),
  1022. .periods_min = 1,
  1023. .periods_max = 1024,
  1024. };
  1025. static struct snd_pcm_hardware snd_cs4231_capture =
  1026. {
  1027. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1028. SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
  1029. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
  1030. SNDRV_PCM_FMTBIT_IMA_ADPCM |
  1031. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |
  1032. SNDRV_PCM_FMTBIT_S16_BE),
  1033. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  1034. .rate_min = 5510,
  1035. .rate_max = 48000,
  1036. .channels_min = 1,
  1037. .channels_max = 2,
  1038. .buffer_bytes_max = (32*1024),
  1039. .period_bytes_min = 64,
  1040. .period_bytes_max = (32*1024),
  1041. .periods_min = 1,
  1042. .periods_max = 1024,
  1043. };
  1044. static int snd_cs4231_playback_open(struct snd_pcm_substream *substream)
  1045. {
  1046. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1047. struct snd_pcm_runtime *runtime = substream->runtime;
  1048. int err;
  1049. runtime->hw = snd_cs4231_playback;
  1050. if ((err = snd_cs4231_open(chip, CS4231_MODE_PLAY)) < 0) {
  1051. snd_free_pages(runtime->dma_area, runtime->dma_bytes);
  1052. return err;
  1053. }
  1054. chip->playback_substream = substream;
  1055. chip->p_periods_sent = 0;
  1056. snd_pcm_set_sync(substream);
  1057. snd_cs4231_xrate(runtime);
  1058. return 0;
  1059. }
  1060. static int snd_cs4231_capture_open(struct snd_pcm_substream *substream)
  1061. {
  1062. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1063. struct snd_pcm_runtime *runtime = substream->runtime;
  1064. int err;
  1065. runtime->hw = snd_cs4231_capture;
  1066. if ((err = snd_cs4231_open(chip, CS4231_MODE_RECORD)) < 0) {
  1067. snd_free_pages(runtime->dma_area, runtime->dma_bytes);
  1068. return err;
  1069. }
  1070. chip->capture_substream = substream;
  1071. chip->c_periods_sent = 0;
  1072. snd_pcm_set_sync(substream);
  1073. snd_cs4231_xrate(runtime);
  1074. return 0;
  1075. }
  1076. static int snd_cs4231_playback_close(struct snd_pcm_substream *substream)
  1077. {
  1078. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1079. snd_cs4231_close(chip, CS4231_MODE_PLAY);
  1080. chip->playback_substream = NULL;
  1081. return 0;
  1082. }
  1083. static int snd_cs4231_capture_close(struct snd_pcm_substream *substream)
  1084. {
  1085. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1086. snd_cs4231_close(chip, CS4231_MODE_RECORD);
  1087. chip->capture_substream = NULL;
  1088. return 0;
  1089. }
  1090. /* XXX We can do some power-management, in particular on EBUS using
  1091. * XXX the audio AUXIO register...
  1092. */
  1093. static struct snd_pcm_ops snd_cs4231_playback_ops = {
  1094. .open = snd_cs4231_playback_open,
  1095. .close = snd_cs4231_playback_close,
  1096. .ioctl = snd_pcm_lib_ioctl,
  1097. .hw_params = snd_cs4231_playback_hw_params,
  1098. .hw_free = snd_pcm_lib_free_pages,
  1099. .prepare = snd_cs4231_playback_prepare,
  1100. .trigger = snd_cs4231_trigger,
  1101. .pointer = snd_cs4231_playback_pointer,
  1102. };
  1103. static struct snd_pcm_ops snd_cs4231_capture_ops = {
  1104. .open = snd_cs4231_capture_open,
  1105. .close = snd_cs4231_capture_close,
  1106. .ioctl = snd_pcm_lib_ioctl,
  1107. .hw_params = snd_cs4231_capture_hw_params,
  1108. .hw_free = snd_pcm_lib_free_pages,
  1109. .prepare = snd_cs4231_capture_prepare,
  1110. .trigger = snd_cs4231_trigger,
  1111. .pointer = snd_cs4231_capture_pointer,
  1112. };
  1113. static int __init snd_cs4231_pcm(struct snd_card *card)
  1114. {
  1115. struct snd_cs4231 *chip = card->private_data;
  1116. struct snd_pcm *pcm;
  1117. int err;
  1118. err = snd_pcm_new(card, "CS4231", 0, 1, 1, &pcm);
  1119. if (err < 0)
  1120. return err;
  1121. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4231_playback_ops);
  1122. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4231_capture_ops);
  1123. /* global setup */
  1124. pcm->private_data = chip;
  1125. pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
  1126. strcpy(pcm->name, "CS4231");
  1127. chip->p_dma.preallocate(chip, pcm);
  1128. chip->pcm = pcm;
  1129. return 0;
  1130. }
  1131. static int __init snd_cs4231_timer(struct snd_card *card)
  1132. {
  1133. struct snd_cs4231 *chip = card->private_data;
  1134. struct snd_timer *timer;
  1135. struct snd_timer_id tid;
  1136. int err;
  1137. /* Timer initialization */
  1138. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1139. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1140. tid.card = card->number;
  1141. tid.device = 0;
  1142. tid.subdevice = 0;
  1143. err = snd_timer_new(card, "CS4231", &tid, &timer);
  1144. if (err < 0)
  1145. return err;
  1146. strcpy(timer->name, "CS4231");
  1147. timer->private_data = chip;
  1148. timer->hw = snd_cs4231_timer_table;
  1149. chip->timer = timer;
  1150. return 0;
  1151. }
  1152. /*
  1153. * MIXER part
  1154. */
  1155. static int snd_cs4231_info_mux(struct snd_kcontrol *kcontrol,
  1156. struct snd_ctl_elem_info *uinfo)
  1157. {
  1158. static char *texts[4] = {
  1159. "Line", "CD", "Mic", "Mix"
  1160. };
  1161. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1162. uinfo->count = 2;
  1163. uinfo->value.enumerated.items = 4;
  1164. if (uinfo->value.enumerated.item > 3)
  1165. uinfo->value.enumerated.item = 3;
  1166. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1167. return 0;
  1168. }
  1169. static int snd_cs4231_get_mux(struct snd_kcontrol *kcontrol,
  1170. struct snd_ctl_elem_value *ucontrol)
  1171. {
  1172. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1173. unsigned long flags;
  1174. spin_lock_irqsave(&chip->lock, flags);
  1175. ucontrol->value.enumerated.item[0] =
  1176. (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1177. ucontrol->value.enumerated.item[1] =
  1178. (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1179. spin_unlock_irqrestore(&chip->lock, flags);
  1180. return 0;
  1181. }
  1182. static int snd_cs4231_put_mux(struct snd_kcontrol *kcontrol,
  1183. struct snd_ctl_elem_value *ucontrol)
  1184. {
  1185. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1186. unsigned long flags;
  1187. unsigned short left, right;
  1188. int change;
  1189. if (ucontrol->value.enumerated.item[0] > 3 ||
  1190. ucontrol->value.enumerated.item[1] > 3)
  1191. return -EINVAL;
  1192. left = ucontrol->value.enumerated.item[0] << 6;
  1193. right = ucontrol->value.enumerated.item[1] << 6;
  1194. spin_lock_irqsave(&chip->lock, flags);
  1195. left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
  1196. right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
  1197. change = left != chip->image[CS4231_LEFT_INPUT] ||
  1198. right != chip->image[CS4231_RIGHT_INPUT];
  1199. snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
  1200. snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
  1201. spin_unlock_irqrestore(&chip->lock, flags);
  1202. return change;
  1203. }
  1204. static int snd_cs4231_info_single(struct snd_kcontrol *kcontrol,
  1205. struct snd_ctl_elem_info *uinfo)
  1206. {
  1207. int mask = (kcontrol->private_value >> 16) & 0xff;
  1208. uinfo->type = (mask == 1) ?
  1209. SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1210. uinfo->count = 1;
  1211. uinfo->value.integer.min = 0;
  1212. uinfo->value.integer.max = mask;
  1213. return 0;
  1214. }
  1215. static int snd_cs4231_get_single(struct snd_kcontrol *kcontrol,
  1216. struct snd_ctl_elem_value *ucontrol)
  1217. {
  1218. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1219. unsigned long flags;
  1220. int reg = kcontrol->private_value & 0xff;
  1221. int shift = (kcontrol->private_value >> 8) & 0xff;
  1222. int mask = (kcontrol->private_value >> 16) & 0xff;
  1223. int invert = (kcontrol->private_value >> 24) & 0xff;
  1224. spin_lock_irqsave(&chip->lock, flags);
  1225. ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
  1226. spin_unlock_irqrestore(&chip->lock, flags);
  1227. if (invert)
  1228. ucontrol->value.integer.value[0] =
  1229. (mask - ucontrol->value.integer.value[0]);
  1230. return 0;
  1231. }
  1232. static int snd_cs4231_put_single(struct snd_kcontrol *kcontrol,
  1233. struct snd_ctl_elem_value *ucontrol)
  1234. {
  1235. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1236. unsigned long flags;
  1237. int reg = kcontrol->private_value & 0xff;
  1238. int shift = (kcontrol->private_value >> 8) & 0xff;
  1239. int mask = (kcontrol->private_value >> 16) & 0xff;
  1240. int invert = (kcontrol->private_value >> 24) & 0xff;
  1241. int change;
  1242. unsigned short val;
  1243. val = (ucontrol->value.integer.value[0] & mask);
  1244. if (invert)
  1245. val = mask - val;
  1246. val <<= shift;
  1247. spin_lock_irqsave(&chip->lock, flags);
  1248. val = (chip->image[reg] & ~(mask << shift)) | val;
  1249. change = val != chip->image[reg];
  1250. snd_cs4231_out(chip, reg, val);
  1251. spin_unlock_irqrestore(&chip->lock, flags);
  1252. return change;
  1253. }
  1254. static int snd_cs4231_info_double(struct snd_kcontrol *kcontrol,
  1255. struct snd_ctl_elem_info *uinfo)
  1256. {
  1257. int mask = (kcontrol->private_value >> 24) & 0xff;
  1258. uinfo->type = mask == 1 ?
  1259. SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1260. uinfo->count = 2;
  1261. uinfo->value.integer.min = 0;
  1262. uinfo->value.integer.max = mask;
  1263. return 0;
  1264. }
  1265. static int snd_cs4231_get_double(struct snd_kcontrol *kcontrol,
  1266. struct snd_ctl_elem_value *ucontrol)
  1267. {
  1268. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1269. unsigned long flags;
  1270. int left_reg = kcontrol->private_value & 0xff;
  1271. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1272. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1273. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1274. int mask = (kcontrol->private_value >> 24) & 0xff;
  1275. int invert = (kcontrol->private_value >> 22) & 1;
  1276. spin_lock_irqsave(&chip->lock, flags);
  1277. ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
  1278. ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
  1279. spin_unlock_irqrestore(&chip->lock, flags);
  1280. if (invert) {
  1281. ucontrol->value.integer.value[0] =
  1282. (mask - ucontrol->value.integer.value[0]);
  1283. ucontrol->value.integer.value[1] =
  1284. (mask - ucontrol->value.integer.value[1]);
  1285. }
  1286. return 0;
  1287. }
  1288. static int snd_cs4231_put_double(struct snd_kcontrol *kcontrol,
  1289. struct snd_ctl_elem_value *ucontrol)
  1290. {
  1291. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1292. unsigned long flags;
  1293. int left_reg = kcontrol->private_value & 0xff;
  1294. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1295. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1296. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1297. int mask = (kcontrol->private_value >> 24) & 0xff;
  1298. int invert = (kcontrol->private_value >> 22) & 1;
  1299. int change;
  1300. unsigned short val1, val2;
  1301. val1 = ucontrol->value.integer.value[0] & mask;
  1302. val2 = ucontrol->value.integer.value[1] & mask;
  1303. if (invert) {
  1304. val1 = mask - val1;
  1305. val2 = mask - val2;
  1306. }
  1307. val1 <<= shift_left;
  1308. val2 <<= shift_right;
  1309. spin_lock_irqsave(&chip->lock, flags);
  1310. val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
  1311. val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
  1312. change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg];
  1313. snd_cs4231_out(chip, left_reg, val1);
  1314. snd_cs4231_out(chip, right_reg, val2);
  1315. spin_unlock_irqrestore(&chip->lock, flags);
  1316. return change;
  1317. }
  1318. #define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
  1319. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1320. .info = snd_cs4231_info_single, \
  1321. .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \
  1322. .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
  1323. #define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
  1324. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1325. .info = snd_cs4231_info_double, \
  1326. .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \
  1327. .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
  1328. static struct snd_kcontrol_new snd_cs4231_controls[] __initdata = {
  1329. CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
  1330. CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
  1331. CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
  1332. CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
  1333. CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
  1334. CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
  1335. CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
  1336. CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
  1337. CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
  1338. CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
  1339. CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
  1340. CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
  1341. CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
  1342. {
  1343. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1344. .name = "Capture Source",
  1345. .info = snd_cs4231_info_mux,
  1346. .get = snd_cs4231_get_mux,
  1347. .put = snd_cs4231_put_mux,
  1348. },
  1349. CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
  1350. CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
  1351. CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1),
  1352. /* SPARC specific uses of XCTL{0,1} general purpose outputs. */
  1353. CS4231_SINGLE("Line Out Switch", 0, CS4231_PIN_CTRL, 6, 1, 1),
  1354. CS4231_SINGLE("Headphone Out Switch", 0, CS4231_PIN_CTRL, 7, 1, 1)
  1355. };
  1356. static int __init snd_cs4231_mixer(struct snd_card *card)
  1357. {
  1358. struct snd_cs4231 *chip = card->private_data;
  1359. int err, idx;
  1360. snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
  1361. strcpy(card->mixername, chip->pcm->name);
  1362. for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) {
  1363. err = snd_ctl_add(card,
  1364. snd_ctl_new1(&snd_cs4231_controls[idx], chip));
  1365. if (err < 0)
  1366. return err;
  1367. }
  1368. return 0;
  1369. }
  1370. static int dev;
  1371. static int __init cs4231_attach_begin(struct snd_card **rcard)
  1372. {
  1373. struct snd_card *card;
  1374. struct snd_cs4231 *chip;
  1375. *rcard = NULL;
  1376. if (dev >= SNDRV_CARDS)
  1377. return -ENODEV;
  1378. if (!enable[dev]) {
  1379. dev++;
  1380. return -ENOENT;
  1381. }
  1382. card = snd_card_new(index[dev], id[dev], THIS_MODULE,
  1383. sizeof(struct snd_cs4231));
  1384. if (card == NULL)
  1385. return -ENOMEM;
  1386. strcpy(card->driver, "CS4231");
  1387. strcpy(card->shortname, "Sun CS4231");
  1388. chip = card->private_data;
  1389. chip->card = card;
  1390. *rcard = card;
  1391. return 0;
  1392. }
  1393. static int __init cs4231_attach_finish(struct snd_card *card)
  1394. {
  1395. struct snd_cs4231 *chip = card->private_data;
  1396. int err;
  1397. err = snd_cs4231_pcm(card);
  1398. if (err < 0)
  1399. goto out_err;
  1400. err = snd_cs4231_mixer(card);
  1401. if (err < 0)
  1402. goto out_err;
  1403. err = snd_cs4231_timer(card);
  1404. if (err < 0)
  1405. goto out_err;
  1406. err = snd_card_register(card);
  1407. if (err < 0)
  1408. goto out_err;
  1409. chip->next = cs4231_list;
  1410. cs4231_list = chip;
  1411. dev++;
  1412. return 0;
  1413. out_err:
  1414. snd_card_free(card);
  1415. return err;
  1416. }
  1417. #ifdef SBUS_SUPPORT
  1418. static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id)
  1419. {
  1420. unsigned long flags;
  1421. unsigned char status;
  1422. u32 csr;
  1423. struct snd_cs4231 *chip = dev_id;
  1424. /*This is IRQ is not raised by the cs4231*/
  1425. if (!(__cs4231_readb(chip, CS4231P(chip, STATUS)) & CS4231_GLOBALIRQ))
  1426. return IRQ_NONE;
  1427. /* ACK the APC interrupt. */
  1428. csr = sbus_readl(chip->port + APCCSR);
  1429. sbus_writel(csr, chip->port + APCCSR);
  1430. if ((csr & APC_PDMA_READY) &&
  1431. (csr & APC_PLAY_INT) &&
  1432. (csr & APC_XINT_PNVA) &&
  1433. !(csr & APC_XINT_EMPT))
  1434. snd_cs4231_play_callback(chip);
  1435. if ((csr & APC_CDMA_READY) &&
  1436. (csr & APC_CAPT_INT) &&
  1437. (csr & APC_XINT_CNVA) &&
  1438. !(csr & APC_XINT_EMPT))
  1439. snd_cs4231_capture_callback(chip);
  1440. status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
  1441. if (status & CS4231_TIMER_IRQ) {
  1442. if (chip->timer)
  1443. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  1444. }
  1445. if ((status & CS4231_RECORD_IRQ) && (csr & APC_CDMA_READY))
  1446. snd_cs4231_overrange(chip);
  1447. /* ACK the CS4231 interrupt. */
  1448. spin_lock_irqsave(&chip->lock, flags);
  1449. snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
  1450. spin_unlock_irqrestore(&chip->lock, flags);
  1451. return IRQ_HANDLED;
  1452. }
  1453. /*
  1454. * SBUS DMA routines
  1455. */
  1456. static int sbus_dma_request(struct cs4231_dma_control *dma_cont, dma_addr_t bus_addr, size_t len)
  1457. {
  1458. unsigned long flags;
  1459. u32 test, csr;
  1460. int err;
  1461. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1462. if (len >= (1 << 24))
  1463. return -EINVAL;
  1464. spin_lock_irqsave(&base->lock, flags);
  1465. csr = sbus_readl(base->regs + APCCSR);
  1466. err = -EINVAL;
  1467. test = APC_CDMA_READY;
  1468. if ( base->dir == APC_PLAY )
  1469. test = APC_PDMA_READY;
  1470. if (!(csr & test))
  1471. goto out;
  1472. err = -EBUSY;
  1473. test = APC_XINT_CNVA;
  1474. if ( base->dir == APC_PLAY )
  1475. test = APC_XINT_PNVA;
  1476. if (!(csr & test))
  1477. goto out;
  1478. err = 0;
  1479. sbus_writel(bus_addr, base->regs + base->dir + APCNVA);
  1480. sbus_writel(len, base->regs + base->dir + APCNC);
  1481. out:
  1482. spin_unlock_irqrestore(&base->lock, flags);
  1483. return err;
  1484. }
  1485. static void sbus_dma_prepare(struct cs4231_dma_control *dma_cont, int d)
  1486. {
  1487. unsigned long flags;
  1488. u32 csr, test;
  1489. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1490. spin_lock_irqsave(&base->lock, flags);
  1491. csr = sbus_readl(base->regs + APCCSR);
  1492. test = APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA |
  1493. APC_XINT_PLAY | APC_XINT_PEMP | APC_XINT_GENL |
  1494. APC_XINT_PENA;
  1495. if ( base->dir == APC_RECORD )
  1496. test = APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA |
  1497. APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL;
  1498. csr |= test;
  1499. sbus_writel(csr, base->regs + APCCSR);
  1500. spin_unlock_irqrestore(&base->lock, flags);
  1501. }
  1502. static void sbus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
  1503. {
  1504. unsigned long flags;
  1505. u32 csr, shift;
  1506. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1507. spin_lock_irqsave(&base->lock, flags);
  1508. if (!on) {
  1509. sbus_writel(0, base->regs + base->dir + APCNC);
  1510. sbus_writel(0, base->regs + base->dir + APCNVA);
  1511. if ( base->dir == APC_PLAY ) {
  1512. sbus_writel(0, base->regs + base->dir + APCC);
  1513. sbus_writel(0, base->regs + base->dir + APCVA);
  1514. }
  1515. udelay(1200);
  1516. }
  1517. csr = sbus_readl(base->regs + APCCSR);
  1518. shift = 0;
  1519. if ( base->dir == APC_PLAY )
  1520. shift = 1;
  1521. if (on)
  1522. csr &= ~(APC_CPAUSE << shift);
  1523. else
  1524. csr |= (APC_CPAUSE << shift);
  1525. sbus_writel(csr, base->regs + APCCSR);
  1526. if (on)
  1527. csr |= (APC_CDMA_READY << shift);
  1528. else
  1529. csr &= ~(APC_CDMA_READY << shift);
  1530. sbus_writel(csr, base->regs + APCCSR);
  1531. spin_unlock_irqrestore(&base->lock, flags);
  1532. }
  1533. static unsigned int sbus_dma_addr(struct cs4231_dma_control *dma_cont)
  1534. {
  1535. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1536. return sbus_readl(base->regs + base->dir + APCVA);
  1537. }
  1538. static void sbus_dma_preallocate(struct snd_cs4231 *chip, struct snd_pcm *pcm)
  1539. {
  1540. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_SBUS,
  1541. snd_dma_sbus_data(chip->dev_u.sdev),
  1542. 64*1024, 128*1024);
  1543. }
  1544. /*
  1545. * Init and exit routines
  1546. */
  1547. static int snd_cs4231_sbus_free(struct snd_cs4231 *chip)
  1548. {
  1549. if (chip->irq[0])
  1550. free_irq(chip->irq[0], chip);
  1551. if (chip->port)
  1552. sbus_iounmap(chip->port, chip->regs_size);
  1553. return 0;
  1554. }
  1555. static int snd_cs4231_sbus_dev_free(struct snd_device *device)
  1556. {
  1557. struct snd_cs4231 *cp = device->device_data;
  1558. return snd_cs4231_sbus_free(cp);
  1559. }
  1560. static struct snd_device_ops snd_cs4231_sbus_dev_ops = {
  1561. .dev_free = snd_cs4231_sbus_dev_free,
  1562. };
  1563. static int __init snd_cs4231_sbus_create(struct snd_card *card,
  1564. struct sbus_dev *sdev,
  1565. int dev)
  1566. {
  1567. struct snd_cs4231 *chip = card->private_data;
  1568. int err;
  1569. spin_lock_init(&chip->lock);
  1570. spin_lock_init(&chip->c_dma.sbus_info.lock);
  1571. spin_lock_init(&chip->p_dma.sbus_info.lock);
  1572. mutex_init(&chip->mce_mutex);
  1573. mutex_init(&chip->open_mutex);
  1574. chip->dev_u.sdev = sdev;
  1575. chip->regs_size = sdev->reg_addrs[0].reg_size;
  1576. memcpy(&chip->image, &snd_cs4231_original_image,
  1577. sizeof(snd_cs4231_original_image));
  1578. chip->port = sbus_ioremap(&sdev->resource[0], 0,
  1579. chip->regs_size, "cs4231");
  1580. if (!chip->port) {
  1581. snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
  1582. return -EIO;
  1583. }
  1584. chip->c_dma.sbus_info.regs = chip->port;
  1585. chip->p_dma.sbus_info.regs = chip->port;
  1586. chip->c_dma.sbus_info.dir = APC_RECORD;
  1587. chip->p_dma.sbus_info.dir = APC_PLAY;
  1588. chip->p_dma.prepare = sbus_dma_prepare;
  1589. chip->p_dma.enable = sbus_dma_enable;
  1590. chip->p_dma.request = sbus_dma_request;
  1591. chip->p_dma.address = sbus_dma_addr;
  1592. chip->p_dma.preallocate = sbus_dma_preallocate;
  1593. chip->c_dma.prepare = sbus_dma_prepare;
  1594. chip->c_dma.enable = sbus_dma_enable;
  1595. chip->c_dma.request = sbus_dma_request;
  1596. chip->c_dma.address = sbus_dma_addr;
  1597. chip->c_dma.preallocate = sbus_dma_preallocate;
  1598. if (request_irq(sdev->irqs[0], snd_cs4231_sbus_interrupt,
  1599. IRQF_SHARED, "cs4231", chip)) {
  1600. snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %d\n",
  1601. dev, sdev->irqs[0]);
  1602. snd_cs4231_sbus_free(chip);
  1603. return -EBUSY;
  1604. }
  1605. chip->irq[0] = sdev->irqs[0];
  1606. if (snd_cs4231_probe(chip) < 0) {
  1607. snd_cs4231_sbus_free(chip);
  1608. return -ENODEV;
  1609. }
  1610. snd_cs4231_init(chip);
  1611. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
  1612. chip, &snd_cs4231_sbus_dev_ops)) < 0) {
  1613. snd_cs4231_sbus_free(chip);
  1614. return err;
  1615. }
  1616. return 0;
  1617. }
  1618. static int __init cs4231_sbus_attach(struct sbus_dev *sdev)
  1619. {
  1620. struct resource *rp = &sdev->resource[0];
  1621. struct snd_card *card;
  1622. int err;
  1623. err = cs4231_attach_begin(&card);
  1624. if (err)
  1625. return err;
  1626. sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
  1627. card->shortname,
  1628. rp->flags & 0xffL,
  1629. (unsigned long long)rp->start,
  1630. sdev->irqs[0]);
  1631. err = snd_cs4231_sbus_create(card, sdev, dev);
  1632. if (err < 0) {
  1633. snd_card_free(card);
  1634. return err;
  1635. }
  1636. return cs4231_attach_finish(card);
  1637. }
  1638. #endif
  1639. #ifdef EBUS_SUPPORT
  1640. static void snd_cs4231_ebus_play_callback(struct ebus_dma_info *p, int event, void *cookie)
  1641. {
  1642. struct snd_cs4231 *chip = cookie;
  1643. snd_cs4231_play_callback(chip);
  1644. }
  1645. static void snd_cs4231_ebus_capture_callback(struct ebus_dma_info *p, int event, void *cookie)
  1646. {
  1647. struct snd_cs4231 *chip = cookie;
  1648. snd_cs4231_capture_callback(chip);
  1649. }
  1650. /*
  1651. * EBUS DMA wrappers
  1652. */
  1653. static int _ebus_dma_request(struct cs4231_dma_control *dma_cont, dma_addr_t bus_addr, size_t len)
  1654. {
  1655. return ebus_dma_request(&dma_cont->ebus_info, bus_addr, len);
  1656. }
  1657. static void _ebus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
  1658. {
  1659. ebus_dma_enable(&dma_cont->ebus_info, on);
  1660. }
  1661. static void _ebus_dma_prepare(struct cs4231_dma_control *dma_cont, int dir)
  1662. {
  1663. ebus_dma_prepare(&dma_cont->ebus_info, dir);
  1664. }
  1665. static unsigned int _ebus_dma_addr(struct cs4231_dma_control *dma_cont)
  1666. {
  1667. return ebus_dma_addr(&dma_cont->ebus_info);
  1668. }
  1669. static void _ebus_dma_preallocate(struct snd_cs4231 *chip, struct snd_pcm *pcm)
  1670. {
  1671. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1672. snd_dma_pci_data(chip->dev_u.pdev),
  1673. 64*1024, 128*1024);
  1674. }
  1675. /*
  1676. * Init and exit routines
  1677. */
  1678. static int snd_cs4231_ebus_free(struct snd_cs4231 *chip)
  1679. {
  1680. if (chip->c_dma.ebus_info.regs) {
  1681. ebus_dma_unregister(&chip->c_dma.ebus_info);
  1682. iounmap(chip->c_dma.ebus_info.regs);
  1683. }
  1684. if (chip->p_dma.ebus_info.regs) {
  1685. ebus_dma_unregister(&chip->p_dma.ebus_info);
  1686. iounmap(chip->p_dma.ebus_info.regs);
  1687. }
  1688. if (chip->port)
  1689. iounmap(chip->port);
  1690. return 0;
  1691. }
  1692. static int snd_cs4231_ebus_dev_free(struct snd_device *device)
  1693. {
  1694. struct snd_cs4231 *cp = device->device_data;
  1695. return snd_cs4231_ebus_free(cp);
  1696. }
  1697. static struct snd_device_ops snd_cs4231_ebus_dev_ops = {
  1698. .dev_free = snd_cs4231_ebus_dev_free,
  1699. };
  1700. static int __init snd_cs4231_ebus_create(struct snd_card *card,
  1701. struct linux_ebus_device *edev,
  1702. int dev)
  1703. {
  1704. struct snd_cs4231 *chip = card->private_data;
  1705. int err;
  1706. spin_lock_init(&chip->lock);
  1707. spin_lock_init(&chip->c_dma.ebus_info.lock);
  1708. spin_lock_init(&chip->p_dma.ebus_info.lock);
  1709. mutex_init(&chip->mce_mutex);
  1710. mutex_init(&chip->open_mutex);
  1711. chip->flags |= CS4231_FLAG_EBUS;
  1712. chip->dev_u.pdev = edev->bus->self;
  1713. memcpy(&chip->image, &snd_cs4231_original_image,
  1714. sizeof(snd_cs4231_original_image));
  1715. strcpy(chip->c_dma.ebus_info.name, "cs4231(capture)");
  1716. chip->c_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
  1717. chip->c_dma.ebus_info.callback = snd_cs4231_ebus_capture_callback;
  1718. chip->c_dma.ebus_info.client_cookie = chip;
  1719. chip->c_dma.ebus_info.irq = edev->irqs[0];
  1720. strcpy(chip->p_dma.ebus_info.name, "cs4231(play)");
  1721. chip->p_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
  1722. chip->p_dma.ebus_info.callback = snd_cs4231_ebus_play_callback;
  1723. chip->p_dma.ebus_info.client_cookie = chip;
  1724. chip->p_dma.ebus_info.irq = edev->irqs[1];
  1725. chip->p_dma.prepare = _ebus_dma_prepare;
  1726. chip->p_dma.enable = _ebus_dma_enable;
  1727. chip->p_dma.request = _ebus_dma_request;
  1728. chip->p_dma.address = _ebus_dma_addr;
  1729. chip->p_dma.preallocate = _ebus_dma_preallocate;
  1730. chip->c_dma.prepare = _ebus_dma_prepare;
  1731. chip->c_dma.enable = _ebus_dma_enable;
  1732. chip->c_dma.request = _ebus_dma_request;
  1733. chip->c_dma.address = _ebus_dma_addr;
  1734. chip->c_dma.preallocate = _ebus_dma_preallocate;
  1735. chip->port = ioremap(edev->resource[0].start, 0x10);
  1736. chip->p_dma.ebus_info.regs = ioremap(edev->resource[1].start, 0x10);
  1737. chip->c_dma.ebus_info.regs = ioremap(edev->resource[2].start, 0x10);
  1738. if (!chip->port || !chip->p_dma.ebus_info.regs || !chip->c_dma.ebus_info.regs) {
  1739. snd_cs4231_ebus_free(chip);
  1740. snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
  1741. return -EIO;
  1742. }
  1743. if (ebus_dma_register(&chip->c_dma.ebus_info)) {
  1744. snd_cs4231_ebus_free(chip);
  1745. snd_printdd("cs4231-%d: Unable to register EBUS capture DMA\n", dev);
  1746. return -EBUSY;
  1747. }
  1748. if (ebus_dma_irq_enable(&chip->c_dma.ebus_info, 1)) {
  1749. snd_cs4231_ebus_free(chip);
  1750. snd_printdd("cs4231-%d: Unable to enable EBUS capture IRQ\n", dev);
  1751. return -EBUSY;
  1752. }
  1753. if (ebus_dma_register(&chip->p_dma.ebus_info)) {
  1754. snd_cs4231_ebus_free(chip);
  1755. snd_printdd("cs4231-%d: Unable to register EBUS play DMA\n", dev);
  1756. return -EBUSY;
  1757. }
  1758. if (ebus_dma_irq_enable(&chip->p_dma.ebus_info, 1)) {
  1759. snd_cs4231_ebus_free(chip);
  1760. snd_printdd("cs4231-%d: Unable to enable EBUS play IRQ\n", dev);
  1761. return -EBUSY;
  1762. }
  1763. if (snd_cs4231_probe(chip) < 0) {
  1764. snd_cs4231_ebus_free(chip);
  1765. return -ENODEV;
  1766. }
  1767. snd_cs4231_init(chip);
  1768. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
  1769. chip, &snd_cs4231_ebus_dev_ops)) < 0) {
  1770. snd_cs4231_ebus_free(chip);
  1771. return err;
  1772. }
  1773. return 0;
  1774. }
  1775. static int __init cs4231_ebus_attach(struct linux_ebus_device *edev)
  1776. {
  1777. struct snd_card *card;
  1778. int err;
  1779. err = cs4231_attach_begin(&card);
  1780. if (err)
  1781. return err;
  1782. sprintf(card->longname, "%s at 0x%lx, irq %d",
  1783. card->shortname,
  1784. edev->resource[0].start,
  1785. edev->irqs[0]);
  1786. err = snd_cs4231_ebus_create(card, edev, dev);
  1787. if (err < 0) {
  1788. snd_card_free(card);
  1789. return err;
  1790. }
  1791. return cs4231_attach_finish(card);
  1792. }
  1793. #endif
  1794. static int __init cs4231_init(void)
  1795. {
  1796. #ifdef SBUS_SUPPORT
  1797. struct sbus_bus *sbus;
  1798. struct sbus_dev *sdev;
  1799. #endif
  1800. #ifdef EBUS_SUPPORT
  1801. struct linux_ebus *ebus;
  1802. struct linux_ebus_device *edev;
  1803. #endif
  1804. int found;
  1805. found = 0;
  1806. #ifdef SBUS_SUPPORT
  1807. for_all_sbusdev(sdev, sbus) {
  1808. if (!strcmp(sdev->prom_name, "SUNW,CS4231")) {
  1809. if (cs4231_sbus_attach(sdev) == 0)
  1810. found++;
  1811. }
  1812. }
  1813. #endif
  1814. #ifdef EBUS_SUPPORT
  1815. for_each_ebus(ebus) {
  1816. for_each_ebusdev(edev, ebus) {
  1817. int match = 0;
  1818. if (!strcmp(edev->prom_node->name, "SUNW,CS4231")) {
  1819. match = 1;
  1820. } else if (!strcmp(edev->prom_node->name, "audio")) {
  1821. const char *compat;
  1822. compat = of_get_property(edev->prom_node,
  1823. "compatible", NULL);
  1824. if (compat && !strcmp(compat, "SUNW,CS4231"))
  1825. match = 1;
  1826. }
  1827. if (match &&
  1828. cs4231_ebus_attach(edev) == 0)
  1829. found++;
  1830. }
  1831. }
  1832. #endif
  1833. return (found > 0) ? 0 : -EIO;
  1834. }
  1835. static void __exit cs4231_exit(void)
  1836. {
  1837. struct snd_cs4231 *p = cs4231_list;
  1838. while (p != NULL) {
  1839. struct snd_cs4231 *next = p->next;
  1840. snd_card_free(p->card);
  1841. p = next;
  1842. }
  1843. cs4231_list = NULL;
  1844. }
  1845. module_init(cs4231_init);
  1846. module_exit(cs4231_exit);