qla_isr.c 81 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_target.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <scsi/scsi_tcq.h>
  12. #include <scsi/scsi_bsg_fc.h>
  13. #include <scsi/scsi_eh.h>
  14. static void qla2x00_mbx_completion(scsi_qla_host_t *, uint16_t);
  15. static void qla2x00_status_entry(scsi_qla_host_t *, struct rsp_que *, void *);
  16. static void qla2x00_status_cont_entry(struct rsp_que *, sts_cont_entry_t *);
  17. static void qla2x00_error_entry(scsi_qla_host_t *, struct rsp_que *,
  18. sts_entry_t *);
  19. /**
  20. * qla2100_intr_handler() - Process interrupts for the ISP2100 and ISP2200.
  21. * @irq:
  22. * @dev_id: SCSI driver HA context
  23. *
  24. * Called by system whenever the host adapter generates an interrupt.
  25. *
  26. * Returns handled flag.
  27. */
  28. irqreturn_t
  29. qla2100_intr_handler(int irq, void *dev_id)
  30. {
  31. scsi_qla_host_t *vha;
  32. struct qla_hw_data *ha;
  33. struct device_reg_2xxx __iomem *reg;
  34. int status;
  35. unsigned long iter;
  36. uint16_t hccr;
  37. uint16_t mb[4];
  38. struct rsp_que *rsp;
  39. unsigned long flags;
  40. rsp = (struct rsp_que *) dev_id;
  41. if (!rsp) {
  42. ql_log(ql_log_info, NULL, 0x505d,
  43. "%s: NULL response queue pointer.\n", __func__);
  44. return (IRQ_NONE);
  45. }
  46. ha = rsp->hw;
  47. reg = &ha->iobase->isp;
  48. status = 0;
  49. spin_lock_irqsave(&ha->hardware_lock, flags);
  50. vha = pci_get_drvdata(ha->pdev);
  51. for (iter = 50; iter--; ) {
  52. hccr = RD_REG_WORD(&reg->hccr);
  53. if (hccr & HCCR_RISC_PAUSE) {
  54. if (pci_channel_offline(ha->pdev))
  55. break;
  56. /*
  57. * Issue a "HARD" reset in order for the RISC interrupt
  58. * bit to be cleared. Schedule a big hammer to get
  59. * out of the RISC PAUSED state.
  60. */
  61. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  62. RD_REG_WORD(&reg->hccr);
  63. ha->isp_ops->fw_dump(vha, 1);
  64. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  65. break;
  66. } else if ((RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) == 0)
  67. break;
  68. if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
  69. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  70. RD_REG_WORD(&reg->hccr);
  71. /* Get mailbox data. */
  72. mb[0] = RD_MAILBOX_REG(ha, reg, 0);
  73. if (mb[0] > 0x3fff && mb[0] < 0x8000) {
  74. qla2x00_mbx_completion(vha, mb[0]);
  75. status |= MBX_INTERRUPT;
  76. } else if (mb[0] > 0x7fff && mb[0] < 0xc000) {
  77. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  78. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  79. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  80. qla2x00_async_event(vha, rsp, mb);
  81. } else {
  82. /*EMPTY*/
  83. ql_dbg(ql_dbg_async, vha, 0x5025,
  84. "Unrecognized interrupt type (%d).\n",
  85. mb[0]);
  86. }
  87. /* Release mailbox registers. */
  88. WRT_REG_WORD(&reg->semaphore, 0);
  89. RD_REG_WORD(&reg->semaphore);
  90. } else {
  91. qla2x00_process_response_queue(rsp);
  92. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  93. RD_REG_WORD(&reg->hccr);
  94. }
  95. }
  96. qla2x00_handle_mbx_completion(ha, status);
  97. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  98. return (IRQ_HANDLED);
  99. }
  100. /**
  101. * qla2300_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
  102. * @irq:
  103. * @dev_id: SCSI driver HA context
  104. *
  105. * Called by system whenever the host adapter generates an interrupt.
  106. *
  107. * Returns handled flag.
  108. */
  109. irqreturn_t
  110. qla2300_intr_handler(int irq, void *dev_id)
  111. {
  112. scsi_qla_host_t *vha;
  113. struct device_reg_2xxx __iomem *reg;
  114. int status;
  115. unsigned long iter;
  116. uint32_t stat;
  117. uint16_t hccr;
  118. uint16_t mb[4];
  119. struct rsp_que *rsp;
  120. struct qla_hw_data *ha;
  121. unsigned long flags;
  122. rsp = (struct rsp_que *) dev_id;
  123. if (!rsp) {
  124. ql_log(ql_log_info, NULL, 0x5058,
  125. "%s: NULL response queue pointer.\n", __func__);
  126. return (IRQ_NONE);
  127. }
  128. ha = rsp->hw;
  129. reg = &ha->iobase->isp;
  130. status = 0;
  131. spin_lock_irqsave(&ha->hardware_lock, flags);
  132. vha = pci_get_drvdata(ha->pdev);
  133. for (iter = 50; iter--; ) {
  134. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  135. if (stat & HSR_RISC_PAUSED) {
  136. if (unlikely(pci_channel_offline(ha->pdev)))
  137. break;
  138. hccr = RD_REG_WORD(&reg->hccr);
  139. if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
  140. ql_log(ql_log_warn, vha, 0x5026,
  141. "Parity error -- HCCR=%x, Dumping "
  142. "firmware.\n", hccr);
  143. else
  144. ql_log(ql_log_warn, vha, 0x5027,
  145. "RISC paused -- HCCR=%x, Dumping "
  146. "firmware.\n", hccr);
  147. /*
  148. * Issue a "HARD" reset in order for the RISC
  149. * interrupt bit to be cleared. Schedule a big
  150. * hammer to get out of the RISC PAUSED state.
  151. */
  152. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  153. RD_REG_WORD(&reg->hccr);
  154. ha->isp_ops->fw_dump(vha, 1);
  155. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  156. break;
  157. } else if ((stat & HSR_RISC_INT) == 0)
  158. break;
  159. switch (stat & 0xff) {
  160. case 0x1:
  161. case 0x2:
  162. case 0x10:
  163. case 0x11:
  164. qla2x00_mbx_completion(vha, MSW(stat));
  165. status |= MBX_INTERRUPT;
  166. /* Release mailbox registers. */
  167. WRT_REG_WORD(&reg->semaphore, 0);
  168. break;
  169. case 0x12:
  170. mb[0] = MSW(stat);
  171. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  172. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  173. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  174. qla2x00_async_event(vha, rsp, mb);
  175. break;
  176. case 0x13:
  177. qla2x00_process_response_queue(rsp);
  178. break;
  179. case 0x15:
  180. mb[0] = MBA_CMPLT_1_16BIT;
  181. mb[1] = MSW(stat);
  182. qla2x00_async_event(vha, rsp, mb);
  183. break;
  184. case 0x16:
  185. mb[0] = MBA_SCSI_COMPLETION;
  186. mb[1] = MSW(stat);
  187. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  188. qla2x00_async_event(vha, rsp, mb);
  189. break;
  190. default:
  191. ql_dbg(ql_dbg_async, vha, 0x5028,
  192. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  193. break;
  194. }
  195. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  196. RD_REG_WORD_RELAXED(&reg->hccr);
  197. }
  198. qla2x00_handle_mbx_completion(ha, status);
  199. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  200. return (IRQ_HANDLED);
  201. }
  202. /**
  203. * qla2x00_mbx_completion() - Process mailbox command completions.
  204. * @ha: SCSI driver HA context
  205. * @mb0: Mailbox0 register
  206. */
  207. static void
  208. qla2x00_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  209. {
  210. uint16_t cnt;
  211. uint32_t mboxes;
  212. uint16_t __iomem *wptr;
  213. struct qla_hw_data *ha = vha->hw;
  214. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  215. /* Read all mbox registers? */
  216. mboxes = (1 << ha->mbx_count) - 1;
  217. if (!ha->mcp)
  218. ql_dbg(ql_dbg_async, vha, 0x5001, "MBX pointer ERROR.\n");
  219. else
  220. mboxes = ha->mcp->in_mb;
  221. /* Load return mailbox registers. */
  222. ha->flags.mbox_int = 1;
  223. ha->mailbox_out[0] = mb0;
  224. mboxes >>= 1;
  225. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1);
  226. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  227. if (IS_QLA2200(ha) && cnt == 8)
  228. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8);
  229. if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0))
  230. ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr);
  231. else if (mboxes & BIT_0)
  232. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  233. wptr++;
  234. mboxes >>= 1;
  235. }
  236. }
  237. static void
  238. qla81xx_idc_event(scsi_qla_host_t *vha, uint16_t aen, uint16_t descr)
  239. {
  240. static char *event[] =
  241. { "Complete", "Request Notification", "Time Extension" };
  242. int rval;
  243. struct device_reg_24xx __iomem *reg24 = &vha->hw->iobase->isp24;
  244. uint16_t __iomem *wptr;
  245. uint16_t cnt, timeout, mb[QLA_IDC_ACK_REGS];
  246. /* Seed data -- mailbox1 -> mailbox7. */
  247. wptr = (uint16_t __iomem *)&reg24->mailbox1;
  248. for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr++)
  249. mb[cnt] = RD_REG_WORD(wptr);
  250. ql_dbg(ql_dbg_async, vha, 0x5021,
  251. "Inter-Driver Communication %s -- "
  252. "%04x %04x %04x %04x %04x %04x %04x.\n",
  253. event[aen & 0xff], mb[0], mb[1], mb[2], mb[3],
  254. mb[4], mb[5], mb[6]);
  255. if ((aen == MBA_IDC_COMPLETE && mb[1] >> 15)) {
  256. vha->hw->flags.idc_compl_status = 1;
  257. if (vha->hw->notify_dcbx_comp)
  258. complete(&vha->hw->dcbx_comp);
  259. }
  260. /* Acknowledgement needed? [Notify && non-zero timeout]. */
  261. timeout = (descr >> 8) & 0xf;
  262. if (aen != MBA_IDC_NOTIFY || !timeout)
  263. return;
  264. ql_dbg(ql_dbg_async, vha, 0x5022,
  265. "%lu Inter-Driver Communication %s -- ACK timeout=%d.\n",
  266. vha->host_no, event[aen & 0xff], timeout);
  267. rval = qla2x00_post_idc_ack_work(vha, mb);
  268. if (rval != QLA_SUCCESS)
  269. ql_log(ql_log_warn, vha, 0x5023,
  270. "IDC failed to post ACK.\n");
  271. }
  272. #define LS_UNKNOWN 2
  273. const char *
  274. qla2x00_get_link_speed_str(struct qla_hw_data *ha, uint16_t speed)
  275. {
  276. static const char * const link_speeds[] = {
  277. "1", "2", "?", "4", "8", "16", "10"
  278. };
  279. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  280. return link_speeds[0];
  281. else if (speed == 0x13)
  282. return link_speeds[6];
  283. else if (speed < 6)
  284. return link_speeds[speed];
  285. else
  286. return link_speeds[LS_UNKNOWN];
  287. }
  288. static void
  289. qla83xx_handle_8200_aen(scsi_qla_host_t *vha, uint16_t *mb)
  290. {
  291. struct qla_hw_data *ha = vha->hw;
  292. /*
  293. * 8200 AEN Interpretation:
  294. * mb[0] = AEN code
  295. * mb[1] = AEN Reason code
  296. * mb[2] = LSW of Peg-Halt Status-1 Register
  297. * mb[6] = MSW of Peg-Halt Status-1 Register
  298. * mb[3] = LSW of Peg-Halt Status-2 register
  299. * mb[7] = MSW of Peg-Halt Status-2 register
  300. * mb[4] = IDC Device-State Register value
  301. * mb[5] = IDC Driver-Presence Register value
  302. */
  303. ql_dbg(ql_dbg_async, vha, 0x506b, "AEN Code: mb[0] = 0x%x AEN reason: "
  304. "mb[1] = 0x%x PH-status1: mb[2] = 0x%x PH-status1: mb[6] = 0x%x.\n",
  305. mb[0], mb[1], mb[2], mb[6]);
  306. ql_dbg(ql_dbg_async, vha, 0x506c, "PH-status2: mb[3] = 0x%x "
  307. "PH-status2: mb[7] = 0x%x Device-State: mb[4] = 0x%x "
  308. "Drv-Presence: mb[5] = 0x%x.\n", mb[3], mb[7], mb[4], mb[5]);
  309. if (mb[1] & (IDC_PEG_HALT_STATUS_CHANGE | IDC_NIC_FW_REPORTED_FAILURE |
  310. IDC_HEARTBEAT_FAILURE)) {
  311. ha->flags.nic_core_hung = 1;
  312. ql_log(ql_log_warn, vha, 0x5060,
  313. "83XX: F/W Error Reported: Check if reset required.\n");
  314. if (mb[1] & IDC_PEG_HALT_STATUS_CHANGE) {
  315. uint32_t protocol_engine_id, fw_err_code, err_level;
  316. /*
  317. * IDC_PEG_HALT_STATUS_CHANGE interpretation:
  318. * - PEG-Halt Status-1 Register:
  319. * (LSW = mb[2], MSW = mb[6])
  320. * Bits 0-7 = protocol-engine ID
  321. * Bits 8-28 = f/w error code
  322. * Bits 29-31 = Error-level
  323. * Error-level 0x1 = Non-Fatal error
  324. * Error-level 0x2 = Recoverable Fatal error
  325. * Error-level 0x4 = UnRecoverable Fatal error
  326. * - PEG-Halt Status-2 Register:
  327. * (LSW = mb[3], MSW = mb[7])
  328. */
  329. protocol_engine_id = (mb[2] & 0xff);
  330. fw_err_code = (((mb[2] & 0xff00) >> 8) |
  331. ((mb[6] & 0x1fff) << 8));
  332. err_level = ((mb[6] & 0xe000) >> 13);
  333. ql_log(ql_log_warn, vha, 0x5061, "PegHalt Status-1 "
  334. "Register: protocol_engine_id=0x%x "
  335. "fw_err_code=0x%x err_level=0x%x.\n",
  336. protocol_engine_id, fw_err_code, err_level);
  337. ql_log(ql_log_warn, vha, 0x5062, "PegHalt Status-2 "
  338. "Register: 0x%x%x.\n", mb[7], mb[3]);
  339. if (err_level == ERR_LEVEL_NON_FATAL) {
  340. ql_log(ql_log_warn, vha, 0x5063,
  341. "Not a fatal error, f/w has recovered "
  342. "iteself.\n");
  343. } else if (err_level == ERR_LEVEL_RECOVERABLE_FATAL) {
  344. ql_log(ql_log_fatal, vha, 0x5064,
  345. "Recoverable Fatal error: Chip reset "
  346. "required.\n");
  347. qla83xx_schedule_work(vha,
  348. QLA83XX_NIC_CORE_RESET);
  349. } else if (err_level == ERR_LEVEL_UNRECOVERABLE_FATAL) {
  350. ql_log(ql_log_fatal, vha, 0x5065,
  351. "Unrecoverable Fatal error: Set FAILED "
  352. "state, reboot required.\n");
  353. qla83xx_schedule_work(vha,
  354. QLA83XX_NIC_CORE_UNRECOVERABLE);
  355. }
  356. }
  357. if (mb[1] & IDC_NIC_FW_REPORTED_FAILURE) {
  358. uint16_t peg_fw_state, nw_interface_link_up;
  359. uint16_t nw_interface_signal_detect, sfp_status;
  360. uint16_t htbt_counter, htbt_monitor_enable;
  361. uint16_t sfp_additonal_info, sfp_multirate;
  362. uint16_t sfp_tx_fault, link_speed, dcbx_status;
  363. /*
  364. * IDC_NIC_FW_REPORTED_FAILURE interpretation:
  365. * - PEG-to-FC Status Register:
  366. * (LSW = mb[2], MSW = mb[6])
  367. * Bits 0-7 = Peg-Firmware state
  368. * Bit 8 = N/W Interface Link-up
  369. * Bit 9 = N/W Interface signal detected
  370. * Bits 10-11 = SFP Status
  371. * SFP Status 0x0 = SFP+ transceiver not expected
  372. * SFP Status 0x1 = SFP+ transceiver not present
  373. * SFP Status 0x2 = SFP+ transceiver invalid
  374. * SFP Status 0x3 = SFP+ transceiver present and
  375. * valid
  376. * Bits 12-14 = Heartbeat Counter
  377. * Bit 15 = Heartbeat Monitor Enable
  378. * Bits 16-17 = SFP Additional Info
  379. * SFP info 0x0 = Unregocnized transceiver for
  380. * Ethernet
  381. * SFP info 0x1 = SFP+ brand validation failed
  382. * SFP info 0x2 = SFP+ speed validation failed
  383. * SFP info 0x3 = SFP+ access error
  384. * Bit 18 = SFP Multirate
  385. * Bit 19 = SFP Tx Fault
  386. * Bits 20-22 = Link Speed
  387. * Bits 23-27 = Reserved
  388. * Bits 28-30 = DCBX Status
  389. * DCBX Status 0x0 = DCBX Disabled
  390. * DCBX Status 0x1 = DCBX Enabled
  391. * DCBX Status 0x2 = DCBX Exchange error
  392. * Bit 31 = Reserved
  393. */
  394. peg_fw_state = (mb[2] & 0x00ff);
  395. nw_interface_link_up = ((mb[2] & 0x0100) >> 8);
  396. nw_interface_signal_detect = ((mb[2] & 0x0200) >> 9);
  397. sfp_status = ((mb[2] & 0x0c00) >> 10);
  398. htbt_counter = ((mb[2] & 0x7000) >> 12);
  399. htbt_monitor_enable = ((mb[2] & 0x8000) >> 15);
  400. sfp_additonal_info = (mb[6] & 0x0003);
  401. sfp_multirate = ((mb[6] & 0x0004) >> 2);
  402. sfp_tx_fault = ((mb[6] & 0x0008) >> 3);
  403. link_speed = ((mb[6] & 0x0070) >> 4);
  404. dcbx_status = ((mb[6] & 0x7000) >> 12);
  405. ql_log(ql_log_warn, vha, 0x5066,
  406. "Peg-to-Fc Status Register:\n"
  407. "peg_fw_state=0x%x, nw_interface_link_up=0x%x, "
  408. "nw_interface_signal_detect=0x%x"
  409. "\nsfp_statis=0x%x.\n ", peg_fw_state,
  410. nw_interface_link_up, nw_interface_signal_detect,
  411. sfp_status);
  412. ql_log(ql_log_warn, vha, 0x5067,
  413. "htbt_counter=0x%x, htbt_monitor_enable=0x%x, "
  414. "sfp_additonal_info=0x%x, sfp_multirate=0x%x.\n ",
  415. htbt_counter, htbt_monitor_enable,
  416. sfp_additonal_info, sfp_multirate);
  417. ql_log(ql_log_warn, vha, 0x5068,
  418. "sfp_tx_fault=0x%x, link_state=0x%x, "
  419. "dcbx_status=0x%x.\n", sfp_tx_fault, link_speed,
  420. dcbx_status);
  421. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  422. }
  423. if (mb[1] & IDC_HEARTBEAT_FAILURE) {
  424. ql_log(ql_log_warn, vha, 0x5069,
  425. "Heartbeat Failure encountered, chip reset "
  426. "required.\n");
  427. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  428. }
  429. }
  430. if (mb[1] & IDC_DEVICE_STATE_CHANGE) {
  431. ql_log(ql_log_info, vha, 0x506a,
  432. "IDC Device-State changed = 0x%x.\n", mb[4]);
  433. if (ha->flags.nic_core_reset_owner)
  434. return;
  435. qla83xx_schedule_work(vha, MBA_IDC_AEN);
  436. }
  437. }
  438. int
  439. qla2x00_is_a_vp_did(scsi_qla_host_t *vha, uint32_t rscn_entry)
  440. {
  441. struct qla_hw_data *ha = vha->hw;
  442. scsi_qla_host_t *vp;
  443. uint32_t vp_did;
  444. unsigned long flags;
  445. int ret = 0;
  446. if (!ha->num_vhosts)
  447. return ret;
  448. spin_lock_irqsave(&ha->vport_slock, flags);
  449. list_for_each_entry(vp, &ha->vp_list, list) {
  450. vp_did = vp->d_id.b24;
  451. if (vp_did == rscn_entry) {
  452. ret = 1;
  453. break;
  454. }
  455. }
  456. spin_unlock_irqrestore(&ha->vport_slock, flags);
  457. return ret;
  458. }
  459. /**
  460. * qla2x00_async_event() - Process aynchronous events.
  461. * @ha: SCSI driver HA context
  462. * @mb: Mailbox registers (0 - 3)
  463. */
  464. void
  465. qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
  466. {
  467. uint16_t handle_cnt;
  468. uint16_t cnt, mbx;
  469. uint32_t handles[5];
  470. struct qla_hw_data *ha = vha->hw;
  471. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  472. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  473. struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
  474. uint32_t rscn_entry, host_pid;
  475. unsigned long flags;
  476. /* Setup to process RIO completion. */
  477. handle_cnt = 0;
  478. if (IS_CNA_CAPABLE(ha))
  479. goto skip_rio;
  480. switch (mb[0]) {
  481. case MBA_SCSI_COMPLETION:
  482. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  483. handle_cnt = 1;
  484. break;
  485. case MBA_CMPLT_1_16BIT:
  486. handles[0] = mb[1];
  487. handle_cnt = 1;
  488. mb[0] = MBA_SCSI_COMPLETION;
  489. break;
  490. case MBA_CMPLT_2_16BIT:
  491. handles[0] = mb[1];
  492. handles[1] = mb[2];
  493. handle_cnt = 2;
  494. mb[0] = MBA_SCSI_COMPLETION;
  495. break;
  496. case MBA_CMPLT_3_16BIT:
  497. handles[0] = mb[1];
  498. handles[1] = mb[2];
  499. handles[2] = mb[3];
  500. handle_cnt = 3;
  501. mb[0] = MBA_SCSI_COMPLETION;
  502. break;
  503. case MBA_CMPLT_4_16BIT:
  504. handles[0] = mb[1];
  505. handles[1] = mb[2];
  506. handles[2] = mb[3];
  507. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  508. handle_cnt = 4;
  509. mb[0] = MBA_SCSI_COMPLETION;
  510. break;
  511. case MBA_CMPLT_5_16BIT:
  512. handles[0] = mb[1];
  513. handles[1] = mb[2];
  514. handles[2] = mb[3];
  515. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  516. handles[4] = (uint32_t)RD_MAILBOX_REG(ha, reg, 7);
  517. handle_cnt = 5;
  518. mb[0] = MBA_SCSI_COMPLETION;
  519. break;
  520. case MBA_CMPLT_2_32BIT:
  521. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  522. handles[1] = le32_to_cpu(
  523. ((uint32_t)(RD_MAILBOX_REG(ha, reg, 7) << 16)) |
  524. RD_MAILBOX_REG(ha, reg, 6));
  525. handle_cnt = 2;
  526. mb[0] = MBA_SCSI_COMPLETION;
  527. break;
  528. default:
  529. break;
  530. }
  531. skip_rio:
  532. switch (mb[0]) {
  533. case MBA_SCSI_COMPLETION: /* Fast Post */
  534. if (!vha->flags.online)
  535. break;
  536. for (cnt = 0; cnt < handle_cnt; cnt++)
  537. qla2x00_process_completed_request(vha, rsp->req,
  538. handles[cnt]);
  539. break;
  540. case MBA_RESET: /* Reset */
  541. ql_dbg(ql_dbg_async, vha, 0x5002,
  542. "Asynchronous RESET.\n");
  543. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  544. break;
  545. case MBA_SYSTEM_ERR: /* System Error */
  546. mbx = (IS_QLA81XX(ha) || IS_QLA83XX(ha)) ?
  547. RD_REG_WORD(&reg24->mailbox7) : 0;
  548. ql_log(ql_log_warn, vha, 0x5003,
  549. "ISP System Error - mbx1=%xh mbx2=%xh mbx3=%xh "
  550. "mbx7=%xh.\n", mb[1], mb[2], mb[3], mbx);
  551. ha->isp_ops->fw_dump(vha, 1);
  552. if (IS_FWI2_CAPABLE(ha)) {
  553. if (mb[1] == 0 && mb[2] == 0) {
  554. ql_log(ql_log_fatal, vha, 0x5004,
  555. "Unrecoverable Hardware Error: adapter "
  556. "marked OFFLINE!\n");
  557. vha->flags.online = 0;
  558. vha->device_flags |= DFLG_DEV_FAILED;
  559. } else {
  560. /* Check to see if MPI timeout occurred */
  561. if ((mbx & MBX_3) && (ha->flags.port0))
  562. set_bit(MPI_RESET_NEEDED,
  563. &vha->dpc_flags);
  564. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  565. }
  566. } else if (mb[1] == 0) {
  567. ql_log(ql_log_fatal, vha, 0x5005,
  568. "Unrecoverable Hardware Error: adapter marked "
  569. "OFFLINE!\n");
  570. vha->flags.online = 0;
  571. vha->device_flags |= DFLG_DEV_FAILED;
  572. } else
  573. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  574. break;
  575. case MBA_REQ_TRANSFER_ERR: /* Request Transfer Error */
  576. ql_log(ql_log_warn, vha, 0x5006,
  577. "ISP Request Transfer Error (%x).\n", mb[1]);
  578. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  579. break;
  580. case MBA_RSP_TRANSFER_ERR: /* Response Transfer Error */
  581. ql_log(ql_log_warn, vha, 0x5007,
  582. "ISP Response Transfer Error.\n");
  583. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  584. break;
  585. case MBA_WAKEUP_THRES: /* Request Queue Wake-up */
  586. ql_dbg(ql_dbg_async, vha, 0x5008,
  587. "Asynchronous WAKEUP_THRES.\n");
  588. break;
  589. case MBA_LIP_OCCURRED: /* Loop Initialization Procedure */
  590. ql_dbg(ql_dbg_async, vha, 0x5009,
  591. "LIP occurred (%x).\n", mb[1]);
  592. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  593. atomic_set(&vha->loop_state, LOOP_DOWN);
  594. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  595. qla2x00_mark_all_devices_lost(vha, 1);
  596. }
  597. if (vha->vp_idx) {
  598. atomic_set(&vha->vp_state, VP_FAILED);
  599. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  600. }
  601. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  602. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  603. vha->flags.management_server_logged_in = 0;
  604. qla2x00_post_aen_work(vha, FCH_EVT_LIP, mb[1]);
  605. break;
  606. case MBA_LOOP_UP: /* Loop Up Event */
  607. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  608. ha->link_data_rate = PORT_SPEED_1GB;
  609. else
  610. ha->link_data_rate = mb[1];
  611. ql_dbg(ql_dbg_async, vha, 0x500a,
  612. "LOOP UP detected (%s Gbps).\n",
  613. qla2x00_get_link_speed_str(ha, ha->link_data_rate));
  614. vha->flags.management_server_logged_in = 0;
  615. qla2x00_post_aen_work(vha, FCH_EVT_LINKUP, ha->link_data_rate);
  616. break;
  617. case MBA_LOOP_DOWN: /* Loop Down Event */
  618. mbx = (IS_QLA81XX(ha) || IS_QLA8031(ha))
  619. ? RD_REG_WORD(&reg24->mailbox4) : 0;
  620. mbx = IS_QLA82XX(ha) ? RD_REG_WORD(&reg82->mailbox_out[4]) : mbx;
  621. ql_dbg(ql_dbg_async, vha, 0x500b,
  622. "LOOP DOWN detected (%x %x %x %x).\n",
  623. mb[1], mb[2], mb[3], mbx);
  624. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  625. atomic_set(&vha->loop_state, LOOP_DOWN);
  626. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  627. vha->device_flags |= DFLG_NO_CABLE;
  628. qla2x00_mark_all_devices_lost(vha, 1);
  629. }
  630. if (vha->vp_idx) {
  631. atomic_set(&vha->vp_state, VP_FAILED);
  632. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  633. }
  634. vha->flags.management_server_logged_in = 0;
  635. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  636. qla2x00_post_aen_work(vha, FCH_EVT_LINKDOWN, 0);
  637. break;
  638. case MBA_LIP_RESET: /* LIP reset occurred */
  639. ql_dbg(ql_dbg_async, vha, 0x500c,
  640. "LIP reset occurred (%x).\n", mb[1]);
  641. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  642. atomic_set(&vha->loop_state, LOOP_DOWN);
  643. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  644. qla2x00_mark_all_devices_lost(vha, 1);
  645. }
  646. if (vha->vp_idx) {
  647. atomic_set(&vha->vp_state, VP_FAILED);
  648. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  649. }
  650. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  651. ha->operating_mode = LOOP;
  652. vha->flags.management_server_logged_in = 0;
  653. qla2x00_post_aen_work(vha, FCH_EVT_LIPRESET, mb[1]);
  654. break;
  655. /* case MBA_DCBX_COMPLETE: */
  656. case MBA_POINT_TO_POINT: /* Point-to-Point */
  657. if (IS_QLA2100(ha))
  658. break;
  659. if (IS_QLA81XX(ha) || IS_QLA82XX(ha) || IS_QLA8031(ha)) {
  660. ql_dbg(ql_dbg_async, vha, 0x500d,
  661. "DCBX Completed -- %04x %04x %04x.\n",
  662. mb[1], mb[2], mb[3]);
  663. if (ha->notify_dcbx_comp)
  664. complete(&ha->dcbx_comp);
  665. } else
  666. ql_dbg(ql_dbg_async, vha, 0x500e,
  667. "Asynchronous P2P MODE received.\n");
  668. /*
  669. * Until there's a transition from loop down to loop up, treat
  670. * this as loop down only.
  671. */
  672. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  673. atomic_set(&vha->loop_state, LOOP_DOWN);
  674. if (!atomic_read(&vha->loop_down_timer))
  675. atomic_set(&vha->loop_down_timer,
  676. LOOP_DOWN_TIME);
  677. qla2x00_mark_all_devices_lost(vha, 1);
  678. }
  679. if (vha->vp_idx) {
  680. atomic_set(&vha->vp_state, VP_FAILED);
  681. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  682. }
  683. if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)))
  684. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  685. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  686. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  687. ha->flags.gpsc_supported = 1;
  688. vha->flags.management_server_logged_in = 0;
  689. break;
  690. case MBA_CHG_IN_CONNECTION: /* Change in connection mode */
  691. if (IS_QLA2100(ha))
  692. break;
  693. ql_dbg(ql_dbg_async, vha, 0x500f,
  694. "Configuration change detected: value=%x.\n", mb[1]);
  695. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  696. atomic_set(&vha->loop_state, LOOP_DOWN);
  697. if (!atomic_read(&vha->loop_down_timer))
  698. atomic_set(&vha->loop_down_timer,
  699. LOOP_DOWN_TIME);
  700. qla2x00_mark_all_devices_lost(vha, 1);
  701. }
  702. if (vha->vp_idx) {
  703. atomic_set(&vha->vp_state, VP_FAILED);
  704. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  705. }
  706. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  707. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  708. break;
  709. case MBA_PORT_UPDATE: /* Port database update */
  710. /*
  711. * Handle only global and vn-port update events
  712. *
  713. * Relevant inputs:
  714. * mb[1] = N_Port handle of changed port
  715. * OR 0xffff for global event
  716. * mb[2] = New login state
  717. * 7 = Port logged out
  718. * mb[3] = LSB is vp_idx, 0xff = all vps
  719. *
  720. * Skip processing if:
  721. * Event is global, vp_idx is NOT all vps,
  722. * vp_idx does not match
  723. * Event is not global, vp_idx does not match
  724. */
  725. if (IS_QLA2XXX_MIDTYPE(ha) &&
  726. ((mb[1] == 0xffff && (mb[3] & 0xff) != 0xff) ||
  727. (mb[1] != 0xffff)) && vha->vp_idx != (mb[3] & 0xff))
  728. break;
  729. /* Global event -- port logout or port unavailable. */
  730. if (mb[1] == 0xffff && mb[2] == 0x7) {
  731. ql_dbg(ql_dbg_async, vha, 0x5010,
  732. "Port unavailable %04x %04x %04x.\n",
  733. mb[1], mb[2], mb[3]);
  734. ql_log(ql_log_warn, vha, 0x505e,
  735. "Link is offline.\n");
  736. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  737. atomic_set(&vha->loop_state, LOOP_DOWN);
  738. atomic_set(&vha->loop_down_timer,
  739. LOOP_DOWN_TIME);
  740. vha->device_flags |= DFLG_NO_CABLE;
  741. qla2x00_mark_all_devices_lost(vha, 1);
  742. }
  743. if (vha->vp_idx) {
  744. atomic_set(&vha->vp_state, VP_FAILED);
  745. fc_vport_set_state(vha->fc_vport,
  746. FC_VPORT_FAILED);
  747. qla2x00_mark_all_devices_lost(vha, 1);
  748. }
  749. vha->flags.management_server_logged_in = 0;
  750. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  751. break;
  752. }
  753. /*
  754. * If PORT UPDATE is global (received LIP_OCCURRED/LIP_RESET
  755. * event etc. earlier indicating loop is down) then process
  756. * it. Otherwise ignore it and Wait for RSCN to come in.
  757. */
  758. atomic_set(&vha->loop_down_timer, 0);
  759. if (mb[1] != 0xffff || (mb[2] != 0x6 && mb[2] != 0x4)) {
  760. ql_dbg(ql_dbg_async, vha, 0x5011,
  761. "Asynchronous PORT UPDATE ignored %04x/%04x/%04x.\n",
  762. mb[1], mb[2], mb[3]);
  763. qlt_async_event(mb[0], vha, mb);
  764. break;
  765. }
  766. ql_dbg(ql_dbg_async, vha, 0x5012,
  767. "Port database changed %04x %04x %04x.\n",
  768. mb[1], mb[2], mb[3]);
  769. ql_log(ql_log_warn, vha, 0x505f,
  770. "Link is operational (%s Gbps).\n",
  771. qla2x00_get_link_speed_str(ha, ha->link_data_rate));
  772. /*
  773. * Mark all devices as missing so we will login again.
  774. */
  775. atomic_set(&vha->loop_state, LOOP_UP);
  776. qla2x00_mark_all_devices_lost(vha, 1);
  777. if (vha->vp_idx == 0 && !qla_ini_mode_enabled(vha))
  778. set_bit(SCR_PENDING, &vha->dpc_flags);
  779. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  780. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  781. qlt_async_event(mb[0], vha, mb);
  782. break;
  783. case MBA_RSCN_UPDATE: /* State Change Registration */
  784. /* Check if the Vport has issued a SCR */
  785. if (vha->vp_idx && test_bit(VP_SCR_NEEDED, &vha->vp_flags))
  786. break;
  787. /* Only handle SCNs for our Vport index. */
  788. if (ha->flags.npiv_supported && vha->vp_idx != (mb[3] & 0xff))
  789. break;
  790. ql_dbg(ql_dbg_async, vha, 0x5013,
  791. "RSCN database changed -- %04x %04x %04x.\n",
  792. mb[1], mb[2], mb[3]);
  793. rscn_entry = ((mb[1] & 0xff) << 16) | mb[2];
  794. host_pid = (vha->d_id.b.domain << 16) | (vha->d_id.b.area << 8)
  795. | vha->d_id.b.al_pa;
  796. if (rscn_entry == host_pid) {
  797. ql_dbg(ql_dbg_async, vha, 0x5014,
  798. "Ignoring RSCN update to local host "
  799. "port ID (%06x).\n", host_pid);
  800. break;
  801. }
  802. /* Ignore reserved bits from RSCN-payload. */
  803. rscn_entry = ((mb[1] & 0x3ff) << 16) | mb[2];
  804. /* Skip RSCNs for virtual ports on the same physical port */
  805. if (qla2x00_is_a_vp_did(vha, rscn_entry))
  806. break;
  807. atomic_set(&vha->loop_down_timer, 0);
  808. vha->flags.management_server_logged_in = 0;
  809. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  810. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  811. qla2x00_post_aen_work(vha, FCH_EVT_RSCN, rscn_entry);
  812. break;
  813. /* case MBA_RIO_RESPONSE: */
  814. case MBA_ZIO_RESPONSE:
  815. ql_dbg(ql_dbg_async, vha, 0x5015,
  816. "[R|Z]IO update completion.\n");
  817. if (IS_FWI2_CAPABLE(ha))
  818. qla24xx_process_response_queue(vha, rsp);
  819. else
  820. qla2x00_process_response_queue(rsp);
  821. break;
  822. case MBA_DISCARD_RND_FRAME:
  823. ql_dbg(ql_dbg_async, vha, 0x5016,
  824. "Discard RND Frame -- %04x %04x %04x.\n",
  825. mb[1], mb[2], mb[3]);
  826. break;
  827. case MBA_TRACE_NOTIFICATION:
  828. ql_dbg(ql_dbg_async, vha, 0x5017,
  829. "Trace Notification -- %04x %04x.\n", mb[1], mb[2]);
  830. break;
  831. case MBA_ISP84XX_ALERT:
  832. ql_dbg(ql_dbg_async, vha, 0x5018,
  833. "ISP84XX Alert Notification -- %04x %04x %04x.\n",
  834. mb[1], mb[2], mb[3]);
  835. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  836. switch (mb[1]) {
  837. case A84_PANIC_RECOVERY:
  838. ql_log(ql_log_info, vha, 0x5019,
  839. "Alert 84XX: panic recovery %04x %04x.\n",
  840. mb[2], mb[3]);
  841. break;
  842. case A84_OP_LOGIN_COMPLETE:
  843. ha->cs84xx->op_fw_version = mb[3] << 16 | mb[2];
  844. ql_log(ql_log_info, vha, 0x501a,
  845. "Alert 84XX: firmware version %x.\n",
  846. ha->cs84xx->op_fw_version);
  847. break;
  848. case A84_DIAG_LOGIN_COMPLETE:
  849. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  850. ql_log(ql_log_info, vha, 0x501b,
  851. "Alert 84XX: diagnostic firmware version %x.\n",
  852. ha->cs84xx->diag_fw_version);
  853. break;
  854. case A84_GOLD_LOGIN_COMPLETE:
  855. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  856. ha->cs84xx->fw_update = 1;
  857. ql_log(ql_log_info, vha, 0x501c,
  858. "Alert 84XX: gold firmware version %x.\n",
  859. ha->cs84xx->gold_fw_version);
  860. break;
  861. default:
  862. ql_log(ql_log_warn, vha, 0x501d,
  863. "Alert 84xx: Invalid Alert %04x %04x %04x.\n",
  864. mb[1], mb[2], mb[3]);
  865. }
  866. spin_unlock_irqrestore(&ha->cs84xx->access_lock, flags);
  867. break;
  868. case MBA_DCBX_START:
  869. ql_dbg(ql_dbg_async, vha, 0x501e,
  870. "DCBX Started -- %04x %04x %04x.\n",
  871. mb[1], mb[2], mb[3]);
  872. break;
  873. case MBA_DCBX_PARAM_UPDATE:
  874. ql_dbg(ql_dbg_async, vha, 0x501f,
  875. "DCBX Parameters Updated -- %04x %04x %04x.\n",
  876. mb[1], mb[2], mb[3]);
  877. break;
  878. case MBA_FCF_CONF_ERR:
  879. ql_dbg(ql_dbg_async, vha, 0x5020,
  880. "FCF Configuration Error -- %04x %04x %04x.\n",
  881. mb[1], mb[2], mb[3]);
  882. break;
  883. case MBA_IDC_NOTIFY:
  884. if (IS_QLA8031(vha->hw)) {
  885. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  886. if (((mb[2] & 0x7fff) == MBC_PORT_RESET ||
  887. (mb[2] & 0x7fff) == MBC_SET_PORT_CONFIG) &&
  888. (mb[4] & INTERNAL_LOOPBACK_MASK) != 0) {
  889. set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
  890. /*
  891. * Extend loop down timer since port is active.
  892. */
  893. if (atomic_read(&vha->loop_state) == LOOP_DOWN)
  894. atomic_set(&vha->loop_down_timer,
  895. LOOP_DOWN_TIME);
  896. qla2xxx_wake_dpc(vha);
  897. }
  898. }
  899. case MBA_IDC_COMPLETE:
  900. if (ha->notify_lb_portup_comp)
  901. complete(&ha->lb_portup_comp);
  902. /* Fallthru */
  903. case MBA_IDC_TIME_EXT:
  904. if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw))
  905. qla81xx_idc_event(vha, mb[0], mb[1]);
  906. break;
  907. case MBA_IDC_AEN:
  908. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  909. mb[5] = RD_REG_WORD(&reg24->mailbox5);
  910. mb[6] = RD_REG_WORD(&reg24->mailbox6);
  911. mb[7] = RD_REG_WORD(&reg24->mailbox7);
  912. qla83xx_handle_8200_aen(vha, mb);
  913. break;
  914. default:
  915. ql_dbg(ql_dbg_async, vha, 0x5057,
  916. "Unknown AEN:%04x %04x %04x %04x\n",
  917. mb[0], mb[1], mb[2], mb[3]);
  918. }
  919. qlt_async_event(mb[0], vha, mb);
  920. if (!vha->vp_idx && ha->num_vhosts)
  921. qla2x00_alert_all_vps(rsp, mb);
  922. }
  923. /**
  924. * qla2x00_process_completed_request() - Process a Fast Post response.
  925. * @ha: SCSI driver HA context
  926. * @index: SRB index
  927. */
  928. void
  929. qla2x00_process_completed_request(struct scsi_qla_host *vha,
  930. struct req_que *req, uint32_t index)
  931. {
  932. srb_t *sp;
  933. struct qla_hw_data *ha = vha->hw;
  934. /* Validate handle. */
  935. if (index >= req->num_outstanding_cmds) {
  936. ql_log(ql_log_warn, vha, 0x3014,
  937. "Invalid SCSI command index (%x).\n", index);
  938. if (IS_QLA82XX(ha))
  939. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  940. else
  941. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  942. return;
  943. }
  944. sp = req->outstanding_cmds[index];
  945. if (sp) {
  946. /* Free outstanding command slot. */
  947. req->outstanding_cmds[index] = NULL;
  948. /* Save ISP completion status */
  949. sp->done(ha, sp, DID_OK << 16);
  950. } else {
  951. ql_log(ql_log_warn, vha, 0x3016, "Invalid SCSI SRB.\n");
  952. if (IS_QLA82XX(ha))
  953. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  954. else
  955. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  956. }
  957. }
  958. srb_t *
  959. qla2x00_get_sp_from_handle(scsi_qla_host_t *vha, const char *func,
  960. struct req_que *req, void *iocb)
  961. {
  962. struct qla_hw_data *ha = vha->hw;
  963. sts_entry_t *pkt = iocb;
  964. srb_t *sp = NULL;
  965. uint16_t index;
  966. index = LSW(pkt->handle);
  967. if (index >= req->num_outstanding_cmds) {
  968. ql_log(ql_log_warn, vha, 0x5031,
  969. "Invalid command index (%x).\n", index);
  970. if (IS_QLA82XX(ha))
  971. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  972. else
  973. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  974. goto done;
  975. }
  976. sp = req->outstanding_cmds[index];
  977. if (!sp) {
  978. ql_log(ql_log_warn, vha, 0x5032,
  979. "Invalid completion handle (%x) -- timed-out.\n", index);
  980. return sp;
  981. }
  982. if (sp->handle != index) {
  983. ql_log(ql_log_warn, vha, 0x5033,
  984. "SRB handle (%x) mismatch %x.\n", sp->handle, index);
  985. return NULL;
  986. }
  987. req->outstanding_cmds[index] = NULL;
  988. done:
  989. return sp;
  990. }
  991. static void
  992. qla2x00_mbx_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  993. struct mbx_entry *mbx)
  994. {
  995. const char func[] = "MBX-IOCB";
  996. const char *type;
  997. fc_port_t *fcport;
  998. srb_t *sp;
  999. struct srb_iocb *lio;
  1000. uint16_t *data;
  1001. uint16_t status;
  1002. sp = qla2x00_get_sp_from_handle(vha, func, req, mbx);
  1003. if (!sp)
  1004. return;
  1005. lio = &sp->u.iocb_cmd;
  1006. type = sp->name;
  1007. fcport = sp->fcport;
  1008. data = lio->u.logio.data;
  1009. data[0] = MBS_COMMAND_ERROR;
  1010. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1011. QLA_LOGIO_LOGIN_RETRIED : 0;
  1012. if (mbx->entry_status) {
  1013. ql_dbg(ql_dbg_async, vha, 0x5043,
  1014. "Async-%s error entry - hdl=%x portid=%02x%02x%02x "
  1015. "entry-status=%x status=%x state-flag=%x "
  1016. "status-flags=%x.\n", type, sp->handle,
  1017. fcport->d_id.b.domain, fcport->d_id.b.area,
  1018. fcport->d_id.b.al_pa, mbx->entry_status,
  1019. le16_to_cpu(mbx->status), le16_to_cpu(mbx->state_flags),
  1020. le16_to_cpu(mbx->status_flags));
  1021. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5029,
  1022. (uint8_t *)mbx, sizeof(*mbx));
  1023. goto logio_done;
  1024. }
  1025. status = le16_to_cpu(mbx->status);
  1026. if (status == 0x30 && sp->type == SRB_LOGIN_CMD &&
  1027. le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE)
  1028. status = 0;
  1029. if (!status && le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE) {
  1030. ql_dbg(ql_dbg_async, vha, 0x5045,
  1031. "Async-%s complete - hdl=%x portid=%02x%02x%02x mbx1=%x.\n",
  1032. type, sp->handle, fcport->d_id.b.domain,
  1033. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1034. le16_to_cpu(mbx->mb1));
  1035. data[0] = MBS_COMMAND_COMPLETE;
  1036. if (sp->type == SRB_LOGIN_CMD) {
  1037. fcport->port_type = FCT_TARGET;
  1038. if (le16_to_cpu(mbx->mb1) & BIT_0)
  1039. fcport->port_type = FCT_INITIATOR;
  1040. else if (le16_to_cpu(mbx->mb1) & BIT_1)
  1041. fcport->flags |= FCF_FCP2_DEVICE;
  1042. }
  1043. goto logio_done;
  1044. }
  1045. data[0] = le16_to_cpu(mbx->mb0);
  1046. switch (data[0]) {
  1047. case MBS_PORT_ID_USED:
  1048. data[1] = le16_to_cpu(mbx->mb1);
  1049. break;
  1050. case MBS_LOOP_ID_USED:
  1051. break;
  1052. default:
  1053. data[0] = MBS_COMMAND_ERROR;
  1054. break;
  1055. }
  1056. ql_log(ql_log_warn, vha, 0x5046,
  1057. "Async-%s failed - hdl=%x portid=%02x%02x%02x status=%x "
  1058. "mb0=%x mb1=%x mb2=%x mb6=%x mb7=%x.\n", type, sp->handle,
  1059. fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1060. status, le16_to_cpu(mbx->mb0), le16_to_cpu(mbx->mb1),
  1061. le16_to_cpu(mbx->mb2), le16_to_cpu(mbx->mb6),
  1062. le16_to_cpu(mbx->mb7));
  1063. logio_done:
  1064. sp->done(vha, sp, 0);
  1065. }
  1066. static void
  1067. qla2x00_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1068. sts_entry_t *pkt, int iocb_type)
  1069. {
  1070. const char func[] = "CT_IOCB";
  1071. const char *type;
  1072. srb_t *sp;
  1073. struct fc_bsg_job *bsg_job;
  1074. uint16_t comp_status;
  1075. int res;
  1076. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1077. if (!sp)
  1078. return;
  1079. bsg_job = sp->u.bsg_job;
  1080. type = "ct pass-through";
  1081. comp_status = le16_to_cpu(pkt->comp_status);
  1082. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1083. * fc payload to the caller
  1084. */
  1085. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1086. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1087. if (comp_status != CS_COMPLETE) {
  1088. if (comp_status == CS_DATA_UNDERRUN) {
  1089. res = DID_OK << 16;
  1090. bsg_job->reply->reply_payload_rcv_len =
  1091. le16_to_cpu(((sts_entry_t *)pkt)->rsp_info_len);
  1092. ql_log(ql_log_warn, vha, 0x5048,
  1093. "CT pass-through-%s error "
  1094. "comp_status-status=0x%x total_byte = 0x%x.\n",
  1095. type, comp_status,
  1096. bsg_job->reply->reply_payload_rcv_len);
  1097. } else {
  1098. ql_log(ql_log_warn, vha, 0x5049,
  1099. "CT pass-through-%s error "
  1100. "comp_status-status=0x%x.\n", type, comp_status);
  1101. res = DID_ERROR << 16;
  1102. bsg_job->reply->reply_payload_rcv_len = 0;
  1103. }
  1104. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5035,
  1105. (uint8_t *)pkt, sizeof(*pkt));
  1106. } else {
  1107. res = DID_OK << 16;
  1108. bsg_job->reply->reply_payload_rcv_len =
  1109. bsg_job->reply_payload.payload_len;
  1110. bsg_job->reply_len = 0;
  1111. }
  1112. sp->done(vha, sp, res);
  1113. }
  1114. static void
  1115. qla24xx_els_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1116. struct sts_entry_24xx *pkt, int iocb_type)
  1117. {
  1118. const char func[] = "ELS_CT_IOCB";
  1119. const char *type;
  1120. srb_t *sp;
  1121. struct fc_bsg_job *bsg_job;
  1122. uint16_t comp_status;
  1123. uint32_t fw_status[3];
  1124. uint8_t* fw_sts_ptr;
  1125. int res;
  1126. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1127. if (!sp)
  1128. return;
  1129. bsg_job = sp->u.bsg_job;
  1130. type = NULL;
  1131. switch (sp->type) {
  1132. case SRB_ELS_CMD_RPT:
  1133. case SRB_ELS_CMD_HST:
  1134. type = "els";
  1135. break;
  1136. case SRB_CT_CMD:
  1137. type = "ct pass-through";
  1138. break;
  1139. default:
  1140. ql_dbg(ql_dbg_user, vha, 0x503e,
  1141. "Unrecognized SRB: (%p) type=%d.\n", sp, sp->type);
  1142. return;
  1143. }
  1144. comp_status = fw_status[0] = le16_to_cpu(pkt->comp_status);
  1145. fw_status[1] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_1);
  1146. fw_status[2] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_2);
  1147. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1148. * fc payload to the caller
  1149. */
  1150. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1151. bsg_job->reply_len = sizeof(struct fc_bsg_reply) + sizeof(fw_status);
  1152. if (comp_status != CS_COMPLETE) {
  1153. if (comp_status == CS_DATA_UNDERRUN) {
  1154. res = DID_OK << 16;
  1155. bsg_job->reply->reply_payload_rcv_len =
  1156. le16_to_cpu(((struct els_sts_entry_24xx *)pkt)->total_byte_count);
  1157. ql_dbg(ql_dbg_user, vha, 0x503f,
  1158. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1159. "error subcode 1=0x%x error subcode 2=0x%x total_byte = 0x%x.\n",
  1160. type, sp->handle, comp_status, fw_status[1], fw_status[2],
  1161. le16_to_cpu(((struct els_sts_entry_24xx *)
  1162. pkt)->total_byte_count));
  1163. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1164. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1165. }
  1166. else {
  1167. ql_dbg(ql_dbg_user, vha, 0x5040,
  1168. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1169. "error subcode 1=0x%x error subcode 2=0x%x.\n",
  1170. type, sp->handle, comp_status,
  1171. le16_to_cpu(((struct els_sts_entry_24xx *)
  1172. pkt)->error_subcode_1),
  1173. le16_to_cpu(((struct els_sts_entry_24xx *)
  1174. pkt)->error_subcode_2));
  1175. res = DID_ERROR << 16;
  1176. bsg_job->reply->reply_payload_rcv_len = 0;
  1177. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1178. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1179. }
  1180. ql_dump_buffer(ql_dbg_user + ql_dbg_buffer, vha, 0x5056,
  1181. (uint8_t *)pkt, sizeof(*pkt));
  1182. }
  1183. else {
  1184. res = DID_OK << 16;
  1185. bsg_job->reply->reply_payload_rcv_len = bsg_job->reply_payload.payload_len;
  1186. bsg_job->reply_len = 0;
  1187. }
  1188. sp->done(vha, sp, res);
  1189. }
  1190. static void
  1191. qla24xx_logio_entry(scsi_qla_host_t *vha, struct req_que *req,
  1192. struct logio_entry_24xx *logio)
  1193. {
  1194. const char func[] = "LOGIO-IOCB";
  1195. const char *type;
  1196. fc_port_t *fcport;
  1197. srb_t *sp;
  1198. struct srb_iocb *lio;
  1199. uint16_t *data;
  1200. uint32_t iop[2];
  1201. sp = qla2x00_get_sp_from_handle(vha, func, req, logio);
  1202. if (!sp)
  1203. return;
  1204. lio = &sp->u.iocb_cmd;
  1205. type = sp->name;
  1206. fcport = sp->fcport;
  1207. data = lio->u.logio.data;
  1208. data[0] = MBS_COMMAND_ERROR;
  1209. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1210. QLA_LOGIO_LOGIN_RETRIED : 0;
  1211. if (logio->entry_status) {
  1212. ql_log(ql_log_warn, fcport->vha, 0x5034,
  1213. "Async-%s error entry - hdl=%x"
  1214. "portid=%02x%02x%02x entry-status=%x.\n",
  1215. type, sp->handle, fcport->d_id.b.domain,
  1216. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1217. logio->entry_status);
  1218. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x504d,
  1219. (uint8_t *)logio, sizeof(*logio));
  1220. goto logio_done;
  1221. }
  1222. if (le16_to_cpu(logio->comp_status) == CS_COMPLETE) {
  1223. ql_dbg(ql_dbg_async, fcport->vha, 0x5036,
  1224. "Async-%s complete - hdl=%x portid=%02x%02x%02x "
  1225. "iop0=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1226. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1227. le32_to_cpu(logio->io_parameter[0]));
  1228. data[0] = MBS_COMMAND_COMPLETE;
  1229. if (sp->type != SRB_LOGIN_CMD)
  1230. goto logio_done;
  1231. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1232. if (iop[0] & BIT_4) {
  1233. fcport->port_type = FCT_TARGET;
  1234. if (iop[0] & BIT_8)
  1235. fcport->flags |= FCF_FCP2_DEVICE;
  1236. } else if (iop[0] & BIT_5)
  1237. fcport->port_type = FCT_INITIATOR;
  1238. if (iop[0] & BIT_7)
  1239. fcport->flags |= FCF_CONF_COMP_SUPPORTED;
  1240. if (logio->io_parameter[7] || logio->io_parameter[8])
  1241. fcport->supported_classes |= FC_COS_CLASS2;
  1242. if (logio->io_parameter[9] || logio->io_parameter[10])
  1243. fcport->supported_classes |= FC_COS_CLASS3;
  1244. goto logio_done;
  1245. }
  1246. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1247. iop[1] = le32_to_cpu(logio->io_parameter[1]);
  1248. switch (iop[0]) {
  1249. case LSC_SCODE_PORTID_USED:
  1250. data[0] = MBS_PORT_ID_USED;
  1251. data[1] = LSW(iop[1]);
  1252. break;
  1253. case LSC_SCODE_NPORT_USED:
  1254. data[0] = MBS_LOOP_ID_USED;
  1255. break;
  1256. default:
  1257. data[0] = MBS_COMMAND_ERROR;
  1258. break;
  1259. }
  1260. ql_dbg(ql_dbg_async, fcport->vha, 0x5037,
  1261. "Async-%s failed - hdl=%x portid=%02x%02x%02x comp=%x "
  1262. "iop0=%x iop1=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1263. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1264. le16_to_cpu(logio->comp_status),
  1265. le32_to_cpu(logio->io_parameter[0]),
  1266. le32_to_cpu(logio->io_parameter[1]));
  1267. logio_done:
  1268. sp->done(vha, sp, 0);
  1269. }
  1270. static void
  1271. qla24xx_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1272. struct tsk_mgmt_entry *tsk)
  1273. {
  1274. const char func[] = "TMF-IOCB";
  1275. const char *type;
  1276. fc_port_t *fcport;
  1277. srb_t *sp;
  1278. struct srb_iocb *iocb;
  1279. struct sts_entry_24xx *sts = (struct sts_entry_24xx *)tsk;
  1280. int error = 1;
  1281. sp = qla2x00_get_sp_from_handle(vha, func, req, tsk);
  1282. if (!sp)
  1283. return;
  1284. iocb = &sp->u.iocb_cmd;
  1285. type = sp->name;
  1286. fcport = sp->fcport;
  1287. if (sts->entry_status) {
  1288. ql_log(ql_log_warn, fcport->vha, 0x5038,
  1289. "Async-%s error - hdl=%x entry-status(%x).\n",
  1290. type, sp->handle, sts->entry_status);
  1291. } else if (sts->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1292. ql_log(ql_log_warn, fcport->vha, 0x5039,
  1293. "Async-%s error - hdl=%x completion status(%x).\n",
  1294. type, sp->handle, sts->comp_status);
  1295. } else if (!(le16_to_cpu(sts->scsi_status) &
  1296. SS_RESPONSE_INFO_LEN_VALID)) {
  1297. ql_log(ql_log_warn, fcport->vha, 0x503a,
  1298. "Async-%s error - hdl=%x no response info(%x).\n",
  1299. type, sp->handle, sts->scsi_status);
  1300. } else if (le32_to_cpu(sts->rsp_data_len) < 4) {
  1301. ql_log(ql_log_warn, fcport->vha, 0x503b,
  1302. "Async-%s error - hdl=%x not enough response(%d).\n",
  1303. type, sp->handle, sts->rsp_data_len);
  1304. } else if (sts->data[3]) {
  1305. ql_log(ql_log_warn, fcport->vha, 0x503c,
  1306. "Async-%s error - hdl=%x response(%x).\n",
  1307. type, sp->handle, sts->data[3]);
  1308. } else {
  1309. error = 0;
  1310. }
  1311. if (error) {
  1312. iocb->u.tmf.data = error;
  1313. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5055,
  1314. (uint8_t *)sts, sizeof(*sts));
  1315. }
  1316. sp->done(vha, sp, 0);
  1317. }
  1318. /**
  1319. * qla2x00_process_response_queue() - Process response queue entries.
  1320. * @ha: SCSI driver HA context
  1321. */
  1322. void
  1323. qla2x00_process_response_queue(struct rsp_que *rsp)
  1324. {
  1325. struct scsi_qla_host *vha;
  1326. struct qla_hw_data *ha = rsp->hw;
  1327. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1328. sts_entry_t *pkt;
  1329. uint16_t handle_cnt;
  1330. uint16_t cnt;
  1331. vha = pci_get_drvdata(ha->pdev);
  1332. if (!vha->flags.online)
  1333. return;
  1334. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  1335. pkt = (sts_entry_t *)rsp->ring_ptr;
  1336. rsp->ring_index++;
  1337. if (rsp->ring_index == rsp->length) {
  1338. rsp->ring_index = 0;
  1339. rsp->ring_ptr = rsp->ring;
  1340. } else {
  1341. rsp->ring_ptr++;
  1342. }
  1343. if (pkt->entry_status != 0) {
  1344. qla2x00_error_entry(vha, rsp, pkt);
  1345. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1346. wmb();
  1347. continue;
  1348. }
  1349. switch (pkt->entry_type) {
  1350. case STATUS_TYPE:
  1351. qla2x00_status_entry(vha, rsp, pkt);
  1352. break;
  1353. case STATUS_TYPE_21:
  1354. handle_cnt = ((sts21_entry_t *)pkt)->handle_count;
  1355. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1356. qla2x00_process_completed_request(vha, rsp->req,
  1357. ((sts21_entry_t *)pkt)->handle[cnt]);
  1358. }
  1359. break;
  1360. case STATUS_TYPE_22:
  1361. handle_cnt = ((sts22_entry_t *)pkt)->handle_count;
  1362. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1363. qla2x00_process_completed_request(vha, rsp->req,
  1364. ((sts22_entry_t *)pkt)->handle[cnt]);
  1365. }
  1366. break;
  1367. case STATUS_CONT_TYPE:
  1368. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  1369. break;
  1370. case MBX_IOCB_TYPE:
  1371. qla2x00_mbx_iocb_entry(vha, rsp->req,
  1372. (struct mbx_entry *)pkt);
  1373. break;
  1374. case CT_IOCB_TYPE:
  1375. qla2x00_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  1376. break;
  1377. default:
  1378. /* Type Not Supported. */
  1379. ql_log(ql_log_warn, vha, 0x504a,
  1380. "Received unknown response pkt type %x "
  1381. "entry status=%x.\n",
  1382. pkt->entry_type, pkt->entry_status);
  1383. break;
  1384. }
  1385. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1386. wmb();
  1387. }
  1388. /* Adjust ring index */
  1389. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), rsp->ring_index);
  1390. }
  1391. static inline void
  1392. qla2x00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1393. uint32_t sense_len, struct rsp_que *rsp, int res)
  1394. {
  1395. struct scsi_qla_host *vha = sp->fcport->vha;
  1396. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1397. uint32_t track_sense_len;
  1398. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1399. sense_len = SCSI_SENSE_BUFFERSIZE;
  1400. SET_CMD_SENSE_LEN(sp, sense_len);
  1401. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1402. track_sense_len = sense_len;
  1403. if (sense_len > par_sense_len)
  1404. sense_len = par_sense_len;
  1405. memcpy(cp->sense_buffer, sense_data, sense_len);
  1406. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1407. track_sense_len -= sense_len;
  1408. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1409. if (track_sense_len != 0) {
  1410. rsp->status_srb = sp;
  1411. cp->result = res;
  1412. }
  1413. if (sense_len) {
  1414. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x301c,
  1415. "Check condition Sense data, nexus%ld:%d:%d cmd=%p.\n",
  1416. sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
  1417. cp);
  1418. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302b,
  1419. cp->sense_buffer, sense_len);
  1420. }
  1421. }
  1422. struct scsi_dif_tuple {
  1423. __be16 guard; /* Checksum */
  1424. __be16 app_tag; /* APPL identifier */
  1425. __be32 ref_tag; /* Target LBA or indirect LBA */
  1426. };
  1427. /*
  1428. * Checks the guard or meta-data for the type of error
  1429. * detected by the HBA. In case of errors, we set the
  1430. * ASC/ASCQ fields in the sense buffer with ILLEGAL_REQUEST
  1431. * to indicate to the kernel that the HBA detected error.
  1432. */
  1433. static inline int
  1434. qla2x00_handle_dif_error(srb_t *sp, struct sts_entry_24xx *sts24)
  1435. {
  1436. struct scsi_qla_host *vha = sp->fcport->vha;
  1437. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  1438. uint8_t *ap = &sts24->data[12];
  1439. uint8_t *ep = &sts24->data[20];
  1440. uint32_t e_ref_tag, a_ref_tag;
  1441. uint16_t e_app_tag, a_app_tag;
  1442. uint16_t e_guard, a_guard;
  1443. /*
  1444. * swab32 of the "data" field in the beginning of qla2x00_status_entry()
  1445. * would make guard field appear at offset 2
  1446. */
  1447. a_guard = le16_to_cpu(*(uint16_t *)(ap + 2));
  1448. a_app_tag = le16_to_cpu(*(uint16_t *)(ap + 0));
  1449. a_ref_tag = le32_to_cpu(*(uint32_t *)(ap + 4));
  1450. e_guard = le16_to_cpu(*(uint16_t *)(ep + 2));
  1451. e_app_tag = le16_to_cpu(*(uint16_t *)(ep + 0));
  1452. e_ref_tag = le32_to_cpu(*(uint32_t *)(ep + 4));
  1453. ql_dbg(ql_dbg_io, vha, 0x3023,
  1454. "iocb(s) %p Returned STATUS.\n", sts24);
  1455. ql_dbg(ql_dbg_io, vha, 0x3024,
  1456. "DIF ERROR in cmd 0x%x lba 0x%llx act ref"
  1457. " tag=0x%x, exp ref_tag=0x%x, act app tag=0x%x, exp app"
  1458. " tag=0x%x, act guard=0x%x, exp guard=0x%x.\n",
  1459. cmd->cmnd[0], (u64)scsi_get_lba(cmd), a_ref_tag, e_ref_tag,
  1460. a_app_tag, e_app_tag, a_guard, e_guard);
  1461. /*
  1462. * Ignore sector if:
  1463. * For type 3: ref & app tag is all 'f's
  1464. * For type 0,1,2: app tag is all 'f's
  1465. */
  1466. if ((a_app_tag == 0xffff) &&
  1467. ((scsi_get_prot_type(cmd) != SCSI_PROT_DIF_TYPE3) ||
  1468. (a_ref_tag == 0xffffffff))) {
  1469. uint32_t blocks_done, resid;
  1470. sector_t lba_s = scsi_get_lba(cmd);
  1471. /* 2TB boundary case covered automatically with this */
  1472. blocks_done = e_ref_tag - (uint32_t)lba_s + 1;
  1473. resid = scsi_bufflen(cmd) - (blocks_done *
  1474. cmd->device->sector_size);
  1475. scsi_set_resid(cmd, resid);
  1476. cmd->result = DID_OK << 16;
  1477. /* Update protection tag */
  1478. if (scsi_prot_sg_count(cmd)) {
  1479. uint32_t i, j = 0, k = 0, num_ent;
  1480. struct scatterlist *sg;
  1481. struct sd_dif_tuple *spt;
  1482. /* Patch the corresponding protection tags */
  1483. scsi_for_each_prot_sg(cmd, sg,
  1484. scsi_prot_sg_count(cmd), i) {
  1485. num_ent = sg_dma_len(sg) / 8;
  1486. if (k + num_ent < blocks_done) {
  1487. k += num_ent;
  1488. continue;
  1489. }
  1490. j = blocks_done - k - 1;
  1491. k = blocks_done;
  1492. break;
  1493. }
  1494. if (k != blocks_done) {
  1495. ql_log(ql_log_warn, vha, 0x302f,
  1496. "unexpected tag values tag:lba=%x:%llx)\n",
  1497. e_ref_tag, (unsigned long long)lba_s);
  1498. return 1;
  1499. }
  1500. spt = page_address(sg_page(sg)) + sg->offset;
  1501. spt += j;
  1502. spt->app_tag = 0xffff;
  1503. if (scsi_get_prot_type(cmd) == SCSI_PROT_DIF_TYPE3)
  1504. spt->ref_tag = 0xffffffff;
  1505. }
  1506. return 0;
  1507. }
  1508. /* check guard */
  1509. if (e_guard != a_guard) {
  1510. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1511. 0x10, 0x1);
  1512. set_driver_byte(cmd, DRIVER_SENSE);
  1513. set_host_byte(cmd, DID_ABORT);
  1514. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1515. return 1;
  1516. }
  1517. /* check ref tag */
  1518. if (e_ref_tag != a_ref_tag) {
  1519. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1520. 0x10, 0x3);
  1521. set_driver_byte(cmd, DRIVER_SENSE);
  1522. set_host_byte(cmd, DID_ABORT);
  1523. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1524. return 1;
  1525. }
  1526. /* check appl tag */
  1527. if (e_app_tag != a_app_tag) {
  1528. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1529. 0x10, 0x2);
  1530. set_driver_byte(cmd, DRIVER_SENSE);
  1531. set_host_byte(cmd, DID_ABORT);
  1532. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1533. return 1;
  1534. }
  1535. return 1;
  1536. }
  1537. static void
  1538. qla25xx_process_bidir_status_iocb(scsi_qla_host_t *vha, void *pkt,
  1539. struct req_que *req, uint32_t index)
  1540. {
  1541. struct qla_hw_data *ha = vha->hw;
  1542. srb_t *sp;
  1543. uint16_t comp_status;
  1544. uint16_t scsi_status;
  1545. uint16_t thread_id;
  1546. uint32_t rval = EXT_STATUS_OK;
  1547. struct fc_bsg_job *bsg_job = NULL;
  1548. sts_entry_t *sts;
  1549. struct sts_entry_24xx *sts24;
  1550. sts = (sts_entry_t *) pkt;
  1551. sts24 = (struct sts_entry_24xx *) pkt;
  1552. /* Validate handle. */
  1553. if (index >= req->num_outstanding_cmds) {
  1554. ql_log(ql_log_warn, vha, 0x70af,
  1555. "Invalid SCSI completion handle 0x%x.\n", index);
  1556. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1557. return;
  1558. }
  1559. sp = req->outstanding_cmds[index];
  1560. if (sp) {
  1561. /* Free outstanding command slot. */
  1562. req->outstanding_cmds[index] = NULL;
  1563. bsg_job = sp->u.bsg_job;
  1564. } else {
  1565. ql_log(ql_log_warn, vha, 0x70b0,
  1566. "Req:%d: Invalid ISP SCSI completion handle(0x%x)\n",
  1567. req->id, index);
  1568. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1569. return;
  1570. }
  1571. if (IS_FWI2_CAPABLE(ha)) {
  1572. comp_status = le16_to_cpu(sts24->comp_status);
  1573. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1574. } else {
  1575. comp_status = le16_to_cpu(sts->comp_status);
  1576. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1577. }
  1578. thread_id = bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
  1579. switch (comp_status) {
  1580. case CS_COMPLETE:
  1581. if (scsi_status == 0) {
  1582. bsg_job->reply->reply_payload_rcv_len =
  1583. bsg_job->reply_payload.payload_len;
  1584. rval = EXT_STATUS_OK;
  1585. }
  1586. goto done;
  1587. case CS_DATA_OVERRUN:
  1588. ql_dbg(ql_dbg_user, vha, 0x70b1,
  1589. "Command completed with date overrun thread_id=%d\n",
  1590. thread_id);
  1591. rval = EXT_STATUS_DATA_OVERRUN;
  1592. break;
  1593. case CS_DATA_UNDERRUN:
  1594. ql_dbg(ql_dbg_user, vha, 0x70b2,
  1595. "Command completed with date underrun thread_id=%d\n",
  1596. thread_id);
  1597. rval = EXT_STATUS_DATA_UNDERRUN;
  1598. break;
  1599. case CS_BIDIR_RD_OVERRUN:
  1600. ql_dbg(ql_dbg_user, vha, 0x70b3,
  1601. "Command completed with read data overrun thread_id=%d\n",
  1602. thread_id);
  1603. rval = EXT_STATUS_DATA_OVERRUN;
  1604. break;
  1605. case CS_BIDIR_RD_WR_OVERRUN:
  1606. ql_dbg(ql_dbg_user, vha, 0x70b4,
  1607. "Command completed with read and write data overrun "
  1608. "thread_id=%d\n", thread_id);
  1609. rval = EXT_STATUS_DATA_OVERRUN;
  1610. break;
  1611. case CS_BIDIR_RD_OVERRUN_WR_UNDERRUN:
  1612. ql_dbg(ql_dbg_user, vha, 0x70b5,
  1613. "Command completed with read data over and write data "
  1614. "underrun thread_id=%d\n", thread_id);
  1615. rval = EXT_STATUS_DATA_OVERRUN;
  1616. break;
  1617. case CS_BIDIR_RD_UNDERRUN:
  1618. ql_dbg(ql_dbg_user, vha, 0x70b6,
  1619. "Command completed with read data data underrun "
  1620. "thread_id=%d\n", thread_id);
  1621. rval = EXT_STATUS_DATA_UNDERRUN;
  1622. break;
  1623. case CS_BIDIR_RD_UNDERRUN_WR_OVERRUN:
  1624. ql_dbg(ql_dbg_user, vha, 0x70b7,
  1625. "Command completed with read data under and write data "
  1626. "overrun thread_id=%d\n", thread_id);
  1627. rval = EXT_STATUS_DATA_UNDERRUN;
  1628. break;
  1629. case CS_BIDIR_RD_WR_UNDERRUN:
  1630. ql_dbg(ql_dbg_user, vha, 0x70b8,
  1631. "Command completed with read and write data underrun "
  1632. "thread_id=%d\n", thread_id);
  1633. rval = EXT_STATUS_DATA_UNDERRUN;
  1634. break;
  1635. case CS_BIDIR_DMA:
  1636. ql_dbg(ql_dbg_user, vha, 0x70b9,
  1637. "Command completed with data DMA error thread_id=%d\n",
  1638. thread_id);
  1639. rval = EXT_STATUS_DMA_ERR;
  1640. break;
  1641. case CS_TIMEOUT:
  1642. ql_dbg(ql_dbg_user, vha, 0x70ba,
  1643. "Command completed with timeout thread_id=%d\n",
  1644. thread_id);
  1645. rval = EXT_STATUS_TIMEOUT;
  1646. break;
  1647. default:
  1648. ql_dbg(ql_dbg_user, vha, 0x70bb,
  1649. "Command completed with completion status=0x%x "
  1650. "thread_id=%d\n", comp_status, thread_id);
  1651. rval = EXT_STATUS_ERR;
  1652. break;
  1653. }
  1654. bsg_job->reply->reply_payload_rcv_len = 0;
  1655. done:
  1656. /* Return the vendor specific reply to API */
  1657. bsg_job->reply->reply_data.vendor_reply.vendor_rsp[0] = rval;
  1658. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1659. /* Always return DID_OK, bsg will send the vendor specific response
  1660. * in this case only */
  1661. sp->done(vha, sp, (DID_OK << 6));
  1662. }
  1663. /**
  1664. * qla2x00_status_entry() - Process a Status IOCB entry.
  1665. * @ha: SCSI driver HA context
  1666. * @pkt: Entry pointer
  1667. */
  1668. static void
  1669. qla2x00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  1670. {
  1671. srb_t *sp;
  1672. fc_port_t *fcport;
  1673. struct scsi_cmnd *cp;
  1674. sts_entry_t *sts;
  1675. struct sts_entry_24xx *sts24;
  1676. uint16_t comp_status;
  1677. uint16_t scsi_status;
  1678. uint16_t ox_id;
  1679. uint8_t lscsi_status;
  1680. int32_t resid;
  1681. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  1682. fw_resid_len;
  1683. uint8_t *rsp_info, *sense_data;
  1684. struct qla_hw_data *ha = vha->hw;
  1685. uint32_t handle;
  1686. uint16_t que;
  1687. struct req_que *req;
  1688. int logit = 1;
  1689. int res = 0;
  1690. uint16_t state_flags = 0;
  1691. sts = (sts_entry_t *) pkt;
  1692. sts24 = (struct sts_entry_24xx *) pkt;
  1693. if (IS_FWI2_CAPABLE(ha)) {
  1694. comp_status = le16_to_cpu(sts24->comp_status);
  1695. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1696. state_flags = le16_to_cpu(sts24->state_flags);
  1697. } else {
  1698. comp_status = le16_to_cpu(sts->comp_status);
  1699. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1700. }
  1701. handle = (uint32_t) LSW(sts->handle);
  1702. que = MSW(sts->handle);
  1703. req = ha->req_q_map[que];
  1704. /* Validate handle. */
  1705. if (handle < req->num_outstanding_cmds)
  1706. sp = req->outstanding_cmds[handle];
  1707. else
  1708. sp = NULL;
  1709. if (sp == NULL) {
  1710. ql_dbg(ql_dbg_io, vha, 0x3017,
  1711. "Invalid status handle (0x%x).\n", sts->handle);
  1712. if (IS_QLA82XX(ha))
  1713. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1714. else
  1715. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1716. qla2xxx_wake_dpc(vha);
  1717. return;
  1718. }
  1719. if (unlikely((state_flags & BIT_1) && (sp->type == SRB_BIDI_CMD))) {
  1720. qla25xx_process_bidir_status_iocb(vha, pkt, req, handle);
  1721. return;
  1722. }
  1723. /* Fast path completion. */
  1724. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  1725. qla2x00_do_host_ramp_up(vha);
  1726. qla2x00_process_completed_request(vha, req, handle);
  1727. return;
  1728. }
  1729. req->outstanding_cmds[handle] = NULL;
  1730. cp = GET_CMD_SP(sp);
  1731. if (cp == NULL) {
  1732. ql_dbg(ql_dbg_io, vha, 0x3018,
  1733. "Command already returned (0x%x/%p).\n",
  1734. sts->handle, sp);
  1735. return;
  1736. }
  1737. lscsi_status = scsi_status & STATUS_MASK;
  1738. fcport = sp->fcport;
  1739. ox_id = 0;
  1740. sense_len = par_sense_len = rsp_info_len = resid_len =
  1741. fw_resid_len = 0;
  1742. if (IS_FWI2_CAPABLE(ha)) {
  1743. if (scsi_status & SS_SENSE_LEN_VALID)
  1744. sense_len = le32_to_cpu(sts24->sense_len);
  1745. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1746. rsp_info_len = le32_to_cpu(sts24->rsp_data_len);
  1747. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER))
  1748. resid_len = le32_to_cpu(sts24->rsp_residual_count);
  1749. if (comp_status == CS_DATA_UNDERRUN)
  1750. fw_resid_len = le32_to_cpu(sts24->residual_len);
  1751. rsp_info = sts24->data;
  1752. sense_data = sts24->data;
  1753. host_to_fcp_swap(sts24->data, sizeof(sts24->data));
  1754. ox_id = le16_to_cpu(sts24->ox_id);
  1755. par_sense_len = sizeof(sts24->data);
  1756. } else {
  1757. if (scsi_status & SS_SENSE_LEN_VALID)
  1758. sense_len = le16_to_cpu(sts->req_sense_length);
  1759. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1760. rsp_info_len = le16_to_cpu(sts->rsp_info_len);
  1761. resid_len = le32_to_cpu(sts->residual_length);
  1762. rsp_info = sts->rsp_info;
  1763. sense_data = sts->req_sense_data;
  1764. par_sense_len = sizeof(sts->req_sense_data);
  1765. }
  1766. /* Check for any FCP transport errors. */
  1767. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID) {
  1768. /* Sense data lies beyond any FCP RESPONSE data. */
  1769. if (IS_FWI2_CAPABLE(ha)) {
  1770. sense_data += rsp_info_len;
  1771. par_sense_len -= rsp_info_len;
  1772. }
  1773. if (rsp_info_len > 3 && rsp_info[3]) {
  1774. ql_dbg(ql_dbg_io, fcport->vha, 0x3019,
  1775. "FCP I/O protocol failure (0x%x/0x%x).\n",
  1776. rsp_info_len, rsp_info[3]);
  1777. res = DID_BUS_BUSY << 16;
  1778. goto out;
  1779. }
  1780. }
  1781. /* Check for overrun. */
  1782. if (IS_FWI2_CAPABLE(ha) && comp_status == CS_COMPLETE &&
  1783. scsi_status & SS_RESIDUAL_OVER)
  1784. comp_status = CS_DATA_OVERRUN;
  1785. /*
  1786. * Based on Host and scsi status generate status code for Linux
  1787. */
  1788. switch (comp_status) {
  1789. case CS_COMPLETE:
  1790. case CS_QUEUE_FULL:
  1791. if (scsi_status == 0) {
  1792. res = DID_OK << 16;
  1793. break;
  1794. }
  1795. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER)) {
  1796. resid = resid_len;
  1797. scsi_set_resid(cp, resid);
  1798. if (!lscsi_status &&
  1799. ((unsigned)(scsi_bufflen(cp) - resid) <
  1800. cp->underflow)) {
  1801. ql_dbg(ql_dbg_io, fcport->vha, 0x301a,
  1802. "Mid-layer underflow "
  1803. "detected (0x%x of 0x%x bytes).\n",
  1804. resid, scsi_bufflen(cp));
  1805. res = DID_ERROR << 16;
  1806. break;
  1807. }
  1808. }
  1809. res = DID_OK << 16 | lscsi_status;
  1810. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1811. ql_dbg(ql_dbg_io, fcport->vha, 0x301b,
  1812. "QUEUE FULL detected.\n");
  1813. break;
  1814. }
  1815. logit = 0;
  1816. if (lscsi_status != SS_CHECK_CONDITION)
  1817. break;
  1818. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1819. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1820. break;
  1821. qla2x00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  1822. rsp, res);
  1823. break;
  1824. case CS_DATA_UNDERRUN:
  1825. /* Use F/W calculated residual length. */
  1826. resid = IS_FWI2_CAPABLE(ha) ? fw_resid_len : resid_len;
  1827. scsi_set_resid(cp, resid);
  1828. if (scsi_status & SS_RESIDUAL_UNDER) {
  1829. if (IS_FWI2_CAPABLE(ha) && fw_resid_len != resid_len) {
  1830. ql_dbg(ql_dbg_io, fcport->vha, 0x301d,
  1831. "Dropped frame(s) detected "
  1832. "(0x%x of 0x%x bytes).\n",
  1833. resid, scsi_bufflen(cp));
  1834. res = DID_ERROR << 16 | lscsi_status;
  1835. goto check_scsi_status;
  1836. }
  1837. if (!lscsi_status &&
  1838. ((unsigned)(scsi_bufflen(cp) - resid) <
  1839. cp->underflow)) {
  1840. ql_dbg(ql_dbg_io, fcport->vha, 0x301e,
  1841. "Mid-layer underflow "
  1842. "detected (0x%x of 0x%x bytes).\n",
  1843. resid, scsi_bufflen(cp));
  1844. res = DID_ERROR << 16;
  1845. break;
  1846. }
  1847. } else if (lscsi_status != SAM_STAT_TASK_SET_FULL &&
  1848. lscsi_status != SAM_STAT_BUSY) {
  1849. /*
  1850. * scsi status of task set and busy are considered to be
  1851. * task not completed.
  1852. */
  1853. ql_dbg(ql_dbg_io, fcport->vha, 0x301f,
  1854. "Dropped frame(s) detected (0x%x "
  1855. "of 0x%x bytes).\n", resid,
  1856. scsi_bufflen(cp));
  1857. res = DID_ERROR << 16 | lscsi_status;
  1858. goto check_scsi_status;
  1859. } else {
  1860. ql_dbg(ql_dbg_io, fcport->vha, 0x3030,
  1861. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  1862. scsi_status, lscsi_status);
  1863. }
  1864. res = DID_OK << 16 | lscsi_status;
  1865. logit = 0;
  1866. check_scsi_status:
  1867. /*
  1868. * Check to see if SCSI Status is non zero. If so report SCSI
  1869. * Status.
  1870. */
  1871. if (lscsi_status != 0) {
  1872. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1873. ql_dbg(ql_dbg_io, fcport->vha, 0x3020,
  1874. "QUEUE FULL detected.\n");
  1875. logit = 1;
  1876. break;
  1877. }
  1878. if (lscsi_status != SS_CHECK_CONDITION)
  1879. break;
  1880. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1881. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1882. break;
  1883. qla2x00_handle_sense(sp, sense_data, par_sense_len,
  1884. sense_len, rsp, res);
  1885. }
  1886. break;
  1887. case CS_PORT_LOGGED_OUT:
  1888. case CS_PORT_CONFIG_CHG:
  1889. case CS_PORT_BUSY:
  1890. case CS_INCOMPLETE:
  1891. case CS_PORT_UNAVAILABLE:
  1892. case CS_TIMEOUT:
  1893. case CS_RESET:
  1894. /*
  1895. * We are going to have the fc class block the rport
  1896. * while we try to recover so instruct the mid layer
  1897. * to requeue until the class decides how to handle this.
  1898. */
  1899. res = DID_TRANSPORT_DISRUPTED << 16;
  1900. if (comp_status == CS_TIMEOUT) {
  1901. if (IS_FWI2_CAPABLE(ha))
  1902. break;
  1903. else if ((le16_to_cpu(sts->status_flags) &
  1904. SF_LOGOUT_SENT) == 0)
  1905. break;
  1906. }
  1907. ql_dbg(ql_dbg_io, fcport->vha, 0x3021,
  1908. "Port down status: port-state=0x%x.\n",
  1909. atomic_read(&fcport->state));
  1910. if (atomic_read(&fcport->state) == FCS_ONLINE)
  1911. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  1912. break;
  1913. case CS_ABORTED:
  1914. res = DID_RESET << 16;
  1915. break;
  1916. case CS_DIF_ERROR:
  1917. logit = qla2x00_handle_dif_error(sp, sts24);
  1918. res = cp->result;
  1919. break;
  1920. case CS_TRANSPORT:
  1921. res = DID_ERROR << 16;
  1922. if (!IS_PI_SPLIT_DET_CAPABLE(ha))
  1923. break;
  1924. if (state_flags & BIT_4)
  1925. scmd_printk(KERN_WARNING, cp,
  1926. "Unsupported device '%s' found.\n",
  1927. cp->device->vendor);
  1928. break;
  1929. default:
  1930. res = DID_ERROR << 16;
  1931. break;
  1932. }
  1933. out:
  1934. if (logit)
  1935. ql_dbg(ql_dbg_io, fcport->vha, 0x3022,
  1936. "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%d "
  1937. "portid=%02x%02x%02x oxid=0x%x cdb=%10phN len=0x%x "
  1938. "rsp_info=0x%x resid=0x%x fw_resid=0x%x.\n",
  1939. comp_status, scsi_status, res, vha->host_no,
  1940. cp->device->id, cp->device->lun, fcport->d_id.b.domain,
  1941. fcport->d_id.b.area, fcport->d_id.b.al_pa, ox_id,
  1942. cp->cmnd, scsi_bufflen(cp), rsp_info_len,
  1943. resid_len, fw_resid_len);
  1944. if (!res)
  1945. qla2x00_do_host_ramp_up(vha);
  1946. if (rsp->status_srb == NULL)
  1947. sp->done(ha, sp, res);
  1948. }
  1949. /**
  1950. * qla2x00_status_cont_entry() - Process a Status Continuations entry.
  1951. * @ha: SCSI driver HA context
  1952. * @pkt: Entry pointer
  1953. *
  1954. * Extended sense data.
  1955. */
  1956. static void
  1957. qla2x00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  1958. {
  1959. uint8_t sense_sz = 0;
  1960. struct qla_hw_data *ha = rsp->hw;
  1961. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  1962. srb_t *sp = rsp->status_srb;
  1963. struct scsi_cmnd *cp;
  1964. uint32_t sense_len;
  1965. uint8_t *sense_ptr;
  1966. if (!sp || !GET_CMD_SENSE_LEN(sp))
  1967. return;
  1968. sense_len = GET_CMD_SENSE_LEN(sp);
  1969. sense_ptr = GET_CMD_SENSE_PTR(sp);
  1970. cp = GET_CMD_SP(sp);
  1971. if (cp == NULL) {
  1972. ql_log(ql_log_warn, vha, 0x3025,
  1973. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  1974. rsp->status_srb = NULL;
  1975. return;
  1976. }
  1977. if (sense_len > sizeof(pkt->data))
  1978. sense_sz = sizeof(pkt->data);
  1979. else
  1980. sense_sz = sense_len;
  1981. /* Move sense data. */
  1982. if (IS_FWI2_CAPABLE(ha))
  1983. host_to_fcp_swap(pkt->data, sizeof(pkt->data));
  1984. memcpy(sense_ptr, pkt->data, sense_sz);
  1985. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302c,
  1986. sense_ptr, sense_sz);
  1987. sense_len -= sense_sz;
  1988. sense_ptr += sense_sz;
  1989. SET_CMD_SENSE_PTR(sp, sense_ptr);
  1990. SET_CMD_SENSE_LEN(sp, sense_len);
  1991. /* Place command on done queue. */
  1992. if (sense_len == 0) {
  1993. rsp->status_srb = NULL;
  1994. sp->done(ha, sp, cp->result);
  1995. }
  1996. }
  1997. /**
  1998. * qla2x00_error_entry() - Process an error entry.
  1999. * @ha: SCSI driver HA context
  2000. * @pkt: Entry pointer
  2001. */
  2002. static void
  2003. qla2x00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, sts_entry_t *pkt)
  2004. {
  2005. srb_t *sp;
  2006. struct qla_hw_data *ha = vha->hw;
  2007. const char func[] = "ERROR-IOCB";
  2008. uint16_t que = MSW(pkt->handle);
  2009. struct req_que *req = NULL;
  2010. int res = DID_ERROR << 16;
  2011. ql_dbg(ql_dbg_async, vha, 0x502a,
  2012. "type of error status in response: 0x%x\n", pkt->entry_status);
  2013. if (que >= ha->max_req_queues || !ha->req_q_map[que])
  2014. goto fatal;
  2015. req = ha->req_q_map[que];
  2016. if (pkt->entry_status & RF_BUSY)
  2017. res = DID_BUS_BUSY << 16;
  2018. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2019. if (sp) {
  2020. sp->done(ha, sp, res);
  2021. return;
  2022. }
  2023. fatal:
  2024. ql_log(ql_log_warn, vha, 0x5030,
  2025. "Error entry - invalid handle/queue.\n");
  2026. if (IS_QLA82XX(ha))
  2027. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  2028. else
  2029. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2030. qla2xxx_wake_dpc(vha);
  2031. }
  2032. /**
  2033. * qla24xx_mbx_completion() - Process mailbox command completions.
  2034. * @ha: SCSI driver HA context
  2035. * @mb0: Mailbox0 register
  2036. */
  2037. static void
  2038. qla24xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  2039. {
  2040. uint16_t cnt;
  2041. uint32_t mboxes;
  2042. uint16_t __iomem *wptr;
  2043. struct qla_hw_data *ha = vha->hw;
  2044. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2045. /* Read all mbox registers? */
  2046. mboxes = (1 << ha->mbx_count) - 1;
  2047. if (!ha->mcp)
  2048. ql_dbg(ql_dbg_async, vha, 0x504e, "MBX pointer ERROR.\n");
  2049. else
  2050. mboxes = ha->mcp->in_mb;
  2051. /* Load return mailbox registers. */
  2052. ha->flags.mbox_int = 1;
  2053. ha->mailbox_out[0] = mb0;
  2054. mboxes >>= 1;
  2055. wptr = (uint16_t __iomem *)&reg->mailbox1;
  2056. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2057. if (mboxes & BIT_0)
  2058. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  2059. mboxes >>= 1;
  2060. wptr++;
  2061. }
  2062. }
  2063. /**
  2064. * qla24xx_process_response_queue() - Process response queue entries.
  2065. * @ha: SCSI driver HA context
  2066. */
  2067. void qla24xx_process_response_queue(struct scsi_qla_host *vha,
  2068. struct rsp_que *rsp)
  2069. {
  2070. struct sts_entry_24xx *pkt;
  2071. struct qla_hw_data *ha = vha->hw;
  2072. if (!vha->flags.online)
  2073. return;
  2074. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  2075. pkt = (struct sts_entry_24xx *)rsp->ring_ptr;
  2076. rsp->ring_index++;
  2077. if (rsp->ring_index == rsp->length) {
  2078. rsp->ring_index = 0;
  2079. rsp->ring_ptr = rsp->ring;
  2080. } else {
  2081. rsp->ring_ptr++;
  2082. }
  2083. if (pkt->entry_status != 0) {
  2084. qla2x00_error_entry(vha, rsp, (sts_entry_t *) pkt);
  2085. (void)qlt_24xx_process_response_error(vha, pkt);
  2086. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2087. wmb();
  2088. continue;
  2089. }
  2090. switch (pkt->entry_type) {
  2091. case STATUS_TYPE:
  2092. qla2x00_status_entry(vha, rsp, pkt);
  2093. break;
  2094. case STATUS_CONT_TYPE:
  2095. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2096. break;
  2097. case VP_RPT_ID_IOCB_TYPE:
  2098. qla24xx_report_id_acquisition(vha,
  2099. (struct vp_rpt_id_entry_24xx *)pkt);
  2100. break;
  2101. case LOGINOUT_PORT_IOCB_TYPE:
  2102. qla24xx_logio_entry(vha, rsp->req,
  2103. (struct logio_entry_24xx *)pkt);
  2104. break;
  2105. case TSK_MGMT_IOCB_TYPE:
  2106. qla24xx_tm_iocb_entry(vha, rsp->req,
  2107. (struct tsk_mgmt_entry *)pkt);
  2108. break;
  2109. case CT_IOCB_TYPE:
  2110. qla24xx_els_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  2111. break;
  2112. case ELS_IOCB_TYPE:
  2113. qla24xx_els_ct_entry(vha, rsp->req, pkt, ELS_IOCB_TYPE);
  2114. break;
  2115. case ABTS_RECV_24XX:
  2116. /* ensure that the ATIO queue is empty */
  2117. qlt_24xx_process_atio_queue(vha);
  2118. case ABTS_RESP_24XX:
  2119. case CTIO_TYPE7:
  2120. case NOTIFY_ACK_TYPE:
  2121. qlt_response_pkt_all_vps(vha, (response_t *)pkt);
  2122. break;
  2123. case MARKER_TYPE:
  2124. /* Do nothing in this case, this check is to prevent it
  2125. * from falling into default case
  2126. */
  2127. break;
  2128. default:
  2129. /* Type Not Supported. */
  2130. ql_dbg(ql_dbg_async, vha, 0x5042,
  2131. "Received unknown response pkt type %x "
  2132. "entry status=%x.\n",
  2133. pkt->entry_type, pkt->entry_status);
  2134. break;
  2135. }
  2136. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2137. wmb();
  2138. }
  2139. /* Adjust ring index */
  2140. if (IS_QLA82XX(ha)) {
  2141. struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
  2142. WRT_REG_DWORD(&reg->rsp_q_out[0], rsp->ring_index);
  2143. } else
  2144. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  2145. }
  2146. static void
  2147. qla2xxx_check_risc_status(scsi_qla_host_t *vha)
  2148. {
  2149. int rval;
  2150. uint32_t cnt;
  2151. struct qla_hw_data *ha = vha->hw;
  2152. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2153. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
  2154. return;
  2155. rval = QLA_SUCCESS;
  2156. WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
  2157. RD_REG_DWORD(&reg->iobase_addr);
  2158. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2159. for (cnt = 10000; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2160. rval == QLA_SUCCESS; cnt--) {
  2161. if (cnt) {
  2162. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2163. udelay(10);
  2164. } else
  2165. rval = QLA_FUNCTION_TIMEOUT;
  2166. }
  2167. if (rval == QLA_SUCCESS)
  2168. goto next_test;
  2169. rval = QLA_SUCCESS;
  2170. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2171. for (cnt = 100; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2172. rval == QLA_SUCCESS; cnt--) {
  2173. if (cnt) {
  2174. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2175. udelay(10);
  2176. } else
  2177. rval = QLA_FUNCTION_TIMEOUT;
  2178. }
  2179. if (rval != QLA_SUCCESS)
  2180. goto done;
  2181. next_test:
  2182. if (RD_REG_DWORD(&reg->iobase_c8) & BIT_3)
  2183. ql_log(ql_log_info, vha, 0x504c,
  2184. "Additional code -- 0x55AA.\n");
  2185. done:
  2186. WRT_REG_DWORD(&reg->iobase_window, 0x0000);
  2187. RD_REG_DWORD(&reg->iobase_window);
  2188. }
  2189. /**
  2190. * qla24xx_intr_handler() - Process interrupts for the ISP23xx and ISP24xx.
  2191. * @irq:
  2192. * @dev_id: SCSI driver HA context
  2193. *
  2194. * Called by system whenever the host adapter generates an interrupt.
  2195. *
  2196. * Returns handled flag.
  2197. */
  2198. irqreturn_t
  2199. qla24xx_intr_handler(int irq, void *dev_id)
  2200. {
  2201. scsi_qla_host_t *vha;
  2202. struct qla_hw_data *ha;
  2203. struct device_reg_24xx __iomem *reg;
  2204. int status;
  2205. unsigned long iter;
  2206. uint32_t stat;
  2207. uint32_t hccr;
  2208. uint16_t mb[8];
  2209. struct rsp_que *rsp;
  2210. unsigned long flags;
  2211. rsp = (struct rsp_que *) dev_id;
  2212. if (!rsp) {
  2213. ql_log(ql_log_info, NULL, 0x5059,
  2214. "%s: NULL response queue pointer.\n", __func__);
  2215. return IRQ_NONE;
  2216. }
  2217. ha = rsp->hw;
  2218. reg = &ha->iobase->isp24;
  2219. status = 0;
  2220. if (unlikely(pci_channel_offline(ha->pdev)))
  2221. return IRQ_HANDLED;
  2222. spin_lock_irqsave(&ha->hardware_lock, flags);
  2223. vha = pci_get_drvdata(ha->pdev);
  2224. for (iter = 50; iter--; ) {
  2225. stat = RD_REG_DWORD(&reg->host_status);
  2226. if (stat & HSRX_RISC_PAUSED) {
  2227. if (unlikely(pci_channel_offline(ha->pdev)))
  2228. break;
  2229. hccr = RD_REG_DWORD(&reg->hccr);
  2230. ql_log(ql_log_warn, vha, 0x504b,
  2231. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2232. hccr);
  2233. qla2xxx_check_risc_status(vha);
  2234. ha->isp_ops->fw_dump(vha, 1);
  2235. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2236. break;
  2237. } else if ((stat & HSRX_RISC_INT) == 0)
  2238. break;
  2239. switch (stat & 0xff) {
  2240. case INTR_ROM_MB_SUCCESS:
  2241. case INTR_ROM_MB_FAILED:
  2242. case INTR_MB_SUCCESS:
  2243. case INTR_MB_FAILED:
  2244. qla24xx_mbx_completion(vha, MSW(stat));
  2245. status |= MBX_INTERRUPT;
  2246. break;
  2247. case INTR_ASYNC_EVENT:
  2248. mb[0] = MSW(stat);
  2249. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2250. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2251. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2252. qla2x00_async_event(vha, rsp, mb);
  2253. break;
  2254. case INTR_RSP_QUE_UPDATE:
  2255. case INTR_RSP_QUE_UPDATE_83XX:
  2256. qla24xx_process_response_queue(vha, rsp);
  2257. break;
  2258. case INTR_ATIO_QUE_UPDATE:
  2259. qlt_24xx_process_atio_queue(vha);
  2260. break;
  2261. case INTR_ATIO_RSP_QUE_UPDATE:
  2262. qlt_24xx_process_atio_queue(vha);
  2263. qla24xx_process_response_queue(vha, rsp);
  2264. break;
  2265. default:
  2266. ql_dbg(ql_dbg_async, vha, 0x504f,
  2267. "Unrecognized interrupt type (%d).\n", stat * 0xff);
  2268. break;
  2269. }
  2270. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2271. RD_REG_DWORD_RELAXED(&reg->hccr);
  2272. if (unlikely(IS_QLA83XX(ha) && (ha->pdev->revision == 1)))
  2273. ndelay(3500);
  2274. }
  2275. qla2x00_handle_mbx_completion(ha, status);
  2276. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2277. return IRQ_HANDLED;
  2278. }
  2279. static irqreturn_t
  2280. qla24xx_msix_rsp_q(int irq, void *dev_id)
  2281. {
  2282. struct qla_hw_data *ha;
  2283. struct rsp_que *rsp;
  2284. struct device_reg_24xx __iomem *reg;
  2285. struct scsi_qla_host *vha;
  2286. unsigned long flags;
  2287. rsp = (struct rsp_que *) dev_id;
  2288. if (!rsp) {
  2289. ql_log(ql_log_info, NULL, 0x505a,
  2290. "%s: NULL response queue pointer.\n", __func__);
  2291. return IRQ_NONE;
  2292. }
  2293. ha = rsp->hw;
  2294. reg = &ha->iobase->isp24;
  2295. spin_lock_irqsave(&ha->hardware_lock, flags);
  2296. vha = pci_get_drvdata(ha->pdev);
  2297. qla24xx_process_response_queue(vha, rsp);
  2298. if (!ha->flags.disable_msix_handshake) {
  2299. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2300. RD_REG_DWORD_RELAXED(&reg->hccr);
  2301. }
  2302. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2303. return IRQ_HANDLED;
  2304. }
  2305. static irqreturn_t
  2306. qla25xx_msix_rsp_q(int irq, void *dev_id)
  2307. {
  2308. struct qla_hw_data *ha;
  2309. struct rsp_que *rsp;
  2310. struct device_reg_24xx __iomem *reg;
  2311. unsigned long flags;
  2312. rsp = (struct rsp_que *) dev_id;
  2313. if (!rsp) {
  2314. ql_log(ql_log_info, NULL, 0x505b,
  2315. "%s: NULL response queue pointer.\n", __func__);
  2316. return IRQ_NONE;
  2317. }
  2318. ha = rsp->hw;
  2319. /* Clear the interrupt, if enabled, for this response queue */
  2320. if (!ha->flags.disable_msix_handshake) {
  2321. reg = &ha->iobase->isp24;
  2322. spin_lock_irqsave(&ha->hardware_lock, flags);
  2323. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2324. RD_REG_DWORD_RELAXED(&reg->hccr);
  2325. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2326. }
  2327. queue_work_on((int) (rsp->id - 1), ha->wq, &rsp->q_work);
  2328. return IRQ_HANDLED;
  2329. }
  2330. static irqreturn_t
  2331. qla24xx_msix_default(int irq, void *dev_id)
  2332. {
  2333. scsi_qla_host_t *vha;
  2334. struct qla_hw_data *ha;
  2335. struct rsp_que *rsp;
  2336. struct device_reg_24xx __iomem *reg;
  2337. int status;
  2338. uint32_t stat;
  2339. uint32_t hccr;
  2340. uint16_t mb[8];
  2341. unsigned long flags;
  2342. rsp = (struct rsp_que *) dev_id;
  2343. if (!rsp) {
  2344. ql_log(ql_log_info, NULL, 0x505c,
  2345. "%s: NULL response queue pointer.\n", __func__);
  2346. return IRQ_NONE;
  2347. }
  2348. ha = rsp->hw;
  2349. reg = &ha->iobase->isp24;
  2350. status = 0;
  2351. spin_lock_irqsave(&ha->hardware_lock, flags);
  2352. vha = pci_get_drvdata(ha->pdev);
  2353. do {
  2354. stat = RD_REG_DWORD(&reg->host_status);
  2355. if (stat & HSRX_RISC_PAUSED) {
  2356. if (unlikely(pci_channel_offline(ha->pdev)))
  2357. break;
  2358. hccr = RD_REG_DWORD(&reg->hccr);
  2359. ql_log(ql_log_info, vha, 0x5050,
  2360. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2361. hccr);
  2362. qla2xxx_check_risc_status(vha);
  2363. ha->isp_ops->fw_dump(vha, 1);
  2364. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2365. break;
  2366. } else if ((stat & HSRX_RISC_INT) == 0)
  2367. break;
  2368. switch (stat & 0xff) {
  2369. case INTR_ROM_MB_SUCCESS:
  2370. case INTR_ROM_MB_FAILED:
  2371. case INTR_MB_SUCCESS:
  2372. case INTR_MB_FAILED:
  2373. qla24xx_mbx_completion(vha, MSW(stat));
  2374. status |= MBX_INTERRUPT;
  2375. break;
  2376. case INTR_ASYNC_EVENT:
  2377. mb[0] = MSW(stat);
  2378. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2379. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2380. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2381. qla2x00_async_event(vha, rsp, mb);
  2382. break;
  2383. case INTR_RSP_QUE_UPDATE:
  2384. case INTR_RSP_QUE_UPDATE_83XX:
  2385. qla24xx_process_response_queue(vha, rsp);
  2386. break;
  2387. case INTR_ATIO_QUE_UPDATE:
  2388. qlt_24xx_process_atio_queue(vha);
  2389. break;
  2390. case INTR_ATIO_RSP_QUE_UPDATE:
  2391. qlt_24xx_process_atio_queue(vha);
  2392. qla24xx_process_response_queue(vha, rsp);
  2393. break;
  2394. default:
  2395. ql_dbg(ql_dbg_async, vha, 0x5051,
  2396. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  2397. break;
  2398. }
  2399. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2400. } while (0);
  2401. qla2x00_handle_mbx_completion(ha, status);
  2402. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2403. return IRQ_HANDLED;
  2404. }
  2405. /* Interrupt handling helpers. */
  2406. struct qla_init_msix_entry {
  2407. const char *name;
  2408. irq_handler_t handler;
  2409. };
  2410. static struct qla_init_msix_entry msix_entries[3] = {
  2411. { "qla2xxx (default)", qla24xx_msix_default },
  2412. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2413. { "qla2xxx (multiq)", qla25xx_msix_rsp_q },
  2414. };
  2415. static struct qla_init_msix_entry qla82xx_msix_entries[2] = {
  2416. { "qla2xxx (default)", qla82xx_msix_default },
  2417. { "qla2xxx (rsp_q)", qla82xx_msix_rsp_q },
  2418. };
  2419. static struct qla_init_msix_entry qla83xx_msix_entries[3] = {
  2420. { "qla2xxx (default)", qla24xx_msix_default },
  2421. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2422. { "qla2xxx (atio_q)", qla83xx_msix_atio_q },
  2423. };
  2424. static void
  2425. qla24xx_disable_msix(struct qla_hw_data *ha)
  2426. {
  2427. int i;
  2428. struct qla_msix_entry *qentry;
  2429. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2430. for (i = 0; i < ha->msix_count; i++) {
  2431. qentry = &ha->msix_entries[i];
  2432. if (qentry->have_irq)
  2433. free_irq(qentry->vector, qentry->rsp);
  2434. }
  2435. pci_disable_msix(ha->pdev);
  2436. kfree(ha->msix_entries);
  2437. ha->msix_entries = NULL;
  2438. ha->flags.msix_enabled = 0;
  2439. ql_dbg(ql_dbg_init, vha, 0x0042,
  2440. "Disabled the MSI.\n");
  2441. }
  2442. static int
  2443. qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp)
  2444. {
  2445. #define MIN_MSIX_COUNT 2
  2446. int i, ret;
  2447. struct msix_entry *entries;
  2448. struct qla_msix_entry *qentry;
  2449. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2450. entries = kzalloc(sizeof(struct msix_entry) * ha->msix_count,
  2451. GFP_KERNEL);
  2452. if (!entries) {
  2453. ql_log(ql_log_warn, vha, 0x00bc,
  2454. "Failed to allocate memory for msix_entry.\n");
  2455. return -ENOMEM;
  2456. }
  2457. for (i = 0; i < ha->msix_count; i++)
  2458. entries[i].entry = i;
  2459. ret = pci_enable_msix(ha->pdev, entries, ha->msix_count);
  2460. if (ret) {
  2461. if (ret < MIN_MSIX_COUNT)
  2462. goto msix_failed;
  2463. ql_log(ql_log_warn, vha, 0x00c6,
  2464. "MSI-X: Failed to enable support "
  2465. "-- %d/%d\n Retry with %d vectors.\n",
  2466. ha->msix_count, ret, ret);
  2467. ha->msix_count = ret;
  2468. ret = pci_enable_msix(ha->pdev, entries, ha->msix_count);
  2469. if (ret) {
  2470. msix_failed:
  2471. ql_log(ql_log_fatal, vha, 0x00c7,
  2472. "MSI-X: Failed to enable support, "
  2473. "giving up -- %d/%d.\n",
  2474. ha->msix_count, ret);
  2475. goto msix_out;
  2476. }
  2477. ha->max_rsp_queues = ha->msix_count - 1;
  2478. }
  2479. ha->msix_entries = kzalloc(sizeof(struct qla_msix_entry) *
  2480. ha->msix_count, GFP_KERNEL);
  2481. if (!ha->msix_entries) {
  2482. ql_log(ql_log_fatal, vha, 0x00c8,
  2483. "Failed to allocate memory for ha->msix_entries.\n");
  2484. ret = -ENOMEM;
  2485. goto msix_out;
  2486. }
  2487. ha->flags.msix_enabled = 1;
  2488. for (i = 0; i < ha->msix_count; i++) {
  2489. qentry = &ha->msix_entries[i];
  2490. qentry->vector = entries[i].vector;
  2491. qentry->entry = entries[i].entry;
  2492. qentry->have_irq = 0;
  2493. qentry->rsp = NULL;
  2494. }
  2495. /* Enable MSI-X vectors for the base queue */
  2496. for (i = 0; i < ha->msix_count; i++) {
  2497. qentry = &ha->msix_entries[i];
  2498. if (QLA_TGT_MODE_ENABLED() && IS_ATIO_MSIX_CAPABLE(ha)) {
  2499. ret = request_irq(qentry->vector,
  2500. qla83xx_msix_entries[i].handler,
  2501. 0, qla83xx_msix_entries[i].name, rsp);
  2502. } else if (IS_QLA82XX(ha)) {
  2503. ret = request_irq(qentry->vector,
  2504. qla82xx_msix_entries[i].handler,
  2505. 0, qla82xx_msix_entries[i].name, rsp);
  2506. } else {
  2507. ret = request_irq(qentry->vector,
  2508. msix_entries[i].handler,
  2509. 0, msix_entries[i].name, rsp);
  2510. }
  2511. if (ret) {
  2512. ql_log(ql_log_fatal, vha, 0x00cb,
  2513. "MSI-X: unable to register handler -- %x/%d.\n",
  2514. qentry->vector, ret);
  2515. qla24xx_disable_msix(ha);
  2516. ha->mqenable = 0;
  2517. goto msix_out;
  2518. }
  2519. qentry->have_irq = 1;
  2520. qentry->rsp = rsp;
  2521. rsp->msix = qentry;
  2522. }
  2523. /* Enable MSI-X vector for response queue update for queue 0 */
  2524. if (IS_QLA83XX(ha)) {
  2525. if (ha->msixbase && ha->mqiobase &&
  2526. (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2527. ha->mqenable = 1;
  2528. } else
  2529. if (ha->mqiobase
  2530. && (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2531. ha->mqenable = 1;
  2532. ql_dbg(ql_dbg_multiq, vha, 0xc005,
  2533. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2534. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2535. ql_dbg(ql_dbg_init, vha, 0x0055,
  2536. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2537. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2538. msix_out:
  2539. kfree(entries);
  2540. return ret;
  2541. }
  2542. int
  2543. qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp)
  2544. {
  2545. int ret;
  2546. device_reg_t __iomem *reg = ha->iobase;
  2547. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2548. /* If possible, enable MSI-X. */
  2549. if (!IS_QLA2432(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2550. !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) && !IS_QLAFX00(ha))
  2551. goto skip_msi;
  2552. if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
  2553. (ha->pdev->subsystem_device == 0x7040 ||
  2554. ha->pdev->subsystem_device == 0x7041 ||
  2555. ha->pdev->subsystem_device == 0x1705)) {
  2556. ql_log(ql_log_warn, vha, 0x0034,
  2557. "MSI-X: Unsupported ISP 2432 SSVID/SSDID (0x%X,0x%X).\n",
  2558. ha->pdev->subsystem_vendor,
  2559. ha->pdev->subsystem_device);
  2560. goto skip_msi;
  2561. }
  2562. if (IS_QLA2432(ha) && (ha->pdev->revision < QLA_MSIX_CHIP_REV_24XX)) {
  2563. ql_log(ql_log_warn, vha, 0x0035,
  2564. "MSI-X; Unsupported ISP2432 (0x%X, 0x%X).\n",
  2565. ha->pdev->revision, QLA_MSIX_CHIP_REV_24XX);
  2566. goto skip_msix;
  2567. }
  2568. ret = qla24xx_enable_msix(ha, rsp);
  2569. if (!ret) {
  2570. ql_dbg(ql_dbg_init, vha, 0x0036,
  2571. "MSI-X: Enabled (0x%X, 0x%X).\n",
  2572. ha->chip_revision, ha->fw_attributes);
  2573. goto clear_risc_ints;
  2574. }
  2575. ql_log(ql_log_info, vha, 0x0037,
  2576. "MSI-X Falling back-to MSI mode -%d.\n", ret);
  2577. skip_msix:
  2578. if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2579. !IS_QLA8001(ha) && !IS_QLA82XX(ha) && !IS_QLAFX00(ha))
  2580. goto skip_msi;
  2581. ret = pci_enable_msi(ha->pdev);
  2582. if (!ret) {
  2583. ql_dbg(ql_dbg_init, vha, 0x0038,
  2584. "MSI: Enabled.\n");
  2585. ha->flags.msi_enabled = 1;
  2586. } else
  2587. ql_log(ql_log_warn, vha, 0x0039,
  2588. "MSI-X; Falling back-to INTa mode -- %d.\n", ret);
  2589. /* Skip INTx on ISP82xx. */
  2590. if (!ha->flags.msi_enabled && IS_QLA82XX(ha))
  2591. return QLA_FUNCTION_FAILED;
  2592. skip_msi:
  2593. ret = request_irq(ha->pdev->irq, ha->isp_ops->intr_handler,
  2594. ha->flags.msi_enabled ? 0 : IRQF_SHARED,
  2595. QLA2XXX_DRIVER_NAME, rsp);
  2596. if (ret) {
  2597. ql_log(ql_log_warn, vha, 0x003a,
  2598. "Failed to reserve interrupt %d already in use.\n",
  2599. ha->pdev->irq);
  2600. goto fail;
  2601. } else if (!ha->flags.msi_enabled) {
  2602. ql_dbg(ql_dbg_init, vha, 0x0125,
  2603. "INTa mode: Enabled.\n");
  2604. ha->flags.mr_intr_valid = 1;
  2605. }
  2606. clear_risc_ints:
  2607. spin_lock_irq(&ha->hardware_lock);
  2608. if (!IS_FWI2_CAPABLE(ha))
  2609. WRT_REG_WORD(&reg->isp.semaphore, 0);
  2610. spin_unlock_irq(&ha->hardware_lock);
  2611. fail:
  2612. return ret;
  2613. }
  2614. void
  2615. qla2x00_free_irqs(scsi_qla_host_t *vha)
  2616. {
  2617. struct qla_hw_data *ha = vha->hw;
  2618. struct rsp_que *rsp;
  2619. /*
  2620. * We need to check that ha->rsp_q_map is valid in case we are called
  2621. * from a probe failure context.
  2622. */
  2623. if (!ha->rsp_q_map || !ha->rsp_q_map[0])
  2624. return;
  2625. rsp = ha->rsp_q_map[0];
  2626. if (ha->flags.msix_enabled)
  2627. qla24xx_disable_msix(ha);
  2628. else if (ha->flags.msi_enabled) {
  2629. free_irq(ha->pdev->irq, rsp);
  2630. pci_disable_msi(ha->pdev);
  2631. } else
  2632. free_irq(ha->pdev->irq, rsp);
  2633. }
  2634. int qla25xx_request_irq(struct rsp_que *rsp)
  2635. {
  2636. struct qla_hw_data *ha = rsp->hw;
  2637. struct qla_init_msix_entry *intr = &msix_entries[2];
  2638. struct qla_msix_entry *msix = rsp->msix;
  2639. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2640. int ret;
  2641. ret = request_irq(msix->vector, intr->handler, 0, intr->name, rsp);
  2642. if (ret) {
  2643. ql_log(ql_log_fatal, vha, 0x00e6,
  2644. "MSI-X: Unable to register handler -- %x/%d.\n",
  2645. msix->vector, ret);
  2646. return ret;
  2647. }
  2648. msix->have_irq = 1;
  2649. msix->rsp = rsp;
  2650. return ret;
  2651. }