hw.h 20 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef HW_H
  17. #define HW_H
  18. #include <linux/if_ether.h>
  19. #include <linux/delay.h>
  20. #include <linux/io.h>
  21. #include "mac.h"
  22. #include "ani.h"
  23. #include "eeprom.h"
  24. #include "calib.h"
  25. #include "reg.h"
  26. #include "phy.h"
  27. #include "../regd.h"
  28. #define ATHEROS_VENDOR_ID 0x168c
  29. #define AR5416_DEVID_PCI 0x0023
  30. #define AR5416_DEVID_PCIE 0x0024
  31. #define AR9160_DEVID_PCI 0x0027
  32. #define AR9280_DEVID_PCI 0x0029
  33. #define AR9280_DEVID_PCIE 0x002a
  34. #define AR9285_DEVID_PCIE 0x002b
  35. #define AR5416_AR9100_DEVID 0x000b
  36. #define AR_SUBVENDOR_ID_NOG 0x0e11
  37. #define AR_SUBVENDOR_ID_NEW_A 0x7065
  38. #define AR5416_MAGIC 0x19641014
  39. #define AR5416_DEVID_AR9287_PCI 0x002D
  40. #define AR5416_DEVID_AR9287_PCIE 0x002E
  41. /* Register read/write primitives */
  42. #define REG_WRITE(_ah, _reg, _val) ath9k_iowrite32((_ah), (_reg), (_val))
  43. #define REG_READ(_ah, _reg) ath9k_ioread32((_ah), (_reg))
  44. #define SM(_v, _f) (((_v) << _f##_S) & _f)
  45. #define MS(_v, _f) (((_v) & _f) >> _f##_S)
  46. #define REG_RMW(_a, _r, _set, _clr) \
  47. REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
  48. #define REG_RMW_FIELD(_a, _r, _f, _v) \
  49. REG_WRITE(_a, _r, \
  50. (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
  51. #define REG_SET_BIT(_a, _r, _f) \
  52. REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
  53. #define REG_CLR_BIT(_a, _r, _f) \
  54. REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
  55. #define DO_DELAY(x) do { \
  56. if ((++(x) % 64) == 0) \
  57. udelay(1); \
  58. } while (0)
  59. #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
  60. int r; \
  61. for (r = 0; r < ((iniarray)->ia_rows); r++) { \
  62. REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
  63. INI_RA((iniarray), r, (column))); \
  64. DO_DELAY(regWr); \
  65. } \
  66. } while (0)
  67. #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
  68. #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
  69. #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
  70. #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
  71. #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
  72. #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
  73. #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
  74. #define AR_GPIOD_MASK 0x00001FFF
  75. #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
  76. #define BASE_ACTIVATE_DELAY 100
  77. #define RTC_PLL_SETTLE_DELAY 1000
  78. #define COEF_SCALE_S 24
  79. #define HT40_CHANNEL_CENTER_SHIFT 10
  80. #define ATH9K_ANTENNA0_CHAINMASK 0x1
  81. #define ATH9K_ANTENNA1_CHAINMASK 0x2
  82. #define ATH9K_NUM_DMA_DEBUG_REGS 8
  83. #define ATH9K_NUM_QUEUES 10
  84. #define MAX_RATE_POWER 63
  85. #define AH_WAIT_TIMEOUT 100000 /* (us) */
  86. #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
  87. #define AH_TIME_QUANTUM 10
  88. #define AR_KEYTABLE_SIZE 128
  89. #define POWER_UP_TIME 200000
  90. #define SPUR_RSSI_THRESH 40
  91. #define CAB_TIMEOUT_VAL 10
  92. #define BEACON_TIMEOUT_VAL 10
  93. #define MIN_BEACON_TIMEOUT_VAL 1
  94. #define SLEEP_SLOP 3
  95. #define INIT_CONFIG_STATUS 0x00000000
  96. #define INIT_RSSI_THR 0x00000700
  97. #define INIT_BCON_CNTRL_REG 0x00000000
  98. #define TU_TO_USEC(_tu) ((_tu) << 10)
  99. enum wireless_mode {
  100. ATH9K_MODE_11A = 0,
  101. ATH9K_MODE_11G,
  102. ATH9K_MODE_11NA_HT20,
  103. ATH9K_MODE_11NG_HT20,
  104. ATH9K_MODE_11NA_HT40PLUS,
  105. ATH9K_MODE_11NA_HT40MINUS,
  106. ATH9K_MODE_11NG_HT40PLUS,
  107. ATH9K_MODE_11NG_HT40MINUS,
  108. ATH9K_MODE_MAX,
  109. };
  110. enum ath9k_ant_setting {
  111. ATH9K_ANT_VARIABLE = 0,
  112. ATH9K_ANT_FIXED_A,
  113. ATH9K_ANT_FIXED_B
  114. };
  115. enum ath9k_hw_caps {
  116. ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
  117. ATH9K_HW_CAP_MIC_CKIP = BIT(1),
  118. ATH9K_HW_CAP_MIC_TKIP = BIT(2),
  119. ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
  120. ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
  121. ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
  122. ATH9K_HW_CAP_VEOL = BIT(6),
  123. ATH9K_HW_CAP_BSSIDMASK = BIT(7),
  124. ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
  125. ATH9K_HW_CAP_HT = BIT(9),
  126. ATH9K_HW_CAP_GTT = BIT(10),
  127. ATH9K_HW_CAP_FASTCC = BIT(11),
  128. ATH9K_HW_CAP_RFSILENT = BIT(12),
  129. ATH9K_HW_CAP_CST = BIT(13),
  130. ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
  131. ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
  132. ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
  133. };
  134. enum ath9k_capability_type {
  135. ATH9K_CAP_CIPHER = 0,
  136. ATH9K_CAP_TKIP_MIC,
  137. ATH9K_CAP_TKIP_SPLIT,
  138. ATH9K_CAP_DIVERSITY,
  139. ATH9K_CAP_TXPOW,
  140. ATH9K_CAP_MCAST_KEYSRCH,
  141. ATH9K_CAP_DS
  142. };
  143. struct ath9k_hw_capabilities {
  144. u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
  145. DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
  146. u16 total_queues;
  147. u16 keycache_size;
  148. u16 low_5ghz_chan, high_5ghz_chan;
  149. u16 low_2ghz_chan, high_2ghz_chan;
  150. u16 rts_aggr_limit;
  151. u8 tx_chainmask;
  152. u8 rx_chainmask;
  153. u16 tx_triglevel_max;
  154. u16 reg_cap;
  155. u8 num_gpio_pins;
  156. u8 num_antcfg_2ghz;
  157. u8 num_antcfg_5ghz;
  158. };
  159. struct ath9k_ops_config {
  160. int dma_beacon_response_time;
  161. int sw_beacon_response_time;
  162. int additional_swba_backoff;
  163. int ack_6mb;
  164. int cwm_ignore_extcca;
  165. u8 pcie_powersave_enable;
  166. u8 pcie_clock_req;
  167. u32 pcie_waen;
  168. u8 analog_shiftreg;
  169. u8 ht_enable;
  170. u32 ofdm_trig_low;
  171. u32 ofdm_trig_high;
  172. u32 cck_trig_high;
  173. u32 cck_trig_low;
  174. u32 enable_ani;
  175. enum ath9k_ant_setting diversity_control;
  176. u16 antenna_switch_swap;
  177. int serialize_regmode;
  178. bool intr_mitigation;
  179. #define SPUR_DISABLE 0
  180. #define SPUR_ENABLE_IOCTL 1
  181. #define SPUR_ENABLE_EEPROM 2
  182. #define AR_EEPROM_MODAL_SPURS 5
  183. #define AR_SPUR_5413_1 1640
  184. #define AR_SPUR_5413_2 1200
  185. #define AR_NO_SPUR 0x8000
  186. #define AR_BASE_FREQ_2GHZ 2300
  187. #define AR_BASE_FREQ_5GHZ 4900
  188. #define AR_SPUR_FEEQ_BOUND_HT40 19
  189. #define AR_SPUR_FEEQ_BOUND_HT20 10
  190. int spurmode;
  191. u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
  192. };
  193. enum ath9k_int {
  194. ATH9K_INT_RX = 0x00000001,
  195. ATH9K_INT_RXDESC = 0x00000002,
  196. ATH9K_INT_RXNOFRM = 0x00000008,
  197. ATH9K_INT_RXEOL = 0x00000010,
  198. ATH9K_INT_RXORN = 0x00000020,
  199. ATH9K_INT_TX = 0x00000040,
  200. ATH9K_INT_TXDESC = 0x00000080,
  201. ATH9K_INT_TIM_TIMER = 0x00000100,
  202. ATH9K_INT_TXURN = 0x00000800,
  203. ATH9K_INT_MIB = 0x00001000,
  204. ATH9K_INT_RXPHY = 0x00004000,
  205. ATH9K_INT_RXKCM = 0x00008000,
  206. ATH9K_INT_SWBA = 0x00010000,
  207. ATH9K_INT_BMISS = 0x00040000,
  208. ATH9K_INT_BNR = 0x00100000,
  209. ATH9K_INT_TIM = 0x00200000,
  210. ATH9K_INT_DTIM = 0x00400000,
  211. ATH9K_INT_DTIMSYNC = 0x00800000,
  212. ATH9K_INT_GPIO = 0x01000000,
  213. ATH9K_INT_CABEND = 0x02000000,
  214. ATH9K_INT_TSFOOR = 0x04000000,
  215. ATH9K_INT_GENTIMER = 0x08000000,
  216. ATH9K_INT_CST = 0x10000000,
  217. ATH9K_INT_GTT = 0x20000000,
  218. ATH9K_INT_FATAL = 0x40000000,
  219. ATH9K_INT_GLOBAL = 0x80000000,
  220. ATH9K_INT_BMISC = ATH9K_INT_TIM |
  221. ATH9K_INT_DTIM |
  222. ATH9K_INT_DTIMSYNC |
  223. ATH9K_INT_TSFOOR |
  224. ATH9K_INT_CABEND,
  225. ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
  226. ATH9K_INT_RXDESC |
  227. ATH9K_INT_RXEOL |
  228. ATH9K_INT_RXORN |
  229. ATH9K_INT_TXURN |
  230. ATH9K_INT_TXDESC |
  231. ATH9K_INT_MIB |
  232. ATH9K_INT_RXPHY |
  233. ATH9K_INT_RXKCM |
  234. ATH9K_INT_SWBA |
  235. ATH9K_INT_BMISS |
  236. ATH9K_INT_GPIO,
  237. ATH9K_INT_NOCARD = 0xffffffff
  238. };
  239. #define CHANNEL_CW_INT 0x00002
  240. #define CHANNEL_CCK 0x00020
  241. #define CHANNEL_OFDM 0x00040
  242. #define CHANNEL_2GHZ 0x00080
  243. #define CHANNEL_5GHZ 0x00100
  244. #define CHANNEL_PASSIVE 0x00200
  245. #define CHANNEL_DYN 0x00400
  246. #define CHANNEL_HALF 0x04000
  247. #define CHANNEL_QUARTER 0x08000
  248. #define CHANNEL_HT20 0x10000
  249. #define CHANNEL_HT40PLUS 0x20000
  250. #define CHANNEL_HT40MINUS 0x40000
  251. #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
  252. #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
  253. #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
  254. #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
  255. #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
  256. #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
  257. #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
  258. #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
  259. #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
  260. #define CHANNEL_ALL \
  261. (CHANNEL_OFDM| \
  262. CHANNEL_CCK| \
  263. CHANNEL_2GHZ | \
  264. CHANNEL_5GHZ | \
  265. CHANNEL_HT20 | \
  266. CHANNEL_HT40PLUS | \
  267. CHANNEL_HT40MINUS)
  268. struct ath9k_channel {
  269. struct ieee80211_channel *chan;
  270. u16 channel;
  271. u32 channelFlags;
  272. u32 chanmode;
  273. int32_t CalValid;
  274. bool oneTimeCalsDone;
  275. int8_t iCoff;
  276. int8_t qCoff;
  277. int16_t rawNoiseFloor;
  278. };
  279. #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
  280. (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
  281. (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
  282. (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
  283. #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
  284. #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
  285. #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
  286. #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
  287. #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
  288. #define IS_CHAN_A_5MHZ_SPACED(_c) \
  289. ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
  290. (((_c)->channel % 20) != 0) && \
  291. (((_c)->channel % 10) != 0))
  292. /* These macros check chanmode and not channelFlags */
  293. #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
  294. #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
  295. ((_c)->chanmode == CHANNEL_G_HT20))
  296. #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
  297. ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
  298. ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
  299. ((_c)->chanmode == CHANNEL_G_HT40MINUS))
  300. #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
  301. enum ath9k_power_mode {
  302. ATH9K_PM_AWAKE = 0,
  303. ATH9K_PM_FULL_SLEEP,
  304. ATH9K_PM_NETWORK_SLEEP,
  305. ATH9K_PM_UNDEFINED
  306. };
  307. enum ath9k_tp_scale {
  308. ATH9K_TP_SCALE_MAX = 0,
  309. ATH9K_TP_SCALE_50,
  310. ATH9K_TP_SCALE_25,
  311. ATH9K_TP_SCALE_12,
  312. ATH9K_TP_SCALE_MIN
  313. };
  314. enum ser_reg_mode {
  315. SER_REG_MODE_OFF = 0,
  316. SER_REG_MODE_ON = 1,
  317. SER_REG_MODE_AUTO = 2,
  318. };
  319. struct ath9k_beacon_state {
  320. u32 bs_nexttbtt;
  321. u32 bs_nextdtim;
  322. u32 bs_intval;
  323. #define ATH9K_BEACON_PERIOD 0x0000ffff
  324. #define ATH9K_BEACON_ENA 0x00800000
  325. #define ATH9K_BEACON_RESET_TSF 0x01000000
  326. #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
  327. u32 bs_dtimperiod;
  328. u16 bs_cfpperiod;
  329. u16 bs_cfpmaxduration;
  330. u32 bs_cfpnext;
  331. u16 bs_timoffset;
  332. u16 bs_bmissthreshold;
  333. u32 bs_sleepduration;
  334. u32 bs_tsfoor_threshold;
  335. };
  336. struct chan_centers {
  337. u16 synth_center;
  338. u16 ctl_center;
  339. u16 ext_center;
  340. };
  341. enum {
  342. ATH9K_RESET_POWER_ON,
  343. ATH9K_RESET_WARM,
  344. ATH9K_RESET_COLD,
  345. };
  346. struct ath9k_hw_version {
  347. u32 magic;
  348. u16 devid;
  349. u16 subvendorid;
  350. u32 macVersion;
  351. u16 macRev;
  352. u16 phyRev;
  353. u16 analog5GhzRev;
  354. u16 analog2GhzRev;
  355. };
  356. /* Generic TSF timer definitions */
  357. #define ATH_MAX_GEN_TIMER 16
  358. #define AR_GENTMR_BIT(_index) (1 << (_index))
  359. /*
  360. * Using de Bruijin sequence to to look up 1's index in a 32 bit number
  361. * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
  362. */
  363. #define debruijn32 0x077CB531UL
  364. struct ath_gen_timer_configuration {
  365. u32 next_addr;
  366. u32 period_addr;
  367. u32 mode_addr;
  368. u32 mode_mask;
  369. };
  370. struct ath_gen_timer {
  371. void (*trigger)(void *arg);
  372. void (*overflow)(void *arg);
  373. void *arg;
  374. u8 index;
  375. };
  376. struct ath_gen_timer_table {
  377. u32 gen_timer_index[32];
  378. struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
  379. union {
  380. unsigned long timer_bits;
  381. u16 val;
  382. } timer_mask;
  383. };
  384. struct ath_hw {
  385. struct ath_softc *ah_sc;
  386. struct ath9k_hw_version hw_version;
  387. struct ath9k_ops_config config;
  388. struct ath9k_hw_capabilities caps;
  389. struct ath9k_channel channels[38];
  390. struct ath9k_channel *curchan;
  391. union {
  392. struct ar5416_eeprom_def def;
  393. struct ar5416_eeprom_4k map4k;
  394. struct ar9287_eeprom map9287;
  395. } eeprom;
  396. const struct eeprom_ops *eep_ops;
  397. enum ath9k_eep_map eep_map;
  398. bool sw_mgmt_crypto;
  399. bool is_pciexpress;
  400. u8 macaddr[ETH_ALEN];
  401. u16 tx_trig_level;
  402. u16 rfsilent;
  403. u32 rfkill_gpio;
  404. u32 rfkill_polarity;
  405. u32 ah_flags;
  406. bool htc_reset_init;
  407. enum nl80211_iftype opmode;
  408. enum ath9k_power_mode power_mode;
  409. struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
  410. struct ath9k_pacal_info pacal_info;
  411. struct ar5416Stats stats;
  412. struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
  413. int16_t curchan_rad_index;
  414. u32 mask_reg;
  415. u32 txok_interrupt_mask;
  416. u32 txerr_interrupt_mask;
  417. u32 txdesc_interrupt_mask;
  418. u32 txeol_interrupt_mask;
  419. u32 txurn_interrupt_mask;
  420. bool chip_fullsleep;
  421. u32 atim_window;
  422. /* Calibration */
  423. enum ath9k_cal_types supp_cals;
  424. struct ath9k_cal_list iq_caldata;
  425. struct ath9k_cal_list adcgain_caldata;
  426. struct ath9k_cal_list adcdc_calinitdata;
  427. struct ath9k_cal_list adcdc_caldata;
  428. struct ath9k_cal_list *cal_list;
  429. struct ath9k_cal_list *cal_list_last;
  430. struct ath9k_cal_list *cal_list_curr;
  431. #define totalPowerMeasI meas0.unsign
  432. #define totalPowerMeasQ meas1.unsign
  433. #define totalIqCorrMeas meas2.sign
  434. #define totalAdcIOddPhase meas0.unsign
  435. #define totalAdcIEvenPhase meas1.unsign
  436. #define totalAdcQOddPhase meas2.unsign
  437. #define totalAdcQEvenPhase meas3.unsign
  438. #define totalAdcDcOffsetIOddPhase meas0.sign
  439. #define totalAdcDcOffsetIEvenPhase meas1.sign
  440. #define totalAdcDcOffsetQOddPhase meas2.sign
  441. #define totalAdcDcOffsetQEvenPhase meas3.sign
  442. union {
  443. u32 unsign[AR5416_MAX_CHAINS];
  444. int32_t sign[AR5416_MAX_CHAINS];
  445. } meas0;
  446. union {
  447. u32 unsign[AR5416_MAX_CHAINS];
  448. int32_t sign[AR5416_MAX_CHAINS];
  449. } meas1;
  450. union {
  451. u32 unsign[AR5416_MAX_CHAINS];
  452. int32_t sign[AR5416_MAX_CHAINS];
  453. } meas2;
  454. union {
  455. u32 unsign[AR5416_MAX_CHAINS];
  456. int32_t sign[AR5416_MAX_CHAINS];
  457. } meas3;
  458. u16 cal_samples;
  459. u32 sta_id1_defaults;
  460. u32 misc_mode;
  461. enum {
  462. AUTO_32KHZ,
  463. USE_32KHZ,
  464. DONT_USE_32KHZ,
  465. } enable_32kHz_clock;
  466. /* RF */
  467. u32 *analogBank0Data;
  468. u32 *analogBank1Data;
  469. u32 *analogBank2Data;
  470. u32 *analogBank3Data;
  471. u32 *analogBank6Data;
  472. u32 *analogBank6TPCData;
  473. u32 *analogBank7Data;
  474. u32 *addac5416_21;
  475. u32 *bank6Temp;
  476. int16_t txpower_indexoffset;
  477. u32 beacon_interval;
  478. u32 slottime;
  479. u32 acktimeout;
  480. u32 ctstimeout;
  481. u32 globaltxtimeout;
  482. u8 gbeacon_rate;
  483. /* ANI */
  484. u32 proc_phyerr;
  485. u32 aniperiod;
  486. struct ar5416AniState *curani;
  487. struct ar5416AniState ani[255];
  488. int totalSizeDesired[5];
  489. int coarse_high[5];
  490. int coarse_low[5];
  491. int firpwr[5];
  492. enum ath9k_ani_cmd ani_function;
  493. u32 intr_txqs;
  494. enum ath9k_ht_extprotspacing extprotspacing;
  495. u8 txchainmask;
  496. u8 rxchainmask;
  497. u32 originalGain[22];
  498. int initPDADC;
  499. int PDADCdelta;
  500. u8 led_pin;
  501. struct ar5416IniArray iniModes;
  502. struct ar5416IniArray iniCommon;
  503. struct ar5416IniArray iniBank0;
  504. struct ar5416IniArray iniBB_RfGain;
  505. struct ar5416IniArray iniBank1;
  506. struct ar5416IniArray iniBank2;
  507. struct ar5416IniArray iniBank3;
  508. struct ar5416IniArray iniBank6;
  509. struct ar5416IniArray iniBank6TPC;
  510. struct ar5416IniArray iniBank7;
  511. struct ar5416IniArray iniAddac;
  512. struct ar5416IniArray iniPcieSerdes;
  513. struct ar5416IniArray iniModesAdditional;
  514. struct ar5416IniArray iniModesRxGain;
  515. struct ar5416IniArray iniModesTxGain;
  516. u32 intr_gen_timer_trigger;
  517. u32 intr_gen_timer_thresh;
  518. struct ath_gen_timer_table hw_gen_timers;
  519. };
  520. /* Initialization, Detach, Reset */
  521. const char *ath9k_hw_probe(u16 vendorid, u16 devid);
  522. void ath9k_hw_detach(struct ath_hw *ah);
  523. int ath9k_hw_init(struct ath_hw *ah);
  524. void ath9k_hw_rf_free(struct ath_hw *ah);
  525. int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
  526. bool bChannelChange);
  527. void ath9k_hw_fill_cap_info(struct ath_hw *ah);
  528. bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
  529. u32 capability, u32 *result);
  530. bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
  531. u32 capability, u32 setting, int *status);
  532. /* Key Cache Management */
  533. bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
  534. bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
  535. bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
  536. const struct ath9k_keyval *k,
  537. const u8 *mac);
  538. bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
  539. /* GPIO / RFKILL / Antennae */
  540. void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
  541. u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
  542. void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
  543. u32 ah_signal_type);
  544. void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
  545. u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
  546. void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
  547. bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
  548. enum ath9k_ant_setting settings,
  549. struct ath9k_channel *chan,
  550. u8 *tx_chainmask, u8 *rx_chainmask,
  551. u8 *antenna_cfgd);
  552. /* General Operation */
  553. bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
  554. u32 ath9k_hw_reverse_bits(u32 val, u32 n);
  555. bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
  556. u16 ath9k_hw_computetxtime(struct ath_hw *ah,
  557. const struct ath_rate_table *rates,
  558. u32 frameLen, u16 rateix, bool shortPreamble);
  559. void ath9k_hw_get_channel_centers(struct ath_hw *ah,
  560. struct ath9k_channel *chan,
  561. struct chan_centers *centers);
  562. u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
  563. void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
  564. bool ath9k_hw_phy_disable(struct ath_hw *ah);
  565. bool ath9k_hw_disable(struct ath_hw *ah);
  566. void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
  567. void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
  568. void ath9k_hw_setopmode(struct ath_hw *ah);
  569. void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
  570. void ath9k_hw_setbssidmask(struct ath_softc *sc);
  571. void ath9k_hw_write_associd(struct ath_softc *sc);
  572. u64 ath9k_hw_gettsf64(struct ath_hw *ah);
  573. void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
  574. void ath9k_hw_reset_tsf(struct ath_hw *ah);
  575. void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
  576. bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
  577. void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode);
  578. void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
  579. void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
  580. const struct ath9k_beacon_state *bs);
  581. bool ath9k_hw_setpower(struct ath_hw *ah,
  582. enum ath9k_power_mode mode);
  583. void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore);
  584. /* Interrupt Handling */
  585. bool ath9k_hw_intrpend(struct ath_hw *ah);
  586. bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
  587. enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
  588. /* Generic hw timer primitives */
  589. struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
  590. void (*trigger)(void *),
  591. void (*overflow)(void *),
  592. void *arg,
  593. u8 timer_index);
  594. void ath_gen_timer_start(struct ath_hw *ah, struct ath_gen_timer *timer,
  595. u32 timer_next, u32 timer_period);
  596. void ath_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
  597. void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
  598. void ath_gen_timer_isr(struct ath_hw *hw);
  599. u32 ath9k_hw_gettsf32(struct ath_hw *ah);
  600. #define ATH_PCIE_CAP_LINK_CTRL 0x70
  601. #define ATH_PCIE_CAP_LINK_L0S 1
  602. #define ATH_PCIE_CAP_LINK_L1 2
  603. void ath_pcie_aspm_disable(struct ath_softc *sc);
  604. #endif