sun4d_smp.c 10 KB

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  1. /* sun4d_smp.c: Sparc SS1000/SC2000 SMP support.
  2. *
  3. * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  4. *
  5. * Based on sun4m's smp.c, which is:
  6. * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
  7. */
  8. #include <asm/head.h>
  9. #include <linux/kernel.h>
  10. #include <linux/sched.h>
  11. #include <linux/threads.h>
  12. #include <linux/smp.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/kernel_stat.h>
  15. #include <linux/init.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/mm.h>
  18. #include <linux/swap.h>
  19. #include <linux/profile.h>
  20. #include <linux/delay.h>
  21. #include <asm/ptrace.h>
  22. #include <asm/atomic.h>
  23. #include <asm/irq_regs.h>
  24. #include <asm/irq.h>
  25. #include <asm/page.h>
  26. #include <asm/pgalloc.h>
  27. #include <asm/pgtable.h>
  28. #include <asm/oplib.h>
  29. #include <asm/sbi.h>
  30. #include <asm/tlbflush.h>
  31. #include <asm/cacheflush.h>
  32. #include <asm/cpudata.h>
  33. #include "irq.h"
  34. #define IRQ_CROSS_CALL 15
  35. extern ctxd_t *srmmu_ctx_table_phys;
  36. static volatile int smp_processors_ready = 0;
  37. static int smp_highest_cpu;
  38. extern volatile unsigned long cpu_callin_map[NR_CPUS];
  39. extern cpuinfo_sparc cpu_data[NR_CPUS];
  40. extern unsigned char boot_cpu_id;
  41. extern volatile int smp_process_available;
  42. extern cpumask_t smp_commenced_mask;
  43. extern int __smp4d_processor_id(void);
  44. /* #define SMP_DEBUG */
  45. #ifdef SMP_DEBUG
  46. #define SMP_PRINTK(x) printk x
  47. #else
  48. #define SMP_PRINTK(x)
  49. #endif
  50. static inline unsigned long swap(volatile unsigned long *ptr, unsigned long val)
  51. {
  52. __asm__ __volatile__("swap [%1], %0\n\t" :
  53. "=&r" (val), "=&r" (ptr) :
  54. "0" (val), "1" (ptr));
  55. return val;
  56. }
  57. static void smp_setup_percpu_timer(void);
  58. extern void cpu_probe(void);
  59. extern void sun4d_distribute_irqs(void);
  60. static unsigned char cpu_leds[32];
  61. static inline void show_leds(int cpuid)
  62. {
  63. cpuid &= 0x1e;
  64. __asm__ __volatile__ ("stba %0, [%1] %2" : :
  65. "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]),
  66. "r" (ECSR_BASE(cpuid) | BB_LEDS),
  67. "i" (ASI_M_CTL));
  68. }
  69. void __init smp4d_callin(void)
  70. {
  71. int cpuid = hard_smp4d_processor_id();
  72. extern spinlock_t sun4d_imsk_lock;
  73. unsigned long flags;
  74. /* Show we are alive */
  75. cpu_leds[cpuid] = 0x6;
  76. show_leds(cpuid);
  77. /* Enable level15 interrupt, disable level14 interrupt for now */
  78. cc_set_imsk((cc_get_imsk() & ~0x8000) | 0x4000);
  79. local_flush_cache_all();
  80. local_flush_tlb_all();
  81. /*
  82. * Unblock the master CPU _only_ when the scheduler state
  83. * of all secondary CPUs will be up-to-date, so after
  84. * the SMP initialization the master will be just allowed
  85. * to call the scheduler code.
  86. */
  87. /* Get our local ticker going. */
  88. smp_setup_percpu_timer();
  89. calibrate_delay();
  90. smp_store_cpu_info(cpuid);
  91. local_flush_cache_all();
  92. local_flush_tlb_all();
  93. /* Allow master to continue. */
  94. swap((unsigned long *)&cpu_callin_map[cpuid], 1);
  95. local_flush_cache_all();
  96. local_flush_tlb_all();
  97. cpu_probe();
  98. while((unsigned long)current_set[cpuid] < PAGE_OFFSET)
  99. barrier();
  100. while(current_set[cpuid]->cpu != cpuid)
  101. barrier();
  102. /* Fix idle thread fields. */
  103. __asm__ __volatile__("ld [%0], %%g6\n\t"
  104. : : "r" (&current_set[cpuid])
  105. : "memory" /* paranoid */);
  106. cpu_leds[cpuid] = 0x9;
  107. show_leds(cpuid);
  108. /* Attach to the address space of init_task. */
  109. atomic_inc(&init_mm.mm_count);
  110. current->active_mm = &init_mm;
  111. local_flush_cache_all();
  112. local_flush_tlb_all();
  113. local_irq_enable(); /* We don't allow PIL 14 yet */
  114. while (!cpu_isset(cpuid, smp_commenced_mask))
  115. barrier();
  116. spin_lock_irqsave(&sun4d_imsk_lock, flags);
  117. cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */
  118. spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
  119. cpu_set(cpuid, cpu_online_map);
  120. }
  121. extern void init_IRQ(void);
  122. extern void cpu_panic(void);
  123. /*
  124. * Cycle through the processors asking the PROM to start each one.
  125. */
  126. extern struct linux_prom_registers smp_penguin_ctable;
  127. extern unsigned long trapbase_cpu1[];
  128. extern unsigned long trapbase_cpu2[];
  129. extern unsigned long trapbase_cpu3[];
  130. void __init smp4d_boot_cpus(void)
  131. {
  132. if (boot_cpu_id)
  133. current_set[0] = NULL;
  134. smp_setup_percpu_timer();
  135. local_flush_cache_all();
  136. }
  137. int __cpuinit smp4d_boot_one_cpu(int i)
  138. {
  139. extern unsigned long sun4d_cpu_startup;
  140. unsigned long *entry = &sun4d_cpu_startup;
  141. struct task_struct *p;
  142. int timeout;
  143. int cpu_node;
  144. cpu_find_by_instance(i, &cpu_node,NULL);
  145. /* Cook up an idler for this guy. */
  146. p = fork_idle(i);
  147. current_set[i] = task_thread_info(p);
  148. /*
  149. * Initialize the contexts table
  150. * Since the call to prom_startcpu() trashes the structure,
  151. * we need to re-initialize it for each cpu
  152. */
  153. smp_penguin_ctable.which_io = 0;
  154. smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
  155. smp_penguin_ctable.reg_size = 0;
  156. /* whirrr, whirrr, whirrrrrrrrr... */
  157. SMP_PRINTK(("Starting CPU %d at %p \n", i, entry));
  158. local_flush_cache_all();
  159. prom_startcpu(cpu_node,
  160. &smp_penguin_ctable, 0, (char *)entry);
  161. SMP_PRINTK(("prom_startcpu returned :)\n"));
  162. /* wheee... it's going... */
  163. for(timeout = 0; timeout < 10000; timeout++) {
  164. if(cpu_callin_map[i])
  165. break;
  166. udelay(200);
  167. }
  168. if (!(cpu_callin_map[i])) {
  169. printk("Processor %d is stuck.\n", i);
  170. return -ENODEV;
  171. }
  172. local_flush_cache_all();
  173. return 0;
  174. }
  175. void __init smp4d_smp_done(void)
  176. {
  177. int i, first;
  178. int *prev;
  179. /* setup cpu list for irq rotation */
  180. first = 0;
  181. prev = &first;
  182. for (i = 0; i < NR_CPUS; i++)
  183. if (cpu_online(i)) {
  184. *prev = i;
  185. prev = &cpu_data(i).next;
  186. }
  187. *prev = first;
  188. local_flush_cache_all();
  189. /* Free unneeded trap tables */
  190. ClearPageReserved(virt_to_page(trapbase_cpu1));
  191. init_page_count(virt_to_page(trapbase_cpu1));
  192. free_page((unsigned long)trapbase_cpu1);
  193. totalram_pages++;
  194. num_physpages++;
  195. ClearPageReserved(virt_to_page(trapbase_cpu2));
  196. init_page_count(virt_to_page(trapbase_cpu2));
  197. free_page((unsigned long)trapbase_cpu2);
  198. totalram_pages++;
  199. num_physpages++;
  200. ClearPageReserved(virt_to_page(trapbase_cpu3));
  201. init_page_count(virt_to_page(trapbase_cpu3));
  202. free_page((unsigned long)trapbase_cpu3);
  203. totalram_pages++;
  204. num_physpages++;
  205. /* Ok, they are spinning and ready to go. */
  206. smp_processors_ready = 1;
  207. sun4d_distribute_irqs();
  208. }
  209. static struct smp_funcall {
  210. smpfunc_t func;
  211. unsigned long arg1;
  212. unsigned long arg2;
  213. unsigned long arg3;
  214. unsigned long arg4;
  215. unsigned long arg5;
  216. unsigned char processors_in[NR_CPUS]; /* Set when ipi entered. */
  217. unsigned char processors_out[NR_CPUS]; /* Set when ipi exited. */
  218. } ccall_info __attribute__((aligned(8)));
  219. static DEFINE_SPINLOCK(cross_call_lock);
  220. /* Cross calls must be serialized, at least currently. */
  221. static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
  222. unsigned long arg2, unsigned long arg3,
  223. unsigned long arg4)
  224. {
  225. if(smp_processors_ready) {
  226. register int high = smp_highest_cpu;
  227. unsigned long flags;
  228. spin_lock_irqsave(&cross_call_lock, flags);
  229. {
  230. /* If you make changes here, make sure gcc generates proper code... */
  231. register smpfunc_t f asm("i0") = func;
  232. register unsigned long a1 asm("i1") = arg1;
  233. register unsigned long a2 asm("i2") = arg2;
  234. register unsigned long a3 asm("i3") = arg3;
  235. register unsigned long a4 asm("i4") = arg4;
  236. register unsigned long a5 asm("i5") = 0;
  237. __asm__ __volatile__(
  238. "std %0, [%6]\n\t"
  239. "std %2, [%6 + 8]\n\t"
  240. "std %4, [%6 + 16]\n\t" : :
  241. "r"(f), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5),
  242. "r" (&ccall_info.func));
  243. }
  244. /* Init receive/complete mapping, plus fire the IPI's off. */
  245. {
  246. register int i;
  247. cpu_clear(smp_processor_id(), mask);
  248. cpus_and(mask, cpu_online_map, mask);
  249. for(i = 0; i <= high; i++) {
  250. if (cpu_isset(i, mask)) {
  251. ccall_info.processors_in[i] = 0;
  252. ccall_info.processors_out[i] = 0;
  253. sun4d_send_ipi(i, IRQ_CROSS_CALL);
  254. }
  255. }
  256. }
  257. {
  258. register int i;
  259. i = 0;
  260. do {
  261. if (!cpu_isset(i, mask))
  262. continue;
  263. while(!ccall_info.processors_in[i])
  264. barrier();
  265. } while(++i <= high);
  266. i = 0;
  267. do {
  268. if (!cpu_isset(i, mask))
  269. continue;
  270. while(!ccall_info.processors_out[i])
  271. barrier();
  272. } while(++i <= high);
  273. }
  274. spin_unlock_irqrestore(&cross_call_lock, flags);
  275. }
  276. }
  277. /* Running cross calls. */
  278. void smp4d_cross_call_irq(void)
  279. {
  280. int i = hard_smp4d_processor_id();
  281. ccall_info.processors_in[i] = 1;
  282. ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
  283. ccall_info.arg4, ccall_info.arg5);
  284. ccall_info.processors_out[i] = 1;
  285. }
  286. void smp4d_percpu_timer_interrupt(struct pt_regs *regs)
  287. {
  288. struct pt_regs *old_regs;
  289. int cpu = hard_smp4d_processor_id();
  290. static int cpu_tick[NR_CPUS];
  291. static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd };
  292. old_regs = set_irq_regs(regs);
  293. bw_get_prof_limit(cpu);
  294. bw_clear_intr_mask(0, 1); /* INTR_TABLE[0] & 1 is Profile IRQ */
  295. cpu_tick[cpu]++;
  296. if (!(cpu_tick[cpu] & 15)) {
  297. if (cpu_tick[cpu] == 0x60)
  298. cpu_tick[cpu] = 0;
  299. cpu_leds[cpu] = led_mask[cpu_tick[cpu] >> 4];
  300. show_leds(cpu);
  301. }
  302. profile_tick(CPU_PROFILING);
  303. if(!--prof_counter(cpu)) {
  304. int user = user_mode(regs);
  305. irq_enter();
  306. update_process_times(user);
  307. irq_exit();
  308. prof_counter(cpu) = prof_multiplier(cpu);
  309. }
  310. set_irq_regs(old_regs);
  311. }
  312. extern unsigned int lvl14_resolution;
  313. static void __init smp_setup_percpu_timer(void)
  314. {
  315. int cpu = hard_smp4d_processor_id();
  316. prof_counter(cpu) = prof_multiplier(cpu) = 1;
  317. load_profile_irq(cpu, lvl14_resolution);
  318. }
  319. void __init smp4d_blackbox_id(unsigned *addr)
  320. {
  321. int rd = *addr & 0x3e000000;
  322. addr[0] = 0xc0800800 | rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */
  323. addr[1] = 0x01000000; /* nop */
  324. addr[2] = 0x01000000; /* nop */
  325. }
  326. void __init smp4d_blackbox_current(unsigned *addr)
  327. {
  328. int rd = *addr & 0x3e000000;
  329. addr[0] = 0xc0800800 | rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */
  330. addr[2] = 0x81282002 | rd | (rd >> 11); /* sll reg, 2, reg */
  331. addr[4] = 0x01000000; /* nop */
  332. }
  333. void __init sun4d_init_smp(void)
  334. {
  335. int i;
  336. extern unsigned int t_nmi[], linux_trap_ipi15_sun4d[], linux_trap_ipi15_sun4m[];
  337. /* Patch ipi15 trap table */
  338. t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m);
  339. /* And set btfixup... */
  340. BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4d_blackbox_id);
  341. BTFIXUPSET_BLACKBOX(load_current, smp4d_blackbox_current);
  342. BTFIXUPSET_CALL(smp_cross_call, smp4d_cross_call, BTFIXUPCALL_NORM);
  343. BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4d_processor_id, BTFIXUPCALL_NORM);
  344. for (i = 0; i < NR_CPUS; i++) {
  345. ccall_info.processors_in[i] = 1;
  346. ccall_info.processors_out[i] = 1;
  347. }
  348. }