ymfpci_main.c 68 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  3. * Routines for control of YMF724/740/744/754 chips
  4. *
  5. * BUGS:
  6. * --
  7. *
  8. * TODO:
  9. * --
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. *
  25. */
  26. #include <sound/driver.h>
  27. #include <linux/delay.h>
  28. #include <linux/init.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/pci.h>
  31. #include <linux/sched.h>
  32. #include <linux/slab.h>
  33. #include <linux/vmalloc.h>
  34. #include <sound/core.h>
  35. #include <sound/control.h>
  36. #include <sound/info.h>
  37. #include <sound/tlv.h>
  38. #include <sound/ymfpci.h>
  39. #include <sound/asoundef.h>
  40. #include <sound/mpu401.h>
  41. #include <asm/io.h>
  42. /*
  43. * constants
  44. */
  45. /*
  46. * common I/O routines
  47. */
  48. static void snd_ymfpci_irq_wait(struct snd_ymfpci *chip);
  49. static inline u8 snd_ymfpci_readb(struct snd_ymfpci *chip, u32 offset)
  50. {
  51. return readb(chip->reg_area_virt + offset);
  52. }
  53. static inline void snd_ymfpci_writeb(struct snd_ymfpci *chip, u32 offset, u8 val)
  54. {
  55. writeb(val, chip->reg_area_virt + offset);
  56. }
  57. static inline u16 snd_ymfpci_readw(struct snd_ymfpci *chip, u32 offset)
  58. {
  59. return readw(chip->reg_area_virt + offset);
  60. }
  61. static inline void snd_ymfpci_writew(struct snd_ymfpci *chip, u32 offset, u16 val)
  62. {
  63. writew(val, chip->reg_area_virt + offset);
  64. }
  65. static inline u32 snd_ymfpci_readl(struct snd_ymfpci *chip, u32 offset)
  66. {
  67. return readl(chip->reg_area_virt + offset);
  68. }
  69. static inline void snd_ymfpci_writel(struct snd_ymfpci *chip, u32 offset, u32 val)
  70. {
  71. writel(val, chip->reg_area_virt + offset);
  72. }
  73. static int snd_ymfpci_codec_ready(struct snd_ymfpci *chip, int secondary)
  74. {
  75. unsigned long end_time;
  76. u32 reg = secondary ? YDSXGR_SECSTATUSADR : YDSXGR_PRISTATUSADR;
  77. end_time = jiffies + msecs_to_jiffies(750);
  78. do {
  79. if ((snd_ymfpci_readw(chip, reg) & 0x8000) == 0)
  80. return 0;
  81. set_current_state(TASK_UNINTERRUPTIBLE);
  82. schedule_timeout_uninterruptible(1);
  83. } while (time_before(jiffies, end_time));
  84. snd_printk(KERN_ERR "codec_ready: codec %i is not ready [0x%x]\n", secondary, snd_ymfpci_readw(chip, reg));
  85. return -EBUSY;
  86. }
  87. static void snd_ymfpci_codec_write(struct snd_ac97 *ac97, u16 reg, u16 val)
  88. {
  89. struct snd_ymfpci *chip = ac97->private_data;
  90. u32 cmd;
  91. snd_ymfpci_codec_ready(chip, 0);
  92. cmd = ((YDSXG_AC97WRITECMD | reg) << 16) | val;
  93. snd_ymfpci_writel(chip, YDSXGR_AC97CMDDATA, cmd);
  94. }
  95. static u16 snd_ymfpci_codec_read(struct snd_ac97 *ac97, u16 reg)
  96. {
  97. struct snd_ymfpci *chip = ac97->private_data;
  98. if (snd_ymfpci_codec_ready(chip, 0))
  99. return ~0;
  100. snd_ymfpci_writew(chip, YDSXGR_AC97CMDADR, YDSXG_AC97READCMD | reg);
  101. if (snd_ymfpci_codec_ready(chip, 0))
  102. return ~0;
  103. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_744 && chip->rev < 2) {
  104. int i;
  105. for (i = 0; i < 600; i++)
  106. snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  107. }
  108. return snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  109. }
  110. /*
  111. * Misc routines
  112. */
  113. static u32 snd_ymfpci_calc_delta(u32 rate)
  114. {
  115. switch (rate) {
  116. case 8000: return 0x02aaab00;
  117. case 11025: return 0x03accd00;
  118. case 16000: return 0x05555500;
  119. case 22050: return 0x07599a00;
  120. case 32000: return 0x0aaaab00;
  121. case 44100: return 0x0eb33300;
  122. default: return ((rate << 16) / 375) << 5;
  123. }
  124. }
  125. static u32 def_rate[8] = {
  126. 100, 2000, 8000, 11025, 16000, 22050, 32000, 48000
  127. };
  128. static u32 snd_ymfpci_calc_lpfK(u32 rate)
  129. {
  130. u32 i;
  131. static u32 val[8] = {
  132. 0x00570000, 0x06AA0000, 0x18B20000, 0x20930000,
  133. 0x2B9A0000, 0x35A10000, 0x3EAA0000, 0x40000000
  134. };
  135. if (rate == 44100)
  136. return 0x40000000; /* FIXME: What's the right value? */
  137. for (i = 0; i < 8; i++)
  138. if (rate <= def_rate[i])
  139. return val[i];
  140. return val[0];
  141. }
  142. static u32 snd_ymfpci_calc_lpfQ(u32 rate)
  143. {
  144. u32 i;
  145. static u32 val[8] = {
  146. 0x35280000, 0x34A70000, 0x32020000, 0x31770000,
  147. 0x31390000, 0x31C90000, 0x33D00000, 0x40000000
  148. };
  149. if (rate == 44100)
  150. return 0x370A0000;
  151. for (i = 0; i < 8; i++)
  152. if (rate <= def_rate[i])
  153. return val[i];
  154. return val[0];
  155. }
  156. /*
  157. * Hardware start management
  158. */
  159. static void snd_ymfpci_hw_start(struct snd_ymfpci *chip)
  160. {
  161. unsigned long flags;
  162. spin_lock_irqsave(&chip->reg_lock, flags);
  163. if (chip->start_count++ > 0)
  164. goto __end;
  165. snd_ymfpci_writel(chip, YDSXGR_MODE,
  166. snd_ymfpci_readl(chip, YDSXGR_MODE) | 3);
  167. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  168. __end:
  169. spin_unlock_irqrestore(&chip->reg_lock, flags);
  170. }
  171. static void snd_ymfpci_hw_stop(struct snd_ymfpci *chip)
  172. {
  173. unsigned long flags;
  174. long timeout = 1000;
  175. spin_lock_irqsave(&chip->reg_lock, flags);
  176. if (--chip->start_count > 0)
  177. goto __end;
  178. snd_ymfpci_writel(chip, YDSXGR_MODE,
  179. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~3);
  180. while (timeout-- > 0) {
  181. if ((snd_ymfpci_readl(chip, YDSXGR_STATUS) & 2) == 0)
  182. break;
  183. }
  184. if (atomic_read(&chip->interrupt_sleep_count)) {
  185. atomic_set(&chip->interrupt_sleep_count, 0);
  186. wake_up(&chip->interrupt_sleep);
  187. }
  188. __end:
  189. spin_unlock_irqrestore(&chip->reg_lock, flags);
  190. }
  191. /*
  192. * Playback voice management
  193. */
  194. static int voice_alloc(struct snd_ymfpci *chip,
  195. enum snd_ymfpci_voice_type type, int pair,
  196. struct snd_ymfpci_voice **rvoice)
  197. {
  198. struct snd_ymfpci_voice *voice, *voice2;
  199. int idx;
  200. *rvoice = NULL;
  201. for (idx = 0; idx < YDSXG_PLAYBACK_VOICES; idx += pair ? 2 : 1) {
  202. voice = &chip->voices[idx];
  203. voice2 = pair ? &chip->voices[idx+1] : NULL;
  204. if (voice->use || (voice2 && voice2->use))
  205. continue;
  206. voice->use = 1;
  207. if (voice2)
  208. voice2->use = 1;
  209. switch (type) {
  210. case YMFPCI_PCM:
  211. voice->pcm = 1;
  212. if (voice2)
  213. voice2->pcm = 1;
  214. break;
  215. case YMFPCI_SYNTH:
  216. voice->synth = 1;
  217. break;
  218. case YMFPCI_MIDI:
  219. voice->midi = 1;
  220. break;
  221. }
  222. snd_ymfpci_hw_start(chip);
  223. if (voice2)
  224. snd_ymfpci_hw_start(chip);
  225. *rvoice = voice;
  226. return 0;
  227. }
  228. return -ENOMEM;
  229. }
  230. static int snd_ymfpci_voice_alloc(struct snd_ymfpci *chip,
  231. enum snd_ymfpci_voice_type type, int pair,
  232. struct snd_ymfpci_voice **rvoice)
  233. {
  234. unsigned long flags;
  235. int result;
  236. snd_assert(rvoice != NULL, return -EINVAL);
  237. snd_assert(!pair || type == YMFPCI_PCM, return -EINVAL);
  238. spin_lock_irqsave(&chip->voice_lock, flags);
  239. for (;;) {
  240. result = voice_alloc(chip, type, pair, rvoice);
  241. if (result == 0 || type != YMFPCI_PCM)
  242. break;
  243. /* TODO: synth/midi voice deallocation */
  244. break;
  245. }
  246. spin_unlock_irqrestore(&chip->voice_lock, flags);
  247. return result;
  248. }
  249. static int snd_ymfpci_voice_free(struct snd_ymfpci *chip, struct snd_ymfpci_voice *pvoice)
  250. {
  251. unsigned long flags;
  252. snd_assert(pvoice != NULL, return -EINVAL);
  253. snd_ymfpci_hw_stop(chip);
  254. spin_lock_irqsave(&chip->voice_lock, flags);
  255. pvoice->use = pvoice->pcm = pvoice->synth = pvoice->midi = 0;
  256. pvoice->ypcm = NULL;
  257. pvoice->interrupt = NULL;
  258. spin_unlock_irqrestore(&chip->voice_lock, flags);
  259. return 0;
  260. }
  261. /*
  262. * PCM part
  263. */
  264. static void snd_ymfpci_pcm_interrupt(struct snd_ymfpci *chip, struct snd_ymfpci_voice *voice)
  265. {
  266. struct snd_ymfpci_pcm *ypcm;
  267. u32 pos, delta;
  268. if ((ypcm = voice->ypcm) == NULL)
  269. return;
  270. if (ypcm->substream == NULL)
  271. return;
  272. spin_lock(&chip->reg_lock);
  273. if (ypcm->running) {
  274. pos = le32_to_cpu(voice->bank[chip->active_bank].start);
  275. if (pos < ypcm->last_pos)
  276. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  277. else
  278. delta = pos - ypcm->last_pos;
  279. ypcm->period_pos += delta;
  280. ypcm->last_pos = pos;
  281. if (ypcm->period_pos >= ypcm->period_size) {
  282. // printk("done - active_bank = 0x%x, start = 0x%x\n", chip->active_bank, voice->bank[chip->active_bank].start);
  283. ypcm->period_pos %= ypcm->period_size;
  284. spin_unlock(&chip->reg_lock);
  285. snd_pcm_period_elapsed(ypcm->substream);
  286. spin_lock(&chip->reg_lock);
  287. }
  288. if (unlikely(ypcm->update_pcm_vol)) {
  289. unsigned int subs = ypcm->substream->number;
  290. unsigned int next_bank = 1 - chip->active_bank;
  291. struct snd_ymfpci_playback_bank *bank;
  292. u32 volume;
  293. bank = &voice->bank[next_bank];
  294. volume = cpu_to_le32(chip->pcm_mixer[subs].left << 15);
  295. bank->left_gain_end = volume;
  296. if (ypcm->output_rear)
  297. bank->eff2_gain_end = volume;
  298. if (ypcm->voices[1])
  299. bank = &ypcm->voices[1]->bank[next_bank];
  300. volume = cpu_to_le32(chip->pcm_mixer[subs].right << 15);
  301. bank->right_gain_end = volume;
  302. if (ypcm->output_rear)
  303. bank->eff3_gain_end = volume;
  304. ypcm->update_pcm_vol--;
  305. }
  306. }
  307. spin_unlock(&chip->reg_lock);
  308. }
  309. static void snd_ymfpci_pcm_capture_interrupt(struct snd_pcm_substream *substream)
  310. {
  311. struct snd_pcm_runtime *runtime = substream->runtime;
  312. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  313. struct snd_ymfpci *chip = ypcm->chip;
  314. u32 pos, delta;
  315. spin_lock(&chip->reg_lock);
  316. if (ypcm->running) {
  317. pos = le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  318. if (pos < ypcm->last_pos)
  319. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  320. else
  321. delta = pos - ypcm->last_pos;
  322. ypcm->period_pos += delta;
  323. ypcm->last_pos = pos;
  324. if (ypcm->period_pos >= ypcm->period_size) {
  325. ypcm->period_pos %= ypcm->period_size;
  326. // printk("done - active_bank = 0x%x, start = 0x%x\n", chip->active_bank, voice->bank[chip->active_bank].start);
  327. spin_unlock(&chip->reg_lock);
  328. snd_pcm_period_elapsed(substream);
  329. spin_lock(&chip->reg_lock);
  330. }
  331. }
  332. spin_unlock(&chip->reg_lock);
  333. }
  334. static int snd_ymfpci_playback_trigger(struct snd_pcm_substream *substream,
  335. int cmd)
  336. {
  337. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  338. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  339. int result = 0;
  340. spin_lock(&chip->reg_lock);
  341. if (ypcm->voices[0] == NULL) {
  342. result = -EINVAL;
  343. goto __unlock;
  344. }
  345. switch (cmd) {
  346. case SNDRV_PCM_TRIGGER_START:
  347. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  348. case SNDRV_PCM_TRIGGER_RESUME:
  349. chip->ctrl_playback[ypcm->voices[0]->number + 1] = cpu_to_le32(ypcm->voices[0]->bank_addr);
  350. if (ypcm->voices[1] != NULL)
  351. chip->ctrl_playback[ypcm->voices[1]->number + 1] = cpu_to_le32(ypcm->voices[1]->bank_addr);
  352. ypcm->running = 1;
  353. break;
  354. case SNDRV_PCM_TRIGGER_STOP:
  355. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  356. case SNDRV_PCM_TRIGGER_SUSPEND:
  357. chip->ctrl_playback[ypcm->voices[0]->number + 1] = 0;
  358. if (ypcm->voices[1] != NULL)
  359. chip->ctrl_playback[ypcm->voices[1]->number + 1] = 0;
  360. ypcm->running = 0;
  361. break;
  362. default:
  363. result = -EINVAL;
  364. break;
  365. }
  366. __unlock:
  367. spin_unlock(&chip->reg_lock);
  368. return result;
  369. }
  370. static int snd_ymfpci_capture_trigger(struct snd_pcm_substream *substream,
  371. int cmd)
  372. {
  373. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  374. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  375. int result = 0;
  376. u32 tmp;
  377. spin_lock(&chip->reg_lock);
  378. switch (cmd) {
  379. case SNDRV_PCM_TRIGGER_START:
  380. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  381. case SNDRV_PCM_TRIGGER_RESUME:
  382. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) | (1 << ypcm->capture_bank_number);
  383. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  384. ypcm->running = 1;
  385. break;
  386. case SNDRV_PCM_TRIGGER_STOP:
  387. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  388. case SNDRV_PCM_TRIGGER_SUSPEND:
  389. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) & ~(1 << ypcm->capture_bank_number);
  390. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  391. ypcm->running = 0;
  392. break;
  393. default:
  394. result = -EINVAL;
  395. break;
  396. }
  397. spin_unlock(&chip->reg_lock);
  398. return result;
  399. }
  400. static int snd_ymfpci_pcm_voice_alloc(struct snd_ymfpci_pcm *ypcm, int voices)
  401. {
  402. int err;
  403. if (ypcm->voices[1] != NULL && voices < 2) {
  404. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[1]);
  405. ypcm->voices[1] = NULL;
  406. }
  407. if (voices == 1 && ypcm->voices[0] != NULL)
  408. return 0; /* already allocated */
  409. if (voices == 2 && ypcm->voices[0] != NULL && ypcm->voices[1] != NULL)
  410. return 0; /* already allocated */
  411. if (voices > 1) {
  412. if (ypcm->voices[0] != NULL && ypcm->voices[1] == NULL) {
  413. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[0]);
  414. ypcm->voices[0] = NULL;
  415. }
  416. }
  417. err = snd_ymfpci_voice_alloc(ypcm->chip, YMFPCI_PCM, voices > 1, &ypcm->voices[0]);
  418. if (err < 0)
  419. return err;
  420. ypcm->voices[0]->ypcm = ypcm;
  421. ypcm->voices[0]->interrupt = snd_ymfpci_pcm_interrupt;
  422. if (voices > 1) {
  423. ypcm->voices[1] = &ypcm->chip->voices[ypcm->voices[0]->number + 1];
  424. ypcm->voices[1]->ypcm = ypcm;
  425. }
  426. return 0;
  427. }
  428. static void snd_ymfpci_pcm_init_voice(struct snd_ymfpci_pcm *ypcm, unsigned int voiceidx,
  429. struct snd_pcm_runtime *runtime,
  430. int has_pcm_volume)
  431. {
  432. struct snd_ymfpci_voice *voice = ypcm->voices[voiceidx];
  433. u32 format;
  434. u32 delta = snd_ymfpci_calc_delta(runtime->rate);
  435. u32 lpfQ = snd_ymfpci_calc_lpfQ(runtime->rate);
  436. u32 lpfK = snd_ymfpci_calc_lpfK(runtime->rate);
  437. struct snd_ymfpci_playback_bank *bank;
  438. unsigned int nbank;
  439. u32 vol_left, vol_right;
  440. u8 use_left, use_right;
  441. snd_assert(voice != NULL, return);
  442. if (runtime->channels == 1) {
  443. use_left = 1;
  444. use_right = 1;
  445. } else {
  446. use_left = (voiceidx & 1) == 0;
  447. use_right = !use_left;
  448. }
  449. if (has_pcm_volume) {
  450. vol_left = cpu_to_le32(ypcm->chip->pcm_mixer
  451. [ypcm->substream->number].left << 15);
  452. vol_right = cpu_to_le32(ypcm->chip->pcm_mixer
  453. [ypcm->substream->number].right << 15);
  454. } else {
  455. vol_left = cpu_to_le32(0x40000000);
  456. vol_right = cpu_to_le32(0x40000000);
  457. }
  458. format = runtime->channels == 2 ? 0x00010000 : 0;
  459. if (snd_pcm_format_width(runtime->format) == 8)
  460. format |= 0x80000000;
  461. if (runtime->channels == 2 && (voiceidx & 1) != 0)
  462. format |= 1;
  463. for (nbank = 0; nbank < 2; nbank++) {
  464. bank = &voice->bank[nbank];
  465. memset(bank, 0, sizeof(*bank));
  466. bank->format = cpu_to_le32(format);
  467. bank->base = cpu_to_le32(runtime->dma_addr);
  468. bank->loop_end = cpu_to_le32(ypcm->buffer_size);
  469. bank->lpfQ = cpu_to_le32(lpfQ);
  470. bank->delta =
  471. bank->delta_end = cpu_to_le32(delta);
  472. bank->lpfK =
  473. bank->lpfK_end = cpu_to_le32(lpfK);
  474. bank->eg_gain =
  475. bank->eg_gain_end = cpu_to_le32(0x40000000);
  476. if (ypcm->output_front) {
  477. if (use_left) {
  478. bank->left_gain =
  479. bank->left_gain_end = vol_left;
  480. }
  481. if (use_right) {
  482. bank->right_gain =
  483. bank->right_gain_end = vol_right;
  484. }
  485. }
  486. if (ypcm->output_rear) {
  487. if (!ypcm->swap_rear) {
  488. if (use_left) {
  489. bank->eff2_gain =
  490. bank->eff2_gain_end = vol_left;
  491. }
  492. if (use_right) {
  493. bank->eff3_gain =
  494. bank->eff3_gain_end = vol_right;
  495. }
  496. } else {
  497. /* The SPDIF out channels seem to be swapped, so we have
  498. * to swap them here, too. The rear analog out channels
  499. * will be wrong, but otherwise AC3 would not work.
  500. */
  501. if (use_left) {
  502. bank->eff3_gain =
  503. bank->eff3_gain_end = vol_left;
  504. }
  505. if (use_right) {
  506. bank->eff2_gain =
  507. bank->eff2_gain_end = vol_right;
  508. }
  509. }
  510. }
  511. }
  512. }
  513. static int __devinit snd_ymfpci_ac3_init(struct snd_ymfpci *chip)
  514. {
  515. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  516. 4096, &chip->ac3_tmp_base) < 0)
  517. return -ENOMEM;
  518. chip->bank_effect[3][0]->base =
  519. chip->bank_effect[3][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr);
  520. chip->bank_effect[3][0]->loop_end =
  521. chip->bank_effect[3][1]->loop_end = cpu_to_le32(1024);
  522. chip->bank_effect[4][0]->base =
  523. chip->bank_effect[4][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr + 2048);
  524. chip->bank_effect[4][0]->loop_end =
  525. chip->bank_effect[4][1]->loop_end = cpu_to_le32(1024);
  526. spin_lock_irq(&chip->reg_lock);
  527. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  528. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) | 3 << 3);
  529. spin_unlock_irq(&chip->reg_lock);
  530. return 0;
  531. }
  532. static int snd_ymfpci_ac3_done(struct snd_ymfpci *chip)
  533. {
  534. spin_lock_irq(&chip->reg_lock);
  535. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  536. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) & ~(3 << 3));
  537. spin_unlock_irq(&chip->reg_lock);
  538. // snd_ymfpci_irq_wait(chip);
  539. if (chip->ac3_tmp_base.area) {
  540. snd_dma_free_pages(&chip->ac3_tmp_base);
  541. chip->ac3_tmp_base.area = NULL;
  542. }
  543. return 0;
  544. }
  545. static int snd_ymfpci_playback_hw_params(struct snd_pcm_substream *substream,
  546. struct snd_pcm_hw_params *hw_params)
  547. {
  548. struct snd_pcm_runtime *runtime = substream->runtime;
  549. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  550. int err;
  551. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  552. return err;
  553. if ((err = snd_ymfpci_pcm_voice_alloc(ypcm, params_channels(hw_params))) < 0)
  554. return err;
  555. return 0;
  556. }
  557. static int snd_ymfpci_playback_hw_free(struct snd_pcm_substream *substream)
  558. {
  559. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  560. struct snd_pcm_runtime *runtime = substream->runtime;
  561. struct snd_ymfpci_pcm *ypcm;
  562. if (runtime->private_data == NULL)
  563. return 0;
  564. ypcm = runtime->private_data;
  565. /* wait, until the PCI operations are not finished */
  566. snd_ymfpci_irq_wait(chip);
  567. snd_pcm_lib_free_pages(substream);
  568. if (ypcm->voices[1]) {
  569. snd_ymfpci_voice_free(chip, ypcm->voices[1]);
  570. ypcm->voices[1] = NULL;
  571. }
  572. if (ypcm->voices[0]) {
  573. snd_ymfpci_voice_free(chip, ypcm->voices[0]);
  574. ypcm->voices[0] = NULL;
  575. }
  576. return 0;
  577. }
  578. static int snd_ymfpci_playback_prepare(struct snd_pcm_substream *substream)
  579. {
  580. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  581. struct snd_pcm_runtime *runtime = substream->runtime;
  582. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  583. unsigned int nvoice;
  584. ypcm->period_size = runtime->period_size;
  585. ypcm->buffer_size = runtime->buffer_size;
  586. ypcm->period_pos = 0;
  587. ypcm->last_pos = 0;
  588. for (nvoice = 0; nvoice < runtime->channels; nvoice++)
  589. snd_ymfpci_pcm_init_voice(ypcm, nvoice, runtime,
  590. substream->pcm == chip->pcm);
  591. return 0;
  592. }
  593. static int snd_ymfpci_capture_hw_params(struct snd_pcm_substream *substream,
  594. struct snd_pcm_hw_params *hw_params)
  595. {
  596. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  597. }
  598. static int snd_ymfpci_capture_hw_free(struct snd_pcm_substream *substream)
  599. {
  600. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  601. /* wait, until the PCI operations are not finished */
  602. snd_ymfpci_irq_wait(chip);
  603. return snd_pcm_lib_free_pages(substream);
  604. }
  605. static int snd_ymfpci_capture_prepare(struct snd_pcm_substream *substream)
  606. {
  607. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  608. struct snd_pcm_runtime *runtime = substream->runtime;
  609. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  610. struct snd_ymfpci_capture_bank * bank;
  611. int nbank;
  612. u32 rate, format;
  613. ypcm->period_size = runtime->period_size;
  614. ypcm->buffer_size = runtime->buffer_size;
  615. ypcm->period_pos = 0;
  616. ypcm->last_pos = 0;
  617. ypcm->shift = 0;
  618. rate = ((48000 * 4096) / runtime->rate) - 1;
  619. format = 0;
  620. if (runtime->channels == 2) {
  621. format |= 2;
  622. ypcm->shift++;
  623. }
  624. if (snd_pcm_format_width(runtime->format) == 8)
  625. format |= 1;
  626. else
  627. ypcm->shift++;
  628. switch (ypcm->capture_bank_number) {
  629. case 0:
  630. snd_ymfpci_writel(chip, YDSXGR_RECFORMAT, format);
  631. snd_ymfpci_writel(chip, YDSXGR_RECSLOTSR, rate);
  632. break;
  633. case 1:
  634. snd_ymfpci_writel(chip, YDSXGR_ADCFORMAT, format);
  635. snd_ymfpci_writel(chip, YDSXGR_ADCSLOTSR, rate);
  636. break;
  637. }
  638. for (nbank = 0; nbank < 2; nbank++) {
  639. bank = chip->bank_capture[ypcm->capture_bank_number][nbank];
  640. bank->base = cpu_to_le32(runtime->dma_addr);
  641. bank->loop_end = cpu_to_le32(ypcm->buffer_size << ypcm->shift);
  642. bank->start = 0;
  643. bank->num_of_loops = 0;
  644. }
  645. return 0;
  646. }
  647. static snd_pcm_uframes_t snd_ymfpci_playback_pointer(struct snd_pcm_substream *substream)
  648. {
  649. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  650. struct snd_pcm_runtime *runtime = substream->runtime;
  651. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  652. struct snd_ymfpci_voice *voice = ypcm->voices[0];
  653. if (!(ypcm->running && voice))
  654. return 0;
  655. return le32_to_cpu(voice->bank[chip->active_bank].start);
  656. }
  657. static snd_pcm_uframes_t snd_ymfpci_capture_pointer(struct snd_pcm_substream *substream)
  658. {
  659. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  660. struct snd_pcm_runtime *runtime = substream->runtime;
  661. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  662. if (!ypcm->running)
  663. return 0;
  664. return le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  665. }
  666. static void snd_ymfpci_irq_wait(struct snd_ymfpci *chip)
  667. {
  668. wait_queue_t wait;
  669. int loops = 4;
  670. while (loops-- > 0) {
  671. if ((snd_ymfpci_readl(chip, YDSXGR_MODE) & 3) == 0)
  672. continue;
  673. init_waitqueue_entry(&wait, current);
  674. add_wait_queue(&chip->interrupt_sleep, &wait);
  675. atomic_inc(&chip->interrupt_sleep_count);
  676. schedule_timeout_uninterruptible(msecs_to_jiffies(50));
  677. remove_wait_queue(&chip->interrupt_sleep, &wait);
  678. }
  679. }
  680. static irqreturn_t snd_ymfpci_interrupt(int irq, void *dev_id)
  681. {
  682. struct snd_ymfpci *chip = dev_id;
  683. u32 status, nvoice, mode;
  684. struct snd_ymfpci_voice *voice;
  685. status = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  686. if (status & 0x80000000) {
  687. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  688. spin_lock(&chip->voice_lock);
  689. for (nvoice = 0; nvoice < YDSXG_PLAYBACK_VOICES; nvoice++) {
  690. voice = &chip->voices[nvoice];
  691. if (voice->interrupt)
  692. voice->interrupt(chip, voice);
  693. }
  694. for (nvoice = 0; nvoice < YDSXG_CAPTURE_VOICES; nvoice++) {
  695. if (chip->capture_substream[nvoice])
  696. snd_ymfpci_pcm_capture_interrupt(chip->capture_substream[nvoice]);
  697. }
  698. #if 0
  699. for (nvoice = 0; nvoice < YDSXG_EFFECT_VOICES; nvoice++) {
  700. if (chip->effect_substream[nvoice])
  701. snd_ymfpci_pcm_effect_interrupt(chip->effect_substream[nvoice]);
  702. }
  703. #endif
  704. spin_unlock(&chip->voice_lock);
  705. spin_lock(&chip->reg_lock);
  706. snd_ymfpci_writel(chip, YDSXGR_STATUS, 0x80000000);
  707. mode = snd_ymfpci_readl(chip, YDSXGR_MODE) | 2;
  708. snd_ymfpci_writel(chip, YDSXGR_MODE, mode);
  709. spin_unlock(&chip->reg_lock);
  710. if (atomic_read(&chip->interrupt_sleep_count)) {
  711. atomic_set(&chip->interrupt_sleep_count, 0);
  712. wake_up(&chip->interrupt_sleep);
  713. }
  714. }
  715. status = snd_ymfpci_readw(chip, YDSXGR_INTFLAG);
  716. if (status & 1) {
  717. if (chip->timer)
  718. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  719. }
  720. snd_ymfpci_writew(chip, YDSXGR_INTFLAG, status);
  721. if (chip->rawmidi)
  722. snd_mpu401_uart_interrupt(irq, chip->rawmidi->private_data);
  723. return IRQ_HANDLED;
  724. }
  725. static struct snd_pcm_hardware snd_ymfpci_playback =
  726. {
  727. .info = (SNDRV_PCM_INFO_MMAP |
  728. SNDRV_PCM_INFO_MMAP_VALID |
  729. SNDRV_PCM_INFO_INTERLEAVED |
  730. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  731. SNDRV_PCM_INFO_PAUSE |
  732. SNDRV_PCM_INFO_RESUME),
  733. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  734. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  735. .rate_min = 8000,
  736. .rate_max = 48000,
  737. .channels_min = 1,
  738. .channels_max = 2,
  739. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  740. .period_bytes_min = 64,
  741. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  742. .periods_min = 3,
  743. .periods_max = 1024,
  744. .fifo_size = 0,
  745. };
  746. static struct snd_pcm_hardware snd_ymfpci_capture =
  747. {
  748. .info = (SNDRV_PCM_INFO_MMAP |
  749. SNDRV_PCM_INFO_MMAP_VALID |
  750. SNDRV_PCM_INFO_INTERLEAVED |
  751. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  752. SNDRV_PCM_INFO_PAUSE |
  753. SNDRV_PCM_INFO_RESUME),
  754. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  755. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  756. .rate_min = 8000,
  757. .rate_max = 48000,
  758. .channels_min = 1,
  759. .channels_max = 2,
  760. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  761. .period_bytes_min = 64,
  762. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  763. .periods_min = 3,
  764. .periods_max = 1024,
  765. .fifo_size = 0,
  766. };
  767. static void snd_ymfpci_pcm_free_substream(struct snd_pcm_runtime *runtime)
  768. {
  769. kfree(runtime->private_data);
  770. }
  771. static int snd_ymfpci_playback_open_1(struct snd_pcm_substream *substream)
  772. {
  773. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  774. struct snd_pcm_runtime *runtime = substream->runtime;
  775. struct snd_ymfpci_pcm *ypcm;
  776. ypcm = kzalloc(sizeof(*ypcm), GFP_KERNEL);
  777. if (ypcm == NULL)
  778. return -ENOMEM;
  779. ypcm->chip = chip;
  780. ypcm->type = PLAYBACK_VOICE;
  781. ypcm->substream = substream;
  782. runtime->hw = snd_ymfpci_playback;
  783. runtime->private_data = ypcm;
  784. runtime->private_free = snd_ymfpci_pcm_free_substream;
  785. /* FIXME? True value is 256/48 = 5.33333 ms */
  786. snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_TIME, 5333, UINT_MAX);
  787. return 0;
  788. }
  789. /* call with spinlock held */
  790. static void ymfpci_open_extension(struct snd_ymfpci *chip)
  791. {
  792. if (! chip->rear_opened) {
  793. if (! chip->spdif_opened) /* set AC3 */
  794. snd_ymfpci_writel(chip, YDSXGR_MODE,
  795. snd_ymfpci_readl(chip, YDSXGR_MODE) | (1 << 30));
  796. /* enable second codec (4CHEN) */
  797. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  798. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) | 0x0010);
  799. }
  800. }
  801. /* call with spinlock held */
  802. static void ymfpci_close_extension(struct snd_ymfpci *chip)
  803. {
  804. if (! chip->rear_opened) {
  805. if (! chip->spdif_opened)
  806. snd_ymfpci_writel(chip, YDSXGR_MODE,
  807. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~(1 << 30));
  808. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  809. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) & ~0x0010);
  810. }
  811. }
  812. static int snd_ymfpci_playback_open(struct snd_pcm_substream *substream)
  813. {
  814. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  815. struct snd_pcm_runtime *runtime = substream->runtime;
  816. struct snd_ymfpci_pcm *ypcm;
  817. struct snd_kcontrol *kctl;
  818. int err;
  819. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  820. return err;
  821. ypcm = runtime->private_data;
  822. ypcm->output_front = 1;
  823. ypcm->output_rear = chip->mode_dup4ch ? 1 : 0;
  824. ypcm->swap_rear = 0;
  825. spin_lock_irq(&chip->reg_lock);
  826. if (ypcm->output_rear) {
  827. ymfpci_open_extension(chip);
  828. chip->rear_opened++;
  829. }
  830. spin_unlock_irq(&chip->reg_lock);
  831. kctl = chip->pcm_mixer[substream->number].ctl;
  832. kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  833. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  834. return 0;
  835. }
  836. static int snd_ymfpci_playback_spdif_open(struct snd_pcm_substream *substream)
  837. {
  838. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  839. struct snd_pcm_runtime *runtime = substream->runtime;
  840. struct snd_ymfpci_pcm *ypcm;
  841. int err;
  842. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  843. return err;
  844. ypcm = runtime->private_data;
  845. ypcm->output_front = 0;
  846. ypcm->output_rear = 1;
  847. ypcm->swap_rear = 1;
  848. spin_lock_irq(&chip->reg_lock);
  849. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  850. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) | 2);
  851. ymfpci_open_extension(chip);
  852. chip->spdif_pcm_bits = chip->spdif_bits;
  853. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  854. chip->spdif_opened++;
  855. spin_unlock_irq(&chip->reg_lock);
  856. chip->spdif_pcm_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  857. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  858. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  859. return 0;
  860. }
  861. static int snd_ymfpci_playback_4ch_open(struct snd_pcm_substream *substream)
  862. {
  863. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  864. struct snd_pcm_runtime *runtime = substream->runtime;
  865. struct snd_ymfpci_pcm *ypcm;
  866. int err;
  867. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  868. return err;
  869. ypcm = runtime->private_data;
  870. ypcm->output_front = 0;
  871. ypcm->output_rear = 1;
  872. ypcm->swap_rear = 0;
  873. spin_lock_irq(&chip->reg_lock);
  874. ymfpci_open_extension(chip);
  875. chip->rear_opened++;
  876. spin_unlock_irq(&chip->reg_lock);
  877. return 0;
  878. }
  879. static int snd_ymfpci_capture_open(struct snd_pcm_substream *substream,
  880. u32 capture_bank_number)
  881. {
  882. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  883. struct snd_pcm_runtime *runtime = substream->runtime;
  884. struct snd_ymfpci_pcm *ypcm;
  885. ypcm = kzalloc(sizeof(*ypcm), GFP_KERNEL);
  886. if (ypcm == NULL)
  887. return -ENOMEM;
  888. ypcm->chip = chip;
  889. ypcm->type = capture_bank_number + CAPTURE_REC;
  890. ypcm->substream = substream;
  891. ypcm->capture_bank_number = capture_bank_number;
  892. chip->capture_substream[capture_bank_number] = substream;
  893. runtime->hw = snd_ymfpci_capture;
  894. /* FIXME? True value is 256/48 = 5.33333 ms */
  895. snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_TIME, 5333, UINT_MAX);
  896. runtime->private_data = ypcm;
  897. runtime->private_free = snd_ymfpci_pcm_free_substream;
  898. snd_ymfpci_hw_start(chip);
  899. return 0;
  900. }
  901. static int snd_ymfpci_capture_rec_open(struct snd_pcm_substream *substream)
  902. {
  903. return snd_ymfpci_capture_open(substream, 0);
  904. }
  905. static int snd_ymfpci_capture_ac97_open(struct snd_pcm_substream *substream)
  906. {
  907. return snd_ymfpci_capture_open(substream, 1);
  908. }
  909. static int snd_ymfpci_playback_close_1(struct snd_pcm_substream *substream)
  910. {
  911. return 0;
  912. }
  913. static int snd_ymfpci_playback_close(struct snd_pcm_substream *substream)
  914. {
  915. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  916. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  917. struct snd_kcontrol *kctl;
  918. spin_lock_irq(&chip->reg_lock);
  919. if (ypcm->output_rear && chip->rear_opened > 0) {
  920. chip->rear_opened--;
  921. ymfpci_close_extension(chip);
  922. }
  923. spin_unlock_irq(&chip->reg_lock);
  924. kctl = chip->pcm_mixer[substream->number].ctl;
  925. kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  926. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  927. return snd_ymfpci_playback_close_1(substream);
  928. }
  929. static int snd_ymfpci_playback_spdif_close(struct snd_pcm_substream *substream)
  930. {
  931. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  932. spin_lock_irq(&chip->reg_lock);
  933. chip->spdif_opened = 0;
  934. ymfpci_close_extension(chip);
  935. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  936. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & ~2);
  937. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  938. spin_unlock_irq(&chip->reg_lock);
  939. chip->spdif_pcm_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  940. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  941. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  942. return snd_ymfpci_playback_close_1(substream);
  943. }
  944. static int snd_ymfpci_playback_4ch_close(struct snd_pcm_substream *substream)
  945. {
  946. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  947. spin_lock_irq(&chip->reg_lock);
  948. if (chip->rear_opened > 0) {
  949. chip->rear_opened--;
  950. ymfpci_close_extension(chip);
  951. }
  952. spin_unlock_irq(&chip->reg_lock);
  953. return snd_ymfpci_playback_close_1(substream);
  954. }
  955. static int snd_ymfpci_capture_close(struct snd_pcm_substream *substream)
  956. {
  957. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  958. struct snd_pcm_runtime *runtime = substream->runtime;
  959. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  960. if (ypcm != NULL) {
  961. chip->capture_substream[ypcm->capture_bank_number] = NULL;
  962. snd_ymfpci_hw_stop(chip);
  963. }
  964. return 0;
  965. }
  966. static struct snd_pcm_ops snd_ymfpci_playback_ops = {
  967. .open = snd_ymfpci_playback_open,
  968. .close = snd_ymfpci_playback_close,
  969. .ioctl = snd_pcm_lib_ioctl,
  970. .hw_params = snd_ymfpci_playback_hw_params,
  971. .hw_free = snd_ymfpci_playback_hw_free,
  972. .prepare = snd_ymfpci_playback_prepare,
  973. .trigger = snd_ymfpci_playback_trigger,
  974. .pointer = snd_ymfpci_playback_pointer,
  975. };
  976. static struct snd_pcm_ops snd_ymfpci_capture_rec_ops = {
  977. .open = snd_ymfpci_capture_rec_open,
  978. .close = snd_ymfpci_capture_close,
  979. .ioctl = snd_pcm_lib_ioctl,
  980. .hw_params = snd_ymfpci_capture_hw_params,
  981. .hw_free = snd_ymfpci_capture_hw_free,
  982. .prepare = snd_ymfpci_capture_prepare,
  983. .trigger = snd_ymfpci_capture_trigger,
  984. .pointer = snd_ymfpci_capture_pointer,
  985. };
  986. int __devinit snd_ymfpci_pcm(struct snd_ymfpci *chip, int device, struct snd_pcm ** rpcm)
  987. {
  988. struct snd_pcm *pcm;
  989. int err;
  990. if (rpcm)
  991. *rpcm = NULL;
  992. if ((err = snd_pcm_new(chip->card, "YMFPCI", device, 32, 1, &pcm)) < 0)
  993. return err;
  994. pcm->private_data = chip;
  995. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_ops);
  996. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_rec_ops);
  997. /* global setup */
  998. pcm->info_flags = 0;
  999. strcpy(pcm->name, "YMFPCI");
  1000. chip->pcm = pcm;
  1001. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1002. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1003. if (rpcm)
  1004. *rpcm = pcm;
  1005. return 0;
  1006. }
  1007. static struct snd_pcm_ops snd_ymfpci_capture_ac97_ops = {
  1008. .open = snd_ymfpci_capture_ac97_open,
  1009. .close = snd_ymfpci_capture_close,
  1010. .ioctl = snd_pcm_lib_ioctl,
  1011. .hw_params = snd_ymfpci_capture_hw_params,
  1012. .hw_free = snd_ymfpci_capture_hw_free,
  1013. .prepare = snd_ymfpci_capture_prepare,
  1014. .trigger = snd_ymfpci_capture_trigger,
  1015. .pointer = snd_ymfpci_capture_pointer,
  1016. };
  1017. int __devinit snd_ymfpci_pcm2(struct snd_ymfpci *chip, int device, struct snd_pcm ** rpcm)
  1018. {
  1019. struct snd_pcm *pcm;
  1020. int err;
  1021. if (rpcm)
  1022. *rpcm = NULL;
  1023. if ((err = snd_pcm_new(chip->card, "YMFPCI - PCM2", device, 0, 1, &pcm)) < 0)
  1024. return err;
  1025. pcm->private_data = chip;
  1026. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_ac97_ops);
  1027. /* global setup */
  1028. pcm->info_flags = 0;
  1029. sprintf(pcm->name, "YMFPCI - %s",
  1030. chip->device_id == PCI_DEVICE_ID_YAMAHA_754 ? "Direct Recording" : "AC'97");
  1031. chip->pcm2 = pcm;
  1032. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1033. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1034. if (rpcm)
  1035. *rpcm = pcm;
  1036. return 0;
  1037. }
  1038. static struct snd_pcm_ops snd_ymfpci_playback_spdif_ops = {
  1039. .open = snd_ymfpci_playback_spdif_open,
  1040. .close = snd_ymfpci_playback_spdif_close,
  1041. .ioctl = snd_pcm_lib_ioctl,
  1042. .hw_params = snd_ymfpci_playback_hw_params,
  1043. .hw_free = snd_ymfpci_playback_hw_free,
  1044. .prepare = snd_ymfpci_playback_prepare,
  1045. .trigger = snd_ymfpci_playback_trigger,
  1046. .pointer = snd_ymfpci_playback_pointer,
  1047. };
  1048. int __devinit snd_ymfpci_pcm_spdif(struct snd_ymfpci *chip, int device, struct snd_pcm ** rpcm)
  1049. {
  1050. struct snd_pcm *pcm;
  1051. int err;
  1052. if (rpcm)
  1053. *rpcm = NULL;
  1054. if ((err = snd_pcm_new(chip->card, "YMFPCI - IEC958", device, 1, 0, &pcm)) < 0)
  1055. return err;
  1056. pcm->private_data = chip;
  1057. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_spdif_ops);
  1058. /* global setup */
  1059. pcm->info_flags = 0;
  1060. strcpy(pcm->name, "YMFPCI - IEC958");
  1061. chip->pcm_spdif = pcm;
  1062. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1063. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1064. if (rpcm)
  1065. *rpcm = pcm;
  1066. return 0;
  1067. }
  1068. static struct snd_pcm_ops snd_ymfpci_playback_4ch_ops = {
  1069. .open = snd_ymfpci_playback_4ch_open,
  1070. .close = snd_ymfpci_playback_4ch_close,
  1071. .ioctl = snd_pcm_lib_ioctl,
  1072. .hw_params = snd_ymfpci_playback_hw_params,
  1073. .hw_free = snd_ymfpci_playback_hw_free,
  1074. .prepare = snd_ymfpci_playback_prepare,
  1075. .trigger = snd_ymfpci_playback_trigger,
  1076. .pointer = snd_ymfpci_playback_pointer,
  1077. };
  1078. int __devinit snd_ymfpci_pcm_4ch(struct snd_ymfpci *chip, int device, struct snd_pcm ** rpcm)
  1079. {
  1080. struct snd_pcm *pcm;
  1081. int err;
  1082. if (rpcm)
  1083. *rpcm = NULL;
  1084. if ((err = snd_pcm_new(chip->card, "YMFPCI - Rear", device, 1, 0, &pcm)) < 0)
  1085. return err;
  1086. pcm->private_data = chip;
  1087. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_4ch_ops);
  1088. /* global setup */
  1089. pcm->info_flags = 0;
  1090. strcpy(pcm->name, "YMFPCI - Rear PCM");
  1091. chip->pcm_4ch = pcm;
  1092. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1093. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1094. if (rpcm)
  1095. *rpcm = pcm;
  1096. return 0;
  1097. }
  1098. static int snd_ymfpci_spdif_default_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1099. {
  1100. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1101. uinfo->count = 1;
  1102. return 0;
  1103. }
  1104. static int snd_ymfpci_spdif_default_get(struct snd_kcontrol *kcontrol,
  1105. struct snd_ctl_elem_value *ucontrol)
  1106. {
  1107. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1108. spin_lock_irq(&chip->reg_lock);
  1109. ucontrol->value.iec958.status[0] = (chip->spdif_bits >> 0) & 0xff;
  1110. ucontrol->value.iec958.status[1] = (chip->spdif_bits >> 8) & 0xff;
  1111. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000;
  1112. spin_unlock_irq(&chip->reg_lock);
  1113. return 0;
  1114. }
  1115. static int snd_ymfpci_spdif_default_put(struct snd_kcontrol *kcontrol,
  1116. struct snd_ctl_elem_value *ucontrol)
  1117. {
  1118. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1119. unsigned int val;
  1120. int change;
  1121. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1122. (ucontrol->value.iec958.status[1] << 8);
  1123. spin_lock_irq(&chip->reg_lock);
  1124. change = chip->spdif_bits != val;
  1125. chip->spdif_bits = val;
  1126. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 1) && chip->pcm_spdif == NULL)
  1127. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1128. spin_unlock_irq(&chip->reg_lock);
  1129. return change;
  1130. }
  1131. static struct snd_kcontrol_new snd_ymfpci_spdif_default __devinitdata =
  1132. {
  1133. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1134. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
  1135. .info = snd_ymfpci_spdif_default_info,
  1136. .get = snd_ymfpci_spdif_default_get,
  1137. .put = snd_ymfpci_spdif_default_put
  1138. };
  1139. static int snd_ymfpci_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1140. {
  1141. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1142. uinfo->count = 1;
  1143. return 0;
  1144. }
  1145. static int snd_ymfpci_spdif_mask_get(struct snd_kcontrol *kcontrol,
  1146. struct snd_ctl_elem_value *ucontrol)
  1147. {
  1148. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1149. spin_lock_irq(&chip->reg_lock);
  1150. ucontrol->value.iec958.status[0] = 0x3e;
  1151. ucontrol->value.iec958.status[1] = 0xff;
  1152. spin_unlock_irq(&chip->reg_lock);
  1153. return 0;
  1154. }
  1155. static struct snd_kcontrol_new snd_ymfpci_spdif_mask __devinitdata =
  1156. {
  1157. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1158. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1159. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
  1160. .info = snd_ymfpci_spdif_mask_info,
  1161. .get = snd_ymfpci_spdif_mask_get,
  1162. };
  1163. static int snd_ymfpci_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1164. {
  1165. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1166. uinfo->count = 1;
  1167. return 0;
  1168. }
  1169. static int snd_ymfpci_spdif_stream_get(struct snd_kcontrol *kcontrol,
  1170. struct snd_ctl_elem_value *ucontrol)
  1171. {
  1172. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1173. spin_lock_irq(&chip->reg_lock);
  1174. ucontrol->value.iec958.status[0] = (chip->spdif_pcm_bits >> 0) & 0xff;
  1175. ucontrol->value.iec958.status[1] = (chip->spdif_pcm_bits >> 8) & 0xff;
  1176. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000;
  1177. spin_unlock_irq(&chip->reg_lock);
  1178. return 0;
  1179. }
  1180. static int snd_ymfpci_spdif_stream_put(struct snd_kcontrol *kcontrol,
  1181. struct snd_ctl_elem_value *ucontrol)
  1182. {
  1183. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1184. unsigned int val;
  1185. int change;
  1186. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1187. (ucontrol->value.iec958.status[1] << 8);
  1188. spin_lock_irq(&chip->reg_lock);
  1189. change = chip->spdif_pcm_bits != val;
  1190. chip->spdif_pcm_bits = val;
  1191. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 2))
  1192. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  1193. spin_unlock_irq(&chip->reg_lock);
  1194. return change;
  1195. }
  1196. static struct snd_kcontrol_new snd_ymfpci_spdif_stream __devinitdata =
  1197. {
  1198. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1199. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1200. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
  1201. .info = snd_ymfpci_spdif_stream_info,
  1202. .get = snd_ymfpci_spdif_stream_get,
  1203. .put = snd_ymfpci_spdif_stream_put
  1204. };
  1205. static int snd_ymfpci_drec_source_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *info)
  1206. {
  1207. static char *texts[3] = {"AC'97", "IEC958", "ZV Port"};
  1208. info->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1209. info->count = 1;
  1210. info->value.enumerated.items = 3;
  1211. if (info->value.enumerated.item > 2)
  1212. info->value.enumerated.item = 2;
  1213. strcpy(info->value.enumerated.name, texts[info->value.enumerated.item]);
  1214. return 0;
  1215. }
  1216. static int snd_ymfpci_drec_source_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *value)
  1217. {
  1218. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1219. u16 reg;
  1220. spin_lock_irq(&chip->reg_lock);
  1221. reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1222. spin_unlock_irq(&chip->reg_lock);
  1223. if (!(reg & 0x100))
  1224. value->value.enumerated.item[0] = 0;
  1225. else
  1226. value->value.enumerated.item[0] = 1 + ((reg & 0x200) != 0);
  1227. return 0;
  1228. }
  1229. static int snd_ymfpci_drec_source_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *value)
  1230. {
  1231. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1232. u16 reg, old_reg;
  1233. spin_lock_irq(&chip->reg_lock);
  1234. old_reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1235. if (value->value.enumerated.item[0] == 0)
  1236. reg = old_reg & ~0x100;
  1237. else
  1238. reg = (old_reg & ~0x300) | 0x100 | ((value->value.enumerated.item[0] == 2) << 9);
  1239. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, reg);
  1240. spin_unlock_irq(&chip->reg_lock);
  1241. return reg != old_reg;
  1242. }
  1243. static struct snd_kcontrol_new snd_ymfpci_drec_source __devinitdata = {
  1244. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  1245. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1246. .name = "Direct Recording Source",
  1247. .info = snd_ymfpci_drec_source_info,
  1248. .get = snd_ymfpci_drec_source_get,
  1249. .put = snd_ymfpci_drec_source_put
  1250. };
  1251. /*
  1252. * Mixer controls
  1253. */
  1254. #define YMFPCI_SINGLE(xname, xindex, reg, shift) \
  1255. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1256. .info = snd_ymfpci_info_single, \
  1257. .get = snd_ymfpci_get_single, .put = snd_ymfpci_put_single, \
  1258. .private_value = ((reg) | ((shift) << 16)) }
  1259. static int snd_ymfpci_info_single(struct snd_kcontrol *kcontrol,
  1260. struct snd_ctl_elem_info *uinfo)
  1261. {
  1262. int reg = kcontrol->private_value & 0xffff;
  1263. switch (reg) {
  1264. case YDSXGR_SPDIFOUTCTRL: break;
  1265. case YDSXGR_SPDIFINCTRL: break;
  1266. default: return -EINVAL;
  1267. }
  1268. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1269. uinfo->count = 1;
  1270. uinfo->value.integer.min = 0;
  1271. uinfo->value.integer.max = 1;
  1272. return 0;
  1273. }
  1274. static int snd_ymfpci_get_single(struct snd_kcontrol *kcontrol,
  1275. struct snd_ctl_elem_value *ucontrol)
  1276. {
  1277. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1278. int reg = kcontrol->private_value & 0xffff;
  1279. unsigned int shift = (kcontrol->private_value >> 16) & 0xff;
  1280. unsigned int mask = 1;
  1281. switch (reg) {
  1282. case YDSXGR_SPDIFOUTCTRL: break;
  1283. case YDSXGR_SPDIFINCTRL: break;
  1284. default: return -EINVAL;
  1285. }
  1286. ucontrol->value.integer.value[0] =
  1287. (snd_ymfpci_readl(chip, reg) >> shift) & mask;
  1288. return 0;
  1289. }
  1290. static int snd_ymfpci_put_single(struct snd_kcontrol *kcontrol,
  1291. struct snd_ctl_elem_value *ucontrol)
  1292. {
  1293. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1294. int reg = kcontrol->private_value & 0xffff;
  1295. unsigned int shift = (kcontrol->private_value >> 16) & 0xff;
  1296. unsigned int mask = 1;
  1297. int change;
  1298. unsigned int val, oval;
  1299. switch (reg) {
  1300. case YDSXGR_SPDIFOUTCTRL: break;
  1301. case YDSXGR_SPDIFINCTRL: break;
  1302. default: return -EINVAL;
  1303. }
  1304. val = (ucontrol->value.integer.value[0] & mask);
  1305. val <<= shift;
  1306. spin_lock_irq(&chip->reg_lock);
  1307. oval = snd_ymfpci_readl(chip, reg);
  1308. val = (oval & ~(mask << shift)) | val;
  1309. change = val != oval;
  1310. snd_ymfpci_writel(chip, reg, val);
  1311. spin_unlock_irq(&chip->reg_lock);
  1312. return change;
  1313. }
  1314. static DECLARE_TLV_DB_LINEAR(db_scale_native, TLV_DB_GAIN_MUTE, 0);
  1315. #define YMFPCI_DOUBLE(xname, xindex, reg) \
  1316. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1317. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
  1318. .info = snd_ymfpci_info_double, \
  1319. .get = snd_ymfpci_get_double, .put = snd_ymfpci_put_double, \
  1320. .private_value = reg, \
  1321. .tlv = { .p = db_scale_native } }
  1322. static int snd_ymfpci_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1323. {
  1324. unsigned int reg = kcontrol->private_value;
  1325. if (reg < 0x80 || reg >= 0xc0)
  1326. return -EINVAL;
  1327. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1328. uinfo->count = 2;
  1329. uinfo->value.integer.min = 0;
  1330. uinfo->value.integer.max = 16383;
  1331. return 0;
  1332. }
  1333. static int snd_ymfpci_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1334. {
  1335. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1336. unsigned int reg = kcontrol->private_value;
  1337. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1338. unsigned int val;
  1339. if (reg < 0x80 || reg >= 0xc0)
  1340. return -EINVAL;
  1341. spin_lock_irq(&chip->reg_lock);
  1342. val = snd_ymfpci_readl(chip, reg);
  1343. spin_unlock_irq(&chip->reg_lock);
  1344. ucontrol->value.integer.value[0] = (val >> shift_left) & mask;
  1345. ucontrol->value.integer.value[1] = (val >> shift_right) & mask;
  1346. return 0;
  1347. }
  1348. static int snd_ymfpci_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1349. {
  1350. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1351. unsigned int reg = kcontrol->private_value;
  1352. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1353. int change;
  1354. unsigned int val1, val2, oval;
  1355. if (reg < 0x80 || reg >= 0xc0)
  1356. return -EINVAL;
  1357. val1 = ucontrol->value.integer.value[0] & mask;
  1358. val2 = ucontrol->value.integer.value[1] & mask;
  1359. val1 <<= shift_left;
  1360. val2 <<= shift_right;
  1361. spin_lock_irq(&chip->reg_lock);
  1362. oval = snd_ymfpci_readl(chip, reg);
  1363. val1 = (oval & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2;
  1364. change = val1 != oval;
  1365. snd_ymfpci_writel(chip, reg, val1);
  1366. spin_unlock_irq(&chip->reg_lock);
  1367. return change;
  1368. }
  1369. /*
  1370. * 4ch duplication
  1371. */
  1372. static int snd_ymfpci_info_dup4ch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1373. {
  1374. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1375. uinfo->count = 1;
  1376. uinfo->value.integer.min = 0;
  1377. uinfo->value.integer.max = 1;
  1378. return 0;
  1379. }
  1380. static int snd_ymfpci_get_dup4ch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1381. {
  1382. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1383. ucontrol->value.integer.value[0] = chip->mode_dup4ch;
  1384. return 0;
  1385. }
  1386. static int snd_ymfpci_put_dup4ch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1387. {
  1388. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1389. int change;
  1390. change = (ucontrol->value.integer.value[0] != chip->mode_dup4ch);
  1391. if (change)
  1392. chip->mode_dup4ch = !!ucontrol->value.integer.value[0];
  1393. return change;
  1394. }
  1395. static struct snd_kcontrol_new snd_ymfpci_controls[] __devinitdata = {
  1396. YMFPCI_DOUBLE("Wave Playback Volume", 0, YDSXGR_NATIVEDACOUTVOL),
  1397. YMFPCI_DOUBLE("Wave Capture Volume", 0, YDSXGR_NATIVEDACLOOPVOL),
  1398. YMFPCI_DOUBLE("Digital Capture Volume", 0, YDSXGR_NATIVEDACINVOL),
  1399. YMFPCI_DOUBLE("Digital Capture Volume", 1, YDSXGR_NATIVEADCINVOL),
  1400. YMFPCI_DOUBLE("ADC Playback Volume", 0, YDSXGR_PRIADCOUTVOL),
  1401. YMFPCI_DOUBLE("ADC Capture Volume", 0, YDSXGR_PRIADCLOOPVOL),
  1402. YMFPCI_DOUBLE("ADC Playback Volume", 1, YDSXGR_SECADCOUTVOL),
  1403. YMFPCI_DOUBLE("ADC Capture Volume", 1, YDSXGR_SECADCLOOPVOL),
  1404. YMFPCI_DOUBLE("FM Legacy Volume", 0, YDSXGR_LEGACYOUTVOL),
  1405. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ", PLAYBACK,VOLUME), 0, YDSXGR_ZVOUTVOL),
  1406. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("", CAPTURE,VOLUME), 0, YDSXGR_ZVLOOPVOL),
  1407. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ",PLAYBACK,VOLUME), 1, YDSXGR_SPDIFOUTVOL),
  1408. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,VOLUME), 1, YDSXGR_SPDIFLOOPVOL),
  1409. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH), 0, YDSXGR_SPDIFOUTCTRL, 0),
  1410. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), 0, YDSXGR_SPDIFINCTRL, 0),
  1411. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("Loop",NONE,NONE), 0, YDSXGR_SPDIFINCTRL, 4),
  1412. {
  1413. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1414. .name = "4ch Duplication",
  1415. .info = snd_ymfpci_info_dup4ch,
  1416. .get = snd_ymfpci_get_dup4ch,
  1417. .put = snd_ymfpci_put_dup4ch,
  1418. },
  1419. };
  1420. /*
  1421. * GPIO
  1422. */
  1423. static int snd_ymfpci_get_gpio_out(struct snd_ymfpci *chip, int pin)
  1424. {
  1425. u16 reg, mode;
  1426. unsigned long flags;
  1427. spin_lock_irqsave(&chip->reg_lock, flags);
  1428. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1429. reg &= ~(1 << (pin + 8));
  1430. reg |= (1 << pin);
  1431. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1432. /* set the level mode for input line */
  1433. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOTYPECONFIG);
  1434. mode &= ~(3 << (pin * 2));
  1435. snd_ymfpci_writew(chip, YDSXGR_GPIOTYPECONFIG, mode);
  1436. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1437. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOINSTATUS);
  1438. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1439. return (mode >> pin) & 1;
  1440. }
  1441. static int snd_ymfpci_set_gpio_out(struct snd_ymfpci *chip, int pin, int enable)
  1442. {
  1443. u16 reg;
  1444. unsigned long flags;
  1445. spin_lock_irqsave(&chip->reg_lock, flags);
  1446. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1447. reg &= ~(1 << pin);
  1448. reg &= ~(1 << (pin + 8));
  1449. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1450. snd_ymfpci_writew(chip, YDSXGR_GPIOOUTCTRL, enable << pin);
  1451. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1452. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1453. return 0;
  1454. }
  1455. static int snd_ymfpci_gpio_sw_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1456. {
  1457. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1458. uinfo->count = 1;
  1459. uinfo->value.integer.min = 0;
  1460. uinfo->value.integer.max = 1;
  1461. return 0;
  1462. }
  1463. static int snd_ymfpci_gpio_sw_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1464. {
  1465. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1466. int pin = (int)kcontrol->private_value;
  1467. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1468. return 0;
  1469. }
  1470. static int snd_ymfpci_gpio_sw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1471. {
  1472. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1473. int pin = (int)kcontrol->private_value;
  1474. if (snd_ymfpci_get_gpio_out(chip, pin) != ucontrol->value.integer.value[0]) {
  1475. snd_ymfpci_set_gpio_out(chip, pin, !!ucontrol->value.integer.value[0]);
  1476. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1477. return 1;
  1478. }
  1479. return 0;
  1480. }
  1481. static struct snd_kcontrol_new snd_ymfpci_rear_shared __devinitdata = {
  1482. .name = "Shared Rear/Line-In Switch",
  1483. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1484. .info = snd_ymfpci_gpio_sw_info,
  1485. .get = snd_ymfpci_gpio_sw_get,
  1486. .put = snd_ymfpci_gpio_sw_put,
  1487. .private_value = 2,
  1488. };
  1489. /*
  1490. * PCM voice volume
  1491. */
  1492. static int snd_ymfpci_pcm_vol_info(struct snd_kcontrol *kcontrol,
  1493. struct snd_ctl_elem_info *uinfo)
  1494. {
  1495. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1496. uinfo->count = 2;
  1497. uinfo->value.integer.min = 0;
  1498. uinfo->value.integer.max = 0x8000;
  1499. return 0;
  1500. }
  1501. static int snd_ymfpci_pcm_vol_get(struct snd_kcontrol *kcontrol,
  1502. struct snd_ctl_elem_value *ucontrol)
  1503. {
  1504. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1505. unsigned int subs = kcontrol->id.subdevice;
  1506. ucontrol->value.integer.value[0] = chip->pcm_mixer[subs].left;
  1507. ucontrol->value.integer.value[1] = chip->pcm_mixer[subs].right;
  1508. return 0;
  1509. }
  1510. static int snd_ymfpci_pcm_vol_put(struct snd_kcontrol *kcontrol,
  1511. struct snd_ctl_elem_value *ucontrol)
  1512. {
  1513. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1514. unsigned int subs = kcontrol->id.subdevice;
  1515. struct snd_pcm_substream *substream;
  1516. unsigned long flags;
  1517. if (ucontrol->value.integer.value[0] != chip->pcm_mixer[subs].left ||
  1518. ucontrol->value.integer.value[1] != chip->pcm_mixer[subs].right) {
  1519. chip->pcm_mixer[subs].left = ucontrol->value.integer.value[0];
  1520. chip->pcm_mixer[subs].right = ucontrol->value.integer.value[1];
  1521. substream = (struct snd_pcm_substream *)kcontrol->private_value;
  1522. spin_lock_irqsave(&chip->voice_lock, flags);
  1523. if (substream->runtime && substream->runtime->private_data) {
  1524. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  1525. ypcm->update_pcm_vol = 2;
  1526. }
  1527. spin_unlock_irqrestore(&chip->voice_lock, flags);
  1528. return 1;
  1529. }
  1530. return 0;
  1531. }
  1532. static struct snd_kcontrol_new snd_ymfpci_pcm_volume __devinitdata = {
  1533. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1534. .name = "PCM Playback Volume",
  1535. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1536. SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1537. .info = snd_ymfpci_pcm_vol_info,
  1538. .get = snd_ymfpci_pcm_vol_get,
  1539. .put = snd_ymfpci_pcm_vol_put,
  1540. };
  1541. /*
  1542. * Mixer routines
  1543. */
  1544. static void snd_ymfpci_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
  1545. {
  1546. struct snd_ymfpci *chip = bus->private_data;
  1547. chip->ac97_bus = NULL;
  1548. }
  1549. static void snd_ymfpci_mixer_free_ac97(struct snd_ac97 *ac97)
  1550. {
  1551. struct snd_ymfpci *chip = ac97->private_data;
  1552. chip->ac97 = NULL;
  1553. }
  1554. int __devinit snd_ymfpci_mixer(struct snd_ymfpci *chip, int rear_switch)
  1555. {
  1556. struct snd_ac97_template ac97;
  1557. struct snd_kcontrol *kctl;
  1558. struct snd_pcm_substream *substream;
  1559. unsigned int idx;
  1560. int err;
  1561. static struct snd_ac97_bus_ops ops = {
  1562. .write = snd_ymfpci_codec_write,
  1563. .read = snd_ymfpci_codec_read,
  1564. };
  1565. if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus)) < 0)
  1566. return err;
  1567. chip->ac97_bus->private_free = snd_ymfpci_mixer_free_ac97_bus;
  1568. chip->ac97_bus->no_vra = 1; /* YMFPCI doesn't need VRA */
  1569. memset(&ac97, 0, sizeof(ac97));
  1570. ac97.private_data = chip;
  1571. ac97.private_free = snd_ymfpci_mixer_free_ac97;
  1572. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
  1573. return err;
  1574. /* to be sure */
  1575. snd_ac97_update_bits(chip->ac97, AC97_EXTENDED_STATUS,
  1576. AC97_EA_VRA|AC97_EA_VRM, 0);
  1577. for (idx = 0; idx < ARRAY_SIZE(snd_ymfpci_controls); idx++) {
  1578. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_controls[idx], chip))) < 0)
  1579. return err;
  1580. }
  1581. /* add S/PDIF control */
  1582. snd_assert(chip->pcm_spdif != NULL, return -EIO);
  1583. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_default, chip))) < 0)
  1584. return err;
  1585. kctl->id.device = chip->pcm_spdif->device;
  1586. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_mask, chip))) < 0)
  1587. return err;
  1588. kctl->id.device = chip->pcm_spdif->device;
  1589. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_stream, chip))) < 0)
  1590. return err;
  1591. kctl->id.device = chip->pcm_spdif->device;
  1592. chip->spdif_pcm_ctl = kctl;
  1593. /* direct recording source */
  1594. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_754 &&
  1595. (err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_drec_source, chip))) < 0)
  1596. return err;
  1597. /*
  1598. * shared rear/line-in
  1599. */
  1600. if (rear_switch) {
  1601. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_rear_shared, chip))) < 0)
  1602. return err;
  1603. }
  1604. /* per-voice volume */
  1605. substream = chip->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
  1606. for (idx = 0; idx < 32; ++idx) {
  1607. kctl = snd_ctl_new1(&snd_ymfpci_pcm_volume, chip);
  1608. if (!kctl)
  1609. return -ENOMEM;
  1610. kctl->id.device = chip->pcm->device;
  1611. kctl->id.subdevice = idx;
  1612. kctl->private_value = (unsigned long)substream;
  1613. if ((err = snd_ctl_add(chip->card, kctl)) < 0)
  1614. return err;
  1615. chip->pcm_mixer[idx].left = 0x8000;
  1616. chip->pcm_mixer[idx].right = 0x8000;
  1617. chip->pcm_mixer[idx].ctl = kctl;
  1618. substream = substream->next;
  1619. }
  1620. return 0;
  1621. }
  1622. /*
  1623. * timer
  1624. */
  1625. static int snd_ymfpci_timer_start(struct snd_timer *timer)
  1626. {
  1627. struct snd_ymfpci *chip;
  1628. unsigned long flags;
  1629. unsigned int count;
  1630. chip = snd_timer_chip(timer);
  1631. count = (timer->sticks << 1) - 1;
  1632. spin_lock_irqsave(&chip->reg_lock, flags);
  1633. snd_ymfpci_writew(chip, YDSXGR_TIMERCOUNT, count);
  1634. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x03);
  1635. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1636. return 0;
  1637. }
  1638. static int snd_ymfpci_timer_stop(struct snd_timer *timer)
  1639. {
  1640. struct snd_ymfpci *chip;
  1641. unsigned long flags;
  1642. chip = snd_timer_chip(timer);
  1643. spin_lock_irqsave(&chip->reg_lock, flags);
  1644. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x00);
  1645. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1646. return 0;
  1647. }
  1648. static int snd_ymfpci_timer_precise_resolution(struct snd_timer *timer,
  1649. unsigned long *num, unsigned long *den)
  1650. {
  1651. *num = 1;
  1652. *den = 48000;
  1653. return 0;
  1654. }
  1655. static struct snd_timer_hardware snd_ymfpci_timer_hw = {
  1656. .flags = SNDRV_TIMER_HW_AUTO,
  1657. .resolution = 20833, /* 1/fs = 20.8333...us */
  1658. .ticks = 0x8000,
  1659. .start = snd_ymfpci_timer_start,
  1660. .stop = snd_ymfpci_timer_stop,
  1661. .precise_resolution = snd_ymfpci_timer_precise_resolution,
  1662. };
  1663. int __devinit snd_ymfpci_timer(struct snd_ymfpci *chip, int device)
  1664. {
  1665. struct snd_timer *timer = NULL;
  1666. struct snd_timer_id tid;
  1667. int err;
  1668. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1669. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1670. tid.card = chip->card->number;
  1671. tid.device = device;
  1672. tid.subdevice = 0;
  1673. if ((err = snd_timer_new(chip->card, "YMFPCI", &tid, &timer)) >= 0) {
  1674. strcpy(timer->name, "YMFPCI timer");
  1675. timer->private_data = chip;
  1676. timer->hw = snd_ymfpci_timer_hw;
  1677. }
  1678. chip->timer = timer;
  1679. return err;
  1680. }
  1681. /*
  1682. * proc interface
  1683. */
  1684. static void snd_ymfpci_proc_read(struct snd_info_entry *entry,
  1685. struct snd_info_buffer *buffer)
  1686. {
  1687. struct snd_ymfpci *chip = entry->private_data;
  1688. int i;
  1689. snd_iprintf(buffer, "YMFPCI\n\n");
  1690. for (i = 0; i <= YDSXGR_WORKBASE; i += 4)
  1691. snd_iprintf(buffer, "%04x: %04x\n", i, snd_ymfpci_readl(chip, i));
  1692. }
  1693. static int __devinit snd_ymfpci_proc_init(struct snd_card *card, struct snd_ymfpci *chip)
  1694. {
  1695. struct snd_info_entry *entry;
  1696. if (! snd_card_proc_new(card, "ymfpci", &entry))
  1697. snd_info_set_text_ops(entry, chip, snd_ymfpci_proc_read);
  1698. return 0;
  1699. }
  1700. /*
  1701. * initialization routines
  1702. */
  1703. static void snd_ymfpci_aclink_reset(struct pci_dev * pci)
  1704. {
  1705. u8 cmd;
  1706. pci_read_config_byte(pci, PCIR_DSXG_CTRL, &cmd);
  1707. #if 0 // force to reset
  1708. if (cmd & 0x03) {
  1709. #endif
  1710. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1711. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd | 0x03);
  1712. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1713. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL1, 0);
  1714. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL2, 0);
  1715. #if 0
  1716. }
  1717. #endif
  1718. }
  1719. static void snd_ymfpci_enable_dsp(struct snd_ymfpci *chip)
  1720. {
  1721. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000001);
  1722. }
  1723. static void snd_ymfpci_disable_dsp(struct snd_ymfpci *chip)
  1724. {
  1725. u32 val;
  1726. int timeout = 1000;
  1727. val = snd_ymfpci_readl(chip, YDSXGR_CONFIG);
  1728. if (val)
  1729. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000000);
  1730. while (timeout-- > 0) {
  1731. val = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  1732. if ((val & 0x00000002) == 0)
  1733. break;
  1734. }
  1735. }
  1736. #include "ymfpci_image.h"
  1737. static void snd_ymfpci_download_image(struct snd_ymfpci *chip)
  1738. {
  1739. int i;
  1740. u16 ctrl;
  1741. unsigned long *inst;
  1742. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x00000000);
  1743. snd_ymfpci_disable_dsp(chip);
  1744. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00010000);
  1745. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00000000);
  1746. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, 0x00000000);
  1747. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT, 0x00000000);
  1748. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0x00000000);
  1749. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0x00000000);
  1750. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0x00000000);
  1751. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1752. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1753. /* setup DSP instruction code */
  1754. for (i = 0; i < YDSXG_DSPLENGTH / 4; i++)
  1755. snd_ymfpci_writel(chip, YDSXGR_DSPINSTRAM + (i << 2), DspInst[i]);
  1756. /* setup control instruction code */
  1757. switch (chip->device_id) {
  1758. case PCI_DEVICE_ID_YAMAHA_724F:
  1759. case PCI_DEVICE_ID_YAMAHA_740C:
  1760. case PCI_DEVICE_ID_YAMAHA_744:
  1761. case PCI_DEVICE_ID_YAMAHA_754:
  1762. inst = CntrlInst1E;
  1763. break;
  1764. default:
  1765. inst = CntrlInst;
  1766. break;
  1767. }
  1768. for (i = 0; i < YDSXG_CTRLLENGTH / 4; i++)
  1769. snd_ymfpci_writel(chip, YDSXGR_CTRLINSTRAM + (i << 2), inst[i]);
  1770. snd_ymfpci_enable_dsp(chip);
  1771. }
  1772. static int __devinit snd_ymfpci_memalloc(struct snd_ymfpci *chip)
  1773. {
  1774. long size, playback_ctrl_size;
  1775. int voice, bank, reg;
  1776. u8 *ptr;
  1777. dma_addr_t ptr_addr;
  1778. playback_ctrl_size = 4 + 4 * YDSXG_PLAYBACK_VOICES;
  1779. chip->bank_size_playback = snd_ymfpci_readl(chip, YDSXGR_PLAYCTRLSIZE) << 2;
  1780. chip->bank_size_capture = snd_ymfpci_readl(chip, YDSXGR_RECCTRLSIZE) << 2;
  1781. chip->bank_size_effect = snd_ymfpci_readl(chip, YDSXGR_EFFCTRLSIZE) << 2;
  1782. chip->work_size = YDSXG_DEFAULT_WORK_SIZE;
  1783. size = ALIGN(playback_ctrl_size, 0x100) +
  1784. ALIGN(chip->bank_size_playback * 2 * YDSXG_PLAYBACK_VOICES, 0x100) +
  1785. ALIGN(chip->bank_size_capture * 2 * YDSXG_CAPTURE_VOICES, 0x100) +
  1786. ALIGN(chip->bank_size_effect * 2 * YDSXG_EFFECT_VOICES, 0x100) +
  1787. chip->work_size;
  1788. /* work_ptr must be aligned to 256 bytes, but it's already
  1789. covered with the kernel page allocation mechanism */
  1790. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  1791. size, &chip->work_ptr) < 0)
  1792. return -ENOMEM;
  1793. ptr = chip->work_ptr.area;
  1794. ptr_addr = chip->work_ptr.addr;
  1795. memset(ptr, 0, size); /* for sure */
  1796. chip->bank_base_playback = ptr;
  1797. chip->bank_base_playback_addr = ptr_addr;
  1798. chip->ctrl_playback = (u32 *)ptr;
  1799. chip->ctrl_playback[0] = cpu_to_le32(YDSXG_PLAYBACK_VOICES);
  1800. ptr += ALIGN(playback_ctrl_size, 0x100);
  1801. ptr_addr += ALIGN(playback_ctrl_size, 0x100);
  1802. for (voice = 0; voice < YDSXG_PLAYBACK_VOICES; voice++) {
  1803. chip->voices[voice].number = voice;
  1804. chip->voices[voice].bank = (struct snd_ymfpci_playback_bank *)ptr;
  1805. chip->voices[voice].bank_addr = ptr_addr;
  1806. for (bank = 0; bank < 2; bank++) {
  1807. chip->bank_playback[voice][bank] = (struct snd_ymfpci_playback_bank *)ptr;
  1808. ptr += chip->bank_size_playback;
  1809. ptr_addr += chip->bank_size_playback;
  1810. }
  1811. }
  1812. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1813. ptr_addr = ALIGN(ptr_addr, 0x100);
  1814. chip->bank_base_capture = ptr;
  1815. chip->bank_base_capture_addr = ptr_addr;
  1816. for (voice = 0; voice < YDSXG_CAPTURE_VOICES; voice++)
  1817. for (bank = 0; bank < 2; bank++) {
  1818. chip->bank_capture[voice][bank] = (struct snd_ymfpci_capture_bank *)ptr;
  1819. ptr += chip->bank_size_capture;
  1820. ptr_addr += chip->bank_size_capture;
  1821. }
  1822. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1823. ptr_addr = ALIGN(ptr_addr, 0x100);
  1824. chip->bank_base_effect = ptr;
  1825. chip->bank_base_effect_addr = ptr_addr;
  1826. for (voice = 0; voice < YDSXG_EFFECT_VOICES; voice++)
  1827. for (bank = 0; bank < 2; bank++) {
  1828. chip->bank_effect[voice][bank] = (struct snd_ymfpci_effect_bank *)ptr;
  1829. ptr += chip->bank_size_effect;
  1830. ptr_addr += chip->bank_size_effect;
  1831. }
  1832. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1833. ptr_addr = ALIGN(ptr_addr, 0x100);
  1834. chip->work_base = ptr;
  1835. chip->work_base_addr = ptr_addr;
  1836. snd_assert(ptr + chip->work_size == chip->work_ptr.area + chip->work_ptr.bytes, );
  1837. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, chip->bank_base_playback_addr);
  1838. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, chip->bank_base_capture_addr);
  1839. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, chip->bank_base_effect_addr);
  1840. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, chip->work_base_addr);
  1841. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, chip->work_size >> 2);
  1842. /* S/PDIF output initialization */
  1843. chip->spdif_bits = chip->spdif_pcm_bits = SNDRV_PCM_DEFAULT_CON_SPDIF & 0xffff;
  1844. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL, 0);
  1845. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1846. /* S/PDIF input initialization */
  1847. snd_ymfpci_writew(chip, YDSXGR_SPDIFINCTRL, 0);
  1848. /* digital mixer setup */
  1849. for (reg = 0x80; reg < 0xc0; reg += 4)
  1850. snd_ymfpci_writel(chip, reg, 0);
  1851. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x3fff3fff);
  1852. snd_ymfpci_writel(chip, YDSXGR_ZVOUTVOL, 0x3fff3fff);
  1853. snd_ymfpci_writel(chip, YDSXGR_SPDIFOUTVOL, 0x3fff3fff);
  1854. snd_ymfpci_writel(chip, YDSXGR_NATIVEADCINVOL, 0x3fff3fff);
  1855. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACINVOL, 0x3fff3fff);
  1856. snd_ymfpci_writel(chip, YDSXGR_PRIADCLOOPVOL, 0x3fff3fff);
  1857. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0x3fff3fff);
  1858. return 0;
  1859. }
  1860. static int snd_ymfpci_free(struct snd_ymfpci *chip)
  1861. {
  1862. u16 ctrl;
  1863. snd_assert(chip != NULL, return -EINVAL);
  1864. if (chip->res_reg_area) { /* don't touch busy hardware */
  1865. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  1866. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0);
  1867. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0);
  1868. snd_ymfpci_writel(chip, YDSXGR_STATUS, ~0);
  1869. snd_ymfpci_disable_dsp(chip);
  1870. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0);
  1871. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0);
  1872. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0);
  1873. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, 0);
  1874. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, 0);
  1875. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1876. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1877. }
  1878. snd_ymfpci_ac3_done(chip);
  1879. /* Set PCI device to D3 state */
  1880. #if 0
  1881. /* FIXME: temporarily disabled, otherwise we cannot fire up
  1882. * the chip again unless reboot. ACPI bug?
  1883. */
  1884. pci_set_power_state(chip->pci, 3);
  1885. #endif
  1886. #ifdef CONFIG_PM
  1887. vfree(chip->saved_regs);
  1888. #endif
  1889. release_and_free_resource(chip->mpu_res);
  1890. release_and_free_resource(chip->fm_res);
  1891. snd_ymfpci_free_gameport(chip);
  1892. if (chip->reg_area_virt)
  1893. iounmap(chip->reg_area_virt);
  1894. if (chip->work_ptr.area)
  1895. snd_dma_free_pages(&chip->work_ptr);
  1896. if (chip->irq >= 0)
  1897. free_irq(chip->irq, chip);
  1898. release_and_free_resource(chip->res_reg_area);
  1899. pci_write_config_word(chip->pci, 0x40, chip->old_legacy_ctrl);
  1900. pci_disable_device(chip->pci);
  1901. kfree(chip);
  1902. return 0;
  1903. }
  1904. static int snd_ymfpci_dev_free(struct snd_device *device)
  1905. {
  1906. struct snd_ymfpci *chip = device->device_data;
  1907. return snd_ymfpci_free(chip);
  1908. }
  1909. #ifdef CONFIG_PM
  1910. static int saved_regs_index[] = {
  1911. /* spdif */
  1912. YDSXGR_SPDIFOUTCTRL,
  1913. YDSXGR_SPDIFOUTSTATUS,
  1914. YDSXGR_SPDIFINCTRL,
  1915. /* volumes */
  1916. YDSXGR_PRIADCLOOPVOL,
  1917. YDSXGR_NATIVEDACINVOL,
  1918. YDSXGR_NATIVEDACOUTVOL,
  1919. // YDSXGR_BUF441OUTVOL,
  1920. YDSXGR_NATIVEADCINVOL,
  1921. YDSXGR_SPDIFLOOPVOL,
  1922. YDSXGR_SPDIFOUTVOL,
  1923. YDSXGR_ZVOUTVOL,
  1924. YDSXGR_LEGACYOUTVOL,
  1925. /* address bases */
  1926. YDSXGR_PLAYCTRLBASE,
  1927. YDSXGR_RECCTRLBASE,
  1928. YDSXGR_EFFCTRLBASE,
  1929. YDSXGR_WORKBASE,
  1930. /* capture set up */
  1931. YDSXGR_MAPOFREC,
  1932. YDSXGR_RECFORMAT,
  1933. YDSXGR_RECSLOTSR,
  1934. YDSXGR_ADCFORMAT,
  1935. YDSXGR_ADCSLOTSR,
  1936. };
  1937. #define YDSXGR_NUM_SAVED_REGS ARRAY_SIZE(saved_regs_index)
  1938. int snd_ymfpci_suspend(struct pci_dev *pci, pm_message_t state)
  1939. {
  1940. struct snd_card *card = pci_get_drvdata(pci);
  1941. struct snd_ymfpci *chip = card->private_data;
  1942. unsigned int i;
  1943. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  1944. snd_pcm_suspend_all(chip->pcm);
  1945. snd_pcm_suspend_all(chip->pcm2);
  1946. snd_pcm_suspend_all(chip->pcm_spdif);
  1947. snd_pcm_suspend_all(chip->pcm_4ch);
  1948. snd_ac97_suspend(chip->ac97);
  1949. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  1950. chip->saved_regs[i] = snd_ymfpci_readl(chip, saved_regs_index[i]);
  1951. chip->saved_ydsxgr_mode = snd_ymfpci_readl(chip, YDSXGR_MODE);
  1952. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  1953. snd_ymfpci_disable_dsp(chip);
  1954. pci_disable_device(pci);
  1955. pci_save_state(pci);
  1956. pci_set_power_state(pci, pci_choose_state(pci, state));
  1957. return 0;
  1958. }
  1959. int snd_ymfpci_resume(struct pci_dev *pci)
  1960. {
  1961. struct snd_card *card = pci_get_drvdata(pci);
  1962. struct snd_ymfpci *chip = card->private_data;
  1963. unsigned int i;
  1964. pci_set_power_state(pci, PCI_D0);
  1965. pci_restore_state(pci);
  1966. if (pci_enable_device(pci) < 0) {
  1967. printk(KERN_ERR "ymfpci: pci_enable_device failed, "
  1968. "disabling device\n");
  1969. snd_card_disconnect(card);
  1970. return -EIO;
  1971. }
  1972. pci_set_master(pci);
  1973. snd_ymfpci_aclink_reset(pci);
  1974. snd_ymfpci_codec_ready(chip, 0);
  1975. snd_ymfpci_download_image(chip);
  1976. udelay(100);
  1977. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  1978. snd_ymfpci_writel(chip, saved_regs_index[i], chip->saved_regs[i]);
  1979. snd_ac97_resume(chip->ac97);
  1980. /* start hw again */
  1981. if (chip->start_count > 0) {
  1982. spin_lock_irq(&chip->reg_lock);
  1983. snd_ymfpci_writel(chip, YDSXGR_MODE, chip->saved_ydsxgr_mode);
  1984. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT);
  1985. spin_unlock_irq(&chip->reg_lock);
  1986. }
  1987. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  1988. return 0;
  1989. }
  1990. #endif /* CONFIG_PM */
  1991. int __devinit snd_ymfpci_create(struct snd_card *card,
  1992. struct pci_dev * pci,
  1993. unsigned short old_legacy_ctrl,
  1994. struct snd_ymfpci ** rchip)
  1995. {
  1996. struct snd_ymfpci *chip;
  1997. int err;
  1998. static struct snd_device_ops ops = {
  1999. .dev_free = snd_ymfpci_dev_free,
  2000. };
  2001. *rchip = NULL;
  2002. /* enable PCI device */
  2003. if ((err = pci_enable_device(pci)) < 0)
  2004. return err;
  2005. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  2006. if (chip == NULL) {
  2007. pci_disable_device(pci);
  2008. return -ENOMEM;
  2009. }
  2010. chip->old_legacy_ctrl = old_legacy_ctrl;
  2011. spin_lock_init(&chip->reg_lock);
  2012. spin_lock_init(&chip->voice_lock);
  2013. init_waitqueue_head(&chip->interrupt_sleep);
  2014. atomic_set(&chip->interrupt_sleep_count, 0);
  2015. chip->card = card;
  2016. chip->pci = pci;
  2017. chip->irq = -1;
  2018. chip->device_id = pci->device;
  2019. pci_read_config_byte(pci, PCI_REVISION_ID, &chip->rev);
  2020. chip->reg_area_phys = pci_resource_start(pci, 0);
  2021. chip->reg_area_virt = ioremap_nocache(chip->reg_area_phys, 0x8000);
  2022. pci_set_master(pci);
  2023. if ((chip->res_reg_area = request_mem_region(chip->reg_area_phys, 0x8000, "YMFPCI")) == NULL) {
  2024. snd_printk(KERN_ERR "unable to grab memory region 0x%lx-0x%lx\n", chip->reg_area_phys, chip->reg_area_phys + 0x8000 - 1);
  2025. snd_ymfpci_free(chip);
  2026. return -EBUSY;
  2027. }
  2028. if (request_irq(pci->irq, snd_ymfpci_interrupt, IRQF_SHARED,
  2029. "YMFPCI", chip)) {
  2030. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  2031. snd_ymfpci_free(chip);
  2032. return -EBUSY;
  2033. }
  2034. chip->irq = pci->irq;
  2035. snd_ymfpci_aclink_reset(pci);
  2036. if (snd_ymfpci_codec_ready(chip, 0) < 0) {
  2037. snd_ymfpci_free(chip);
  2038. return -EIO;
  2039. }
  2040. snd_ymfpci_download_image(chip);
  2041. udelay(100); /* seems we need a delay after downloading image.. */
  2042. if (snd_ymfpci_memalloc(chip) < 0) {
  2043. snd_ymfpci_free(chip);
  2044. return -EIO;
  2045. }
  2046. if ((err = snd_ymfpci_ac3_init(chip)) < 0) {
  2047. snd_ymfpci_free(chip);
  2048. return err;
  2049. }
  2050. #ifdef CONFIG_PM
  2051. chip->saved_regs = vmalloc(YDSXGR_NUM_SAVED_REGS * sizeof(u32));
  2052. if (chip->saved_regs == NULL) {
  2053. snd_ymfpci_free(chip);
  2054. return -ENOMEM;
  2055. }
  2056. #endif
  2057. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  2058. snd_ymfpci_free(chip);
  2059. return err;
  2060. }
  2061. snd_ymfpci_proc_init(card, chip);
  2062. snd_card_set_dev(card, &pci->dev);
  2063. *rchip = chip;
  2064. return 0;
  2065. }