longhaul.c 21 KB

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  1. /*
  2. * (C) 2001-2004 Dave Jones. <davej@codemonkey.org.uk>
  3. * (C) 2002 Padraig Brady. <padraig@antefacto.com>
  4. *
  5. * Licensed under the terms of the GNU GPL License version 2.
  6. * Based upon datasheets & sample CPUs kindly provided by VIA.
  7. *
  8. * VIA have currently 3 different versions of Longhaul.
  9. * Version 1 (Longhaul) uses the BCR2 MSR at 0x1147.
  10. * It is present only in Samuel 1 (C5A), Samuel 2 (C5B) stepping 0.
  11. * Version 2 of longhaul is the same as v1, but adds voltage scaling.
  12. * Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C)
  13. * voltage scaling support has currently been disabled in this driver
  14. * until we have code that gets it right.
  15. * Version 3 of longhaul got renamed to Powersaver and redesigned
  16. * to use the POWERSAVER MSR at 0x110a.
  17. * It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
  18. * It's pretty much the same feature wise to longhaul v2, though
  19. * there is provision for scaling FSB too, but this doesn't work
  20. * too well in practice so we don't even try to use this.
  21. *
  22. * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
  23. */
  24. #include <linux/kernel.h>
  25. #include <linux/module.h>
  26. #include <linux/moduleparam.h>
  27. #include <linux/init.h>
  28. #include <linux/cpufreq.h>
  29. #include <linux/pci.h>
  30. #include <linux/slab.h>
  31. #include <linux/string.h>
  32. #include <asm/msr.h>
  33. #include <asm/timex.h>
  34. #include <asm/io.h>
  35. #include <asm/acpi.h>
  36. #include <linux/acpi.h>
  37. #include <acpi/processor.h>
  38. #include "longhaul.h"
  39. #define PFX "longhaul: "
  40. #define TYPE_LONGHAUL_V1 1
  41. #define TYPE_LONGHAUL_V2 2
  42. #define TYPE_POWERSAVER 3
  43. #define CPU_SAMUEL 1
  44. #define CPU_SAMUEL2 2
  45. #define CPU_EZRA 3
  46. #define CPU_EZRA_T 4
  47. #define CPU_NEHEMIAH 5
  48. /* Flags */
  49. #define USE_ACPI_C3 (1 << 1)
  50. #define USE_NORTHBRIDGE (1 << 2)
  51. static int cpu_model;
  52. static unsigned int numscales=16;
  53. static unsigned int fsb;
  54. static struct mV_pos *vrm_mV_table;
  55. static unsigned char *mV_vrm_table;
  56. struct f_msr {
  57. unsigned char vrm;
  58. };
  59. static struct f_msr f_msr_table[32];
  60. static unsigned int highest_speed, lowest_speed; /* kHz */
  61. static unsigned int minmult, maxmult;
  62. static int can_scale_voltage;
  63. static struct acpi_processor *pr = NULL;
  64. static struct acpi_processor_cx *cx = NULL;
  65. static u8 longhaul_flags;
  66. /* Module parameters */
  67. static int scale_voltage;
  68. static int ignore_latency;
  69. #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "longhaul", msg)
  70. /* Clock ratios multiplied by 10 */
  71. static int clock_ratio[32];
  72. static int eblcr_table[32];
  73. static int longhaul_version;
  74. static struct cpufreq_frequency_table *longhaul_table;
  75. #ifdef CONFIG_CPU_FREQ_DEBUG
  76. static char speedbuffer[8];
  77. static char *print_speed(int speed)
  78. {
  79. if (speed < 1000) {
  80. snprintf(speedbuffer, sizeof(speedbuffer),"%dMHz", speed);
  81. return speedbuffer;
  82. }
  83. if (speed%1000 == 0)
  84. snprintf(speedbuffer, sizeof(speedbuffer),
  85. "%dGHz", speed/1000);
  86. else
  87. snprintf(speedbuffer, sizeof(speedbuffer),
  88. "%d.%dGHz", speed/1000, (speed%1000)/100);
  89. return speedbuffer;
  90. }
  91. #endif
  92. static unsigned int calc_speed(int mult)
  93. {
  94. int khz;
  95. khz = (mult/10)*fsb;
  96. if (mult%10)
  97. khz += fsb/2;
  98. khz *= 1000;
  99. return khz;
  100. }
  101. static int longhaul_get_cpu_mult(void)
  102. {
  103. unsigned long invalue=0,lo, hi;
  104. rdmsr (MSR_IA32_EBL_CR_POWERON, lo, hi);
  105. invalue = (lo & (1<<22|1<<23|1<<24|1<<25)) >>22;
  106. if (longhaul_version==TYPE_LONGHAUL_V2 || longhaul_version==TYPE_POWERSAVER) {
  107. if (lo & (1<<27))
  108. invalue+=16;
  109. }
  110. return eblcr_table[invalue];
  111. }
  112. /* For processor with BCR2 MSR */
  113. static void do_longhaul1(unsigned int clock_ratio_index)
  114. {
  115. union msr_bcr2 bcr2;
  116. rdmsrl(MSR_VIA_BCR2, bcr2.val);
  117. /* Enable software clock multiplier */
  118. bcr2.bits.ESOFTBF = 1;
  119. bcr2.bits.CLOCKMUL = clock_ratio_index;
  120. /* Sync to timer tick */
  121. safe_halt();
  122. /* Change frequency on next halt or sleep */
  123. wrmsrl(MSR_VIA_BCR2, bcr2.val);
  124. /* Invoke transition */
  125. ACPI_FLUSH_CPU_CACHE();
  126. halt();
  127. /* Disable software clock multiplier */
  128. local_irq_disable();
  129. rdmsrl(MSR_VIA_BCR2, bcr2.val);
  130. bcr2.bits.ESOFTBF = 0;
  131. wrmsrl(MSR_VIA_BCR2, bcr2.val);
  132. }
  133. /* For processor with Longhaul MSR */
  134. static void do_powersaver(int cx_address, unsigned int clock_ratio_index)
  135. {
  136. union msr_longhaul longhaul;
  137. u32 t;
  138. rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
  139. longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
  140. longhaul.bits.SoftBusRatio = clock_ratio_index & 0xf;
  141. longhaul.bits.SoftBusRatio4 = (clock_ratio_index & 0x10) >> 4;
  142. longhaul.bits.EnableSoftBusRatio = 1;
  143. if (can_scale_voltage) {
  144. longhaul.bits.SoftVID = f_msr_table[clock_ratio_index].vrm;
  145. longhaul.bits.EnableSoftVID = 1;
  146. }
  147. /* Sync to timer tick */
  148. safe_halt();
  149. /* Change frequency on next halt or sleep */
  150. wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
  151. if (!cx_address) {
  152. ACPI_FLUSH_CPU_CACHE();
  153. /* Invoke C1 */
  154. halt();
  155. } else {
  156. ACPI_FLUSH_CPU_CACHE();
  157. /* Invoke C3 */
  158. inb(cx_address);
  159. /* Dummy op - must do something useless after P_LVL3 read */
  160. t = inl(acpi_fadt.xpm_tmr_blk.address);
  161. }
  162. /* Disable bus ratio bit */
  163. local_irq_disable();
  164. longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
  165. longhaul.bits.EnableSoftBusRatio = 0;
  166. longhaul.bits.EnableSoftBSEL = 0;
  167. longhaul.bits.EnableSoftVID = 0;
  168. wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
  169. }
  170. /**
  171. * longhaul_set_cpu_frequency()
  172. * @clock_ratio_index : bitpattern of the new multiplier.
  173. *
  174. * Sets a new clock ratio.
  175. */
  176. static void longhaul_setstate(unsigned int clock_ratio_index)
  177. {
  178. int speed, mult;
  179. struct cpufreq_freqs freqs;
  180. static unsigned int old_ratio=-1;
  181. unsigned long flags;
  182. unsigned int pic1_mask, pic2_mask;
  183. if (old_ratio == clock_ratio_index)
  184. return;
  185. old_ratio = clock_ratio_index;
  186. mult = clock_ratio[clock_ratio_index];
  187. if (mult == -1)
  188. return;
  189. speed = calc_speed(mult);
  190. if ((speed > highest_speed) || (speed < lowest_speed))
  191. return;
  192. freqs.old = calc_speed(longhaul_get_cpu_mult());
  193. freqs.new = speed;
  194. freqs.cpu = 0; /* longhaul.c is UP only driver */
  195. cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
  196. dprintk ("Setting to FSB:%dMHz Mult:%d.%dx (%s)\n",
  197. fsb, mult/10, mult%10, print_speed(speed/1000));
  198. preempt_disable();
  199. local_irq_save(flags);
  200. pic2_mask = inb(0xA1);
  201. pic1_mask = inb(0x21); /* works on C3. save mask. */
  202. outb(0xFF,0xA1); /* Overkill */
  203. outb(0xFE,0x21); /* TMR0 only */
  204. if (longhaul_flags & USE_NORTHBRIDGE) {
  205. /* Disable AGP and PCI arbiters */
  206. outb(3, 0x22);
  207. } else if ((pr != NULL) && pr->flags.bm_control) {
  208. /* Disable bus master arbitration */
  209. acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1,
  210. ACPI_MTX_DO_NOT_LOCK);
  211. }
  212. switch (longhaul_version) {
  213. /*
  214. * Longhaul v1. (Samuel[C5A] and Samuel2 stepping 0[C5B])
  215. * Software controlled multipliers only.
  216. *
  217. * *NB* Until we get voltage scaling working v1 & v2 are the same code.
  218. * Longhaul v2 appears in Samuel2 Steppings 1->7 [C5b] and Ezra [C5C]
  219. */
  220. case TYPE_LONGHAUL_V1:
  221. case TYPE_LONGHAUL_V2:
  222. do_longhaul1(clock_ratio_index);
  223. break;
  224. /*
  225. * Longhaul v3 (aka Powersaver). (Ezra-T [C5M] & Nehemiah [C5N])
  226. * We can scale voltage with this too, but that's currently
  227. * disabled until we come up with a decent 'match freq to voltage'
  228. * algorithm.
  229. * When we add voltage scaling, we will also need to do the
  230. * voltage/freq setting in order depending on the direction
  231. * of scaling (like we do in powernow-k7.c)
  232. * Nehemiah can do FSB scaling too, but this has never been proven
  233. * to work in practice.
  234. */
  235. case TYPE_POWERSAVER:
  236. if (longhaul_flags & USE_ACPI_C3) {
  237. /* Don't allow wakeup */
  238. acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0,
  239. ACPI_MTX_DO_NOT_LOCK);
  240. do_powersaver(cx->address, clock_ratio_index);
  241. } else {
  242. do_powersaver(0, clock_ratio_index);
  243. }
  244. break;
  245. }
  246. if (longhaul_flags & USE_NORTHBRIDGE) {
  247. /* Enable arbiters */
  248. outb(0, 0x22);
  249. } else if ((pr != NULL) && pr->flags.bm_control) {
  250. /* Enable bus master arbitration */
  251. acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0,
  252. ACPI_MTX_DO_NOT_LOCK);
  253. }
  254. outb(pic2_mask,0xA1); /* restore mask */
  255. outb(pic1_mask,0x21);
  256. local_irq_restore(flags);
  257. preempt_enable();
  258. cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
  259. }
  260. /*
  261. * Centaur decided to make life a little more tricky.
  262. * Only longhaul v1 is allowed to read EBLCR BSEL[0:1].
  263. * Samuel2 and above have to try and guess what the FSB is.
  264. * We do this by assuming we booted at maximum multiplier, and interpolate
  265. * between that value multiplied by possible FSBs and cpu_mhz which
  266. * was calculated at boot time. Really ugly, but no other way to do this.
  267. */
  268. #define ROUNDING 0xf
  269. static int _guess(int guess, int mult)
  270. {
  271. int target;
  272. target = ((mult/10)*guess);
  273. if (mult%10 != 0)
  274. target += (guess/2);
  275. target += ROUNDING/2;
  276. target &= ~ROUNDING;
  277. return target;
  278. }
  279. static int guess_fsb(int mult)
  280. {
  281. int speed = (cpu_khz/1000);
  282. int i;
  283. int speeds[] = { 66, 100, 133, 200 };
  284. speed += ROUNDING/2;
  285. speed &= ~ROUNDING;
  286. for (i=0; i<4; i++) {
  287. if (_guess(speeds[i], mult) == speed)
  288. return speeds[i];
  289. }
  290. return 0;
  291. }
  292. static int __init longhaul_get_ranges(void)
  293. {
  294. unsigned long invalue;
  295. unsigned int ezra_t_multipliers[32]= {
  296. 90, 30, 40, 100, 55, 35, 45, 95,
  297. 50, 70, 80, 60, 120, 75, 85, 65,
  298. -1, 110, 120, -1, 135, 115, 125, 105,
  299. 130, 150, 160, 140, -1, 155, -1, 145 };
  300. unsigned int j, k = 0;
  301. union msr_longhaul longhaul;
  302. int mult = 0;
  303. switch (longhaul_version) {
  304. case TYPE_LONGHAUL_V1:
  305. case TYPE_LONGHAUL_V2:
  306. /* Ugh, Longhaul v1 didn't have the min/max MSRs.
  307. Assume min=3.0x & max = whatever we booted at. */
  308. minmult = 30;
  309. maxmult = mult = longhaul_get_cpu_mult();
  310. break;
  311. case TYPE_POWERSAVER:
  312. /* Ezra-T */
  313. if (cpu_model==CPU_EZRA_T) {
  314. minmult = 30;
  315. rdmsrl (MSR_VIA_LONGHAUL, longhaul.val);
  316. invalue = longhaul.bits.MaxMHzBR;
  317. if (longhaul.bits.MaxMHzBR4)
  318. invalue += 16;
  319. maxmult = mult = ezra_t_multipliers[invalue];
  320. break;
  321. }
  322. /* Nehemiah */
  323. if (cpu_model==CPU_NEHEMIAH) {
  324. rdmsrl (MSR_VIA_LONGHAUL, longhaul.val);
  325. /*
  326. * TODO: This code works, but raises a lot of questions.
  327. * - Some Nehemiah's seem to have broken Min/MaxMHzBR's.
  328. * We get around this by using a hardcoded multiplier of 4.0x
  329. * for the minimimum speed, and the speed we booted up at for the max.
  330. * This is done in longhaul_get_cpu_mult() by reading the EBLCR register.
  331. * - According to some VIA documentation EBLCR is only
  332. * in pre-Nehemiah C3s. How this still works is a mystery.
  333. * We're possibly using something undocumented and unsupported,
  334. * But it works, so we don't grumble.
  335. */
  336. minmult=40;
  337. maxmult = mult = longhaul_get_cpu_mult();
  338. break;
  339. }
  340. }
  341. fsb = guess_fsb(mult);
  342. dprintk ("MinMult:%d.%dx MaxMult:%d.%dx\n",
  343. minmult/10, minmult%10, maxmult/10, maxmult%10);
  344. if (fsb == 0) {
  345. printk (KERN_INFO PFX "Invalid (reserved) FSB!\n");
  346. return -EINVAL;
  347. }
  348. highest_speed = calc_speed(maxmult);
  349. lowest_speed = calc_speed(minmult);
  350. dprintk ("FSB:%dMHz Lowest speed: %s Highest speed:%s\n", fsb,
  351. print_speed(lowest_speed/1000),
  352. print_speed(highest_speed/1000));
  353. if (lowest_speed == highest_speed) {
  354. printk (KERN_INFO PFX "highestspeed == lowest, aborting.\n");
  355. return -EINVAL;
  356. }
  357. if (lowest_speed > highest_speed) {
  358. printk (KERN_INFO PFX "nonsense! lowest (%d > %d) !\n",
  359. lowest_speed, highest_speed);
  360. return -EINVAL;
  361. }
  362. longhaul_table = kmalloc((numscales + 1) * sizeof(struct cpufreq_frequency_table), GFP_KERNEL);
  363. if(!longhaul_table)
  364. return -ENOMEM;
  365. for (j=0; j < numscales; j++) {
  366. unsigned int ratio;
  367. ratio = clock_ratio[j];
  368. if (ratio == -1)
  369. continue;
  370. if (ratio > maxmult || ratio < minmult)
  371. continue;
  372. longhaul_table[k].frequency = calc_speed(ratio);
  373. longhaul_table[k].index = j;
  374. k++;
  375. }
  376. longhaul_table[k].frequency = CPUFREQ_TABLE_END;
  377. if (!k) {
  378. kfree (longhaul_table);
  379. return -EINVAL;
  380. }
  381. return 0;
  382. }
  383. static void __init longhaul_setup_voltagescaling(void)
  384. {
  385. union msr_longhaul longhaul;
  386. struct mV_pos minvid, maxvid;
  387. unsigned int j, speed, pos, kHz_step, numvscales;
  388. rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
  389. if (!(longhaul.bits.RevisionID & 1)) {
  390. printk(KERN_INFO PFX "Voltage scaling not supported by CPU.\n");
  391. return;
  392. }
  393. if (!longhaul.bits.VRMRev) {
  394. printk (KERN_INFO PFX "VRM 8.5\n");
  395. vrm_mV_table = &vrm85_mV[0];
  396. mV_vrm_table = &mV_vrm85[0];
  397. } else {
  398. printk (KERN_INFO PFX "Mobile VRM\n");
  399. vrm_mV_table = &mobilevrm_mV[0];
  400. mV_vrm_table = &mV_mobilevrm[0];
  401. }
  402. minvid = vrm_mV_table[longhaul.bits.MinimumVID];
  403. maxvid = vrm_mV_table[longhaul.bits.MaximumVID];
  404. numvscales = maxvid.pos - minvid.pos + 1;
  405. kHz_step = (highest_speed - lowest_speed) / numvscales;
  406. if (minvid.mV == 0 || maxvid.mV == 0 || minvid.mV > maxvid.mV) {
  407. printk (KERN_INFO PFX "Bogus values Min:%d.%03d Max:%d.%03d. "
  408. "Voltage scaling disabled.\n",
  409. minvid.mV/1000, minvid.mV%1000, maxvid.mV/1000, maxvid.mV%1000);
  410. return;
  411. }
  412. if (minvid.mV == maxvid.mV) {
  413. printk (KERN_INFO PFX "Claims to support voltage scaling but min & max are "
  414. "both %d.%03d. Voltage scaling disabled\n",
  415. maxvid.mV/1000, maxvid.mV%1000);
  416. return;
  417. }
  418. printk(KERN_INFO PFX "Max VID=%d.%03d Min VID=%d.%03d, %d possible voltage scales\n",
  419. maxvid.mV/1000, maxvid.mV%1000,
  420. minvid.mV/1000, minvid.mV%1000,
  421. numvscales);
  422. j = 0;
  423. while (longhaul_table[j].frequency != CPUFREQ_TABLE_END) {
  424. speed = longhaul_table[j].frequency;
  425. pos = (speed - lowest_speed) / kHz_step + minvid.pos;
  426. f_msr_table[longhaul_table[j].index].vrm = mV_vrm_table[pos];
  427. j++;
  428. }
  429. can_scale_voltage = 1;
  430. }
  431. static int longhaul_verify(struct cpufreq_policy *policy)
  432. {
  433. return cpufreq_frequency_table_verify(policy, longhaul_table);
  434. }
  435. static int longhaul_target(struct cpufreq_policy *policy,
  436. unsigned int target_freq, unsigned int relation)
  437. {
  438. unsigned int table_index = 0;
  439. unsigned int new_clock_ratio = 0;
  440. if (cpufreq_frequency_table_target(policy, longhaul_table, target_freq, relation, &table_index))
  441. return -EINVAL;
  442. new_clock_ratio = longhaul_table[table_index].index & 0xFF;
  443. longhaul_setstate(new_clock_ratio);
  444. return 0;
  445. }
  446. static unsigned int longhaul_get(unsigned int cpu)
  447. {
  448. if (cpu)
  449. return 0;
  450. return calc_speed(longhaul_get_cpu_mult());
  451. }
  452. static acpi_status longhaul_walk_callback(acpi_handle obj_handle,
  453. u32 nesting_level,
  454. void *context, void **return_value)
  455. {
  456. struct acpi_device *d;
  457. if ( acpi_bus_get_device(obj_handle, &d) ) {
  458. return 0;
  459. }
  460. *return_value = (void *)acpi_driver_data(d);
  461. return 1;
  462. }
  463. /* VIA don't support PM2 reg, but have something similar */
  464. static int enable_arbiter_disable(void)
  465. {
  466. struct pci_dev *dev;
  467. int reg;
  468. u8 pci_cmd;
  469. /* Find PLE133 host bridge */
  470. reg = 0x78;
  471. dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8601_0, NULL);
  472. /* Find CLE266 host bridge */
  473. if (dev == NULL) {
  474. reg = 0x76;
  475. dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_862X_0, NULL);
  476. /* Find CN400 V-Link host bridge */
  477. if (dev == NULL)
  478. dev = pci_find_device(PCI_VENDOR_ID_VIA, 0x7259, NULL);
  479. }
  480. if (dev != NULL) {
  481. /* Enable access to port 0x22 */
  482. pci_read_config_byte(dev, reg, &pci_cmd);
  483. if ( !(pci_cmd & 1<<7) ) {
  484. pci_cmd |= 1<<7;
  485. pci_write_config_byte(dev, reg, pci_cmd);
  486. }
  487. return 1;
  488. }
  489. return 0;
  490. }
  491. static int __init longhaul_cpu_init(struct cpufreq_policy *policy)
  492. {
  493. struct cpuinfo_x86 *c = cpu_data;
  494. char *cpuname=NULL;
  495. int ret;
  496. /* Check what we have on this motherboard */
  497. switch (c->x86_model) {
  498. case 6:
  499. cpu_model = CPU_SAMUEL;
  500. cpuname = "C3 'Samuel' [C5A]";
  501. longhaul_version = TYPE_LONGHAUL_V1;
  502. memcpy (clock_ratio, samuel1_clock_ratio, sizeof(samuel1_clock_ratio));
  503. memcpy (eblcr_table, samuel1_eblcr, sizeof(samuel1_eblcr));
  504. break;
  505. case 7:
  506. longhaul_version = TYPE_LONGHAUL_V1;
  507. switch (c->x86_mask) {
  508. case 0:
  509. cpu_model = CPU_SAMUEL2;
  510. cpuname = "C3 'Samuel 2' [C5B]";
  511. /* Note, this is not a typo, early Samuel2's had Samuel1 ratios. */
  512. memcpy (clock_ratio, samuel1_clock_ratio, sizeof(samuel1_clock_ratio));
  513. memcpy (eblcr_table, samuel2_eblcr, sizeof(samuel2_eblcr));
  514. break;
  515. case 1 ... 15:
  516. if (c->x86_mask < 8) {
  517. cpu_model = CPU_SAMUEL2;
  518. cpuname = "C3 'Samuel 2' [C5B]";
  519. } else {
  520. cpu_model = CPU_EZRA;
  521. cpuname = "C3 'Ezra' [C5C]";
  522. }
  523. memcpy (clock_ratio, ezra_clock_ratio, sizeof(ezra_clock_ratio));
  524. memcpy (eblcr_table, ezra_eblcr, sizeof(ezra_eblcr));
  525. break;
  526. }
  527. break;
  528. case 8:
  529. cpu_model = CPU_EZRA_T;
  530. cpuname = "C3 'Ezra-T' [C5M]";
  531. longhaul_version = TYPE_POWERSAVER;
  532. numscales=32;
  533. memcpy (clock_ratio, ezrat_clock_ratio, sizeof(ezrat_clock_ratio));
  534. memcpy (eblcr_table, ezrat_eblcr, sizeof(ezrat_eblcr));
  535. break;
  536. case 9:
  537. cpu_model = CPU_NEHEMIAH;
  538. longhaul_version = TYPE_POWERSAVER;
  539. numscales=32;
  540. switch (c->x86_mask) {
  541. case 0 ... 1:
  542. cpuname = "C3 'Nehemiah A' [C5N]";
  543. memcpy (clock_ratio, nehemiah_a_clock_ratio, sizeof(nehemiah_a_clock_ratio));
  544. memcpy (eblcr_table, nehemiah_a_eblcr, sizeof(nehemiah_a_eblcr));
  545. break;
  546. case 2 ... 4:
  547. cpuname = "C3 'Nehemiah B' [C5N]";
  548. memcpy (clock_ratio, nehemiah_b_clock_ratio, sizeof(nehemiah_b_clock_ratio));
  549. memcpy (eblcr_table, nehemiah_b_eblcr, sizeof(nehemiah_b_eblcr));
  550. break;
  551. case 5 ... 15:
  552. cpuname = "C3 'Nehemiah C' [C5N]";
  553. memcpy (clock_ratio, nehemiah_c_clock_ratio, sizeof(nehemiah_c_clock_ratio));
  554. memcpy (eblcr_table, nehemiah_c_eblcr, sizeof(nehemiah_c_eblcr));
  555. break;
  556. }
  557. break;
  558. default:
  559. cpuname = "Unknown";
  560. break;
  561. }
  562. printk (KERN_INFO PFX "VIA %s CPU detected. ", cpuname);
  563. switch (longhaul_version) {
  564. case TYPE_LONGHAUL_V1:
  565. case TYPE_LONGHAUL_V2:
  566. printk ("Longhaul v%d supported.\n", longhaul_version);
  567. break;
  568. case TYPE_POWERSAVER:
  569. printk ("Powersaver supported.\n");
  570. break;
  571. };
  572. /* Find ACPI data for processor */
  573. acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT, ACPI_UINT32_MAX,
  574. &longhaul_walk_callback, NULL, (void *)&pr);
  575. /* Check ACPI support for C3 state */
  576. if ((pr != NULL) && (longhaul_version == TYPE_POWERSAVER)) {
  577. cx = &pr->power.states[ACPI_STATE_C3];
  578. if (cx->address > 0 &&
  579. (cx->latency <= 1000 || ignore_latency != 0) ) {
  580. longhaul_flags |= USE_ACPI_C3;
  581. goto print_support_type;
  582. }
  583. }
  584. /* Check if northbridge is friendly */
  585. if (enable_arbiter_disable()) {
  586. longhaul_flags |= USE_NORTHBRIDGE;
  587. goto print_support_type;
  588. }
  589. /* No ACPI C3 or we can't use it */
  590. /* Check ACPI support for bus master arbiter disable */
  591. if ((pr == NULL) || !(pr->flags.bm_control)) {
  592. printk(KERN_ERR PFX
  593. "No ACPI support. Unsupported northbridge.\n");
  594. return -ENODEV;
  595. }
  596. print_support_type:
  597. if (!(longhaul_flags & USE_NORTHBRIDGE)) {
  598. printk (KERN_INFO PFX "Using ACPI support.\n");
  599. } else {
  600. printk (KERN_INFO PFX "Using northbridge support.\n");
  601. }
  602. ret = longhaul_get_ranges();
  603. if (ret != 0)
  604. return ret;
  605. if ((longhaul_version==TYPE_LONGHAUL_V2 || longhaul_version==TYPE_POWERSAVER) &&
  606. (scale_voltage != 0))
  607. longhaul_setup_voltagescaling();
  608. policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
  609. policy->cpuinfo.transition_latency = 200000; /* nsec */
  610. policy->cur = calc_speed(longhaul_get_cpu_mult());
  611. ret = cpufreq_frequency_table_cpuinfo(policy, longhaul_table);
  612. if (ret)
  613. return ret;
  614. cpufreq_frequency_table_get_attr(longhaul_table, policy->cpu);
  615. return 0;
  616. }
  617. static int __devexit longhaul_cpu_exit(struct cpufreq_policy *policy)
  618. {
  619. cpufreq_frequency_table_put_attr(policy->cpu);
  620. return 0;
  621. }
  622. static struct freq_attr* longhaul_attr[] = {
  623. &cpufreq_freq_attr_scaling_available_freqs,
  624. NULL,
  625. };
  626. static struct cpufreq_driver longhaul_driver = {
  627. .verify = longhaul_verify,
  628. .target = longhaul_target,
  629. .get = longhaul_get,
  630. .init = longhaul_cpu_init,
  631. .exit = __devexit_p(longhaul_cpu_exit),
  632. .name = "longhaul",
  633. .owner = THIS_MODULE,
  634. .attr = longhaul_attr,
  635. };
  636. static int __init longhaul_init(void)
  637. {
  638. struct cpuinfo_x86 *c = cpu_data;
  639. if (c->x86_vendor != X86_VENDOR_CENTAUR || c->x86 != 6)
  640. return -ENODEV;
  641. #ifdef CONFIG_SMP
  642. if (num_online_cpus() > 1) {
  643. printk(KERN_ERR PFX "More than 1 CPU detected, longhaul disabled.\n");
  644. return -ENODEV;
  645. }
  646. #endif
  647. #ifdef CONFIG_X86_IO_APIC
  648. if (cpu_has_apic) {
  649. printk(KERN_ERR PFX "APIC detected. Longhaul is currently broken in this configuration.\n");
  650. return -ENODEV;
  651. }
  652. #endif
  653. switch (c->x86_model) {
  654. case 6 ... 9:
  655. return cpufreq_register_driver(&longhaul_driver);
  656. case 10:
  657. printk(KERN_ERR PFX "Use acpi-cpufreq driver for VIA C7\n");
  658. default:
  659. ;;
  660. }
  661. return -ENODEV;
  662. }
  663. static void __exit longhaul_exit(void)
  664. {
  665. int i;
  666. for (i=0; i < numscales; i++) {
  667. if (clock_ratio[i] == maxmult) {
  668. longhaul_setstate(i);
  669. break;
  670. }
  671. }
  672. cpufreq_unregister_driver(&longhaul_driver);
  673. kfree(longhaul_table);
  674. }
  675. module_param (scale_voltage, int, 0644);
  676. MODULE_PARM_DESC(scale_voltage, "Scale voltage of processor");
  677. module_param(ignore_latency, int, 0644);
  678. MODULE_PARM_DESC(ignore_latency, "Skip ACPI C3 latency test");
  679. MODULE_AUTHOR ("Dave Jones <davej@codemonkey.org.uk>");
  680. MODULE_DESCRIPTION ("Longhaul driver for VIA Cyrix processors.");
  681. MODULE_LICENSE ("GPL");
  682. late_initcall(longhaul_init);
  683. module_exit(longhaul_exit);