cx23885.h 18 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/pci.h>
  22. #include <linux/i2c.h>
  23. #include <linux/i2c-algo-bit.h>
  24. #include <linux/kdev_t.h>
  25. #include <linux/slab.h>
  26. #include <media/v4l2-device.h>
  27. #include <media/tuner.h>
  28. #include <media/tveeprom.h>
  29. #include <media/videobuf-dma-sg.h>
  30. #include <media/videobuf-dvb.h>
  31. #include <media/ir-core.h>
  32. #include "btcx-risc.h"
  33. #include "cx23885-reg.h"
  34. #include "media/cx2341x.h"
  35. #include <linux/version.h>
  36. #include <linux/mutex.h>
  37. #define CX23885_VERSION_CODE KERNEL_VERSION(0, 0, 2)
  38. #define UNSET (-1U)
  39. #define CX23885_MAXBOARDS 8
  40. /* Max number of inputs by card */
  41. #define MAX_CX23885_INPUT 8
  42. #define INPUT(nr) (&cx23885_boards[dev->board].input[nr])
  43. #define RESOURCE_OVERLAY 1
  44. #define RESOURCE_VIDEO 2
  45. #define RESOURCE_VBI 4
  46. #define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
  47. #define CX23885_BOARD_NOAUTO UNSET
  48. #define CX23885_BOARD_UNKNOWN 0
  49. #define CX23885_BOARD_HAUPPAUGE_HVR1800lp 1
  50. #define CX23885_BOARD_HAUPPAUGE_HVR1800 2
  51. #define CX23885_BOARD_HAUPPAUGE_HVR1250 3
  52. #define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4
  53. #define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5
  54. #define CX23885_BOARD_HAUPPAUGE_HVR1500 6
  55. #define CX23885_BOARD_HAUPPAUGE_HVR1200 7
  56. #define CX23885_BOARD_HAUPPAUGE_HVR1700 8
  57. #define CX23885_BOARD_HAUPPAUGE_HVR1400 9
  58. #define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10
  59. #define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11
  60. #define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12
  61. #define CX23885_BOARD_COMPRO_VIDEOMATE_E650F 13
  62. #define CX23885_BOARD_TBS_6920 14
  63. #define CX23885_BOARD_TEVII_S470 15
  64. #define CX23885_BOARD_DVBWORLD_2005 16
  65. #define CX23885_BOARD_NETUP_DUAL_DVBS2_CI 17
  66. #define CX23885_BOARD_HAUPPAUGE_HVR1270 18
  67. #define CX23885_BOARD_HAUPPAUGE_HVR1275 19
  68. #define CX23885_BOARD_HAUPPAUGE_HVR1255 20
  69. #define CX23885_BOARD_HAUPPAUGE_HVR1210 21
  70. #define CX23885_BOARD_MYGICA_X8506 22
  71. #define CX23885_BOARD_MAGICPRO_PROHDTVE2 23
  72. #define CX23885_BOARD_HAUPPAUGE_HVR1850 24
  73. #define CX23885_BOARD_COMPRO_VIDEOMATE_E800 25
  74. #define CX23885_BOARD_HAUPPAUGE_HVR1290 26
  75. #define CX23885_BOARD_MYGICA_X8558PRO 27
  76. #define CX23885_BOARD_LEADTEK_WINFAST_PXTV1200 28
  77. #define GPIO_0 0x00000001
  78. #define GPIO_1 0x00000002
  79. #define GPIO_2 0x00000004
  80. #define GPIO_3 0x00000008
  81. #define GPIO_4 0x00000010
  82. #define GPIO_5 0x00000020
  83. #define GPIO_6 0x00000040
  84. #define GPIO_7 0x00000080
  85. #define GPIO_8 0x00000100
  86. #define GPIO_9 0x00000200
  87. #define GPIO_10 0x00000400
  88. #define GPIO_11 0x00000800
  89. #define GPIO_12 0x00001000
  90. #define GPIO_13 0x00002000
  91. #define GPIO_14 0x00004000
  92. #define GPIO_15 0x00008000
  93. /* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
  94. #define CX23885_NORMS (\
  95. V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \
  96. V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \
  97. V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \
  98. V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK)
  99. struct cx23885_fmt {
  100. char *name;
  101. u32 fourcc; /* v4l2 format id */
  102. int depth;
  103. int flags;
  104. u32 cxformat;
  105. };
  106. struct cx23885_ctrl {
  107. struct v4l2_queryctrl v;
  108. u32 off;
  109. u32 reg;
  110. u32 mask;
  111. u32 shift;
  112. };
  113. struct cx23885_tvnorm {
  114. char *name;
  115. v4l2_std_id id;
  116. u32 cxiformat;
  117. u32 cxoformat;
  118. };
  119. struct cx23885_fh {
  120. struct cx23885_dev *dev;
  121. enum v4l2_buf_type type;
  122. int radio;
  123. u32 resources;
  124. /* video overlay */
  125. struct v4l2_window win;
  126. struct v4l2_clip *clips;
  127. unsigned int nclips;
  128. /* video capture */
  129. struct cx23885_fmt *fmt;
  130. unsigned int width, height;
  131. /* vbi capture */
  132. struct videobuf_queue vidq;
  133. struct videobuf_queue vbiq;
  134. /* MPEG Encoder specifics ONLY */
  135. struct videobuf_queue mpegq;
  136. atomic_t v4l_reading;
  137. };
  138. enum cx23885_itype {
  139. CX23885_VMUX_COMPOSITE1 = 1,
  140. CX23885_VMUX_COMPOSITE2,
  141. CX23885_VMUX_COMPOSITE3,
  142. CX23885_VMUX_COMPOSITE4,
  143. CX23885_VMUX_SVIDEO,
  144. CX23885_VMUX_COMPONENT,
  145. CX23885_VMUX_TELEVISION,
  146. CX23885_VMUX_CABLE,
  147. CX23885_VMUX_DVB,
  148. CX23885_VMUX_DEBUG,
  149. CX23885_RADIO,
  150. };
  151. enum cx23885_src_sel_type {
  152. CX23885_SRC_SEL_EXT_656_VIDEO = 0,
  153. CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO
  154. };
  155. /* buffer for one video frame */
  156. struct cx23885_buffer {
  157. /* common v4l buffer stuff -- must be first */
  158. struct videobuf_buffer vb;
  159. /* cx23885 specific */
  160. unsigned int bpl;
  161. struct btcx_riscmem risc;
  162. struct cx23885_fmt *fmt;
  163. u32 count;
  164. };
  165. struct cx23885_input {
  166. enum cx23885_itype type;
  167. unsigned int vmux;
  168. u32 gpio0, gpio1, gpio2, gpio3;
  169. };
  170. typedef enum {
  171. CX23885_MPEG_UNDEFINED = 0,
  172. CX23885_MPEG_DVB,
  173. CX23885_ANALOG_VIDEO,
  174. CX23885_MPEG_ENCODER,
  175. } port_t;
  176. struct cx23885_board {
  177. char *name;
  178. port_t porta, portb, portc;
  179. unsigned int tuner_type;
  180. unsigned int radio_type;
  181. unsigned char tuner_addr;
  182. unsigned char radio_addr;
  183. /* Vendors can and do run the PCIe bridge at different
  184. * clock rates, driven physically by crystals on the PCBs.
  185. * The core has to accomodate this. This allows the user
  186. * to add new boards with new frequencys. The value is
  187. * expressed in Hz.
  188. *
  189. * The core framework will default this value based on
  190. * current designs, but it can vary.
  191. */
  192. u32 clk_freq;
  193. struct cx23885_input input[MAX_CX23885_INPUT];
  194. int cimax; /* for NetUP */
  195. };
  196. struct cx23885_subid {
  197. u16 subvendor;
  198. u16 subdevice;
  199. u32 card;
  200. };
  201. struct cx23885_i2c {
  202. struct cx23885_dev *dev;
  203. int nr;
  204. /* i2c i/o */
  205. struct i2c_adapter i2c_adap;
  206. struct i2c_algo_bit_data i2c_algo;
  207. struct i2c_client i2c_client;
  208. u32 i2c_rc;
  209. /* 885 registers used for raw addess */
  210. u32 i2c_period;
  211. u32 reg_ctrl;
  212. u32 reg_stat;
  213. u32 reg_addr;
  214. u32 reg_rdata;
  215. u32 reg_wdata;
  216. };
  217. struct cx23885_dmaqueue {
  218. struct list_head active;
  219. struct list_head queued;
  220. struct timer_list timeout;
  221. struct btcx_riscmem stopper;
  222. u32 count;
  223. };
  224. struct cx23885_tsport {
  225. struct cx23885_dev *dev;
  226. int nr;
  227. int sram_chno;
  228. struct videobuf_dvb_frontends frontends;
  229. /* dma queues */
  230. struct cx23885_dmaqueue mpegq;
  231. u32 ts_packet_size;
  232. u32 ts_packet_count;
  233. int width;
  234. int height;
  235. spinlock_t slock;
  236. /* registers */
  237. u32 reg_gpcnt;
  238. u32 reg_gpcnt_ctl;
  239. u32 reg_dma_ctl;
  240. u32 reg_lngth;
  241. u32 reg_hw_sop_ctrl;
  242. u32 reg_gen_ctrl;
  243. u32 reg_bd_pkt_status;
  244. u32 reg_sop_status;
  245. u32 reg_fifo_ovfl_stat;
  246. u32 reg_vld_misc;
  247. u32 reg_ts_clk_en;
  248. u32 reg_ts_int_msk;
  249. u32 reg_ts_int_stat;
  250. u32 reg_src_sel;
  251. /* Default register vals */
  252. int pci_irqmask;
  253. u32 dma_ctl_val;
  254. u32 ts_int_msk_val;
  255. u32 gen_ctrl_val;
  256. u32 ts_clk_en_val;
  257. u32 src_sel_val;
  258. u32 vld_misc_val;
  259. u32 hw_sop_ctrl_val;
  260. /* Allow a single tsport to have multiple frontends */
  261. u32 num_frontends;
  262. void *port_priv;
  263. };
  264. struct cx23885_kernel_ir {
  265. struct cx23885_dev *cx;
  266. char *name;
  267. char *phys;
  268. struct input_dev *inp_dev;
  269. struct ir_dev_props props;
  270. };
  271. struct cx23885_dev {
  272. atomic_t refcount;
  273. struct v4l2_device v4l2_dev;
  274. /* pci stuff */
  275. struct pci_dev *pci;
  276. unsigned char pci_rev, pci_lat;
  277. int pci_bus, pci_slot;
  278. u32 __iomem *lmmio;
  279. u8 __iomem *bmmio;
  280. int pci_irqmask;
  281. spinlock_t pci_irqmask_lock; /* protects mask reg too */
  282. int hwrevision;
  283. /* This valud is board specific and is used to configure the
  284. * AV core so we see nice clean and stable video and audio. */
  285. u32 clk_freq;
  286. /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
  287. struct cx23885_i2c i2c_bus[3];
  288. int nr;
  289. struct mutex lock;
  290. struct mutex gpio_lock;
  291. /* board details */
  292. unsigned int board;
  293. char name[32];
  294. struct cx23885_tsport ts1, ts2;
  295. /* sram configuration */
  296. struct sram_channel *sram_channels;
  297. enum {
  298. CX23885_BRIDGE_UNDEFINED = 0,
  299. CX23885_BRIDGE_885 = 885,
  300. CX23885_BRIDGE_887 = 887,
  301. CX23885_BRIDGE_888 = 888,
  302. } bridge;
  303. /* Analog video */
  304. u32 resources;
  305. unsigned int input;
  306. u32 tvaudio;
  307. v4l2_std_id tvnorm;
  308. unsigned int tuner_type;
  309. unsigned char tuner_addr;
  310. unsigned int radio_type;
  311. unsigned char radio_addr;
  312. unsigned int has_radio;
  313. struct v4l2_subdev *sd_cx25840;
  314. struct work_struct cx25840_work;
  315. /* Infrared */
  316. struct v4l2_subdev *sd_ir;
  317. struct work_struct ir_rx_work;
  318. unsigned long ir_rx_notifications;
  319. struct work_struct ir_tx_work;
  320. unsigned long ir_tx_notifications;
  321. struct cx23885_kernel_ir *kernel_ir;
  322. atomic_t ir_input_stopping;
  323. /* V4l */
  324. u32 freq;
  325. struct video_device *video_dev;
  326. struct video_device *vbi_dev;
  327. struct video_device *radio_dev;
  328. struct cx23885_dmaqueue vidq;
  329. struct cx23885_dmaqueue vbiq;
  330. spinlock_t slock;
  331. /* MPEG Encoder ONLY settings */
  332. u32 cx23417_mailbox;
  333. struct cx2341x_mpeg_params mpeg_params;
  334. struct video_device *v4l_device;
  335. atomic_t v4l_reader_count;
  336. struct cx23885_tvnorm encodernorm;
  337. };
  338. static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev)
  339. {
  340. return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev);
  341. }
  342. #define call_all(dev, o, f, args...) \
  343. v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)
  344. #define CX23885_HW_888_IR (1 << 0)
  345. #define CX23885_HW_AV_CORE (1 << 1)
  346. #define call_hw(dev, grpid, o, f, args...) \
  347. v4l2_device_call_all(&dev->v4l2_dev, grpid, o, f, ##args)
  348. extern struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw);
  349. #define SRAM_CH01 0 /* Video A */
  350. #define SRAM_CH02 1 /* VBI A */
  351. #define SRAM_CH03 2 /* Video B */
  352. #define SRAM_CH04 3 /* Transport via B */
  353. #define SRAM_CH05 4 /* VBI B */
  354. #define SRAM_CH06 5 /* Video C */
  355. #define SRAM_CH07 6 /* Transport via C */
  356. #define SRAM_CH08 7 /* Audio Internal A */
  357. #define SRAM_CH09 8 /* Audio Internal B */
  358. #define SRAM_CH10 9 /* Audio External */
  359. #define SRAM_CH11 10 /* COMB_3D_N */
  360. #define SRAM_CH12 11 /* Comb 3D N1 */
  361. #define SRAM_CH13 12 /* Comb 3D N2 */
  362. #define SRAM_CH14 13 /* MOE Vid */
  363. #define SRAM_CH15 14 /* MOE RSLT */
  364. struct sram_channel {
  365. char *name;
  366. u32 cmds_start;
  367. u32 ctrl_start;
  368. u32 cdt;
  369. u32 fifo_start;
  370. u32 fifo_size;
  371. u32 ptr1_reg;
  372. u32 ptr2_reg;
  373. u32 cnt1_reg;
  374. u32 cnt2_reg;
  375. u32 jumponly;
  376. };
  377. /* ----------------------------------------------------------- */
  378. #define cx_read(reg) readl(dev->lmmio + ((reg)>>2))
  379. #define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
  380. #define cx_andor(reg, mask, value) \
  381. writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
  382. ((value) & (mask)), dev->lmmio+((reg)>>2))
  383. #define cx_set(reg, bit) cx_andor((reg), (bit), (bit))
  384. #define cx_clear(reg, bit) cx_andor((reg), (bit), 0)
  385. /* ----------------------------------------------------------- */
  386. /* cx23885-core.c */
  387. extern int cx23885_sram_channel_setup(struct cx23885_dev *dev,
  388. struct sram_channel *ch,
  389. unsigned int bpl, u32 risc);
  390. extern void cx23885_sram_channel_dump(struct cx23885_dev *dev,
  391. struct sram_channel *ch);
  392. extern int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
  393. u32 reg, u32 mask, u32 value);
  394. extern int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
  395. struct scatterlist *sglist,
  396. unsigned int top_offset, unsigned int bottom_offset,
  397. unsigned int bpl, unsigned int padding, unsigned int lines);
  398. void cx23885_cancel_buffers(struct cx23885_tsport *port);
  399. extern int cx23885_restart_queue(struct cx23885_tsport *port,
  400. struct cx23885_dmaqueue *q);
  401. extern void cx23885_wakeup(struct cx23885_tsport *port,
  402. struct cx23885_dmaqueue *q, u32 count);
  403. extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);
  404. extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);
  405. extern u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask);
  406. extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,
  407. int asoutput);
  408. extern void cx23885_irq_add_enable(struct cx23885_dev *dev, u32 mask);
  409. extern void cx23885_irq_enable(struct cx23885_dev *dev, u32 mask);
  410. extern void cx23885_irq_disable(struct cx23885_dev *dev, u32 mask);
  411. extern void cx23885_irq_remove(struct cx23885_dev *dev, u32 mask);
  412. /* ----------------------------------------------------------- */
  413. /* cx23885-cards.c */
  414. extern struct cx23885_board cx23885_boards[];
  415. extern const unsigned int cx23885_bcount;
  416. extern struct cx23885_subid cx23885_subids[];
  417. extern const unsigned int cx23885_idcount;
  418. extern int cx23885_tuner_callback(void *priv, int component,
  419. int command, int arg);
  420. extern void cx23885_card_list(struct cx23885_dev *dev);
  421. extern int cx23885_ir_init(struct cx23885_dev *dev);
  422. extern void cx23885_ir_pci_int_enable(struct cx23885_dev *dev);
  423. extern void cx23885_ir_fini(struct cx23885_dev *dev);
  424. extern void cx23885_gpio_setup(struct cx23885_dev *dev);
  425. extern void cx23885_card_setup(struct cx23885_dev *dev);
  426. extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev);
  427. extern int cx23885_dvb_register(struct cx23885_tsport *port);
  428. extern int cx23885_dvb_unregister(struct cx23885_tsport *port);
  429. extern int cx23885_buf_prepare(struct videobuf_queue *q,
  430. struct cx23885_tsport *port,
  431. struct cx23885_buffer *buf,
  432. enum v4l2_field field);
  433. extern void cx23885_buf_queue(struct cx23885_tsport *port,
  434. struct cx23885_buffer *buf);
  435. extern void cx23885_free_buffer(struct videobuf_queue *q,
  436. struct cx23885_buffer *buf);
  437. /* ----------------------------------------------------------- */
  438. /* cx23885-video.c */
  439. /* Video */
  440. extern int cx23885_video_register(struct cx23885_dev *dev);
  441. extern void cx23885_video_unregister(struct cx23885_dev *dev);
  442. extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status);
  443. /* ----------------------------------------------------------- */
  444. /* cx23885-vbi.c */
  445. extern int cx23885_vbi_fmt(struct file *file, void *priv,
  446. struct v4l2_format *f);
  447. extern void cx23885_vbi_timeout(unsigned long data);
  448. extern struct videobuf_queue_ops cx23885_vbi_qops;
  449. /* cx23885-i2c.c */
  450. extern int cx23885_i2c_register(struct cx23885_i2c *bus);
  451. extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);
  452. extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);
  453. /* ----------------------------------------------------------- */
  454. /* cx23885-417.c */
  455. extern int cx23885_417_register(struct cx23885_dev *dev);
  456. extern void cx23885_417_unregister(struct cx23885_dev *dev);
  457. extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);
  458. extern void cx23885_417_check_encoder(struct cx23885_dev *dev);
  459. extern void cx23885_mc417_init(struct cx23885_dev *dev);
  460. extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value);
  461. extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);
  462. extern int mc417_register_read(struct cx23885_dev *dev,
  463. u16 address, u32 *value);
  464. extern int mc417_register_write(struct cx23885_dev *dev,
  465. u16 address, u32 value);
  466. extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask);
  467. extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask);
  468. extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput);
  469. /* ----------------------------------------------------------- */
  470. /* tv norms */
  471. static inline unsigned int norm_maxw(v4l2_std_id norm)
  472. {
  473. return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 720 : 768;
  474. }
  475. static inline unsigned int norm_maxh(v4l2_std_id norm)
  476. {
  477. return (norm & V4L2_STD_625_50) ? 576 : 480;
  478. }
  479. static inline unsigned int norm_swidth(v4l2_std_id norm)
  480. {
  481. return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922;
  482. }