init.c 43 KB

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  1. /*
  2. * Copyright (c) 2011 Atheros Communications Inc.
  3. * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18. #include <linux/moduleparam.h>
  19. #include <linux/errno.h>
  20. #include <linux/export.h>
  21. #include <linux/of.h>
  22. #include <linux/mmc/sdio_func.h>
  23. #include <linux/vmalloc.h>
  24. #include "core.h"
  25. #include "cfg80211.h"
  26. #include "target.h"
  27. #include "debug.h"
  28. #include "hif-ops.h"
  29. #include "htc-ops.h"
  30. static const struct ath6kl_hw hw_list[] = {
  31. {
  32. .id = AR6003_HW_2_0_VERSION,
  33. .name = "ar6003 hw 2.0",
  34. .dataset_patch_addr = 0x57e884,
  35. .app_load_addr = 0x543180,
  36. .board_ext_data_addr = 0x57e500,
  37. .reserved_ram_size = 6912,
  38. .refclk_hz = 26000000,
  39. .uarttx_pin = 8,
  40. .flags = 0,
  41. /* hw2.0 needs override address hardcoded */
  42. .app_start_override_addr = 0x944C00,
  43. .fw = {
  44. .dir = AR6003_HW_2_0_FW_DIR,
  45. .otp = AR6003_HW_2_0_OTP_FILE,
  46. .fw = AR6003_HW_2_0_FIRMWARE_FILE,
  47. .tcmd = AR6003_HW_2_0_TCMD_FIRMWARE_FILE,
  48. .patch = AR6003_HW_2_0_PATCH_FILE,
  49. },
  50. .fw_board = AR6003_HW_2_0_BOARD_DATA_FILE,
  51. .fw_default_board = AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE,
  52. },
  53. {
  54. .id = AR6003_HW_2_1_1_VERSION,
  55. .name = "ar6003 hw 2.1.1",
  56. .dataset_patch_addr = 0x57ff74,
  57. .app_load_addr = 0x1234,
  58. .board_ext_data_addr = 0x542330,
  59. .reserved_ram_size = 512,
  60. .refclk_hz = 26000000,
  61. .uarttx_pin = 8,
  62. .testscript_addr = 0x57ef74,
  63. .flags = 0,
  64. .fw = {
  65. .dir = AR6003_HW_2_1_1_FW_DIR,
  66. .otp = AR6003_HW_2_1_1_OTP_FILE,
  67. .fw = AR6003_HW_2_1_1_FIRMWARE_FILE,
  68. .tcmd = AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE,
  69. .patch = AR6003_HW_2_1_1_PATCH_FILE,
  70. .utf = AR6003_HW_2_1_1_UTF_FIRMWARE_FILE,
  71. .testscript = AR6003_HW_2_1_1_TESTSCRIPT_FILE,
  72. },
  73. .fw_board = AR6003_HW_2_1_1_BOARD_DATA_FILE,
  74. .fw_default_board = AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE,
  75. },
  76. {
  77. .id = AR6004_HW_1_0_VERSION,
  78. .name = "ar6004 hw 1.0",
  79. .dataset_patch_addr = 0x57e884,
  80. .app_load_addr = 0x1234,
  81. .board_ext_data_addr = 0x437000,
  82. .reserved_ram_size = 19456,
  83. .board_addr = 0x433900,
  84. .refclk_hz = 26000000,
  85. .uarttx_pin = 11,
  86. .flags = ATH6KL_HW_64BIT_RATES |
  87. ATH6KL_HW_AP_INACTIVITY_MINS,
  88. .fw = {
  89. .dir = AR6004_HW_1_0_FW_DIR,
  90. .fw = AR6004_HW_1_0_FIRMWARE_FILE,
  91. },
  92. .fw_board = AR6004_HW_1_0_BOARD_DATA_FILE,
  93. .fw_default_board = AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE,
  94. },
  95. {
  96. .id = AR6004_HW_1_1_VERSION,
  97. .name = "ar6004 hw 1.1",
  98. .dataset_patch_addr = 0x57e884,
  99. .app_load_addr = 0x1234,
  100. .board_ext_data_addr = 0x437000,
  101. .reserved_ram_size = 11264,
  102. .board_addr = 0x43d400,
  103. .refclk_hz = 40000000,
  104. .uarttx_pin = 11,
  105. .flags = ATH6KL_HW_64BIT_RATES |
  106. ATH6KL_HW_AP_INACTIVITY_MINS,
  107. .fw = {
  108. .dir = AR6004_HW_1_1_FW_DIR,
  109. .fw = AR6004_HW_1_1_FIRMWARE_FILE,
  110. },
  111. .fw_board = AR6004_HW_1_1_BOARD_DATA_FILE,
  112. .fw_default_board = AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE,
  113. },
  114. {
  115. .id = AR6004_HW_1_2_VERSION,
  116. .name = "ar6004 hw 1.2",
  117. .dataset_patch_addr = 0x436ecc,
  118. .app_load_addr = 0x1234,
  119. .board_ext_data_addr = 0x437000,
  120. .reserved_ram_size = 9216,
  121. .board_addr = 0x435c00,
  122. .refclk_hz = 40000000,
  123. .uarttx_pin = 11,
  124. .flags = ATH6KL_HW_64BIT_RATES |
  125. ATH6KL_HW_AP_INACTIVITY_MINS,
  126. .fw = {
  127. .dir = AR6004_HW_1_2_FW_DIR,
  128. .fw = AR6004_HW_1_2_FIRMWARE_FILE,
  129. },
  130. .fw_board = AR6004_HW_1_2_BOARD_DATA_FILE,
  131. .fw_default_board = AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE,
  132. },
  133. {
  134. .id = AR6004_HW_1_3_VERSION,
  135. .name = "ar6004 hw 1.3",
  136. .dataset_patch_addr = 0x437860,
  137. .app_load_addr = 0x1234,
  138. .board_ext_data_addr = 0x437000,
  139. .reserved_ram_size = 7168,
  140. .board_addr = 0x436400,
  141. .refclk_hz = 40000000,
  142. .uarttx_pin = 11,
  143. .flags = ATH6KL_HW_64BIT_RATES |
  144. ATH6KL_HW_AP_INACTIVITY_MINS,
  145. .fw = {
  146. .dir = AR6004_HW_1_3_FW_DIR,
  147. .fw = AR6004_HW_1_3_FIRMWARE_FILE,
  148. },
  149. .fw_board = AR6004_HW_1_3_BOARD_DATA_FILE,
  150. .fw_default_board = AR6004_HW_1_3_DEFAULT_BOARD_DATA_FILE,
  151. },
  152. };
  153. /*
  154. * Include definitions here that can be used to tune the WLAN module
  155. * behavior. Different customers can tune the behavior as per their needs,
  156. * here.
  157. */
  158. /*
  159. * This configuration item enable/disable keepalive support.
  160. * Keepalive support: In the absence of any data traffic to AP, null
  161. * frames will be sent to the AP at periodic interval, to keep the association
  162. * active. This configuration item defines the periodic interval.
  163. * Use value of zero to disable keepalive support
  164. * Default: 60 seconds
  165. */
  166. #define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60
  167. /*
  168. * This configuration item sets the value of disconnect timeout
  169. * Firmware delays sending the disconnec event to the host for this
  170. * timeout after is gets disconnected from the current AP.
  171. * If the firmware successly roams within the disconnect timeout
  172. * it sends a new connect event
  173. */
  174. #define WLAN_CONFIG_DISCONNECT_TIMEOUT 10
  175. #define ATH6KL_DATA_OFFSET 64
  176. struct sk_buff *ath6kl_buf_alloc(int size)
  177. {
  178. struct sk_buff *skb;
  179. u16 reserved;
  180. /* Add chacheline space at front and back of buffer */
  181. reserved = (2 * L1_CACHE_BYTES) + ATH6KL_DATA_OFFSET +
  182. sizeof(struct htc_packet) + ATH6KL_HTC_ALIGN_BYTES;
  183. skb = dev_alloc_skb(size + reserved);
  184. if (skb)
  185. skb_reserve(skb, reserved - L1_CACHE_BYTES);
  186. return skb;
  187. }
  188. void ath6kl_init_profile_info(struct ath6kl_vif *vif)
  189. {
  190. vif->ssid_len = 0;
  191. memset(vif->ssid, 0, sizeof(vif->ssid));
  192. vif->dot11_auth_mode = OPEN_AUTH;
  193. vif->auth_mode = NONE_AUTH;
  194. vif->prwise_crypto = NONE_CRYPT;
  195. vif->prwise_crypto_len = 0;
  196. vif->grp_crypto = NONE_CRYPT;
  197. vif->grp_crypto_len = 0;
  198. memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
  199. memset(vif->req_bssid, 0, sizeof(vif->req_bssid));
  200. memset(vif->bssid, 0, sizeof(vif->bssid));
  201. vif->bss_ch = 0;
  202. }
  203. static int ath6kl_set_host_app_area(struct ath6kl *ar)
  204. {
  205. u32 address, data;
  206. struct host_app_area host_app_area;
  207. /* Fetch the address of the host_app_area_s
  208. * instance in the host interest area */
  209. address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_app_host_interest));
  210. address = TARG_VTOP(ar->target_type, address);
  211. if (ath6kl_diag_read32(ar, address, &data))
  212. return -EIO;
  213. address = TARG_VTOP(ar->target_type, data);
  214. host_app_area.wmi_protocol_ver = cpu_to_le32(WMI_PROTOCOL_VERSION);
  215. if (ath6kl_diag_write(ar, address, (u8 *) &host_app_area,
  216. sizeof(struct host_app_area)))
  217. return -EIO;
  218. return 0;
  219. }
  220. static inline void set_ac2_ep_map(struct ath6kl *ar,
  221. u8 ac,
  222. enum htc_endpoint_id ep)
  223. {
  224. ar->ac2ep_map[ac] = ep;
  225. ar->ep2ac_map[ep] = ac;
  226. }
  227. /* connect to a service */
  228. static int ath6kl_connectservice(struct ath6kl *ar,
  229. struct htc_service_connect_req *con_req,
  230. char *desc)
  231. {
  232. int status;
  233. struct htc_service_connect_resp response;
  234. memset(&response, 0, sizeof(response));
  235. status = ath6kl_htc_conn_service(ar->htc_target, con_req, &response);
  236. if (status) {
  237. ath6kl_err("failed to connect to %s service status:%d\n",
  238. desc, status);
  239. return status;
  240. }
  241. switch (con_req->svc_id) {
  242. case WMI_CONTROL_SVC:
  243. if (test_bit(WMI_ENABLED, &ar->flag))
  244. ath6kl_wmi_set_control_ep(ar->wmi, response.endpoint);
  245. ar->ctrl_ep = response.endpoint;
  246. break;
  247. case WMI_DATA_BE_SVC:
  248. set_ac2_ep_map(ar, WMM_AC_BE, response.endpoint);
  249. break;
  250. case WMI_DATA_BK_SVC:
  251. set_ac2_ep_map(ar, WMM_AC_BK, response.endpoint);
  252. break;
  253. case WMI_DATA_VI_SVC:
  254. set_ac2_ep_map(ar, WMM_AC_VI, response.endpoint);
  255. break;
  256. case WMI_DATA_VO_SVC:
  257. set_ac2_ep_map(ar, WMM_AC_VO, response.endpoint);
  258. break;
  259. default:
  260. ath6kl_err("service id is not mapped %d\n", con_req->svc_id);
  261. return -EINVAL;
  262. }
  263. return 0;
  264. }
  265. static int ath6kl_init_service_ep(struct ath6kl *ar)
  266. {
  267. struct htc_service_connect_req connect;
  268. memset(&connect, 0, sizeof(connect));
  269. /* these fields are the same for all service endpoints */
  270. connect.ep_cb.tx_comp_multi = ath6kl_tx_complete;
  271. connect.ep_cb.rx = ath6kl_rx;
  272. connect.ep_cb.rx_refill = ath6kl_rx_refill;
  273. connect.ep_cb.tx_full = ath6kl_tx_queue_full;
  274. /*
  275. * Set the max queue depth so that our ath6kl_tx_queue_full handler
  276. * gets called.
  277. */
  278. connect.max_txq_depth = MAX_DEFAULT_SEND_QUEUE_DEPTH;
  279. connect.ep_cb.rx_refill_thresh = ATH6KL_MAX_RX_BUFFERS / 4;
  280. if (!connect.ep_cb.rx_refill_thresh)
  281. connect.ep_cb.rx_refill_thresh++;
  282. /* connect to control service */
  283. connect.svc_id = WMI_CONTROL_SVC;
  284. if (ath6kl_connectservice(ar, &connect, "WMI CONTROL"))
  285. return -EIO;
  286. connect.flags |= HTC_FLGS_TX_BNDL_PAD_EN;
  287. /*
  288. * Limit the HTC message size on the send path, although e can
  289. * receive A-MSDU frames of 4K, we will only send ethernet-sized
  290. * (802.3) frames on the send path.
  291. */
  292. connect.max_rxmsg_sz = WMI_MAX_TX_DATA_FRAME_LENGTH;
  293. /*
  294. * To reduce the amount of committed memory for larger A_MSDU
  295. * frames, use the recv-alloc threshold mechanism for larger
  296. * packets.
  297. */
  298. connect.ep_cb.rx_alloc_thresh = ATH6KL_BUFFER_SIZE;
  299. connect.ep_cb.rx_allocthresh = ath6kl_alloc_amsdu_rxbuf;
  300. /*
  301. * For the remaining data services set the connection flag to
  302. * reduce dribbling, if configured to do so.
  303. */
  304. connect.conn_flags |= HTC_CONN_FLGS_REDUCE_CRED_DRIB;
  305. connect.conn_flags &= ~HTC_CONN_FLGS_THRESH_MASK;
  306. connect.conn_flags |= HTC_CONN_FLGS_THRESH_LVL_HALF;
  307. connect.svc_id = WMI_DATA_BE_SVC;
  308. if (ath6kl_connectservice(ar, &connect, "WMI DATA BE"))
  309. return -EIO;
  310. /* connect to back-ground map this to WMI LOW_PRI */
  311. connect.svc_id = WMI_DATA_BK_SVC;
  312. if (ath6kl_connectservice(ar, &connect, "WMI DATA BK"))
  313. return -EIO;
  314. /* connect to Video service, map this to to HI PRI */
  315. connect.svc_id = WMI_DATA_VI_SVC;
  316. if (ath6kl_connectservice(ar, &connect, "WMI DATA VI"))
  317. return -EIO;
  318. /*
  319. * Connect to VO service, this is currently not mapped to a WMI
  320. * priority stream due to historical reasons. WMI originally
  321. * defined 3 priorities over 3 mailboxes We can change this when
  322. * WMI is reworked so that priorities are not dependent on
  323. * mailboxes.
  324. */
  325. connect.svc_id = WMI_DATA_VO_SVC;
  326. if (ath6kl_connectservice(ar, &connect, "WMI DATA VO"))
  327. return -EIO;
  328. return 0;
  329. }
  330. void ath6kl_init_control_info(struct ath6kl_vif *vif)
  331. {
  332. ath6kl_init_profile_info(vif);
  333. vif->def_txkey_index = 0;
  334. memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
  335. vif->ch_hint = 0;
  336. }
  337. /*
  338. * Set HTC/Mbox operational parameters, this can only be called when the
  339. * target is in the BMI phase.
  340. */
  341. static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val,
  342. u8 htc_ctrl_buf)
  343. {
  344. int status;
  345. u32 blk_size;
  346. blk_size = ar->mbox_info.block_size;
  347. if (htc_ctrl_buf)
  348. blk_size |= ((u32)htc_ctrl_buf) << 16;
  349. /* set the host interest area for the block size */
  350. status = ath6kl_bmi_write_hi32(ar, hi_mbox_io_block_sz, blk_size);
  351. if (status) {
  352. ath6kl_err("bmi_write_memory for IO block size failed\n");
  353. goto out;
  354. }
  355. ath6kl_dbg(ATH6KL_DBG_TRC, "block size set: %d (target addr:0x%X)\n",
  356. blk_size,
  357. ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_mbox_io_block_sz)));
  358. if (mbox_isr_yield_val) {
  359. /* set the host interest area for the mbox ISR yield limit */
  360. status = ath6kl_bmi_write_hi32(ar, hi_mbox_isr_yield_limit,
  361. mbox_isr_yield_val);
  362. if (status) {
  363. ath6kl_err("bmi_write_memory for yield limit failed\n");
  364. goto out;
  365. }
  366. }
  367. out:
  368. return status;
  369. }
  370. static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx)
  371. {
  372. int ret;
  373. /*
  374. * Configure the device for rx dot11 header rules. "0,0" are the
  375. * default values. Required if checksum offload is needed. Set
  376. * RxMetaVersion to 2.
  377. */
  378. ret = ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, idx,
  379. ar->rx_meta_ver, 0, 0);
  380. if (ret) {
  381. ath6kl_err("unable to set the rx frame format: %d\n", ret);
  382. return ret;
  383. }
  384. if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN) {
  385. ret = ath6kl_wmi_pmparams_cmd(ar->wmi, idx, 0, 1, 0, 0, 1,
  386. IGNORE_PS_FAIL_DURING_SCAN);
  387. if (ret) {
  388. ath6kl_err("unable to set power save fail event policy: %d\n",
  389. ret);
  390. return ret;
  391. }
  392. }
  393. if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER)) {
  394. ret = ath6kl_wmi_set_lpreamble_cmd(ar->wmi, idx, 0,
  395. WMI_FOLLOW_BARKER_IN_ERP);
  396. if (ret) {
  397. ath6kl_err("unable to set barker preamble policy: %d\n",
  398. ret);
  399. return ret;
  400. }
  401. }
  402. ret = ath6kl_wmi_set_keepalive_cmd(ar->wmi, idx,
  403. WLAN_CONFIG_KEEP_ALIVE_INTERVAL);
  404. if (ret) {
  405. ath6kl_err("unable to set keep alive interval: %d\n", ret);
  406. return ret;
  407. }
  408. ret = ath6kl_wmi_disctimeout_cmd(ar->wmi, idx,
  409. WLAN_CONFIG_DISCONNECT_TIMEOUT);
  410. if (ret) {
  411. ath6kl_err("unable to set disconnect timeout: %d\n", ret);
  412. return ret;
  413. }
  414. if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST)) {
  415. ret = ath6kl_wmi_set_wmm_txop(ar->wmi, idx, WMI_TXOP_DISABLED);
  416. if (ret) {
  417. ath6kl_err("unable to set txop bursting: %d\n", ret);
  418. return ret;
  419. }
  420. }
  421. if (ar->p2p && (ar->vif_max == 1 || idx)) {
  422. ret = ath6kl_wmi_info_req_cmd(ar->wmi, idx,
  423. P2P_FLAG_CAPABILITIES_REQ |
  424. P2P_FLAG_MACADDR_REQ |
  425. P2P_FLAG_HMODEL_REQ);
  426. if (ret) {
  427. ath6kl_dbg(ATH6KL_DBG_TRC,
  428. "failed to request P2P capabilities (%d) - assuming P2P not supported\n",
  429. ret);
  430. ar->p2p = false;
  431. }
  432. }
  433. if (ar->p2p && (ar->vif_max == 1 || idx)) {
  434. /* Enable Probe Request reporting for P2P */
  435. ret = ath6kl_wmi_probe_report_req_cmd(ar->wmi, idx, true);
  436. if (ret) {
  437. ath6kl_dbg(ATH6KL_DBG_TRC,
  438. "failed to enable Probe Request reporting (%d)\n",
  439. ret);
  440. }
  441. }
  442. return ret;
  443. }
  444. int ath6kl_configure_target(struct ath6kl *ar)
  445. {
  446. u32 param, ram_reserved_size;
  447. u8 fw_iftype, fw_mode = 0, fw_submode = 0;
  448. int i, status;
  449. param = !!(ar->conf_flags & ATH6KL_CONF_UART_DEBUG);
  450. if (ath6kl_bmi_write_hi32(ar, hi_serial_enable, param)) {
  451. ath6kl_err("bmi_write_memory for uart debug failed\n");
  452. return -EIO;
  453. }
  454. /*
  455. * Note: Even though the firmware interface type is
  456. * chosen as BSS_STA for all three interfaces, can
  457. * be configured to IBSS/AP as long as the fw submode
  458. * remains normal mode (0 - AP, STA and IBSS). But
  459. * due to an target assert in firmware only one interface is
  460. * configured for now.
  461. */
  462. fw_iftype = HI_OPTION_FW_MODE_BSS_STA;
  463. for (i = 0; i < ar->vif_max; i++)
  464. fw_mode |= fw_iftype << (i * HI_OPTION_FW_MODE_BITS);
  465. /*
  466. * Submodes when fw does not support dynamic interface
  467. * switching:
  468. * vif[0] - AP/STA/IBSS
  469. * vif[1] - "P2P dev"/"P2P GO"/"P2P Client"
  470. * vif[2] - "P2P dev"/"P2P GO"/"P2P Client"
  471. * Otherwise, All the interface are initialized to p2p dev.
  472. */
  473. if (test_bit(ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX,
  474. ar->fw_capabilities)) {
  475. for (i = 0; i < ar->vif_max; i++)
  476. fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV <<
  477. (i * HI_OPTION_FW_SUBMODE_BITS);
  478. } else {
  479. for (i = 0; i < ar->max_norm_iface; i++)
  480. fw_submode |= HI_OPTION_FW_SUBMODE_NONE <<
  481. (i * HI_OPTION_FW_SUBMODE_BITS);
  482. for (i = ar->max_norm_iface; i < ar->vif_max; i++)
  483. fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV <<
  484. (i * HI_OPTION_FW_SUBMODE_BITS);
  485. if (ar->p2p && ar->vif_max == 1)
  486. fw_submode = HI_OPTION_FW_SUBMODE_P2PDEV;
  487. }
  488. if (ath6kl_bmi_write_hi32(ar, hi_app_host_interest,
  489. HTC_PROTOCOL_VERSION) != 0) {
  490. ath6kl_err("bmi_write_memory for htc version failed\n");
  491. return -EIO;
  492. }
  493. /* set the firmware mode to STA/IBSS/AP */
  494. param = 0;
  495. if (ath6kl_bmi_read_hi32(ar, hi_option_flag, &param) != 0) {
  496. ath6kl_err("bmi_read_memory for setting fwmode failed\n");
  497. return -EIO;
  498. }
  499. param |= (ar->vif_max << HI_OPTION_NUM_DEV_SHIFT);
  500. param |= fw_mode << HI_OPTION_FW_MODE_SHIFT;
  501. param |= fw_submode << HI_OPTION_FW_SUBMODE_SHIFT;
  502. param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
  503. param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
  504. if (ath6kl_bmi_write_hi32(ar, hi_option_flag, param) != 0) {
  505. ath6kl_err("bmi_write_memory for setting fwmode failed\n");
  506. return -EIO;
  507. }
  508. ath6kl_dbg(ATH6KL_DBG_TRC, "firmware mode set\n");
  509. /*
  510. * Hardcode the address use for the extended board data
  511. * Ideally this should be pre-allocate by the OS at boot time
  512. * But since it is a new feature and board data is loaded
  513. * at init time, we have to workaround this from host.
  514. * It is difficult to patch the firmware boot code,
  515. * but possible in theory.
  516. */
  517. if (ar->target_type == TARGET_TYPE_AR6003) {
  518. param = ar->hw.board_ext_data_addr;
  519. ram_reserved_size = ar->hw.reserved_ram_size;
  520. if (ath6kl_bmi_write_hi32(ar, hi_board_ext_data, param) != 0) {
  521. ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n");
  522. return -EIO;
  523. }
  524. if (ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz,
  525. ram_reserved_size) != 0) {
  526. ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n");
  527. return -EIO;
  528. }
  529. }
  530. /* set the block size for the target */
  531. if (ath6kl_set_htc_params(ar, MBOX_YIELD_LIMIT, 0))
  532. /* use default number of control buffers */
  533. return -EIO;
  534. /* Configure GPIO AR600x UART */
  535. status = ath6kl_bmi_write_hi32(ar, hi_dbg_uart_txpin,
  536. ar->hw.uarttx_pin);
  537. if (status)
  538. return status;
  539. /* Configure target refclk_hz */
  540. status = ath6kl_bmi_write_hi32(ar, hi_refclk_hz, ar->hw.refclk_hz);
  541. if (status)
  542. return status;
  543. return 0;
  544. }
  545. /* firmware upload */
  546. static int ath6kl_get_fw(struct ath6kl *ar, const char *filename,
  547. u8 **fw, size_t *fw_len)
  548. {
  549. const struct firmware *fw_entry;
  550. int ret;
  551. ret = request_firmware(&fw_entry, filename, ar->dev);
  552. if (ret)
  553. return ret;
  554. *fw_len = fw_entry->size;
  555. *fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL);
  556. if (*fw == NULL)
  557. ret = -ENOMEM;
  558. release_firmware(fw_entry);
  559. return ret;
  560. }
  561. #ifdef CONFIG_OF
  562. /*
  563. * Check the device tree for a board-id and use it to construct
  564. * the pathname to the firmware file. Used (for now) to find a
  565. * fallback to the "bdata.bin" file--typically a symlink to the
  566. * appropriate board-specific file.
  567. */
  568. static bool check_device_tree(struct ath6kl *ar)
  569. {
  570. static const char *board_id_prop = "atheros,board-id";
  571. struct device_node *node;
  572. char board_filename[64];
  573. const char *board_id;
  574. int ret;
  575. for_each_compatible_node(node, NULL, "atheros,ath6kl") {
  576. board_id = of_get_property(node, board_id_prop, NULL);
  577. if (board_id == NULL) {
  578. ath6kl_warn("No \"%s\" property on %s node.\n",
  579. board_id_prop, node->name);
  580. continue;
  581. }
  582. snprintf(board_filename, sizeof(board_filename),
  583. "%s/bdata.%s.bin", ar->hw.fw.dir, board_id);
  584. ret = ath6kl_get_fw(ar, board_filename, &ar->fw_board,
  585. &ar->fw_board_len);
  586. if (ret) {
  587. ath6kl_err("Failed to get DT board file %s: %d\n",
  588. board_filename, ret);
  589. continue;
  590. }
  591. return true;
  592. }
  593. return false;
  594. }
  595. #else
  596. static bool check_device_tree(struct ath6kl *ar)
  597. {
  598. return false;
  599. }
  600. #endif /* CONFIG_OF */
  601. static int ath6kl_fetch_board_file(struct ath6kl *ar)
  602. {
  603. const char *filename;
  604. int ret;
  605. if (ar->fw_board != NULL)
  606. return 0;
  607. if (WARN_ON(ar->hw.fw_board == NULL))
  608. return -EINVAL;
  609. filename = ar->hw.fw_board;
  610. ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
  611. &ar->fw_board_len);
  612. if (ret == 0) {
  613. /* managed to get proper board file */
  614. return 0;
  615. }
  616. if (check_device_tree(ar)) {
  617. /* got board file from device tree */
  618. return 0;
  619. }
  620. /* there was no proper board file, try to use default instead */
  621. ath6kl_warn("Failed to get board file %s (%d), trying to find default board file.\n",
  622. filename, ret);
  623. filename = ar->hw.fw_default_board;
  624. ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
  625. &ar->fw_board_len);
  626. if (ret) {
  627. ath6kl_err("Failed to get default board file %s: %d\n",
  628. filename, ret);
  629. return ret;
  630. }
  631. ath6kl_warn("WARNING! No proper board file was not found, instead using a default board file.\n");
  632. ath6kl_warn("Most likely your hardware won't work as specified. Install correct board file!\n");
  633. return 0;
  634. }
  635. static int ath6kl_fetch_otp_file(struct ath6kl *ar)
  636. {
  637. char filename[100];
  638. int ret;
  639. if (ar->fw_otp != NULL)
  640. return 0;
  641. if (ar->hw.fw.otp == NULL) {
  642. ath6kl_dbg(ATH6KL_DBG_BOOT,
  643. "no OTP file configured for this hw\n");
  644. return 0;
  645. }
  646. snprintf(filename, sizeof(filename), "%s/%s",
  647. ar->hw.fw.dir, ar->hw.fw.otp);
  648. ret = ath6kl_get_fw(ar, filename, &ar->fw_otp,
  649. &ar->fw_otp_len);
  650. if (ret) {
  651. ath6kl_err("Failed to get OTP file %s: %d\n",
  652. filename, ret);
  653. return ret;
  654. }
  655. return 0;
  656. }
  657. static int ath6kl_fetch_testmode_file(struct ath6kl *ar)
  658. {
  659. char filename[100];
  660. int ret;
  661. if (ar->testmode == 0)
  662. return 0;
  663. ath6kl_dbg(ATH6KL_DBG_BOOT, "testmode %d\n", ar->testmode);
  664. if (ar->testmode == 2) {
  665. if (ar->hw.fw.utf == NULL) {
  666. ath6kl_warn("testmode 2 not supported\n");
  667. return -EOPNOTSUPP;
  668. }
  669. snprintf(filename, sizeof(filename), "%s/%s",
  670. ar->hw.fw.dir, ar->hw.fw.utf);
  671. } else {
  672. if (ar->hw.fw.tcmd == NULL) {
  673. ath6kl_warn("testmode 1 not supported\n");
  674. return -EOPNOTSUPP;
  675. }
  676. snprintf(filename, sizeof(filename), "%s/%s",
  677. ar->hw.fw.dir, ar->hw.fw.tcmd);
  678. }
  679. set_bit(TESTMODE, &ar->flag);
  680. ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len);
  681. if (ret) {
  682. ath6kl_err("Failed to get testmode %d firmware file %s: %d\n",
  683. ar->testmode, filename, ret);
  684. return ret;
  685. }
  686. return 0;
  687. }
  688. static int ath6kl_fetch_fw_file(struct ath6kl *ar)
  689. {
  690. char filename[100];
  691. int ret;
  692. if (ar->fw != NULL)
  693. return 0;
  694. /* FIXME: remove WARN_ON() as we won't support FW API 1 for long */
  695. if (WARN_ON(ar->hw.fw.fw == NULL))
  696. return -EINVAL;
  697. snprintf(filename, sizeof(filename), "%s/%s",
  698. ar->hw.fw.dir, ar->hw.fw.fw);
  699. ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len);
  700. if (ret) {
  701. ath6kl_err("Failed to get firmware file %s: %d\n",
  702. filename, ret);
  703. return ret;
  704. }
  705. return 0;
  706. }
  707. static int ath6kl_fetch_patch_file(struct ath6kl *ar)
  708. {
  709. char filename[100];
  710. int ret;
  711. if (ar->fw_patch != NULL)
  712. return 0;
  713. if (ar->hw.fw.patch == NULL)
  714. return 0;
  715. snprintf(filename, sizeof(filename), "%s/%s",
  716. ar->hw.fw.dir, ar->hw.fw.patch);
  717. ret = ath6kl_get_fw(ar, filename, &ar->fw_patch,
  718. &ar->fw_patch_len);
  719. if (ret) {
  720. ath6kl_err("Failed to get patch file %s: %d\n",
  721. filename, ret);
  722. return ret;
  723. }
  724. return 0;
  725. }
  726. static int ath6kl_fetch_testscript_file(struct ath6kl *ar)
  727. {
  728. char filename[100];
  729. int ret;
  730. if (ar->testmode != 2)
  731. return 0;
  732. if (ar->fw_testscript != NULL)
  733. return 0;
  734. if (ar->hw.fw.testscript == NULL)
  735. return 0;
  736. snprintf(filename, sizeof(filename), "%s/%s",
  737. ar->hw.fw.dir, ar->hw.fw.testscript);
  738. ret = ath6kl_get_fw(ar, filename, &ar->fw_testscript,
  739. &ar->fw_testscript_len);
  740. if (ret) {
  741. ath6kl_err("Failed to get testscript file %s: %d\n",
  742. filename, ret);
  743. return ret;
  744. }
  745. return 0;
  746. }
  747. static int ath6kl_fetch_fw_api1(struct ath6kl *ar)
  748. {
  749. int ret;
  750. ret = ath6kl_fetch_otp_file(ar);
  751. if (ret)
  752. return ret;
  753. ret = ath6kl_fetch_fw_file(ar);
  754. if (ret)
  755. return ret;
  756. ret = ath6kl_fetch_patch_file(ar);
  757. if (ret)
  758. return ret;
  759. ret = ath6kl_fetch_testscript_file(ar);
  760. if (ret)
  761. return ret;
  762. return 0;
  763. }
  764. static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name)
  765. {
  766. size_t magic_len, len, ie_len;
  767. const struct firmware *fw;
  768. struct ath6kl_fw_ie *hdr;
  769. char filename[100];
  770. const u8 *data;
  771. int ret, ie_id, i, index, bit;
  772. __le32 *val;
  773. snprintf(filename, sizeof(filename), "%s/%s", ar->hw.fw.dir, name);
  774. ret = request_firmware(&fw, filename, ar->dev);
  775. if (ret)
  776. return ret;
  777. data = fw->data;
  778. len = fw->size;
  779. /* magic also includes the null byte, check that as well */
  780. magic_len = strlen(ATH6KL_FIRMWARE_MAGIC) + 1;
  781. if (len < magic_len) {
  782. ret = -EINVAL;
  783. goto out;
  784. }
  785. if (memcmp(data, ATH6KL_FIRMWARE_MAGIC, magic_len) != 0) {
  786. ret = -EINVAL;
  787. goto out;
  788. }
  789. len -= magic_len;
  790. data += magic_len;
  791. /* loop elements */
  792. while (len > sizeof(struct ath6kl_fw_ie)) {
  793. /* hdr is unaligned! */
  794. hdr = (struct ath6kl_fw_ie *) data;
  795. ie_id = le32_to_cpup(&hdr->id);
  796. ie_len = le32_to_cpup(&hdr->len);
  797. len -= sizeof(*hdr);
  798. data += sizeof(*hdr);
  799. if (len < ie_len) {
  800. ret = -EINVAL;
  801. goto out;
  802. }
  803. switch (ie_id) {
  804. case ATH6KL_FW_IE_FW_VERSION:
  805. strlcpy(ar->wiphy->fw_version, data,
  806. sizeof(ar->wiphy->fw_version));
  807. ath6kl_dbg(ATH6KL_DBG_BOOT,
  808. "found fw version %s\n",
  809. ar->wiphy->fw_version);
  810. break;
  811. case ATH6KL_FW_IE_OTP_IMAGE:
  812. ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n",
  813. ie_len);
  814. ar->fw_otp = kmemdup(data, ie_len, GFP_KERNEL);
  815. if (ar->fw_otp == NULL) {
  816. ret = -ENOMEM;
  817. goto out;
  818. }
  819. ar->fw_otp_len = ie_len;
  820. break;
  821. case ATH6KL_FW_IE_FW_IMAGE:
  822. ath6kl_dbg(ATH6KL_DBG_BOOT, "found fw image ie (%zd B)\n",
  823. ie_len);
  824. /* in testmode we already might have a fw file */
  825. if (ar->fw != NULL)
  826. break;
  827. ar->fw = vmalloc(ie_len);
  828. if (ar->fw == NULL) {
  829. ret = -ENOMEM;
  830. goto out;
  831. }
  832. memcpy(ar->fw, data, ie_len);
  833. ar->fw_len = ie_len;
  834. break;
  835. case ATH6KL_FW_IE_PATCH_IMAGE:
  836. ath6kl_dbg(ATH6KL_DBG_BOOT, "found patch image ie (%zd B)\n",
  837. ie_len);
  838. ar->fw_patch = kmemdup(data, ie_len, GFP_KERNEL);
  839. if (ar->fw_patch == NULL) {
  840. ret = -ENOMEM;
  841. goto out;
  842. }
  843. ar->fw_patch_len = ie_len;
  844. break;
  845. case ATH6KL_FW_IE_RESERVED_RAM_SIZE:
  846. val = (__le32 *) data;
  847. ar->hw.reserved_ram_size = le32_to_cpup(val);
  848. ath6kl_dbg(ATH6KL_DBG_BOOT,
  849. "found reserved ram size ie 0x%d\n",
  850. ar->hw.reserved_ram_size);
  851. break;
  852. case ATH6KL_FW_IE_CAPABILITIES:
  853. ath6kl_dbg(ATH6KL_DBG_BOOT,
  854. "found firmware capabilities ie (%zd B)\n",
  855. ie_len);
  856. for (i = 0; i < ATH6KL_FW_CAPABILITY_MAX; i++) {
  857. index = i / 8;
  858. bit = i % 8;
  859. if (index == ie_len)
  860. break;
  861. if (data[index] & (1 << bit))
  862. __set_bit(i, ar->fw_capabilities);
  863. }
  864. ath6kl_dbg_dump(ATH6KL_DBG_BOOT, "capabilities", "",
  865. ar->fw_capabilities,
  866. sizeof(ar->fw_capabilities));
  867. break;
  868. case ATH6KL_FW_IE_PATCH_ADDR:
  869. if (ie_len != sizeof(*val))
  870. break;
  871. val = (__le32 *) data;
  872. ar->hw.dataset_patch_addr = le32_to_cpup(val);
  873. ath6kl_dbg(ATH6KL_DBG_BOOT,
  874. "found patch address ie 0x%x\n",
  875. ar->hw.dataset_patch_addr);
  876. break;
  877. case ATH6KL_FW_IE_BOARD_ADDR:
  878. if (ie_len != sizeof(*val))
  879. break;
  880. val = (__le32 *) data;
  881. ar->hw.board_addr = le32_to_cpup(val);
  882. ath6kl_dbg(ATH6KL_DBG_BOOT,
  883. "found board address ie 0x%x\n",
  884. ar->hw.board_addr);
  885. break;
  886. case ATH6KL_FW_IE_VIF_MAX:
  887. if (ie_len != sizeof(*val))
  888. break;
  889. val = (__le32 *) data;
  890. ar->vif_max = min_t(unsigned int, le32_to_cpup(val),
  891. ATH6KL_VIF_MAX);
  892. if (ar->vif_max > 1 && !ar->p2p)
  893. ar->max_norm_iface = 2;
  894. ath6kl_dbg(ATH6KL_DBG_BOOT,
  895. "found vif max ie %d\n", ar->vif_max);
  896. break;
  897. default:
  898. ath6kl_dbg(ATH6KL_DBG_BOOT, "Unknown fw ie: %u\n",
  899. le32_to_cpup(&hdr->id));
  900. break;
  901. }
  902. len -= ie_len;
  903. data += ie_len;
  904. };
  905. ret = 0;
  906. out:
  907. release_firmware(fw);
  908. return ret;
  909. }
  910. int ath6kl_init_fetch_firmwares(struct ath6kl *ar)
  911. {
  912. int ret;
  913. ret = ath6kl_fetch_board_file(ar);
  914. if (ret)
  915. return ret;
  916. ret = ath6kl_fetch_testmode_file(ar);
  917. if (ret)
  918. return ret;
  919. ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API4_FILE);
  920. if (ret == 0) {
  921. ar->fw_api = 4;
  922. goto out;
  923. }
  924. ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API3_FILE);
  925. if (ret == 0) {
  926. ar->fw_api = 3;
  927. goto out;
  928. }
  929. ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API2_FILE);
  930. if (ret == 0) {
  931. ar->fw_api = 2;
  932. goto out;
  933. }
  934. ret = ath6kl_fetch_fw_api1(ar);
  935. if (ret)
  936. return ret;
  937. ar->fw_api = 1;
  938. out:
  939. ath6kl_dbg(ATH6KL_DBG_BOOT, "using fw api %d\n", ar->fw_api);
  940. return 0;
  941. }
  942. static int ath6kl_upload_board_file(struct ath6kl *ar)
  943. {
  944. u32 board_address, board_ext_address, param;
  945. u32 board_data_size, board_ext_data_size;
  946. int ret;
  947. if (WARN_ON(ar->fw_board == NULL))
  948. return -ENOENT;
  949. /*
  950. * Determine where in Target RAM to write Board Data.
  951. * For AR6004, host determine Target RAM address for
  952. * writing board data.
  953. */
  954. if (ar->hw.board_addr != 0) {
  955. board_address = ar->hw.board_addr;
  956. ath6kl_bmi_write_hi32(ar, hi_board_data,
  957. board_address);
  958. } else {
  959. ath6kl_bmi_read_hi32(ar, hi_board_data, &board_address);
  960. }
  961. /* determine where in target ram to write extended board data */
  962. ath6kl_bmi_read_hi32(ar, hi_board_ext_data, &board_ext_address);
  963. if (ar->target_type == TARGET_TYPE_AR6003 &&
  964. board_ext_address == 0) {
  965. ath6kl_err("Failed to get board file target address.\n");
  966. return -EINVAL;
  967. }
  968. switch (ar->target_type) {
  969. case TARGET_TYPE_AR6003:
  970. board_data_size = AR6003_BOARD_DATA_SZ;
  971. board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ;
  972. if (ar->fw_board_len > (board_data_size + board_ext_data_size))
  973. board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ_V2;
  974. break;
  975. case TARGET_TYPE_AR6004:
  976. board_data_size = AR6004_BOARD_DATA_SZ;
  977. board_ext_data_size = AR6004_BOARD_EXT_DATA_SZ;
  978. break;
  979. default:
  980. WARN_ON(1);
  981. return -EINVAL;
  982. break;
  983. }
  984. if (board_ext_address &&
  985. ar->fw_board_len == (board_data_size + board_ext_data_size)) {
  986. /* write extended board data */
  987. ath6kl_dbg(ATH6KL_DBG_BOOT,
  988. "writing extended board data to 0x%x (%d B)\n",
  989. board_ext_address, board_ext_data_size);
  990. ret = ath6kl_bmi_write(ar, board_ext_address,
  991. ar->fw_board + board_data_size,
  992. board_ext_data_size);
  993. if (ret) {
  994. ath6kl_err("Failed to write extended board data: %d\n",
  995. ret);
  996. return ret;
  997. }
  998. /* record that extended board data is initialized */
  999. param = (board_ext_data_size << 16) | 1;
  1000. ath6kl_bmi_write_hi32(ar, hi_board_ext_data_config, param);
  1001. }
  1002. if (ar->fw_board_len < board_data_size) {
  1003. ath6kl_err("Too small board file: %zu\n", ar->fw_board_len);
  1004. ret = -EINVAL;
  1005. return ret;
  1006. }
  1007. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing board file to 0x%x (%d B)\n",
  1008. board_address, board_data_size);
  1009. ret = ath6kl_bmi_write(ar, board_address, ar->fw_board,
  1010. board_data_size);
  1011. if (ret) {
  1012. ath6kl_err("Board file bmi write failed: %d\n", ret);
  1013. return ret;
  1014. }
  1015. /* record the fact that Board Data IS initialized */
  1016. ath6kl_bmi_write_hi32(ar, hi_board_data_initialized, 1);
  1017. return ret;
  1018. }
  1019. static int ath6kl_upload_otp(struct ath6kl *ar)
  1020. {
  1021. u32 address, param;
  1022. bool from_hw = false;
  1023. int ret;
  1024. if (ar->fw_otp == NULL)
  1025. return 0;
  1026. address = ar->hw.app_load_addr;
  1027. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing otp to 0x%x (%zd B)\n", address,
  1028. ar->fw_otp_len);
  1029. ret = ath6kl_bmi_fast_download(ar, address, ar->fw_otp,
  1030. ar->fw_otp_len);
  1031. if (ret) {
  1032. ath6kl_err("Failed to upload OTP file: %d\n", ret);
  1033. return ret;
  1034. }
  1035. /* read firmware start address */
  1036. ret = ath6kl_bmi_read_hi32(ar, hi_app_start, &address);
  1037. if (ret) {
  1038. ath6kl_err("Failed to read hi_app_start: %d\n", ret);
  1039. return ret;
  1040. }
  1041. if (ar->hw.app_start_override_addr == 0) {
  1042. ar->hw.app_start_override_addr = address;
  1043. from_hw = true;
  1044. }
  1045. ath6kl_dbg(ATH6KL_DBG_BOOT, "app_start_override_addr%s 0x%x\n",
  1046. from_hw ? " (from hw)" : "",
  1047. ar->hw.app_start_override_addr);
  1048. /* execute the OTP code */
  1049. ath6kl_dbg(ATH6KL_DBG_BOOT, "executing OTP at 0x%x\n",
  1050. ar->hw.app_start_override_addr);
  1051. param = 0;
  1052. ath6kl_bmi_execute(ar, ar->hw.app_start_override_addr, &param);
  1053. return ret;
  1054. }
  1055. static int ath6kl_upload_firmware(struct ath6kl *ar)
  1056. {
  1057. u32 address;
  1058. int ret;
  1059. if (WARN_ON(ar->fw == NULL))
  1060. return 0;
  1061. address = ar->hw.app_load_addr;
  1062. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing firmware to 0x%x (%zd B)\n",
  1063. address, ar->fw_len);
  1064. ret = ath6kl_bmi_fast_download(ar, address, ar->fw, ar->fw_len);
  1065. if (ret) {
  1066. ath6kl_err("Failed to write firmware: %d\n", ret);
  1067. return ret;
  1068. }
  1069. /*
  1070. * Set starting address for firmware
  1071. * Don't need to setup app_start override addr on AR6004
  1072. */
  1073. if (ar->target_type != TARGET_TYPE_AR6004) {
  1074. address = ar->hw.app_start_override_addr;
  1075. ath6kl_bmi_set_app_start(ar, address);
  1076. }
  1077. return ret;
  1078. }
  1079. static int ath6kl_upload_patch(struct ath6kl *ar)
  1080. {
  1081. u32 address;
  1082. int ret;
  1083. if (ar->fw_patch == NULL)
  1084. return 0;
  1085. address = ar->hw.dataset_patch_addr;
  1086. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing patch to 0x%x (%zd B)\n",
  1087. address, ar->fw_patch_len);
  1088. ret = ath6kl_bmi_write(ar, address, ar->fw_patch, ar->fw_patch_len);
  1089. if (ret) {
  1090. ath6kl_err("Failed to write patch file: %d\n", ret);
  1091. return ret;
  1092. }
  1093. ath6kl_bmi_write_hi32(ar, hi_dset_list_head, address);
  1094. return 0;
  1095. }
  1096. static int ath6kl_upload_testscript(struct ath6kl *ar)
  1097. {
  1098. u32 address;
  1099. int ret;
  1100. if (ar->testmode != 2)
  1101. return 0;
  1102. if (ar->fw_testscript == NULL)
  1103. return 0;
  1104. address = ar->hw.testscript_addr;
  1105. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing testscript to 0x%x (%zd B)\n",
  1106. address, ar->fw_testscript_len);
  1107. ret = ath6kl_bmi_write(ar, address, ar->fw_testscript,
  1108. ar->fw_testscript_len);
  1109. if (ret) {
  1110. ath6kl_err("Failed to write testscript file: %d\n", ret);
  1111. return ret;
  1112. }
  1113. ath6kl_bmi_write_hi32(ar, hi_ota_testscript, address);
  1114. ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz, 4096);
  1115. ath6kl_bmi_write_hi32(ar, hi_test_apps_related, 1);
  1116. return 0;
  1117. }
  1118. static int ath6kl_init_upload(struct ath6kl *ar)
  1119. {
  1120. u32 param, options, sleep, address;
  1121. int status = 0;
  1122. if (ar->target_type != TARGET_TYPE_AR6003 &&
  1123. ar->target_type != TARGET_TYPE_AR6004)
  1124. return -EINVAL;
  1125. /* temporarily disable system sleep */
  1126. address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
  1127. status = ath6kl_bmi_reg_read(ar, address, &param);
  1128. if (status)
  1129. return status;
  1130. options = param;
  1131. param |= ATH6KL_OPTION_SLEEP_DISABLE;
  1132. status = ath6kl_bmi_reg_write(ar, address, param);
  1133. if (status)
  1134. return status;
  1135. address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
  1136. status = ath6kl_bmi_reg_read(ar, address, &param);
  1137. if (status)
  1138. return status;
  1139. sleep = param;
  1140. param |= SM(SYSTEM_SLEEP_DISABLE, 1);
  1141. status = ath6kl_bmi_reg_write(ar, address, param);
  1142. if (status)
  1143. return status;
  1144. ath6kl_dbg(ATH6KL_DBG_TRC, "old options: %d, old sleep: %d\n",
  1145. options, sleep);
  1146. /* program analog PLL register */
  1147. /* no need to control 40/44MHz clock on AR6004 */
  1148. if (ar->target_type != TARGET_TYPE_AR6004) {
  1149. status = ath6kl_bmi_reg_write(ar, ATH6KL_ANALOG_PLL_REGISTER,
  1150. 0xF9104001);
  1151. if (status)
  1152. return status;
  1153. /* Run at 80/88MHz by default */
  1154. param = SM(CPU_CLOCK_STANDARD, 1);
  1155. address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS;
  1156. status = ath6kl_bmi_reg_write(ar, address, param);
  1157. if (status)
  1158. return status;
  1159. }
  1160. param = 0;
  1161. address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS;
  1162. param = SM(LPO_CAL_ENABLE, 1);
  1163. status = ath6kl_bmi_reg_write(ar, address, param);
  1164. if (status)
  1165. return status;
  1166. /* WAR to avoid SDIO CRC err */
  1167. if (ar->version.target_ver == AR6003_HW_2_0_VERSION ||
  1168. ar->version.target_ver == AR6003_HW_2_1_1_VERSION) {
  1169. ath6kl_err("temporary war to avoid sdio crc error\n");
  1170. param = 0x28;
  1171. address = GPIO_BASE_ADDRESS + GPIO_PIN9_ADDRESS;
  1172. status = ath6kl_bmi_reg_write(ar, address, param);
  1173. if (status)
  1174. return status;
  1175. param = 0x20;
  1176. address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS;
  1177. status = ath6kl_bmi_reg_write(ar, address, param);
  1178. if (status)
  1179. return status;
  1180. address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS;
  1181. status = ath6kl_bmi_reg_write(ar, address, param);
  1182. if (status)
  1183. return status;
  1184. address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS;
  1185. status = ath6kl_bmi_reg_write(ar, address, param);
  1186. if (status)
  1187. return status;
  1188. address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS;
  1189. status = ath6kl_bmi_reg_write(ar, address, param);
  1190. if (status)
  1191. return status;
  1192. }
  1193. /* write EEPROM data to Target RAM */
  1194. status = ath6kl_upload_board_file(ar);
  1195. if (status)
  1196. return status;
  1197. /* transfer One time Programmable data */
  1198. status = ath6kl_upload_otp(ar);
  1199. if (status)
  1200. return status;
  1201. /* Download Target firmware */
  1202. status = ath6kl_upload_firmware(ar);
  1203. if (status)
  1204. return status;
  1205. status = ath6kl_upload_patch(ar);
  1206. if (status)
  1207. return status;
  1208. /* Download the test script */
  1209. status = ath6kl_upload_testscript(ar);
  1210. if (status)
  1211. return status;
  1212. /* Restore system sleep */
  1213. address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
  1214. status = ath6kl_bmi_reg_write(ar, address, sleep);
  1215. if (status)
  1216. return status;
  1217. address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
  1218. param = options | 0x20;
  1219. status = ath6kl_bmi_reg_write(ar, address, param);
  1220. if (status)
  1221. return status;
  1222. return status;
  1223. }
  1224. int ath6kl_init_hw_params(struct ath6kl *ar)
  1225. {
  1226. const struct ath6kl_hw *uninitialized_var(hw);
  1227. int i;
  1228. for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
  1229. hw = &hw_list[i];
  1230. if (hw->id == ar->version.target_ver)
  1231. break;
  1232. }
  1233. if (i == ARRAY_SIZE(hw_list)) {
  1234. ath6kl_err("Unsupported hardware version: 0x%x\n",
  1235. ar->version.target_ver);
  1236. return -EINVAL;
  1237. }
  1238. ar->hw = *hw;
  1239. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1240. "target_ver 0x%x target_type 0x%x dataset_patch 0x%x app_load_addr 0x%x\n",
  1241. ar->version.target_ver, ar->target_type,
  1242. ar->hw.dataset_patch_addr, ar->hw.app_load_addr);
  1243. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1244. "app_start_override_addr 0x%x board_ext_data_addr 0x%x reserved_ram_size 0x%x",
  1245. ar->hw.app_start_override_addr, ar->hw.board_ext_data_addr,
  1246. ar->hw.reserved_ram_size);
  1247. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1248. "refclk_hz %d uarttx_pin %d",
  1249. ar->hw.refclk_hz, ar->hw.uarttx_pin);
  1250. return 0;
  1251. }
  1252. static const char *ath6kl_init_get_hif_name(enum ath6kl_hif_type type)
  1253. {
  1254. switch (type) {
  1255. case ATH6KL_HIF_TYPE_SDIO:
  1256. return "sdio";
  1257. case ATH6KL_HIF_TYPE_USB:
  1258. return "usb";
  1259. }
  1260. return NULL;
  1261. }
  1262. static int __ath6kl_init_hw_start(struct ath6kl *ar)
  1263. {
  1264. long timeleft;
  1265. int ret, i;
  1266. ath6kl_dbg(ATH6KL_DBG_BOOT, "hw start\n");
  1267. ret = ath6kl_hif_power_on(ar);
  1268. if (ret)
  1269. return ret;
  1270. ret = ath6kl_configure_target(ar);
  1271. if (ret)
  1272. goto err_power_off;
  1273. ret = ath6kl_init_upload(ar);
  1274. if (ret)
  1275. goto err_power_off;
  1276. /* Do we need to finish the BMI phase */
  1277. /* FIXME: return error from ath6kl_bmi_done() */
  1278. if (ath6kl_bmi_done(ar)) {
  1279. ret = -EIO;
  1280. goto err_power_off;
  1281. }
  1282. /*
  1283. * The reason we have to wait for the target here is that the
  1284. * driver layer has to init BMI in order to set the host block
  1285. * size.
  1286. */
  1287. if (ath6kl_htc_wait_target(ar->htc_target)) {
  1288. ret = -EIO;
  1289. goto err_power_off;
  1290. }
  1291. if (ath6kl_init_service_ep(ar)) {
  1292. ret = -EIO;
  1293. goto err_cleanup_scatter;
  1294. }
  1295. /* setup credit distribution */
  1296. ath6kl_htc_credit_setup(ar->htc_target, &ar->credit_state_info);
  1297. /* start HTC */
  1298. ret = ath6kl_htc_start(ar->htc_target);
  1299. if (ret) {
  1300. /* FIXME: call this */
  1301. ath6kl_cookie_cleanup(ar);
  1302. goto err_cleanup_scatter;
  1303. }
  1304. /* Wait for Wmi event to be ready */
  1305. timeleft = wait_event_interruptible_timeout(ar->event_wq,
  1306. test_bit(WMI_READY,
  1307. &ar->flag),
  1308. WMI_TIMEOUT);
  1309. ath6kl_dbg(ATH6KL_DBG_BOOT, "firmware booted\n");
  1310. if (test_and_clear_bit(FIRST_BOOT, &ar->flag)) {
  1311. ath6kl_info("%s %s fw %s api %d%s\n",
  1312. ar->hw.name,
  1313. ath6kl_init_get_hif_name(ar->hif_type),
  1314. ar->wiphy->fw_version,
  1315. ar->fw_api,
  1316. test_bit(TESTMODE, &ar->flag) ? " testmode" : "");
  1317. }
  1318. if (ar->version.abi_ver != ATH6KL_ABI_VERSION) {
  1319. ath6kl_err("abi version mismatch: host(0x%x), target(0x%x)\n",
  1320. ATH6KL_ABI_VERSION, ar->version.abi_ver);
  1321. ret = -EIO;
  1322. goto err_htc_stop;
  1323. }
  1324. if (!timeleft || signal_pending(current)) {
  1325. ath6kl_err("wmi is not ready or wait was interrupted\n");
  1326. ret = -EIO;
  1327. goto err_htc_stop;
  1328. }
  1329. ath6kl_dbg(ATH6KL_DBG_TRC, "%s: wmi is ready\n", __func__);
  1330. /* communicate the wmi protocol verision to the target */
  1331. /* FIXME: return error */
  1332. if ((ath6kl_set_host_app_area(ar)) != 0)
  1333. ath6kl_err("unable to set the host app area\n");
  1334. for (i = 0; i < ar->vif_max; i++) {
  1335. ret = ath6kl_target_config_wlan_params(ar, i);
  1336. if (ret)
  1337. goto err_htc_stop;
  1338. }
  1339. return 0;
  1340. err_htc_stop:
  1341. ath6kl_htc_stop(ar->htc_target);
  1342. err_cleanup_scatter:
  1343. ath6kl_hif_cleanup_scatter(ar);
  1344. err_power_off:
  1345. ath6kl_hif_power_off(ar);
  1346. return ret;
  1347. }
  1348. int ath6kl_init_hw_start(struct ath6kl *ar)
  1349. {
  1350. int err;
  1351. err = __ath6kl_init_hw_start(ar);
  1352. if (err)
  1353. return err;
  1354. ar->state = ATH6KL_STATE_ON;
  1355. return 0;
  1356. }
  1357. static int __ath6kl_init_hw_stop(struct ath6kl *ar)
  1358. {
  1359. int ret;
  1360. ath6kl_dbg(ATH6KL_DBG_BOOT, "hw stop\n");
  1361. ath6kl_htc_stop(ar->htc_target);
  1362. ath6kl_hif_stop(ar);
  1363. ath6kl_bmi_reset(ar);
  1364. ret = ath6kl_hif_power_off(ar);
  1365. if (ret)
  1366. ath6kl_warn("failed to power off hif: %d\n", ret);
  1367. return 0;
  1368. }
  1369. int ath6kl_init_hw_stop(struct ath6kl *ar)
  1370. {
  1371. int err;
  1372. err = __ath6kl_init_hw_stop(ar);
  1373. if (err)
  1374. return err;
  1375. ar->state = ATH6KL_STATE_OFF;
  1376. return 0;
  1377. }
  1378. void ath6kl_init_hw_restart(struct ath6kl *ar)
  1379. {
  1380. clear_bit(WMI_READY, &ar->flag);
  1381. ath6kl_cfg80211_stop_all(ar);
  1382. if (__ath6kl_init_hw_stop(ar)) {
  1383. ath6kl_dbg(ATH6KL_DBG_RECOVERY, "Failed to stop during fw error recovery\n");
  1384. return;
  1385. }
  1386. if (__ath6kl_init_hw_start(ar)) {
  1387. ath6kl_dbg(ATH6KL_DBG_RECOVERY, "Failed to restart during fw error recovery\n");
  1388. return;
  1389. }
  1390. }
  1391. /* FIXME: move this to cfg80211.c and rename to ath6kl_cfg80211_vif_stop() */
  1392. void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready)
  1393. {
  1394. static u8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  1395. bool discon_issued;
  1396. netif_stop_queue(vif->ndev);
  1397. clear_bit(WLAN_ENABLED, &vif->flags);
  1398. if (wmi_ready) {
  1399. discon_issued = test_bit(CONNECTED, &vif->flags) ||
  1400. test_bit(CONNECT_PEND, &vif->flags);
  1401. ath6kl_disconnect(vif);
  1402. del_timer(&vif->disconnect_timer);
  1403. if (discon_issued)
  1404. ath6kl_disconnect_event(vif, DISCONNECT_CMD,
  1405. (vif->nw_type & AP_NETWORK) ?
  1406. bcast_mac : vif->bssid,
  1407. 0, NULL, 0);
  1408. }
  1409. if (vif->scan_req) {
  1410. cfg80211_scan_done(vif->scan_req, true);
  1411. vif->scan_req = NULL;
  1412. }
  1413. /* need to clean up enhanced bmiss detection fw state */
  1414. ath6kl_cfg80211_sta_bmiss_enhance(vif, false);
  1415. }
  1416. void ath6kl_stop_txrx(struct ath6kl *ar)
  1417. {
  1418. struct ath6kl_vif *vif, *tmp_vif;
  1419. int i;
  1420. set_bit(DESTROY_IN_PROGRESS, &ar->flag);
  1421. if (down_interruptible(&ar->sem)) {
  1422. ath6kl_err("down_interruptible failed\n");
  1423. return;
  1424. }
  1425. for (i = 0; i < AP_MAX_NUM_STA; i++)
  1426. aggr_reset_state(ar->sta_list[i].aggr_conn);
  1427. spin_lock_bh(&ar->list_lock);
  1428. list_for_each_entry_safe(vif, tmp_vif, &ar->vif_list, list) {
  1429. list_del(&vif->list);
  1430. spin_unlock_bh(&ar->list_lock);
  1431. ath6kl_cleanup_vif(vif, test_bit(WMI_READY, &ar->flag));
  1432. rtnl_lock();
  1433. ath6kl_cfg80211_vif_cleanup(vif);
  1434. rtnl_unlock();
  1435. spin_lock_bh(&ar->list_lock);
  1436. }
  1437. spin_unlock_bh(&ar->list_lock);
  1438. clear_bit(WMI_READY, &ar->flag);
  1439. /*
  1440. * After wmi_shudown all WMI events will be dropped. We
  1441. * need to cleanup the buffers allocated in AP mode and
  1442. * give disconnect notification to stack, which usually
  1443. * happens in the disconnect_event. Simulate the disconnect
  1444. * event by calling the function directly. Sometimes
  1445. * disconnect_event will be received when the debug logs
  1446. * are collected.
  1447. */
  1448. ath6kl_wmi_shutdown(ar->wmi);
  1449. clear_bit(WMI_ENABLED, &ar->flag);
  1450. if (ar->htc_target) {
  1451. ath6kl_dbg(ATH6KL_DBG_TRC, "%s: shut down htc\n", __func__);
  1452. ath6kl_htc_stop(ar->htc_target);
  1453. }
  1454. /*
  1455. * Try to reset the device if we can. The driver may have been
  1456. * configure NOT to reset the target during a debug session.
  1457. */
  1458. ath6kl_dbg(ATH6KL_DBG_TRC,
  1459. "attempting to reset target on instance destroy\n");
  1460. ath6kl_reset_device(ar, ar->target_type, true, true);
  1461. clear_bit(WLAN_ENABLED, &ar->flag);
  1462. up(&ar->sem);
  1463. }
  1464. EXPORT_SYMBOL(ath6kl_stop_txrx);