mx51_efika.c 4.4 KB

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  1. /*
  2. * based on code from the following
  3. * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  4. * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
  5. * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
  6. *
  7. * The code contained herein is licensed under the GNU General Public
  8. * License. You may obtain a copy of the GNU General Public License
  9. * Version 2 or later at the following locations:
  10. *
  11. * http://www.opensource.org/licenses/gpl-license.html
  12. * http://www.gnu.org/copyleft/gpl.html
  13. */
  14. #include <linux/init.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/i2c.h>
  17. #include <linux/gpio.h>
  18. #include <linux/leds.h>
  19. #include <linux/input.h>
  20. #include <linux/delay.h>
  21. #include <linux/io.h>
  22. #include <linux/fsl_devices.h>
  23. #include <linux/spi/flash.h>
  24. #include <linux/spi/spi.h>
  25. #include <mach/common.h>
  26. #include <mach/hardware.h>
  27. #include <mach/iomux-mx51.h>
  28. #include <mach/i2c.h>
  29. #include <mach/mxc_ehci.h>
  30. #include <asm/irq.h>
  31. #include <asm/setup.h>
  32. #include <asm/mach-types.h>
  33. #include <asm/mach/arch.h>
  34. #include <asm/mach/time.h>
  35. #include "devices-imx51.h"
  36. #include "devices.h"
  37. #include "efika.h"
  38. #define MX51_USB_PLL_DIV_24_MHZ 0x01
  39. #define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24)
  40. #define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25)
  41. static iomux_v3_cfg_t mx51efika_pads[] = {
  42. /* UART1 */
  43. MX51_PAD_UART1_RXD__UART1_RXD,
  44. MX51_PAD_UART1_TXD__UART1_TXD,
  45. MX51_PAD_UART1_RTS__UART1_RTS,
  46. MX51_PAD_UART1_CTS__UART1_CTS,
  47. /* SD 1 */
  48. MX51_PAD_SD1_CMD__SD1_CMD,
  49. MX51_PAD_SD1_CLK__SD1_CLK,
  50. MX51_PAD_SD1_DATA0__SD1_DATA0,
  51. MX51_PAD_SD1_DATA1__SD1_DATA1,
  52. MX51_PAD_SD1_DATA2__SD1_DATA2,
  53. MX51_PAD_SD1_DATA3__SD1_DATA3,
  54. /* SD 2 */
  55. MX51_PAD_SD2_CMD__SD2_CMD,
  56. MX51_PAD_SD2_CLK__SD2_CLK,
  57. MX51_PAD_SD2_DATA0__SD2_DATA0,
  58. MX51_PAD_SD2_DATA1__SD2_DATA1,
  59. MX51_PAD_SD2_DATA2__SD2_DATA2,
  60. MX51_PAD_SD2_DATA3__SD2_DATA3,
  61. /* SD/MMC WP/CD */
  62. MX51_PAD_GPIO1_0__SD1_CD,
  63. MX51_PAD_GPIO1_1__SD1_WP,
  64. MX51_PAD_GPIO1_7__SD2_WP,
  65. MX51_PAD_GPIO1_8__SD2_CD,
  66. /* spi */
  67. MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
  68. MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
  69. MX51_PAD_CSPI1_SS0__GPIO4_24,
  70. MX51_PAD_CSPI1_SS1__GPIO4_25,
  71. MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
  72. MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
  73. };
  74. /* Serial ports */
  75. static const struct imxuart_platform_data uart_pdata = {
  76. .flags = IMXUART_HAVE_RTSCTS,
  77. };
  78. /* This function is board specific as the bit mask for the plldiv will also
  79. * be different for other Freescale SoCs, thus a common bitmask is not
  80. * possible and cannot get place in /plat-mxc/ehci.c.
  81. */
  82. static int initialize_otg_port(struct platform_device *pdev)
  83. {
  84. u32 v;
  85. void __iomem *usb_base;
  86. void __iomem *usbother_base;
  87. usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
  88. if (!usb_base)
  89. return -ENOMEM;
  90. usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
  91. /* Set the PHY clock to 19.2MHz */
  92. v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
  93. v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
  94. v |= MX51_USB_PLL_DIV_24_MHZ;
  95. __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
  96. iounmap(usb_base);
  97. mdelay(10);
  98. return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
  99. }
  100. static struct mxc_usbh_platform_data dr_utmi_config = {
  101. .init = initialize_otg_port,
  102. .portsc = MXC_EHCI_UTMI_16BIT,
  103. };
  104. static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
  105. {
  106. .name = "u-boot",
  107. .offset = 0,
  108. .size = SZ_256K,
  109. },
  110. {
  111. .name = "config",
  112. .offset = MTDPART_OFS_APPEND,
  113. .size = SZ_64K,
  114. },
  115. };
  116. static struct flash_platform_data mx51_efika_spi_flash_data = {
  117. .name = "spi_flash",
  118. .parts = mx51_efika_spi_nor_partitions,
  119. .nr_parts = ARRAY_SIZE(mx51_efika_spi_nor_partitions),
  120. .type = "sst25vf032b",
  121. };
  122. static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
  123. {
  124. .modalias = "m25p80",
  125. .max_speed_hz = 25000000,
  126. .bus_num = 0,
  127. .chip_select = 1,
  128. .platform_data = &mx51_efika_spi_flash_data,
  129. .irq = -1,
  130. },
  131. };
  132. static int mx51_efika_spi_cs[] = {
  133. EFIKAMX_SPI_CS0,
  134. EFIKAMX_SPI_CS1,
  135. };
  136. static const struct spi_imx_master mx51_efika_spi_pdata __initconst = {
  137. .chipselect = mx51_efika_spi_cs,
  138. .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs),
  139. };
  140. void __init efika_board_common_init(void)
  141. {
  142. mxc_iomux_v3_setup_multiple_pads(mx51efika_pads,
  143. ARRAY_SIZE(mx51efika_pads));
  144. mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
  145. imx51_add_imx_uart(0, &uart_pdata);
  146. imx51_add_sdhci_esdhc_imx(0, NULL);
  147. spi_register_board_info(mx51_efika_spi_board_info,
  148. ARRAY_SIZE(mx51_efika_spi_board_info));
  149. imx51_add_ecspi(0, &mx51_efika_spi_pdata);
  150. }