devices.c 16 KB

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  1. #include <linux/module.h>
  2. #include <linux/kernel.h>
  3. #include <linux/init.h>
  4. #include <linux/platform_device.h>
  5. #include <linux/dma-mapping.h>
  6. #include <asm/arch/gpio.h>
  7. #include <asm/arch/udc.h>
  8. #include <asm/arch/pxafb.h>
  9. #include <asm/arch/mmc.h>
  10. #include <asm/arch/irda.h>
  11. #include <asm/arch/i2c.h>
  12. #include <asm/arch/mfp-pxa27x.h>
  13. #include <asm/arch/ohci.h>
  14. #include <asm/arch/pxa27x_keypad.h>
  15. #include <asm/arch/camera.h>
  16. #include "devices.h"
  17. #include "generic.h"
  18. void __init pxa_register_device(struct platform_device *dev, void *data)
  19. {
  20. int ret;
  21. dev->dev.platform_data = data;
  22. ret = platform_device_register(dev);
  23. if (ret)
  24. dev_err(&dev->dev, "unable to register device: %d\n", ret);
  25. }
  26. static struct resource pxamci_resources[] = {
  27. [0] = {
  28. .start = 0x41100000,
  29. .end = 0x41100fff,
  30. .flags = IORESOURCE_MEM,
  31. },
  32. [1] = {
  33. .start = IRQ_MMC,
  34. .end = IRQ_MMC,
  35. .flags = IORESOURCE_IRQ,
  36. },
  37. [2] = {
  38. .start = 21,
  39. .end = 21,
  40. .flags = IORESOURCE_DMA,
  41. },
  42. [3] = {
  43. .start = 22,
  44. .end = 22,
  45. .flags = IORESOURCE_DMA,
  46. },
  47. };
  48. static u64 pxamci_dmamask = 0xffffffffUL;
  49. struct platform_device pxa_device_mci = {
  50. .name = "pxa2xx-mci",
  51. .id = 0,
  52. .dev = {
  53. .dma_mask = &pxamci_dmamask,
  54. .coherent_dma_mask = 0xffffffff,
  55. },
  56. .num_resources = ARRAY_SIZE(pxamci_resources),
  57. .resource = pxamci_resources,
  58. };
  59. void __init pxa_set_mci_info(struct pxamci_platform_data *info)
  60. {
  61. pxa_register_device(&pxa_device_mci, info);
  62. }
  63. static struct pxa2xx_udc_mach_info pxa_udc_info;
  64. void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
  65. {
  66. memcpy(&pxa_udc_info, info, sizeof *info);
  67. }
  68. static struct resource pxa2xx_udc_resources[] = {
  69. [0] = {
  70. .start = 0x40600000,
  71. .end = 0x4060ffff,
  72. .flags = IORESOURCE_MEM,
  73. },
  74. [1] = {
  75. .start = IRQ_USB,
  76. .end = IRQ_USB,
  77. .flags = IORESOURCE_IRQ,
  78. },
  79. };
  80. static u64 udc_dma_mask = ~(u32)0;
  81. struct platform_device pxa25x_device_udc = {
  82. .name = "pxa25x-udc",
  83. .id = -1,
  84. .resource = pxa2xx_udc_resources,
  85. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  86. .dev = {
  87. .platform_data = &pxa_udc_info,
  88. .dma_mask = &udc_dma_mask,
  89. }
  90. };
  91. struct platform_device pxa27x_device_udc = {
  92. .name = "pxa27x-udc",
  93. .id = -1,
  94. .resource = pxa2xx_udc_resources,
  95. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  96. .dev = {
  97. .platform_data = &pxa_udc_info,
  98. .dma_mask = &udc_dma_mask,
  99. }
  100. };
  101. static struct resource pxafb_resources[] = {
  102. [0] = {
  103. .start = 0x44000000,
  104. .end = 0x4400ffff,
  105. .flags = IORESOURCE_MEM,
  106. },
  107. [1] = {
  108. .start = IRQ_LCD,
  109. .end = IRQ_LCD,
  110. .flags = IORESOURCE_IRQ,
  111. },
  112. };
  113. static u64 fb_dma_mask = ~(u64)0;
  114. struct platform_device pxa_device_fb = {
  115. .name = "pxa2xx-fb",
  116. .id = -1,
  117. .dev = {
  118. .dma_mask = &fb_dma_mask,
  119. .coherent_dma_mask = 0xffffffff,
  120. },
  121. .num_resources = ARRAY_SIZE(pxafb_resources),
  122. .resource = pxafb_resources,
  123. };
  124. void __init set_pxa_fb_info(struct pxafb_mach_info *info)
  125. {
  126. pxa_register_device(&pxa_device_fb, info);
  127. }
  128. void __init set_pxa_fb_parent(struct device *parent_dev)
  129. {
  130. pxa_device_fb.dev.parent = parent_dev;
  131. }
  132. static struct resource pxa_resource_ffuart[] = {
  133. {
  134. .start = __PREG(FFUART),
  135. .end = __PREG(FFUART) + 35,
  136. .flags = IORESOURCE_MEM,
  137. }, {
  138. .start = IRQ_FFUART,
  139. .end = IRQ_FFUART,
  140. .flags = IORESOURCE_IRQ,
  141. }
  142. };
  143. struct platform_device pxa_device_ffuart= {
  144. .name = "pxa2xx-uart",
  145. .id = 0,
  146. .resource = pxa_resource_ffuart,
  147. .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
  148. };
  149. static struct resource pxa_resource_btuart[] = {
  150. {
  151. .start = __PREG(BTUART),
  152. .end = __PREG(BTUART) + 35,
  153. .flags = IORESOURCE_MEM,
  154. }, {
  155. .start = IRQ_BTUART,
  156. .end = IRQ_BTUART,
  157. .flags = IORESOURCE_IRQ,
  158. }
  159. };
  160. struct platform_device pxa_device_btuart = {
  161. .name = "pxa2xx-uart",
  162. .id = 1,
  163. .resource = pxa_resource_btuart,
  164. .num_resources = ARRAY_SIZE(pxa_resource_btuart),
  165. };
  166. static struct resource pxa_resource_stuart[] = {
  167. {
  168. .start = __PREG(STUART),
  169. .end = __PREG(STUART) + 35,
  170. .flags = IORESOURCE_MEM,
  171. }, {
  172. .start = IRQ_STUART,
  173. .end = IRQ_STUART,
  174. .flags = IORESOURCE_IRQ,
  175. }
  176. };
  177. struct platform_device pxa_device_stuart = {
  178. .name = "pxa2xx-uart",
  179. .id = 2,
  180. .resource = pxa_resource_stuart,
  181. .num_resources = ARRAY_SIZE(pxa_resource_stuart),
  182. };
  183. static struct resource pxa_resource_hwuart[] = {
  184. {
  185. .start = __PREG(HWUART),
  186. .end = __PREG(HWUART) + 47,
  187. .flags = IORESOURCE_MEM,
  188. }, {
  189. .start = IRQ_HWUART,
  190. .end = IRQ_HWUART,
  191. .flags = IORESOURCE_IRQ,
  192. }
  193. };
  194. struct platform_device pxa_device_hwuart = {
  195. .name = "pxa2xx-uart",
  196. .id = 3,
  197. .resource = pxa_resource_hwuart,
  198. .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
  199. };
  200. static struct resource pxai2c_resources[] = {
  201. {
  202. .start = 0x40301680,
  203. .end = 0x403016a3,
  204. .flags = IORESOURCE_MEM,
  205. }, {
  206. .start = IRQ_I2C,
  207. .end = IRQ_I2C,
  208. .flags = IORESOURCE_IRQ,
  209. },
  210. };
  211. struct platform_device pxa_device_i2c = {
  212. .name = "pxa2xx-i2c",
  213. .id = 0,
  214. .resource = pxai2c_resources,
  215. .num_resources = ARRAY_SIZE(pxai2c_resources),
  216. };
  217. static unsigned long pxa27x_i2c_mfp_cfg[] = {
  218. GPIO117_I2C_SCL,
  219. GPIO118_I2C_SDA,
  220. };
  221. void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
  222. {
  223. if (cpu_is_pxa27x())
  224. pxa2xx_mfp_config(ARRAY_AND_SIZE(pxa27x_i2c_mfp_cfg));
  225. pxa_register_device(&pxa_device_i2c, info);
  226. }
  227. static struct resource pxai2s_resources[] = {
  228. {
  229. .start = 0x40400000,
  230. .end = 0x40400083,
  231. .flags = IORESOURCE_MEM,
  232. }, {
  233. .start = IRQ_I2S,
  234. .end = IRQ_I2S,
  235. .flags = IORESOURCE_IRQ,
  236. },
  237. };
  238. struct platform_device pxa_device_i2s = {
  239. .name = "pxa2xx-i2s",
  240. .id = -1,
  241. .resource = pxai2s_resources,
  242. .num_resources = ARRAY_SIZE(pxai2s_resources),
  243. };
  244. static u64 pxaficp_dmamask = ~(u32)0;
  245. struct platform_device pxa_device_ficp = {
  246. .name = "pxa2xx-ir",
  247. .id = -1,
  248. .dev = {
  249. .dma_mask = &pxaficp_dmamask,
  250. .coherent_dma_mask = 0xffffffff,
  251. },
  252. };
  253. void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
  254. {
  255. pxa_register_device(&pxa_device_ficp, info);
  256. }
  257. struct platform_device pxa_device_rtc = {
  258. .name = "sa1100-rtc",
  259. .id = -1,
  260. };
  261. #ifdef CONFIG_PXA25x
  262. static struct resource pxa25x_resource_pwm0[] = {
  263. [0] = {
  264. .start = 0x40b00000,
  265. .end = 0x40b0000f,
  266. .flags = IORESOURCE_MEM,
  267. },
  268. };
  269. struct platform_device pxa25x_device_pwm0 = {
  270. .name = "pxa25x-pwm",
  271. .id = 0,
  272. .resource = pxa25x_resource_pwm0,
  273. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
  274. };
  275. static struct resource pxa25x_resource_pwm1[] = {
  276. [0] = {
  277. .start = 0x40c00000,
  278. .end = 0x40c0000f,
  279. .flags = IORESOURCE_MEM,
  280. },
  281. };
  282. struct platform_device pxa25x_device_pwm1 = {
  283. .name = "pxa25x-pwm",
  284. .id = 1,
  285. .resource = pxa25x_resource_pwm1,
  286. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
  287. };
  288. static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
  289. static struct resource pxa25x_resource_ssp[] = {
  290. [0] = {
  291. .start = 0x41000000,
  292. .end = 0x4100001f,
  293. .flags = IORESOURCE_MEM,
  294. },
  295. [1] = {
  296. .start = IRQ_SSP,
  297. .end = IRQ_SSP,
  298. .flags = IORESOURCE_IRQ,
  299. },
  300. [2] = {
  301. /* DRCMR for RX */
  302. .start = 13,
  303. .end = 13,
  304. .flags = IORESOURCE_DMA,
  305. },
  306. [3] = {
  307. /* DRCMR for TX */
  308. .start = 14,
  309. .end = 14,
  310. .flags = IORESOURCE_DMA,
  311. },
  312. };
  313. struct platform_device pxa25x_device_ssp = {
  314. .name = "pxa25x-ssp",
  315. .id = 0,
  316. .dev = {
  317. .dma_mask = &pxa25x_ssp_dma_mask,
  318. .coherent_dma_mask = DMA_BIT_MASK(32),
  319. },
  320. .resource = pxa25x_resource_ssp,
  321. .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
  322. };
  323. static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
  324. static struct resource pxa25x_resource_nssp[] = {
  325. [0] = {
  326. .start = 0x41400000,
  327. .end = 0x4140002f,
  328. .flags = IORESOURCE_MEM,
  329. },
  330. [1] = {
  331. .start = IRQ_NSSP,
  332. .end = IRQ_NSSP,
  333. .flags = IORESOURCE_IRQ,
  334. },
  335. [2] = {
  336. /* DRCMR for RX */
  337. .start = 15,
  338. .end = 15,
  339. .flags = IORESOURCE_DMA,
  340. },
  341. [3] = {
  342. /* DRCMR for TX */
  343. .start = 16,
  344. .end = 16,
  345. .flags = IORESOURCE_DMA,
  346. },
  347. };
  348. struct platform_device pxa25x_device_nssp = {
  349. .name = "pxa25x-nssp",
  350. .id = 1,
  351. .dev = {
  352. .dma_mask = &pxa25x_nssp_dma_mask,
  353. .coherent_dma_mask = DMA_BIT_MASK(32),
  354. },
  355. .resource = pxa25x_resource_nssp,
  356. .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
  357. };
  358. static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
  359. static struct resource pxa25x_resource_assp[] = {
  360. [0] = {
  361. .start = 0x41500000,
  362. .end = 0x4150002f,
  363. .flags = IORESOURCE_MEM,
  364. },
  365. [1] = {
  366. .start = IRQ_ASSP,
  367. .end = IRQ_ASSP,
  368. .flags = IORESOURCE_IRQ,
  369. },
  370. [2] = {
  371. /* DRCMR for RX */
  372. .start = 23,
  373. .end = 23,
  374. .flags = IORESOURCE_DMA,
  375. },
  376. [3] = {
  377. /* DRCMR for TX */
  378. .start = 24,
  379. .end = 24,
  380. .flags = IORESOURCE_DMA,
  381. },
  382. };
  383. struct platform_device pxa25x_device_assp = {
  384. /* ASSP is basically equivalent to NSSP */
  385. .name = "pxa25x-nssp",
  386. .id = 2,
  387. .dev = {
  388. .dma_mask = &pxa25x_assp_dma_mask,
  389. .coherent_dma_mask = DMA_BIT_MASK(32),
  390. },
  391. .resource = pxa25x_resource_assp,
  392. .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
  393. };
  394. #endif /* CONFIG_PXA25x */
  395. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  396. static struct resource pxa27x_resource_keypad[] = {
  397. [0] = {
  398. .start = 0x41500000,
  399. .end = 0x4150004c,
  400. .flags = IORESOURCE_MEM,
  401. },
  402. [1] = {
  403. .start = IRQ_KEYPAD,
  404. .end = IRQ_KEYPAD,
  405. .flags = IORESOURCE_IRQ,
  406. },
  407. };
  408. struct platform_device pxa27x_device_keypad = {
  409. .name = "pxa27x-keypad",
  410. .id = -1,
  411. .resource = pxa27x_resource_keypad,
  412. .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
  413. };
  414. void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
  415. {
  416. pxa_register_device(&pxa27x_device_keypad, info);
  417. }
  418. static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
  419. static struct resource pxa27x_resource_ohci[] = {
  420. [0] = {
  421. .start = 0x4C000000,
  422. .end = 0x4C00ff6f,
  423. .flags = IORESOURCE_MEM,
  424. },
  425. [1] = {
  426. .start = IRQ_USBH1,
  427. .end = IRQ_USBH1,
  428. .flags = IORESOURCE_IRQ,
  429. },
  430. };
  431. struct platform_device pxa27x_device_ohci = {
  432. .name = "pxa27x-ohci",
  433. .id = -1,
  434. .dev = {
  435. .dma_mask = &pxa27x_ohci_dma_mask,
  436. .coherent_dma_mask = DMA_BIT_MASK(32),
  437. },
  438. .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
  439. .resource = pxa27x_resource_ohci,
  440. };
  441. void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
  442. {
  443. pxa_register_device(&pxa27x_device_ohci, info);
  444. }
  445. static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
  446. static struct resource pxa27x_resource_ssp1[] = {
  447. [0] = {
  448. .start = 0x41000000,
  449. .end = 0x4100003f,
  450. .flags = IORESOURCE_MEM,
  451. },
  452. [1] = {
  453. .start = IRQ_SSP,
  454. .end = IRQ_SSP,
  455. .flags = IORESOURCE_IRQ,
  456. },
  457. [2] = {
  458. /* DRCMR for RX */
  459. .start = 13,
  460. .end = 13,
  461. .flags = IORESOURCE_DMA,
  462. },
  463. [3] = {
  464. /* DRCMR for TX */
  465. .start = 14,
  466. .end = 14,
  467. .flags = IORESOURCE_DMA,
  468. },
  469. };
  470. struct platform_device pxa27x_device_ssp1 = {
  471. .name = "pxa27x-ssp",
  472. .id = 0,
  473. .dev = {
  474. .dma_mask = &pxa27x_ssp1_dma_mask,
  475. .coherent_dma_mask = DMA_BIT_MASK(32),
  476. },
  477. .resource = pxa27x_resource_ssp1,
  478. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  479. };
  480. static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
  481. static struct resource pxa27x_resource_ssp2[] = {
  482. [0] = {
  483. .start = 0x41700000,
  484. .end = 0x4170003f,
  485. .flags = IORESOURCE_MEM,
  486. },
  487. [1] = {
  488. .start = IRQ_SSP2,
  489. .end = IRQ_SSP2,
  490. .flags = IORESOURCE_IRQ,
  491. },
  492. [2] = {
  493. /* DRCMR for RX */
  494. .start = 15,
  495. .end = 15,
  496. .flags = IORESOURCE_DMA,
  497. },
  498. [3] = {
  499. /* DRCMR for TX */
  500. .start = 16,
  501. .end = 16,
  502. .flags = IORESOURCE_DMA,
  503. },
  504. };
  505. struct platform_device pxa27x_device_ssp2 = {
  506. .name = "pxa27x-ssp",
  507. .id = 1,
  508. .dev = {
  509. .dma_mask = &pxa27x_ssp2_dma_mask,
  510. .coherent_dma_mask = DMA_BIT_MASK(32),
  511. },
  512. .resource = pxa27x_resource_ssp2,
  513. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  514. };
  515. static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
  516. static struct resource pxa27x_resource_ssp3[] = {
  517. [0] = {
  518. .start = 0x41900000,
  519. .end = 0x4190003f,
  520. .flags = IORESOURCE_MEM,
  521. },
  522. [1] = {
  523. .start = IRQ_SSP3,
  524. .end = IRQ_SSP3,
  525. .flags = IORESOURCE_IRQ,
  526. },
  527. [2] = {
  528. /* DRCMR for RX */
  529. .start = 66,
  530. .end = 66,
  531. .flags = IORESOURCE_DMA,
  532. },
  533. [3] = {
  534. /* DRCMR for TX */
  535. .start = 67,
  536. .end = 67,
  537. .flags = IORESOURCE_DMA,
  538. },
  539. };
  540. struct platform_device pxa27x_device_ssp3 = {
  541. .name = "pxa27x-ssp",
  542. .id = 2,
  543. .dev = {
  544. .dma_mask = &pxa27x_ssp3_dma_mask,
  545. .coherent_dma_mask = DMA_BIT_MASK(32),
  546. },
  547. .resource = pxa27x_resource_ssp3,
  548. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  549. };
  550. static struct resource pxa27x_resource_pwm0[] = {
  551. [0] = {
  552. .start = 0x40b00000,
  553. .end = 0x40b0001f,
  554. .flags = IORESOURCE_MEM,
  555. },
  556. };
  557. struct platform_device pxa27x_device_pwm0 = {
  558. .name = "pxa27x-pwm",
  559. .id = 0,
  560. .resource = pxa27x_resource_pwm0,
  561. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
  562. };
  563. static struct resource pxa27x_resource_pwm1[] = {
  564. [0] = {
  565. .start = 0x40c00000,
  566. .end = 0x40c0001f,
  567. .flags = IORESOURCE_MEM,
  568. },
  569. };
  570. struct platform_device pxa27x_device_pwm1 = {
  571. .name = "pxa27x-pwm",
  572. .id = 1,
  573. .resource = pxa27x_resource_pwm1,
  574. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
  575. };
  576. static struct resource pxa27x_resource_camera[] = {
  577. [0] = {
  578. .start = 0x50000000,
  579. .end = 0x50000fff,
  580. .flags = IORESOURCE_MEM,
  581. },
  582. [1] = {
  583. .start = IRQ_CAMERA,
  584. .end = IRQ_CAMERA,
  585. .flags = IORESOURCE_IRQ,
  586. },
  587. };
  588. static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
  589. static struct platform_device pxa27x_device_camera = {
  590. .name = "pxa27x-camera",
  591. .id = 0, /* This is used to put cameras on this interface */
  592. .dev = {
  593. .dma_mask = &pxa27x_dma_mask_camera,
  594. .coherent_dma_mask = 0xffffffff,
  595. },
  596. .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
  597. .resource = pxa27x_resource_camera,
  598. };
  599. void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
  600. {
  601. pxa_register_device(&pxa27x_device_camera, info);
  602. }
  603. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  604. #ifdef CONFIG_PXA3xx
  605. static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
  606. static struct resource pxa3xx_resource_ssp4[] = {
  607. [0] = {
  608. .start = 0x41a00000,
  609. .end = 0x41a0003f,
  610. .flags = IORESOURCE_MEM,
  611. },
  612. [1] = {
  613. .start = IRQ_SSP4,
  614. .end = IRQ_SSP4,
  615. .flags = IORESOURCE_IRQ,
  616. },
  617. [2] = {
  618. /* DRCMR for RX */
  619. .start = 2,
  620. .end = 2,
  621. .flags = IORESOURCE_DMA,
  622. },
  623. [3] = {
  624. /* DRCMR for TX */
  625. .start = 3,
  626. .end = 3,
  627. .flags = IORESOURCE_DMA,
  628. },
  629. };
  630. struct platform_device pxa3xx_device_ssp4 = {
  631. /* PXA3xx SSP is basically equivalent to PXA27x */
  632. .name = "pxa27x-ssp",
  633. .id = 3,
  634. .dev = {
  635. .dma_mask = &pxa3xx_ssp4_dma_mask,
  636. .coherent_dma_mask = DMA_BIT_MASK(32),
  637. },
  638. .resource = pxa3xx_resource_ssp4,
  639. .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
  640. };
  641. static struct resource pxa3xx_resources_mci2[] = {
  642. [0] = {
  643. .start = 0x42000000,
  644. .end = 0x42000fff,
  645. .flags = IORESOURCE_MEM,
  646. },
  647. [1] = {
  648. .start = IRQ_MMC2,
  649. .end = IRQ_MMC2,
  650. .flags = IORESOURCE_IRQ,
  651. },
  652. [2] = {
  653. .start = 93,
  654. .end = 93,
  655. .flags = IORESOURCE_DMA,
  656. },
  657. [3] = {
  658. .start = 94,
  659. .end = 94,
  660. .flags = IORESOURCE_DMA,
  661. },
  662. };
  663. struct platform_device pxa3xx_device_mci2 = {
  664. .name = "pxa2xx-mci",
  665. .id = 1,
  666. .dev = {
  667. .dma_mask = &pxamci_dmamask,
  668. .coherent_dma_mask = 0xffffffff,
  669. },
  670. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
  671. .resource = pxa3xx_resources_mci2,
  672. };
  673. void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
  674. {
  675. pxa_register_device(&pxa3xx_device_mci2, info);
  676. }
  677. static struct resource pxa3xx_resources_mci3[] = {
  678. [0] = {
  679. .start = 0x42500000,
  680. .end = 0x42500fff,
  681. .flags = IORESOURCE_MEM,
  682. },
  683. [1] = {
  684. .start = IRQ_MMC3,
  685. .end = IRQ_MMC3,
  686. .flags = IORESOURCE_IRQ,
  687. },
  688. [2] = {
  689. .start = 100,
  690. .end = 100,
  691. .flags = IORESOURCE_DMA,
  692. },
  693. [3] = {
  694. .start = 101,
  695. .end = 101,
  696. .flags = IORESOURCE_DMA,
  697. },
  698. };
  699. struct platform_device pxa3xx_device_mci3 = {
  700. .name = "pxa2xx-mci",
  701. .id = 2,
  702. .dev = {
  703. .dma_mask = &pxamci_dmamask,
  704. .coherent_dma_mask = 0xffffffff,
  705. },
  706. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
  707. .resource = pxa3xx_resources_mci3,
  708. };
  709. void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
  710. {
  711. pxa_register_device(&pxa3xx_device_mci3, info);
  712. }
  713. #endif /* CONFIG_PXA3xx */