armada-370-xp.dtsi 5.0 KB

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  1. /*
  2. * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
  3. *
  4. * Copyright (C) 2012 Marvell
  5. *
  6. * Lior Amsalem <alior@marvell.com>
  7. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  8. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  9. * Ben Dooks <ben.dooks@codethink.co.uk>
  10. *
  11. * This file is licensed under the terms of the GNU General Public
  12. * License version 2. This program is licensed "as is" without any
  13. * warranty of any kind, whether express or implied.
  14. *
  15. * This file contains the definitions that are common to the Armada
  16. * 370 and Armada XP SoC.
  17. */
  18. /include/ "skeleton64.dtsi"
  19. / {
  20. model = "Marvell Armada 370 and XP SoC";
  21. compatible = "marvell,armada-370-xp";
  22. cpus {
  23. #address-cells = <1>;
  24. #size-cells = <0>;
  25. cpu@0 {
  26. compatible = "marvell,sheeva-v7";
  27. device_type = "cpu";
  28. reg = <0>;
  29. };
  30. };
  31. soc {
  32. #address-cells = <1>;
  33. #size-cells = <1>;
  34. compatible = "simple-bus";
  35. interrupt-parent = <&mpic>;
  36. ranges = <0 0 0xd0000000 0x100000>;
  37. internal-regs {
  38. compatible = "simple-bus";
  39. #address-cells = <1>;
  40. #size-cells = <1>;
  41. ranges;
  42. mpic: interrupt-controller@20000 {
  43. compatible = "marvell,mpic";
  44. #interrupt-cells = <1>;
  45. #size-cells = <1>;
  46. interrupt-controller;
  47. };
  48. coherency-fabric@20200 {
  49. compatible = "marvell,coherency-fabric";
  50. reg = <0x20200 0xb0>, <0x21810 0x1c>;
  51. };
  52. serial@12000 {
  53. compatible = "snps,dw-apb-uart";
  54. reg = <0x12000 0x100>;
  55. reg-shift = <2>;
  56. interrupts = <41>;
  57. reg-io-width = <1>;
  58. status = "disabled";
  59. };
  60. serial@12100 {
  61. compatible = "snps,dw-apb-uart";
  62. reg = <0x12100 0x100>;
  63. reg-shift = <2>;
  64. interrupts = <42>;
  65. reg-io-width = <1>;
  66. status = "disabled";
  67. };
  68. timer@20300 {
  69. compatible = "marvell,armada-370-xp-timer";
  70. reg = <0x20300 0x30>, <0x21040 0x30>;
  71. interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
  72. clocks = <&coreclk 2>;
  73. };
  74. sata@a0000 {
  75. compatible = "marvell,orion-sata";
  76. reg = <0xa0000 0x2400>;
  77. interrupts = <55>;
  78. clocks = <&gateclk 15>, <&gateclk 30>;
  79. clock-names = "0", "1";
  80. status = "disabled";
  81. };
  82. mdio {
  83. #address-cells = <1>;
  84. #size-cells = <0>;
  85. compatible = "marvell,orion-mdio";
  86. reg = <0x72004 0x4>;
  87. };
  88. ethernet@70000 {
  89. compatible = "marvell,armada-370-neta";
  90. reg = <0x70000 0x2500>;
  91. interrupts = <8>;
  92. clocks = <&gateclk 4>;
  93. status = "disabled";
  94. };
  95. ethernet@74000 {
  96. compatible = "marvell,armada-370-neta";
  97. reg = <0x74000 0x2500>;
  98. interrupts = <10>;
  99. clocks = <&gateclk 3>;
  100. status = "disabled";
  101. };
  102. i2c0: i2c@11000 {
  103. compatible = "marvell,mv64xxx-i2c";
  104. reg = <0x11000 0x20>;
  105. #address-cells = <1>;
  106. #size-cells = <0>;
  107. interrupts = <31>;
  108. timeout-ms = <1000>;
  109. clocks = <&coreclk 0>;
  110. status = "disabled";
  111. };
  112. i2c1: i2c@11100 {
  113. compatible = "marvell,mv64xxx-i2c";
  114. reg = <0x11100 0x20>;
  115. #address-cells = <1>;
  116. #size-cells = <0>;
  117. interrupts = <32>;
  118. timeout-ms = <1000>;
  119. clocks = <&coreclk 0>;
  120. status = "disabled";
  121. };
  122. rtc@10300 {
  123. compatible = "marvell,orion-rtc";
  124. reg = <0x10300 0x20>;
  125. interrupts = <50>;
  126. };
  127. mvsdio@d4000 {
  128. compatible = "marvell,orion-sdio";
  129. reg = <0xd4000 0x200>;
  130. interrupts = <54>;
  131. clocks = <&gateclk 17>;
  132. status = "disabled";
  133. };
  134. usb@50000 {
  135. compatible = "marvell,orion-ehci";
  136. reg = <0x50000 0x500>;
  137. interrupts = <45>;
  138. status = "disabled";
  139. };
  140. usb@51000 {
  141. compatible = "marvell,orion-ehci";
  142. reg = <0x51000 0x500>;
  143. interrupts = <46>;
  144. status = "disabled";
  145. };
  146. spi0: spi@10600 {
  147. compatible = "marvell,orion-spi";
  148. reg = <0x10600 0x28>;
  149. #address-cells = <1>;
  150. #size-cells = <0>;
  151. cell-index = <0>;
  152. interrupts = <30>;
  153. clocks = <&coreclk 0>;
  154. status = "disabled";
  155. };
  156. spi1: spi@10680 {
  157. compatible = "marvell,orion-spi";
  158. reg = <0x10680 0x28>;
  159. #address-cells = <1>;
  160. #size-cells = <0>;
  161. cell-index = <1>;
  162. interrupts = <92>;
  163. clocks = <&coreclk 0>;
  164. status = "disabled";
  165. };
  166. devbus-bootcs@10400 {
  167. compatible = "marvell,mvebu-devbus";
  168. reg = <0x10400 0x8>;
  169. #address-cells = <1>;
  170. #size-cells = <1>;
  171. clocks = <&coreclk 0>;
  172. status = "disabled";
  173. };
  174. devbus-cs0@10408 {
  175. compatible = "marvell,mvebu-devbus";
  176. reg = <0x10408 0x8>;
  177. #address-cells = <1>;
  178. #size-cells = <1>;
  179. clocks = <&coreclk 0>;
  180. status = "disabled";
  181. };
  182. devbus-cs1@10410 {
  183. compatible = "marvell,mvebu-devbus";
  184. reg = <0x10410 0x8>;
  185. #address-cells = <1>;
  186. #size-cells = <1>;
  187. clocks = <&coreclk 0>;
  188. status = "disabled";
  189. };
  190. devbus-cs2@10418 {
  191. compatible = "marvell,mvebu-devbus";
  192. reg = <0x10418 0x8>;
  193. #address-cells = <1>;
  194. #size-cells = <1>;
  195. clocks = <&coreclk 0>;
  196. status = "disabled";
  197. };
  198. devbus-cs3@10420 {
  199. compatible = "marvell,mvebu-devbus";
  200. reg = <0x10420 0x8>;
  201. #address-cells = <1>;
  202. #size-cells = <1>;
  203. clocks = <&coreclk 0>;
  204. status = "disabled";
  205. };
  206. };
  207. };
  208. };