entry_64.S 30 KB

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  1. /*
  2. * PowerPC version
  3. * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  4. * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
  5. * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
  6. * Adapted for Power Macintosh by Paul Mackerras.
  7. * Low-level exception handlers and MMU support
  8. * rewritten by Paul Mackerras.
  9. * Copyright (C) 1996 Paul Mackerras.
  10. * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
  11. *
  12. * This file contains the system call entry code, context switch
  13. * code, and exception/interrupt return code for PowerPC.
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License
  17. * as published by the Free Software Foundation; either version
  18. * 2 of the License, or (at your option) any later version.
  19. */
  20. #include <linux/errno.h>
  21. #include <asm/unistd.h>
  22. #include <asm/processor.h>
  23. #include <asm/page.h>
  24. #include <asm/mmu.h>
  25. #include <asm/thread_info.h>
  26. #include <asm/ppc_asm.h>
  27. #include <asm/asm-offsets.h>
  28. #include <asm/cputable.h>
  29. #include <asm/firmware.h>
  30. #include <asm/bug.h>
  31. #include <asm/ptrace.h>
  32. #include <asm/irqflags.h>
  33. #include <asm/ftrace.h>
  34. #include <asm/hw_irq.h>
  35. #include <asm/context_tracking.h>
  36. /*
  37. * System calls.
  38. */
  39. .section ".toc","aw"
  40. .SYS_CALL_TABLE:
  41. .tc .sys_call_table[TC],.sys_call_table
  42. /* This value is used to mark exception frames on the stack. */
  43. exception_marker:
  44. .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
  45. .section ".text"
  46. .align 7
  47. #undef SHOW_SYSCALLS
  48. .globl system_call_common
  49. system_call_common:
  50. andi. r10,r12,MSR_PR
  51. mr r10,r1
  52. addi r1,r1,-INT_FRAME_SIZE
  53. beq- 1f
  54. ld r1,PACAKSAVE(r13)
  55. 1: std r10,0(r1)
  56. std r11,_NIP(r1)
  57. std r12,_MSR(r1)
  58. std r0,GPR0(r1)
  59. std r10,GPR1(r1)
  60. beq 2f /* if from kernel mode */
  61. ACCOUNT_CPU_USER_ENTRY(r10, r11)
  62. 2: std r2,GPR2(r1)
  63. std r3,GPR3(r1)
  64. mfcr r2
  65. std r4,GPR4(r1)
  66. std r5,GPR5(r1)
  67. std r6,GPR6(r1)
  68. std r7,GPR7(r1)
  69. std r8,GPR8(r1)
  70. li r11,0
  71. std r11,GPR9(r1)
  72. std r11,GPR10(r1)
  73. std r11,GPR11(r1)
  74. std r11,GPR12(r1)
  75. std r11,_XER(r1)
  76. std r11,_CTR(r1)
  77. std r9,GPR13(r1)
  78. mflr r10
  79. /*
  80. * This clears CR0.SO (bit 28), which is the error indication on
  81. * return from this system call.
  82. */
  83. rldimi r2,r11,28,(63-28)
  84. li r11,0xc01
  85. std r10,_LINK(r1)
  86. std r11,_TRAP(r1)
  87. std r3,ORIG_GPR3(r1)
  88. std r2,_CCR(r1)
  89. ld r2,PACATOC(r13)
  90. addi r9,r1,STACK_FRAME_OVERHEAD
  91. ld r11,exception_marker@toc(r2)
  92. std r11,-16(r9) /* "regshere" marker */
  93. #if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(CONFIG_PPC_SPLPAR)
  94. BEGIN_FW_FTR_SECTION
  95. beq 33f
  96. /* if from user, see if there are any DTL entries to process */
  97. ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */
  98. ld r11,PACA_DTL_RIDX(r13) /* get log read index */
  99. ld r10,LPPACA_DTLIDX(r10) /* get log write index */
  100. cmpd cr1,r11,r10
  101. beq+ cr1,33f
  102. bl .accumulate_stolen_time
  103. REST_GPR(0,r1)
  104. REST_4GPRS(3,r1)
  105. REST_2GPRS(7,r1)
  106. addi r9,r1,STACK_FRAME_OVERHEAD
  107. 33:
  108. END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
  109. #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */
  110. /*
  111. * A syscall should always be called with interrupts enabled
  112. * so we just unconditionally hard-enable here. When some kind
  113. * of irq tracing is used, we additionally check that condition
  114. * is correct
  115. */
  116. #if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG)
  117. lbz r10,PACASOFTIRQEN(r13)
  118. xori r10,r10,1
  119. 1: tdnei r10,0
  120. EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
  121. #endif
  122. #ifdef CONFIG_PPC_BOOK3E
  123. wrteei 1
  124. #else
  125. ld r11,PACAKMSR(r13)
  126. ori r11,r11,MSR_EE
  127. mtmsrd r11,1
  128. #endif /* CONFIG_PPC_BOOK3E */
  129. /* We do need to set SOFTE in the stack frame or the return
  130. * from interrupt will be painful
  131. */
  132. li r10,1
  133. std r10,SOFTE(r1)
  134. #ifdef SHOW_SYSCALLS
  135. bl .do_show_syscall
  136. REST_GPR(0,r1)
  137. REST_4GPRS(3,r1)
  138. REST_2GPRS(7,r1)
  139. addi r9,r1,STACK_FRAME_OVERHEAD
  140. #endif
  141. CURRENT_THREAD_INFO(r11, r1)
  142. ld r10,TI_FLAGS(r11)
  143. andi. r11,r10,_TIF_SYSCALL_T_OR_A
  144. bne syscall_dotrace
  145. .Lsyscall_dotrace_cont:
  146. cmpldi 0,r0,NR_syscalls
  147. bge- syscall_enosys
  148. system_call: /* label this so stack traces look sane */
  149. /*
  150. * Need to vector to 32 Bit or default sys_call_table here,
  151. * based on caller's run-mode / personality.
  152. */
  153. ld r11,.SYS_CALL_TABLE@toc(2)
  154. andi. r10,r10,_TIF_32BIT
  155. beq 15f
  156. addi r11,r11,8 /* use 32-bit syscall entries */
  157. clrldi r3,r3,32
  158. clrldi r4,r4,32
  159. clrldi r5,r5,32
  160. clrldi r6,r6,32
  161. clrldi r7,r7,32
  162. clrldi r8,r8,32
  163. 15:
  164. slwi r0,r0,4
  165. ldx r10,r11,r0 /* Fetch system call handler [ptr] */
  166. mtctr r10
  167. bctrl /* Call handler */
  168. syscall_exit:
  169. std r3,RESULT(r1)
  170. #ifdef SHOW_SYSCALLS
  171. bl .do_show_syscall_exit
  172. ld r3,RESULT(r1)
  173. #endif
  174. CURRENT_THREAD_INFO(r12, r1)
  175. ld r8,_MSR(r1)
  176. #ifdef CONFIG_PPC_BOOK3S
  177. /* No MSR:RI on BookE */
  178. andi. r10,r8,MSR_RI
  179. beq- unrecov_restore
  180. #endif
  181. /*
  182. * Disable interrupts so current_thread_info()->flags can't change,
  183. * and so that we don't get interrupted after loading SRR0/1.
  184. */
  185. #ifdef CONFIG_PPC_BOOK3E
  186. wrteei 0
  187. #else
  188. ld r10,PACAKMSR(r13)
  189. /*
  190. * For performance reasons we clear RI the same time that we
  191. * clear EE. We only need to clear RI just before we restore r13
  192. * below, but batching it with EE saves us one expensive mtmsrd call.
  193. * We have to be careful to restore RI if we branch anywhere from
  194. * here (eg syscall_exit_work).
  195. */
  196. li r9,MSR_RI
  197. andc r11,r10,r9
  198. mtmsrd r11,1
  199. #endif /* CONFIG_PPC_BOOK3E */
  200. ld r9,TI_FLAGS(r12)
  201. li r11,-_LAST_ERRNO
  202. andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
  203. bne- syscall_exit_work
  204. cmpld r3,r11
  205. ld r5,_CCR(r1)
  206. bge- syscall_error
  207. .Lsyscall_error_cont:
  208. ld r7,_NIP(r1)
  209. BEGIN_FTR_SECTION
  210. stdcx. r0,0,r1 /* to clear the reservation */
  211. END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
  212. andi. r6,r8,MSR_PR
  213. ld r4,_LINK(r1)
  214. beq- 1f
  215. ACCOUNT_CPU_USER_EXIT(r11, r12)
  216. HMT_MEDIUM_LOW_HAS_PPR
  217. ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
  218. 1: ld r2,GPR2(r1)
  219. ld r1,GPR1(r1)
  220. mtlr r4
  221. mtcr r5
  222. mtspr SPRN_SRR0,r7
  223. mtspr SPRN_SRR1,r8
  224. RFI
  225. b . /* prevent speculative execution */
  226. syscall_error:
  227. oris r5,r5,0x1000 /* Set SO bit in CR */
  228. neg r3,r3
  229. std r5,_CCR(r1)
  230. b .Lsyscall_error_cont
  231. /* Traced system call support */
  232. syscall_dotrace:
  233. bl .save_nvgprs
  234. addi r3,r1,STACK_FRAME_OVERHEAD
  235. bl .do_syscall_trace_enter
  236. /*
  237. * Restore argument registers possibly just changed.
  238. * We use the return value of do_syscall_trace_enter
  239. * for the call number to look up in the table (r0).
  240. */
  241. mr r0,r3
  242. ld r3,GPR3(r1)
  243. ld r4,GPR4(r1)
  244. ld r5,GPR5(r1)
  245. ld r6,GPR6(r1)
  246. ld r7,GPR7(r1)
  247. ld r8,GPR8(r1)
  248. addi r9,r1,STACK_FRAME_OVERHEAD
  249. CURRENT_THREAD_INFO(r10, r1)
  250. ld r10,TI_FLAGS(r10)
  251. b .Lsyscall_dotrace_cont
  252. syscall_enosys:
  253. li r3,-ENOSYS
  254. b syscall_exit
  255. syscall_exit_work:
  256. #ifdef CONFIG_PPC_BOOK3S
  257. mtmsrd r10,1 /* Restore RI */
  258. #endif
  259. /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
  260. If TIF_NOERROR is set, just save r3 as it is. */
  261. andi. r0,r9,_TIF_RESTOREALL
  262. beq+ 0f
  263. REST_NVGPRS(r1)
  264. b 2f
  265. 0: cmpld r3,r11 /* r10 is -LAST_ERRNO */
  266. blt+ 1f
  267. andi. r0,r9,_TIF_NOERROR
  268. bne- 1f
  269. ld r5,_CCR(r1)
  270. neg r3,r3
  271. oris r5,r5,0x1000 /* Set SO bit in CR */
  272. std r5,_CCR(r1)
  273. 1: std r3,GPR3(r1)
  274. 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
  275. beq 4f
  276. /* Clear per-syscall TIF flags if any are set. */
  277. li r11,_TIF_PERSYSCALL_MASK
  278. addi r12,r12,TI_FLAGS
  279. 3: ldarx r10,0,r12
  280. andc r10,r10,r11
  281. stdcx. r10,0,r12
  282. bne- 3b
  283. subi r12,r12,TI_FLAGS
  284. 4: /* Anything else left to do? */
  285. SET_DEFAULT_THREAD_PPR(r3, r10) /* Set thread.ppr = 3 */
  286. andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
  287. beq .ret_from_except_lite
  288. /* Re-enable interrupts */
  289. #ifdef CONFIG_PPC_BOOK3E
  290. wrteei 1
  291. #else
  292. ld r10,PACAKMSR(r13)
  293. ori r10,r10,MSR_EE
  294. mtmsrd r10,1
  295. #endif /* CONFIG_PPC_BOOK3E */
  296. bl .save_nvgprs
  297. addi r3,r1,STACK_FRAME_OVERHEAD
  298. bl .do_syscall_trace_leave
  299. b .ret_from_except
  300. /* Save non-volatile GPRs, if not already saved. */
  301. _GLOBAL(save_nvgprs)
  302. ld r11,_TRAP(r1)
  303. andi. r0,r11,1
  304. beqlr-
  305. SAVE_NVGPRS(r1)
  306. clrrdi r0,r11,1
  307. std r0,_TRAP(r1)
  308. blr
  309. /*
  310. * The sigsuspend and rt_sigsuspend system calls can call do_signal
  311. * and thus put the process into the stopped state where we might
  312. * want to examine its user state with ptrace. Therefore we need
  313. * to save all the nonvolatile registers (r14 - r31) before calling
  314. * the C code. Similarly, fork, vfork and clone need the full
  315. * register state on the stack so that it can be copied to the child.
  316. */
  317. _GLOBAL(ppc_fork)
  318. bl .save_nvgprs
  319. bl .sys_fork
  320. b syscall_exit
  321. _GLOBAL(ppc_vfork)
  322. bl .save_nvgprs
  323. bl .sys_vfork
  324. b syscall_exit
  325. _GLOBAL(ppc_clone)
  326. bl .save_nvgprs
  327. bl .sys_clone
  328. b syscall_exit
  329. _GLOBAL(ppc32_swapcontext)
  330. bl .save_nvgprs
  331. bl .compat_sys_swapcontext
  332. b syscall_exit
  333. _GLOBAL(ppc64_swapcontext)
  334. bl .save_nvgprs
  335. bl .sys_swapcontext
  336. b syscall_exit
  337. _GLOBAL(ret_from_fork)
  338. bl .schedule_tail
  339. REST_NVGPRS(r1)
  340. li r3,0
  341. b syscall_exit
  342. _GLOBAL(ret_from_kernel_thread)
  343. bl .schedule_tail
  344. REST_NVGPRS(r1)
  345. ld r14, 0(r14)
  346. mtlr r14
  347. mr r3,r15
  348. blrl
  349. li r3,0
  350. b syscall_exit
  351. .section ".toc","aw"
  352. DSCR_DEFAULT:
  353. .tc dscr_default[TC],dscr_default
  354. .section ".text"
  355. /*
  356. * This routine switches between two different tasks. The process
  357. * state of one is saved on its kernel stack. Then the state
  358. * of the other is restored from its kernel stack. The memory
  359. * management hardware is updated to the second process's state.
  360. * Finally, we can return to the second process, via ret_from_except.
  361. * On entry, r3 points to the THREAD for the current task, r4
  362. * points to the THREAD for the new task.
  363. *
  364. * Note: there are two ways to get to the "going out" portion
  365. * of this code; either by coming in via the entry (_switch)
  366. * or via "fork" which must set up an environment equivalent
  367. * to the "_switch" path. If you change this you'll have to change
  368. * the fork code also.
  369. *
  370. * The code which creates the new task context is in 'copy_thread'
  371. * in arch/powerpc/kernel/process.c
  372. */
  373. .align 7
  374. _GLOBAL(_switch)
  375. mflr r0
  376. std r0,16(r1)
  377. stdu r1,-SWITCH_FRAME_SIZE(r1)
  378. /* r3-r13 are caller saved -- Cort */
  379. SAVE_8GPRS(14, r1)
  380. SAVE_10GPRS(22, r1)
  381. mflr r20 /* Return to switch caller */
  382. mfmsr r22
  383. li r0, MSR_FP
  384. #ifdef CONFIG_VSX
  385. BEGIN_FTR_SECTION
  386. oris r0,r0,MSR_VSX@h /* Disable VSX */
  387. END_FTR_SECTION_IFSET(CPU_FTR_VSX)
  388. #endif /* CONFIG_VSX */
  389. #ifdef CONFIG_ALTIVEC
  390. BEGIN_FTR_SECTION
  391. oris r0,r0,MSR_VEC@h /* Disable altivec */
  392. mfspr r24,SPRN_VRSAVE /* save vrsave register value */
  393. std r24,THREAD_VRSAVE(r3)
  394. END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
  395. #endif /* CONFIG_ALTIVEC */
  396. #ifdef CONFIG_PPC64
  397. BEGIN_FTR_SECTION
  398. mfspr r25,SPRN_DSCR
  399. std r25,THREAD_DSCR(r3)
  400. END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
  401. #endif
  402. and. r0,r0,r22
  403. beq+ 1f
  404. andc r22,r22,r0
  405. MTMSRD(r22)
  406. isync
  407. 1: std r20,_NIP(r1)
  408. mfcr r23
  409. std r23,_CCR(r1)
  410. std r1,KSP(r3) /* Set old stack pointer */
  411. #ifdef CONFIG_PPC_BOOK3S_64
  412. BEGIN_FTR_SECTION
  413. /*
  414. * Back up the TAR across context switches. Note that the TAR is not
  415. * available for use in the kernel. (To provide this, the TAR should
  416. * be backed up/restored on exception entry/exit instead, and be in
  417. * pt_regs. FIXME, this should be in pt_regs anyway (for debug).)
  418. */
  419. mfspr r0,SPRN_TAR
  420. std r0,THREAD_TAR(r3)
  421. /* Event based branch registers */
  422. mfspr r0, SPRN_BESCR
  423. std r0, THREAD_BESCR(r3)
  424. mfspr r0, SPRN_EBBHR
  425. std r0, THREAD_EBBHR(r3)
  426. mfspr r0, SPRN_EBBRR
  427. std r0, THREAD_EBBRR(r3)
  428. /* PMU registers made user read/(write) by EBB */
  429. mfspr r0, SPRN_SIAR
  430. std r0, THREAD_SIAR(r3)
  431. mfspr r0, SPRN_SDAR
  432. std r0, THREAD_SDAR(r3)
  433. mfspr r0, SPRN_SIER
  434. std r0, THREAD_SIER(r3)
  435. mfspr r0, SPRN_MMCR0
  436. std r0, THREAD_MMCR0(r3)
  437. mfspr r0, SPRN_MMCR2
  438. std r0, THREAD_MMCR2(r3)
  439. mfspr r0, SPRN_MMCRA
  440. std r0, THREAD_MMCRA(r3)
  441. END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
  442. #endif
  443. #ifdef CONFIG_SMP
  444. /* We need a sync somewhere here to make sure that if the
  445. * previous task gets rescheduled on another CPU, it sees all
  446. * stores it has performed on this one.
  447. */
  448. sync
  449. #endif /* CONFIG_SMP */
  450. /*
  451. * If we optimise away the clear of the reservation in system
  452. * calls because we know the CPU tracks the address of the
  453. * reservation, then we need to clear it here to cover the
  454. * case that the kernel context switch path has no larx
  455. * instructions.
  456. */
  457. BEGIN_FTR_SECTION
  458. ldarx r6,0,r1
  459. END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS)
  460. #ifdef CONFIG_PPC_BOOK3S
  461. /* Cancel all explict user streams as they will have no use after context
  462. * switch and will stop the HW from creating streams itself
  463. */
  464. DCBT_STOP_ALL_STREAM_IDS(r6)
  465. #endif
  466. addi r6,r4,-THREAD /* Convert THREAD to 'current' */
  467. std r6,PACACURRENT(r13) /* Set new 'current' */
  468. ld r8,KSP(r4) /* new stack pointer */
  469. #ifdef CONFIG_PPC_BOOK3S
  470. BEGIN_FTR_SECTION
  471. BEGIN_FTR_SECTION_NESTED(95)
  472. clrrdi r6,r8,28 /* get its ESID */
  473. clrrdi r9,r1,28 /* get current sp ESID */
  474. FTR_SECTION_ELSE_NESTED(95)
  475. clrrdi r6,r8,40 /* get its 1T ESID */
  476. clrrdi r9,r1,40 /* get current sp 1T ESID */
  477. ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_1T_SEGMENT, 95)
  478. FTR_SECTION_ELSE
  479. b 2f
  480. ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_SLB)
  481. clrldi. r0,r6,2 /* is new ESID c00000000? */
  482. cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
  483. cror eq,4*cr1+eq,eq
  484. beq 2f /* if yes, don't slbie it */
  485. /* Bolt in the new stack SLB entry */
  486. ld r7,KSP_VSID(r4) /* Get new stack's VSID */
  487. oris r0,r6,(SLB_ESID_V)@h
  488. ori r0,r0,(SLB_NUM_BOLTED-1)@l
  489. BEGIN_FTR_SECTION
  490. li r9,MMU_SEGSIZE_1T /* insert B field */
  491. oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
  492. rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
  493. END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
  494. /* Update the last bolted SLB. No write barriers are needed
  495. * here, provided we only update the current CPU's SLB shadow
  496. * buffer.
  497. */
  498. ld r9,PACA_SLBSHADOWPTR(r13)
  499. li r12,0
  500. std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
  501. std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */
  502. std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */
  503. /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
  504. * we have 1TB segments, the only CPUs known to have the errata
  505. * only support less than 1TB of system memory and we'll never
  506. * actually hit this code path.
  507. */
  508. slbie r6
  509. slbie r6 /* Workaround POWER5 < DD2.1 issue */
  510. slbmte r7,r0
  511. isync
  512. 2:
  513. #endif /* !CONFIG_PPC_BOOK3S */
  514. CURRENT_THREAD_INFO(r7, r8) /* base of new stack */
  515. /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
  516. because we don't need to leave the 288-byte ABI gap at the
  517. top of the kernel stack. */
  518. addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
  519. mr r1,r8 /* start using new stack pointer */
  520. std r7,PACAKSAVE(r13)
  521. #ifdef CONFIG_PPC_BOOK3S_64
  522. BEGIN_FTR_SECTION
  523. /* Event based branch registers */
  524. ld r0, THREAD_BESCR(r4)
  525. mtspr SPRN_BESCR, r0
  526. ld r0, THREAD_EBBHR(r4)
  527. mtspr SPRN_EBBHR, r0
  528. ld r0, THREAD_EBBRR(r4)
  529. mtspr SPRN_EBBRR, r0
  530. /* PMU registers made user read/(write) by EBB */
  531. ld r0, THREAD_SIAR(r4)
  532. mtspr SPRN_SIAR, r0
  533. ld r0, THREAD_SDAR(r4)
  534. mtspr SPRN_SDAR, r0
  535. ld r0, THREAD_SIER(r4)
  536. mtspr SPRN_SIER, r0
  537. ld r0, THREAD_MMCR0(r4)
  538. mtspr SPRN_MMCR0, r0
  539. ld r0, THREAD_MMCR2(r4)
  540. mtspr SPRN_MMCR2, r0
  541. ld r0, THREAD_MMCRA(r4)
  542. mtspr SPRN_MMCRA, r0
  543. ld r0,THREAD_TAR(r4)
  544. mtspr SPRN_TAR,r0
  545. END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
  546. #endif
  547. #ifdef CONFIG_ALTIVEC
  548. BEGIN_FTR_SECTION
  549. ld r0,THREAD_VRSAVE(r4)
  550. mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
  551. END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
  552. #endif /* CONFIG_ALTIVEC */
  553. #ifdef CONFIG_PPC64
  554. BEGIN_FTR_SECTION
  555. lwz r6,THREAD_DSCR_INHERIT(r4)
  556. ld r7,DSCR_DEFAULT@toc(2)
  557. ld r0,THREAD_DSCR(r4)
  558. cmpwi r6,0
  559. bne 1f
  560. ld r0,0(r7)
  561. 1: cmpd r0,r25
  562. beq 2f
  563. mtspr SPRN_DSCR,r0
  564. 2:
  565. END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
  566. #endif
  567. ld r6,_CCR(r1)
  568. mtcrf 0xFF,r6
  569. /* r3-r13 are destroyed -- Cort */
  570. REST_8GPRS(14, r1)
  571. REST_10GPRS(22, r1)
  572. /* convert old thread to its task_struct for return value */
  573. addi r3,r3,-THREAD
  574. ld r7,_NIP(r1) /* Return to _switch caller in new task */
  575. mtlr r7
  576. addi r1,r1,SWITCH_FRAME_SIZE
  577. blr
  578. .align 7
  579. _GLOBAL(ret_from_except)
  580. ld r11,_TRAP(r1)
  581. andi. r0,r11,1
  582. bne .ret_from_except_lite
  583. REST_NVGPRS(r1)
  584. _GLOBAL(ret_from_except_lite)
  585. /*
  586. * Disable interrupts so that current_thread_info()->flags
  587. * can't change between when we test it and when we return
  588. * from the interrupt.
  589. */
  590. #ifdef CONFIG_PPC_BOOK3E
  591. wrteei 0
  592. #else
  593. ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
  594. mtmsrd r10,1 /* Update machine state */
  595. #endif /* CONFIG_PPC_BOOK3E */
  596. CURRENT_THREAD_INFO(r9, r1)
  597. ld r3,_MSR(r1)
  598. ld r4,TI_FLAGS(r9)
  599. andi. r3,r3,MSR_PR
  600. beq resume_kernel
  601. /* Check current_thread_info()->flags */
  602. andi. r0,r4,_TIF_USER_WORK_MASK
  603. beq restore
  604. andi. r0,r4,_TIF_NEED_RESCHED
  605. beq 1f
  606. bl .restore_interrupts
  607. SCHEDULE_USER
  608. b .ret_from_except_lite
  609. 1: bl .save_nvgprs
  610. bl .restore_interrupts
  611. addi r3,r1,STACK_FRAME_OVERHEAD
  612. bl .do_notify_resume
  613. b .ret_from_except
  614. resume_kernel:
  615. /* check current_thread_info, _TIF_EMULATE_STACK_STORE */
  616. CURRENT_THREAD_INFO(r9, r1)
  617. ld r8,TI_FLAGS(r9)
  618. andis. r8,r8,_TIF_EMULATE_STACK_STORE@h
  619. beq+ 1f
  620. addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
  621. lwz r3,GPR1(r1)
  622. subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
  623. mr r4,r1 /* src: current exception frame */
  624. mr r1,r3 /* Reroute the trampoline frame to r1 */
  625. /* Copy from the original to the trampoline. */
  626. li r5,INT_FRAME_SIZE/8 /* size: INT_FRAME_SIZE */
  627. li r6,0 /* start offset: 0 */
  628. mtctr r5
  629. 2: ldx r0,r6,r4
  630. stdx r0,r6,r3
  631. addi r6,r6,8
  632. bdnz 2b
  633. /* Do real store operation to complete stwu */
  634. lwz r5,GPR1(r1)
  635. std r8,0(r5)
  636. /* Clear _TIF_EMULATE_STACK_STORE flag */
  637. lis r11,_TIF_EMULATE_STACK_STORE@h
  638. addi r5,r9,TI_FLAGS
  639. 0: ldarx r4,0,r5
  640. andc r4,r4,r11
  641. stdcx. r4,0,r5
  642. bne- 0b
  643. 1:
  644. #ifdef CONFIG_PREEMPT
  645. /* Check if we need to preempt */
  646. andi. r0,r4,_TIF_NEED_RESCHED
  647. beq+ restore
  648. /* Check that preempt_count() == 0 and interrupts are enabled */
  649. lwz r8,TI_PREEMPT(r9)
  650. cmpwi cr1,r8,0
  651. ld r0,SOFTE(r1)
  652. cmpdi r0,0
  653. crandc eq,cr1*4+eq,eq
  654. bne restore
  655. /*
  656. * Here we are preempting the current task. We want to make
  657. * sure we are soft-disabled first
  658. */
  659. SOFT_DISABLE_INTS(r3,r4)
  660. 1: bl .preempt_schedule_irq
  661. /* Re-test flags and eventually loop */
  662. CURRENT_THREAD_INFO(r9, r1)
  663. ld r4,TI_FLAGS(r9)
  664. andi. r0,r4,_TIF_NEED_RESCHED
  665. bne 1b
  666. /*
  667. * arch_local_irq_restore() from preempt_schedule_irq above may
  668. * enable hard interrupt but we really should disable interrupts
  669. * when we return from the interrupt, and so that we don't get
  670. * interrupted after loading SRR0/1.
  671. */
  672. #ifdef CONFIG_PPC_BOOK3E
  673. wrteei 0
  674. #else
  675. ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */
  676. mtmsrd r10,1 /* Update machine state */
  677. #endif /* CONFIG_PPC_BOOK3E */
  678. #endif /* CONFIG_PREEMPT */
  679. .globl fast_exc_return_irq
  680. fast_exc_return_irq:
  681. restore:
  682. /*
  683. * This is the main kernel exit path. First we check if we
  684. * are about to re-enable interrupts
  685. */
  686. ld r5,SOFTE(r1)
  687. lbz r6,PACASOFTIRQEN(r13)
  688. cmpwi cr0,r5,0
  689. beq restore_irq_off
  690. /* We are enabling, were we already enabled ? Yes, just return */
  691. cmpwi cr0,r6,1
  692. beq cr0,do_restore
  693. /*
  694. * We are about to soft-enable interrupts (we are hard disabled
  695. * at this point). We check if there's anything that needs to
  696. * be replayed first.
  697. */
  698. lbz r0,PACAIRQHAPPENED(r13)
  699. cmpwi cr0,r0,0
  700. bne- restore_check_irq_replay
  701. /*
  702. * Get here when nothing happened while soft-disabled, just
  703. * soft-enable and move-on. We will hard-enable as a side
  704. * effect of rfi
  705. */
  706. restore_no_replay:
  707. TRACE_ENABLE_INTS
  708. li r0,1
  709. stb r0,PACASOFTIRQEN(r13);
  710. /*
  711. * Final return path. BookE is handled in a different file
  712. */
  713. do_restore:
  714. #ifdef CONFIG_PPC_BOOK3E
  715. b .exception_return_book3e
  716. #else
  717. /*
  718. * Clear the reservation. If we know the CPU tracks the address of
  719. * the reservation then we can potentially save some cycles and use
  720. * a larx. On POWER6 and POWER7 this is significantly faster.
  721. */
  722. BEGIN_FTR_SECTION
  723. stdcx. r0,0,r1 /* to clear the reservation */
  724. FTR_SECTION_ELSE
  725. ldarx r4,0,r1
  726. ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
  727. /*
  728. * Some code path such as load_up_fpu or altivec return directly
  729. * here. They run entirely hard disabled and do not alter the
  730. * interrupt state. They also don't use lwarx/stwcx. and thus
  731. * are known not to leave dangling reservations.
  732. */
  733. .globl fast_exception_return
  734. fast_exception_return:
  735. ld r3,_MSR(r1)
  736. ld r4,_CTR(r1)
  737. ld r0,_LINK(r1)
  738. mtctr r4
  739. mtlr r0
  740. ld r4,_XER(r1)
  741. mtspr SPRN_XER,r4
  742. REST_8GPRS(5, r1)
  743. andi. r0,r3,MSR_RI
  744. beq- unrecov_restore
  745. /*
  746. * Clear RI before restoring r13. If we are returning to
  747. * userspace and we take an exception after restoring r13,
  748. * we end up corrupting the userspace r13 value.
  749. */
  750. ld r4,PACAKMSR(r13) /* Get kernel MSR without EE */
  751. andc r4,r4,r0 /* r0 contains MSR_RI here */
  752. mtmsrd r4,1
  753. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  754. /* TM debug */
  755. std r3, PACATMSCRATCH(r13) /* Stash returned-to MSR */
  756. #endif
  757. /*
  758. * r13 is our per cpu area, only restore it if we are returning to
  759. * userspace the value stored in the stack frame may belong to
  760. * another CPU.
  761. */
  762. andi. r0,r3,MSR_PR
  763. beq 1f
  764. ACCOUNT_CPU_USER_EXIT(r2, r4)
  765. RESTORE_PPR(r2, r4)
  766. REST_GPR(13, r1)
  767. 1:
  768. mtspr SPRN_SRR1,r3
  769. ld r2,_CCR(r1)
  770. mtcrf 0xFF,r2
  771. ld r2,_NIP(r1)
  772. mtspr SPRN_SRR0,r2
  773. ld r0,GPR0(r1)
  774. ld r2,GPR2(r1)
  775. ld r3,GPR3(r1)
  776. ld r4,GPR4(r1)
  777. ld r1,GPR1(r1)
  778. rfid
  779. b . /* prevent speculative execution */
  780. #endif /* CONFIG_PPC_BOOK3E */
  781. /*
  782. * We are returning to a context with interrupts soft disabled.
  783. *
  784. * However, we may also about to hard enable, so we need to
  785. * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
  786. * or that bit can get out of sync and bad things will happen
  787. */
  788. restore_irq_off:
  789. ld r3,_MSR(r1)
  790. lbz r7,PACAIRQHAPPENED(r13)
  791. andi. r0,r3,MSR_EE
  792. beq 1f
  793. rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS
  794. stb r7,PACAIRQHAPPENED(r13)
  795. 1: li r0,0
  796. stb r0,PACASOFTIRQEN(r13);
  797. TRACE_DISABLE_INTS
  798. b do_restore
  799. /*
  800. * Something did happen, check if a re-emit is needed
  801. * (this also clears paca->irq_happened)
  802. */
  803. restore_check_irq_replay:
  804. /* XXX: We could implement a fast path here where we check
  805. * for irq_happened being just 0x01, in which case we can
  806. * clear it and return. That means that we would potentially
  807. * miss a decrementer having wrapped all the way around.
  808. *
  809. * Still, this might be useful for things like hash_page
  810. */
  811. bl .__check_irq_replay
  812. cmpwi cr0,r3,0
  813. beq restore_no_replay
  814. /*
  815. * We need to re-emit an interrupt. We do so by re-using our
  816. * existing exception frame. We first change the trap value,
  817. * but we need to ensure we preserve the low nibble of it
  818. */
  819. ld r4,_TRAP(r1)
  820. clrldi r4,r4,60
  821. or r4,r4,r3
  822. std r4,_TRAP(r1)
  823. /*
  824. * Then find the right handler and call it. Interrupts are
  825. * still soft-disabled and we keep them that way.
  826. */
  827. cmpwi cr0,r3,0x500
  828. bne 1f
  829. addi r3,r1,STACK_FRAME_OVERHEAD;
  830. bl .do_IRQ
  831. b .ret_from_except
  832. 1: cmpwi cr0,r3,0x900
  833. bne 1f
  834. addi r3,r1,STACK_FRAME_OVERHEAD;
  835. bl .timer_interrupt
  836. b .ret_from_except
  837. #ifdef CONFIG_PPC_DOORBELL
  838. 1:
  839. #ifdef CONFIG_PPC_BOOK3E
  840. cmpwi cr0,r3,0x280
  841. #else
  842. BEGIN_FTR_SECTION
  843. cmpwi cr0,r3,0xe80
  844. FTR_SECTION_ELSE
  845. cmpwi cr0,r3,0xa00
  846. ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
  847. #endif /* CONFIG_PPC_BOOK3E */
  848. bne 1f
  849. addi r3,r1,STACK_FRAME_OVERHEAD;
  850. bl .doorbell_exception
  851. b .ret_from_except
  852. #endif /* CONFIG_PPC_DOORBELL */
  853. 1: b .ret_from_except /* What else to do here ? */
  854. unrecov_restore:
  855. addi r3,r1,STACK_FRAME_OVERHEAD
  856. bl .unrecoverable_exception
  857. b unrecov_restore
  858. #ifdef CONFIG_PPC_RTAS
  859. /*
  860. * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
  861. * called with the MMU off.
  862. *
  863. * In addition, we need to be in 32b mode, at least for now.
  864. *
  865. * Note: r3 is an input parameter to rtas, so don't trash it...
  866. */
  867. _GLOBAL(enter_rtas)
  868. mflr r0
  869. std r0,16(r1)
  870. stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
  871. /* Because RTAS is running in 32b mode, it clobbers the high order half
  872. * of all registers that it saves. We therefore save those registers
  873. * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
  874. */
  875. SAVE_GPR(2, r1) /* Save the TOC */
  876. SAVE_GPR(13, r1) /* Save paca */
  877. SAVE_8GPRS(14, r1) /* Save the non-volatiles */
  878. SAVE_10GPRS(22, r1) /* ditto */
  879. mfcr r4
  880. std r4,_CCR(r1)
  881. mfctr r5
  882. std r5,_CTR(r1)
  883. mfspr r6,SPRN_XER
  884. std r6,_XER(r1)
  885. mfdar r7
  886. std r7,_DAR(r1)
  887. mfdsisr r8
  888. std r8,_DSISR(r1)
  889. /* Temporary workaround to clear CR until RTAS can be modified to
  890. * ignore all bits.
  891. */
  892. li r0,0
  893. mtcr r0
  894. #ifdef CONFIG_BUG
  895. /* There is no way it is acceptable to get here with interrupts enabled,
  896. * check it with the asm equivalent of WARN_ON
  897. */
  898. lbz r0,PACASOFTIRQEN(r13)
  899. 1: tdnei r0,0
  900. EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
  901. #endif
  902. /* Hard-disable interrupts */
  903. mfmsr r6
  904. rldicl r7,r6,48,1
  905. rotldi r7,r7,16
  906. mtmsrd r7,1
  907. /* Unfortunately, the stack pointer and the MSR are also clobbered,
  908. * so they are saved in the PACA which allows us to restore
  909. * our original state after RTAS returns.
  910. */
  911. std r1,PACAR1(r13)
  912. std r6,PACASAVEDMSR(r13)
  913. /* Setup our real return addr */
  914. LOAD_REG_ADDR(r4,.rtas_return_loc)
  915. clrldi r4,r4,2 /* convert to realmode address */
  916. mtlr r4
  917. li r0,0
  918. ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
  919. andc r0,r6,r0
  920. li r9,1
  921. rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
  922. ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI
  923. andc r6,r0,r9
  924. sync /* disable interrupts so SRR0/1 */
  925. mtmsrd r0 /* don't get trashed */
  926. LOAD_REG_ADDR(r4, rtas)
  927. ld r5,RTASENTRY(r4) /* get the rtas->entry value */
  928. ld r4,RTASBASE(r4) /* get the rtas->base value */
  929. mtspr SPRN_SRR0,r5
  930. mtspr SPRN_SRR1,r6
  931. rfid
  932. b . /* prevent speculative execution */
  933. _STATIC(rtas_return_loc)
  934. /* relocation is off at this point */
  935. GET_PACA(r4)
  936. clrldi r4,r4,2 /* convert to realmode address */
  937. bcl 20,31,$+4
  938. 0: mflr r3
  939. ld r3,(1f-0b)(r3) /* get &.rtas_restore_regs */
  940. mfmsr r6
  941. li r0,MSR_RI
  942. andc r6,r6,r0
  943. sync
  944. mtmsrd r6
  945. ld r1,PACAR1(r4) /* Restore our SP */
  946. ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
  947. mtspr SPRN_SRR0,r3
  948. mtspr SPRN_SRR1,r4
  949. rfid
  950. b . /* prevent speculative execution */
  951. .align 3
  952. 1: .llong .rtas_restore_regs
  953. _STATIC(rtas_restore_regs)
  954. /* relocation is on at this point */
  955. REST_GPR(2, r1) /* Restore the TOC */
  956. REST_GPR(13, r1) /* Restore paca */
  957. REST_8GPRS(14, r1) /* Restore the non-volatiles */
  958. REST_10GPRS(22, r1) /* ditto */
  959. GET_PACA(r13)
  960. ld r4,_CCR(r1)
  961. mtcr r4
  962. ld r5,_CTR(r1)
  963. mtctr r5
  964. ld r6,_XER(r1)
  965. mtspr SPRN_XER,r6
  966. ld r7,_DAR(r1)
  967. mtdar r7
  968. ld r8,_DSISR(r1)
  969. mtdsisr r8
  970. addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
  971. ld r0,16(r1) /* get return address */
  972. mtlr r0
  973. blr /* return to caller */
  974. #endif /* CONFIG_PPC_RTAS */
  975. _GLOBAL(enter_prom)
  976. mflr r0
  977. std r0,16(r1)
  978. stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
  979. /* Because PROM is running in 32b mode, it clobbers the high order half
  980. * of all registers that it saves. We therefore save those registers
  981. * PROM might touch to the stack. (r0, r3-r13 are caller saved)
  982. */
  983. SAVE_GPR(2, r1)
  984. SAVE_GPR(13, r1)
  985. SAVE_8GPRS(14, r1)
  986. SAVE_10GPRS(22, r1)
  987. mfcr r10
  988. mfmsr r11
  989. std r10,_CCR(r1)
  990. std r11,_MSR(r1)
  991. /* Get the PROM entrypoint */
  992. mtlr r4
  993. /* Switch MSR to 32 bits mode
  994. */
  995. #ifdef CONFIG_PPC_BOOK3E
  996. rlwinm r11,r11,0,1,31
  997. mtmsr r11
  998. #else /* CONFIG_PPC_BOOK3E */
  999. mfmsr r11
  1000. li r12,1
  1001. rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
  1002. andc r11,r11,r12
  1003. li r12,1
  1004. rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
  1005. andc r11,r11,r12
  1006. mtmsrd r11
  1007. #endif /* CONFIG_PPC_BOOK3E */
  1008. isync
  1009. /* Enter PROM here... */
  1010. blrl
  1011. /* Just make sure that r1 top 32 bits didn't get
  1012. * corrupt by OF
  1013. */
  1014. rldicl r1,r1,0,32
  1015. /* Restore the MSR (back to 64 bits) */
  1016. ld r0,_MSR(r1)
  1017. MTMSRD(r0)
  1018. isync
  1019. /* Restore other registers */
  1020. REST_GPR(2, r1)
  1021. REST_GPR(13, r1)
  1022. REST_8GPRS(14, r1)
  1023. REST_10GPRS(22, r1)
  1024. ld r4,_CCR(r1)
  1025. mtcr r4
  1026. addi r1,r1,PROM_FRAME_SIZE
  1027. ld r0,16(r1)
  1028. mtlr r0
  1029. blr
  1030. #ifdef CONFIG_FUNCTION_TRACER
  1031. #ifdef CONFIG_DYNAMIC_FTRACE
  1032. _GLOBAL(mcount)
  1033. _GLOBAL(_mcount)
  1034. blr
  1035. _GLOBAL(ftrace_caller)
  1036. /* Taken from output of objdump from lib64/glibc */
  1037. mflr r3
  1038. ld r11, 0(r1)
  1039. stdu r1, -112(r1)
  1040. std r3, 128(r1)
  1041. ld r4, 16(r11)
  1042. subi r3, r3, MCOUNT_INSN_SIZE
  1043. .globl ftrace_call
  1044. ftrace_call:
  1045. bl ftrace_stub
  1046. nop
  1047. #ifdef CONFIG_FUNCTION_GRAPH_TRACER
  1048. .globl ftrace_graph_call
  1049. ftrace_graph_call:
  1050. b ftrace_graph_stub
  1051. _GLOBAL(ftrace_graph_stub)
  1052. #endif
  1053. ld r0, 128(r1)
  1054. mtlr r0
  1055. addi r1, r1, 112
  1056. _GLOBAL(ftrace_stub)
  1057. blr
  1058. #else
  1059. _GLOBAL(mcount)
  1060. blr
  1061. _GLOBAL(_mcount)
  1062. /* Taken from output of objdump from lib64/glibc */
  1063. mflr r3
  1064. ld r11, 0(r1)
  1065. stdu r1, -112(r1)
  1066. std r3, 128(r1)
  1067. ld r4, 16(r11)
  1068. subi r3, r3, MCOUNT_INSN_SIZE
  1069. LOAD_REG_ADDR(r5,ftrace_trace_function)
  1070. ld r5,0(r5)
  1071. ld r5,0(r5)
  1072. mtctr r5
  1073. bctrl
  1074. nop
  1075. #ifdef CONFIG_FUNCTION_GRAPH_TRACER
  1076. b ftrace_graph_caller
  1077. #endif
  1078. ld r0, 128(r1)
  1079. mtlr r0
  1080. addi r1, r1, 112
  1081. _GLOBAL(ftrace_stub)
  1082. blr
  1083. #endif /* CONFIG_DYNAMIC_FTRACE */
  1084. #ifdef CONFIG_FUNCTION_GRAPH_TRACER
  1085. _GLOBAL(ftrace_graph_caller)
  1086. /* load r4 with local address */
  1087. ld r4, 128(r1)
  1088. subi r4, r4, MCOUNT_INSN_SIZE
  1089. /* get the parent address */
  1090. ld r11, 112(r1)
  1091. addi r3, r11, 16
  1092. bl .prepare_ftrace_return
  1093. nop
  1094. ld r0, 128(r1)
  1095. mtlr r0
  1096. addi r1, r1, 112
  1097. blr
  1098. _GLOBAL(return_to_handler)
  1099. /* need to save return values */
  1100. std r4, -24(r1)
  1101. std r3, -16(r1)
  1102. std r31, -8(r1)
  1103. mr r31, r1
  1104. stdu r1, -112(r1)
  1105. bl .ftrace_return_to_handler
  1106. nop
  1107. /* return value has real return address */
  1108. mtlr r3
  1109. ld r1, 0(r1)
  1110. ld r4, -24(r1)
  1111. ld r3, -16(r1)
  1112. ld r31, -8(r1)
  1113. /* Jump back to real return address */
  1114. blr
  1115. _GLOBAL(mod_return_to_handler)
  1116. /* need to save return values */
  1117. std r4, -32(r1)
  1118. std r3, -24(r1)
  1119. /* save TOC */
  1120. std r2, -16(r1)
  1121. std r31, -8(r1)
  1122. mr r31, r1
  1123. stdu r1, -112(r1)
  1124. /*
  1125. * We are in a module using the module's TOC.
  1126. * Switch to our TOC to run inside the core kernel.
  1127. */
  1128. ld r2, PACATOC(r13)
  1129. bl .ftrace_return_to_handler
  1130. nop
  1131. /* return value has real return address */
  1132. mtlr r3
  1133. ld r1, 0(r1)
  1134. ld r4, -32(r1)
  1135. ld r3, -24(r1)
  1136. ld r2, -16(r1)
  1137. ld r31, -8(r1)
  1138. /* Jump back to real return address */
  1139. blr
  1140. #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
  1141. #endif /* CONFIG_FUNCTION_TRACER */