soc-cache.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997
  1. /*
  2. * soc-cache.c -- ASoC register cache helpers
  3. *
  4. * Copyright 2009 Wolfson Microelectronics PLC.
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #include <linux/i2c.h>
  14. #include <linux/spi/spi.h>
  15. #include <sound/soc.h>
  16. static unsigned int snd_soc_4_12_read(struct snd_soc_codec *codec,
  17. unsigned int reg)
  18. {
  19. int ret;
  20. unsigned int val;
  21. if (reg >= codec->driver->reg_cache_size ||
  22. snd_soc_codec_volatile_register(codec, reg)) {
  23. if (codec->cache_only)
  24. return -1;
  25. BUG_ON(!codec->hw_read);
  26. return codec->hw_read(codec, reg);
  27. }
  28. ret = snd_soc_cache_read(codec, reg, &val);
  29. if (ret < 0)
  30. return -1;
  31. return val;
  32. }
  33. static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
  34. unsigned int value)
  35. {
  36. u8 data[2];
  37. int ret;
  38. data[0] = (reg << 4) | ((value >> 8) & 0x000f);
  39. data[1] = value & 0x00ff;
  40. if (!snd_soc_codec_volatile_register(codec, reg) &&
  41. reg < codec->driver->reg_cache_size) {
  42. ret = snd_soc_cache_write(codec, reg, value);
  43. if (ret < 0)
  44. return -1;
  45. }
  46. if (codec->cache_only) {
  47. codec->cache_sync = 1;
  48. return 0;
  49. }
  50. ret = codec->hw_write(codec->control_data, data, 2);
  51. if (ret == 2)
  52. return 0;
  53. if (ret < 0)
  54. return ret;
  55. else
  56. return -EIO;
  57. }
  58. #if defined(CONFIG_SPI_MASTER)
  59. static int snd_soc_4_12_spi_write(void *control_data, const char *data,
  60. int len)
  61. {
  62. struct spi_device *spi = control_data;
  63. struct spi_transfer t;
  64. struct spi_message m;
  65. u8 msg[2];
  66. if (len <= 0)
  67. return 0;
  68. msg[0] = data[1];
  69. msg[1] = data[0];
  70. spi_message_init(&m);
  71. memset(&t, 0, (sizeof t));
  72. t.tx_buf = &msg[0];
  73. t.len = len;
  74. spi_message_add_tail(&t, &m);
  75. spi_sync(spi, &m);
  76. return len;
  77. }
  78. #else
  79. #define snd_soc_4_12_spi_write NULL
  80. #endif
  81. static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec,
  82. unsigned int reg)
  83. {
  84. int ret;
  85. unsigned int val;
  86. if (reg >= codec->driver->reg_cache_size ||
  87. snd_soc_codec_volatile_register(codec, reg)) {
  88. if (codec->cache_only)
  89. return -1;
  90. BUG_ON(!codec->hw_read);
  91. return codec->hw_read(codec, reg);
  92. }
  93. ret = snd_soc_cache_read(codec, reg, &val);
  94. if (ret < 0)
  95. return -1;
  96. return val;
  97. }
  98. static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
  99. unsigned int value)
  100. {
  101. u8 data[2];
  102. int ret;
  103. data[0] = (reg << 1) | ((value >> 8) & 0x0001);
  104. data[1] = value & 0x00ff;
  105. if (!snd_soc_codec_volatile_register(codec, reg) &&
  106. reg < codec->driver->reg_cache_size) {
  107. ret = snd_soc_cache_write(codec, reg, value);
  108. if (ret < 0)
  109. return -1;
  110. }
  111. if (codec->cache_only) {
  112. codec->cache_sync = 1;
  113. return 0;
  114. }
  115. ret = codec->hw_write(codec->control_data, data, 2);
  116. if (ret == 2)
  117. return 0;
  118. if (ret < 0)
  119. return ret;
  120. else
  121. return -EIO;
  122. }
  123. #if defined(CONFIG_SPI_MASTER)
  124. static int snd_soc_7_9_spi_write(void *control_data, const char *data,
  125. int len)
  126. {
  127. struct spi_device *spi = control_data;
  128. struct spi_transfer t;
  129. struct spi_message m;
  130. u8 msg[2];
  131. if (len <= 0)
  132. return 0;
  133. msg[0] = data[0];
  134. msg[1] = data[1];
  135. spi_message_init(&m);
  136. memset(&t, 0, (sizeof t));
  137. t.tx_buf = &msg[0];
  138. t.len = len;
  139. spi_message_add_tail(&t, &m);
  140. spi_sync(spi, &m);
  141. return len;
  142. }
  143. #else
  144. #define snd_soc_7_9_spi_write NULL
  145. #endif
  146. static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
  147. unsigned int value)
  148. {
  149. u8 data[2];
  150. int ret;
  151. reg &= 0xff;
  152. data[0] = reg;
  153. data[1] = value & 0xff;
  154. if (!snd_soc_codec_volatile_register(codec, reg) &&
  155. reg < codec->driver->reg_cache_size) {
  156. ret = snd_soc_cache_write(codec, reg, value);
  157. if (ret < 0)
  158. return -1;
  159. }
  160. if (codec->cache_only) {
  161. codec->cache_sync = 1;
  162. return 0;
  163. }
  164. if (codec->hw_write(codec->control_data, data, 2) == 2)
  165. return 0;
  166. else
  167. return -EIO;
  168. }
  169. static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec,
  170. unsigned int reg)
  171. {
  172. int ret;
  173. unsigned int val;
  174. reg &= 0xff;
  175. if (reg >= codec->driver->reg_cache_size ||
  176. snd_soc_codec_volatile_register(codec, reg)) {
  177. if (codec->cache_only)
  178. return -1;
  179. BUG_ON(!codec->hw_read);
  180. return codec->hw_read(codec, reg);
  181. }
  182. ret = snd_soc_cache_read(codec, reg, &val);
  183. if (ret < 0)
  184. return -1;
  185. return val;
  186. }
  187. #if defined(CONFIG_SPI_MASTER)
  188. static int snd_soc_8_8_spi_write(void *control_data, const char *data,
  189. int len)
  190. {
  191. struct spi_device *spi = control_data;
  192. struct spi_transfer t;
  193. struct spi_message m;
  194. u8 msg[2];
  195. if (len <= 0)
  196. return 0;
  197. msg[0] = data[0];
  198. msg[1] = data[1];
  199. spi_message_init(&m);
  200. memset(&t, 0, (sizeof t));
  201. t.tx_buf = &msg[0];
  202. t.len = len;
  203. spi_message_add_tail(&t, &m);
  204. spi_sync(spi, &m);
  205. return len;
  206. }
  207. #else
  208. #define snd_soc_8_8_spi_write NULL
  209. #endif
  210. static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
  211. unsigned int value)
  212. {
  213. u8 data[3];
  214. int ret;
  215. data[0] = reg;
  216. data[1] = (value >> 8) & 0xff;
  217. data[2] = value & 0xff;
  218. if (!snd_soc_codec_volatile_register(codec, reg) &&
  219. reg < codec->driver->reg_cache_size) {
  220. ret = snd_soc_cache_write(codec, reg, value);
  221. if (ret < 0)
  222. return -1;
  223. }
  224. if (codec->cache_only) {
  225. codec->cache_sync = 1;
  226. return 0;
  227. }
  228. if (codec->hw_write(codec->control_data, data, 3) == 3)
  229. return 0;
  230. else
  231. return -EIO;
  232. }
  233. static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec,
  234. unsigned int reg)
  235. {
  236. int ret;
  237. unsigned int val;
  238. if (reg >= codec->driver->reg_cache_size ||
  239. snd_soc_codec_volatile_register(codec, reg)) {
  240. if (codec->cache_only)
  241. return -1;
  242. BUG_ON(!codec->hw_read);
  243. return codec->hw_read(codec, reg);
  244. }
  245. ret = snd_soc_cache_read(codec, reg, &val);
  246. if (ret < 0)
  247. return -1;
  248. return val;
  249. }
  250. #if defined(CONFIG_SPI_MASTER)
  251. static int snd_soc_8_16_spi_write(void *control_data, const char *data,
  252. int len)
  253. {
  254. struct spi_device *spi = control_data;
  255. struct spi_transfer t;
  256. struct spi_message m;
  257. u8 msg[3];
  258. if (len <= 0)
  259. return 0;
  260. msg[0] = data[0];
  261. msg[1] = data[1];
  262. msg[2] = data[2];
  263. spi_message_init(&m);
  264. memset(&t, 0, (sizeof t));
  265. t.tx_buf = &msg[0];
  266. t.len = len;
  267. spi_message_add_tail(&t, &m);
  268. spi_sync(spi, &m);
  269. return len;
  270. }
  271. #else
  272. #define snd_soc_8_16_spi_write NULL
  273. #endif
  274. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  275. static unsigned int snd_soc_8_8_read_i2c(struct snd_soc_codec *codec,
  276. unsigned int r)
  277. {
  278. struct i2c_msg xfer[2];
  279. u8 reg = r;
  280. u8 data;
  281. int ret;
  282. struct i2c_client *client = codec->control_data;
  283. /* Write register */
  284. xfer[0].addr = client->addr;
  285. xfer[0].flags = 0;
  286. xfer[0].len = 1;
  287. xfer[0].buf = &reg;
  288. /* Read data */
  289. xfer[1].addr = client->addr;
  290. xfer[1].flags = I2C_M_RD;
  291. xfer[1].len = 1;
  292. xfer[1].buf = &data;
  293. ret = i2c_transfer(client->adapter, xfer, 2);
  294. if (ret != 2) {
  295. dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
  296. return 0;
  297. }
  298. return data;
  299. }
  300. #else
  301. #define snd_soc_8_8_read_i2c NULL
  302. #endif
  303. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  304. static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
  305. unsigned int r)
  306. {
  307. struct i2c_msg xfer[2];
  308. u8 reg = r;
  309. u16 data;
  310. int ret;
  311. struct i2c_client *client = codec->control_data;
  312. /* Write register */
  313. xfer[0].addr = client->addr;
  314. xfer[0].flags = 0;
  315. xfer[0].len = 1;
  316. xfer[0].buf = &reg;
  317. /* Read data */
  318. xfer[1].addr = client->addr;
  319. xfer[1].flags = I2C_M_RD;
  320. xfer[1].len = 2;
  321. xfer[1].buf = (u8 *)&data;
  322. ret = i2c_transfer(client->adapter, xfer, 2);
  323. if (ret != 2) {
  324. dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
  325. return 0;
  326. }
  327. return (data >> 8) | ((data & 0xff) << 8);
  328. }
  329. #else
  330. #define snd_soc_8_16_read_i2c NULL
  331. #endif
  332. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  333. static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
  334. unsigned int r)
  335. {
  336. struct i2c_msg xfer[2];
  337. u16 reg = r;
  338. u8 data;
  339. int ret;
  340. struct i2c_client *client = codec->control_data;
  341. /* Write register */
  342. xfer[0].addr = client->addr;
  343. xfer[0].flags = 0;
  344. xfer[0].len = 2;
  345. xfer[0].buf = (u8 *)&reg;
  346. /* Read data */
  347. xfer[1].addr = client->addr;
  348. xfer[1].flags = I2C_M_RD;
  349. xfer[1].len = 1;
  350. xfer[1].buf = &data;
  351. ret = i2c_transfer(client->adapter, xfer, 2);
  352. if (ret != 2) {
  353. dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
  354. return 0;
  355. }
  356. return data;
  357. }
  358. #else
  359. #define snd_soc_16_8_read_i2c NULL
  360. #endif
  361. static unsigned int snd_soc_16_8_read(struct snd_soc_codec *codec,
  362. unsigned int reg)
  363. {
  364. int ret;
  365. unsigned int val;
  366. reg &= 0xff;
  367. if (reg >= codec->driver->reg_cache_size ||
  368. snd_soc_codec_volatile_register(codec, reg)) {
  369. if (codec->cache_only)
  370. return -1;
  371. BUG_ON(!codec->hw_read);
  372. return codec->hw_read(codec, reg);
  373. }
  374. ret = snd_soc_cache_read(codec, reg, &val);
  375. if (ret < 0)
  376. return -1;
  377. return val;
  378. }
  379. static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
  380. unsigned int value)
  381. {
  382. u8 data[3];
  383. int ret;
  384. data[0] = (reg >> 8) & 0xff;
  385. data[1] = reg & 0xff;
  386. data[2] = value;
  387. reg &= 0xff;
  388. if (!snd_soc_codec_volatile_register(codec, reg) &&
  389. reg < codec->driver->reg_cache_size) {
  390. ret = snd_soc_cache_write(codec, reg, value);
  391. if (ret < 0)
  392. return -1;
  393. }
  394. if (codec->cache_only) {
  395. codec->cache_sync = 1;
  396. return 0;
  397. }
  398. ret = codec->hw_write(codec->control_data, data, 3);
  399. if (ret == 3)
  400. return 0;
  401. if (ret < 0)
  402. return ret;
  403. else
  404. return -EIO;
  405. }
  406. #if defined(CONFIG_SPI_MASTER)
  407. static int snd_soc_16_8_spi_write(void *control_data, const char *data,
  408. int len)
  409. {
  410. struct spi_device *spi = control_data;
  411. struct spi_transfer t;
  412. struct spi_message m;
  413. u8 msg[3];
  414. if (len <= 0)
  415. return 0;
  416. msg[0] = data[0];
  417. msg[1] = data[1];
  418. msg[2] = data[2];
  419. spi_message_init(&m);
  420. memset(&t, 0, (sizeof t));
  421. t.tx_buf = &msg[0];
  422. t.len = len;
  423. spi_message_add_tail(&t, &m);
  424. spi_sync(spi, &m);
  425. return len;
  426. }
  427. #else
  428. #define snd_soc_16_8_spi_write NULL
  429. #endif
  430. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  431. static unsigned int snd_soc_16_16_read_i2c(struct snd_soc_codec *codec,
  432. unsigned int r)
  433. {
  434. struct i2c_msg xfer[2];
  435. u16 reg = cpu_to_be16(r);
  436. u16 data;
  437. int ret;
  438. struct i2c_client *client = codec->control_data;
  439. /* Write register */
  440. xfer[0].addr = client->addr;
  441. xfer[0].flags = 0;
  442. xfer[0].len = 2;
  443. xfer[0].buf = (u8 *)&reg;
  444. /* Read data */
  445. xfer[1].addr = client->addr;
  446. xfer[1].flags = I2C_M_RD;
  447. xfer[1].len = 2;
  448. xfer[1].buf = (u8 *)&data;
  449. ret = i2c_transfer(client->adapter, xfer, 2);
  450. if (ret != 2) {
  451. dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
  452. return 0;
  453. }
  454. return be16_to_cpu(data);
  455. }
  456. #else
  457. #define snd_soc_16_16_read_i2c NULL
  458. #endif
  459. static unsigned int snd_soc_16_16_read(struct snd_soc_codec *codec,
  460. unsigned int reg)
  461. {
  462. int ret;
  463. unsigned int val;
  464. if (reg >= codec->driver->reg_cache_size ||
  465. snd_soc_codec_volatile_register(codec, reg)) {
  466. if (codec->cache_only)
  467. return -1;
  468. BUG_ON(!codec->hw_read);
  469. return codec->hw_read(codec, reg);
  470. }
  471. ret = snd_soc_cache_read(codec, reg, &val);
  472. if (ret < 0)
  473. return -1;
  474. return val;
  475. }
  476. static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg,
  477. unsigned int value)
  478. {
  479. u8 data[4];
  480. int ret;
  481. data[0] = (reg >> 8) & 0xff;
  482. data[1] = reg & 0xff;
  483. data[2] = (value >> 8) & 0xff;
  484. data[3] = value & 0xff;
  485. if (!snd_soc_codec_volatile_register(codec, reg) &&
  486. reg < codec->driver->reg_cache_size) {
  487. ret = snd_soc_cache_write(codec, reg, value);
  488. if (ret < 0)
  489. return -1;
  490. }
  491. if (codec->cache_only) {
  492. codec->cache_sync = 1;
  493. return 0;
  494. }
  495. ret = codec->hw_write(codec->control_data, data, 4);
  496. if (ret == 4)
  497. return 0;
  498. if (ret < 0)
  499. return ret;
  500. else
  501. return -EIO;
  502. }
  503. #if defined(CONFIG_SPI_MASTER)
  504. static int snd_soc_16_16_spi_write(void *control_data, const char *data,
  505. int len)
  506. {
  507. struct spi_device *spi = control_data;
  508. struct spi_transfer t;
  509. struct spi_message m;
  510. u8 msg[4];
  511. if (len <= 0)
  512. return 0;
  513. msg[0] = data[0];
  514. msg[1] = data[1];
  515. msg[2] = data[2];
  516. msg[3] = data[3];
  517. spi_message_init(&m);
  518. memset(&t, 0, (sizeof t));
  519. t.tx_buf = &msg[0];
  520. t.len = len;
  521. spi_message_add_tail(&t, &m);
  522. spi_sync(spi, &m);
  523. return len;
  524. }
  525. #else
  526. #define snd_soc_16_16_spi_write NULL
  527. #endif
  528. static struct {
  529. int addr_bits;
  530. int data_bits;
  531. int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
  532. int (*spi_write)(void *, const char *, int);
  533. unsigned int (*read)(struct snd_soc_codec *, unsigned int);
  534. unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
  535. } io_types[] = {
  536. {
  537. .addr_bits = 4, .data_bits = 12,
  538. .write = snd_soc_4_12_write, .read = snd_soc_4_12_read,
  539. .spi_write = snd_soc_4_12_spi_write,
  540. },
  541. {
  542. .addr_bits = 7, .data_bits = 9,
  543. .write = snd_soc_7_9_write, .read = snd_soc_7_9_read,
  544. .spi_write = snd_soc_7_9_spi_write,
  545. },
  546. {
  547. .addr_bits = 8, .data_bits = 8,
  548. .write = snd_soc_8_8_write, .read = snd_soc_8_8_read,
  549. .i2c_read = snd_soc_8_8_read_i2c,
  550. .spi_write = snd_soc_8_8_spi_write,
  551. },
  552. {
  553. .addr_bits = 8, .data_bits = 16,
  554. .write = snd_soc_8_16_write, .read = snd_soc_8_16_read,
  555. .i2c_read = snd_soc_8_16_read_i2c,
  556. .spi_write = snd_soc_8_16_spi_write,
  557. },
  558. {
  559. .addr_bits = 16, .data_bits = 8,
  560. .write = snd_soc_16_8_write, .read = snd_soc_16_8_read,
  561. .i2c_read = snd_soc_16_8_read_i2c,
  562. .spi_write = snd_soc_16_8_spi_write,
  563. },
  564. {
  565. .addr_bits = 16, .data_bits = 16,
  566. .write = snd_soc_16_16_write, .read = snd_soc_16_16_read,
  567. .i2c_read = snd_soc_16_16_read_i2c,
  568. .spi_write = snd_soc_16_16_spi_write,
  569. },
  570. };
  571. /**
  572. * snd_soc_codec_set_cache_io: Set up standard I/O functions.
  573. *
  574. * @codec: CODEC to configure.
  575. * @type: Type of cache.
  576. * @addr_bits: Number of bits of register address data.
  577. * @data_bits: Number of bits of data per register.
  578. * @control: Control bus used.
  579. *
  580. * Register formats are frequently shared between many I2C and SPI
  581. * devices. In order to promote code reuse the ASoC core provides
  582. * some standard implementations of CODEC read and write operations
  583. * which can be set up using this function.
  584. *
  585. * The caller is responsible for allocating and initialising the
  586. * actual cache.
  587. *
  588. * Note that at present this code cannot be used by CODECs with
  589. * volatile registers.
  590. */
  591. int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
  592. int addr_bits, int data_bits,
  593. enum snd_soc_control_type control)
  594. {
  595. int i;
  596. for (i = 0; i < ARRAY_SIZE(io_types); i++)
  597. if (io_types[i].addr_bits == addr_bits &&
  598. io_types[i].data_bits == data_bits)
  599. break;
  600. if (i == ARRAY_SIZE(io_types)) {
  601. printk(KERN_ERR
  602. "No I/O functions for %d bit address %d bit data\n",
  603. addr_bits, data_bits);
  604. return -EINVAL;
  605. }
  606. codec->driver->write = io_types[i].write;
  607. codec->driver->read = io_types[i].read;
  608. switch (control) {
  609. case SND_SOC_CUSTOM:
  610. break;
  611. case SND_SOC_I2C:
  612. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  613. codec->hw_write = (hw_write_t)i2c_master_send;
  614. #endif
  615. if (io_types[i].i2c_read)
  616. codec->hw_read = io_types[i].i2c_read;
  617. codec->control_data = container_of(codec->dev,
  618. struct i2c_client,
  619. dev);
  620. break;
  621. case SND_SOC_SPI:
  622. if (io_types[i].spi_write)
  623. codec->hw_write = io_types[i].spi_write;
  624. codec->control_data = container_of(codec->dev,
  625. struct spi_device,
  626. dev);
  627. break;
  628. }
  629. return 0;
  630. }
  631. EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
  632. static int snd_soc_flat_cache_sync(struct snd_soc_codec *codec)
  633. {
  634. int i;
  635. struct snd_soc_codec_driver *codec_drv;
  636. unsigned int val;
  637. codec_drv = codec->driver;
  638. for (i = 0; i < codec_drv->reg_cache_size; ++i) {
  639. snd_soc_cache_read(codec, i, &val);
  640. if (codec_drv->reg_cache_default) {
  641. switch (codec_drv->reg_word_size) {
  642. case 1: {
  643. const u8 *cache;
  644. cache = codec_drv->reg_cache_default;
  645. if (cache[i] == val)
  646. continue;
  647. }
  648. break;
  649. case 2: {
  650. const u16 *cache;
  651. cache = codec_drv->reg_cache_default;
  652. if (cache[i] == val)
  653. continue;
  654. }
  655. break;
  656. default:
  657. BUG();
  658. }
  659. }
  660. snd_soc_write(codec, i, val);
  661. dev_dbg(codec->dev, "Synced register %#x, value = %#x\n",
  662. i, val);
  663. }
  664. return 0;
  665. }
  666. static int snd_soc_flat_cache_write(struct snd_soc_codec *codec,
  667. unsigned int reg, unsigned int value)
  668. {
  669. switch (codec->driver->reg_word_size) {
  670. case 1: {
  671. u8 *cache;
  672. cache = codec->reg_cache;
  673. cache[reg] = value;
  674. }
  675. break;
  676. case 2: {
  677. u16 *cache;
  678. cache = codec->reg_cache;
  679. cache[reg] = value;
  680. }
  681. break;
  682. default:
  683. BUG();
  684. }
  685. return 0;
  686. }
  687. static int snd_soc_flat_cache_read(struct snd_soc_codec *codec,
  688. unsigned int reg, unsigned int *value)
  689. {
  690. switch (codec->driver->reg_word_size) {
  691. case 1: {
  692. u8 *cache;
  693. cache = codec->reg_cache;
  694. *value = cache[reg];
  695. }
  696. break;
  697. case 2: {
  698. u16 *cache;
  699. cache = codec->reg_cache;
  700. *value = cache[reg];
  701. }
  702. break;
  703. default:
  704. BUG();
  705. }
  706. return 0;
  707. }
  708. static int snd_soc_flat_cache_exit(struct snd_soc_codec *codec)
  709. {
  710. if (!codec->reg_cache)
  711. return 0;
  712. kfree(codec->reg_cache);
  713. codec->reg_cache = NULL;
  714. return 0;
  715. }
  716. static int snd_soc_flat_cache_init(struct snd_soc_codec *codec)
  717. {
  718. struct snd_soc_codec_driver *codec_drv;
  719. size_t reg_size;
  720. codec_drv = codec->driver;
  721. reg_size = codec_drv->reg_cache_size * codec_drv->reg_word_size;
  722. if (codec_drv->reg_cache_default)
  723. codec->reg_cache = kmemdup(codec_drv->reg_cache_default,
  724. reg_size, GFP_KERNEL);
  725. else
  726. codec->reg_cache = kzalloc(reg_size, GFP_KERNEL);
  727. if (!codec->reg_cache)
  728. return -ENOMEM;
  729. return 0;
  730. }
  731. /* an array of all supported compression types */
  732. static const struct snd_soc_cache_ops cache_types[] = {
  733. {
  734. .id = SND_SOC_NO_COMPRESSION,
  735. .init = snd_soc_flat_cache_init,
  736. .exit = snd_soc_flat_cache_exit,
  737. .read = snd_soc_flat_cache_read,
  738. .write = snd_soc_flat_cache_write,
  739. .sync = snd_soc_flat_cache_sync
  740. }
  741. };
  742. int snd_soc_cache_init(struct snd_soc_codec *codec)
  743. {
  744. int i;
  745. for (i = 0; i < ARRAY_SIZE(cache_types); ++i)
  746. if (cache_types[i].id == codec->driver->compress_type)
  747. break;
  748. if (i == ARRAY_SIZE(cache_types)) {
  749. dev_err(codec->dev, "Could not match compress type: %d\n",
  750. codec->driver->compress_type);
  751. return -EINVAL;
  752. }
  753. mutex_init(&codec->cache_rw_mutex);
  754. codec->cache_ops = &cache_types[i];
  755. if (codec->cache_ops->init)
  756. return codec->cache_ops->init(codec);
  757. return -EINVAL;
  758. }
  759. /*
  760. * NOTE: keep in mind that this function might be called
  761. * multiple times.
  762. */
  763. int snd_soc_cache_exit(struct snd_soc_codec *codec)
  764. {
  765. if (codec->cache_ops && codec->cache_ops->exit)
  766. return codec->cache_ops->exit(codec);
  767. return -EINVAL;
  768. }
  769. /**
  770. * snd_soc_cache_read: Fetch the value of a given register from the cache.
  771. *
  772. * @codec: CODEC to configure.
  773. * @reg: The register index.
  774. * @value: The value to be returned.
  775. */
  776. int snd_soc_cache_read(struct snd_soc_codec *codec,
  777. unsigned int reg, unsigned int *value)
  778. {
  779. int ret;
  780. mutex_lock(&codec->cache_rw_mutex);
  781. if (value && codec->cache_ops && codec->cache_ops->read) {
  782. ret = codec->cache_ops->read(codec, reg, value);
  783. mutex_unlock(&codec->cache_rw_mutex);
  784. return ret;
  785. }
  786. mutex_unlock(&codec->cache_rw_mutex);
  787. return -EINVAL;
  788. }
  789. EXPORT_SYMBOL_GPL(snd_soc_cache_read);
  790. /**
  791. * snd_soc_cache_write: Set the value of a given register in the cache.
  792. *
  793. * @codec: CODEC to configure.
  794. * @reg: The register index.
  795. * @value: The new register value.
  796. */
  797. int snd_soc_cache_write(struct snd_soc_codec *codec,
  798. unsigned int reg, unsigned int value)
  799. {
  800. int ret;
  801. mutex_lock(&codec->cache_rw_mutex);
  802. if (codec->cache_ops && codec->cache_ops->write) {
  803. ret = codec->cache_ops->write(codec, reg, value);
  804. mutex_unlock(&codec->cache_rw_mutex);
  805. return ret;
  806. }
  807. mutex_unlock(&codec->cache_rw_mutex);
  808. return -EINVAL;
  809. }
  810. EXPORT_SYMBOL_GPL(snd_soc_cache_write);
  811. /**
  812. * snd_soc_cache_sync: Sync the register cache with the hardware.
  813. *
  814. * @codec: CODEC to configure.
  815. *
  816. * Any registers that should not be synced should be marked as
  817. * volatile. In general drivers can choose not to use the provided
  818. * syncing functionality if they so require.
  819. */
  820. int snd_soc_cache_sync(struct snd_soc_codec *codec)
  821. {
  822. int ret;
  823. if (!codec->cache_sync) {
  824. return 0;
  825. }
  826. if (codec->cache_ops && codec->cache_ops->sync) {
  827. ret = codec->cache_ops->sync(codec);
  828. if (!ret)
  829. codec->cache_sync = 0;
  830. return ret;
  831. }
  832. return -EINVAL;
  833. }
  834. EXPORT_SYMBOL_GPL(snd_soc_cache_sync);