twl4030.c 70 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl4030.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x91, /* REG_CODEC_MODE (0x1) */
  43. 0xc3, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x20, /* REG_ANAMICL (0x5) */
  47. 0x00, /* REG_ANAMICR (0x6) */
  48. 0x00, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0c, /* REG_ATXL1PGA (0xA) */
  52. 0x0c, /* REG_ATXR1PGA (0xB) */
  53. 0x00, /* REG_AVTXL2PGA (0xC) */
  54. 0x00, /* REG_AVTXR2PGA (0xD) */
  55. 0x01, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x00, /* REG_ARXR1PGA (0x10) */
  58. 0x00, /* REG_ARXL1PGA (0x11) */
  59. 0x6c, /* REG_ARXR2PGA (0x12) */
  60. 0x6c, /* REG_ARXL2PGA (0x13) */
  61. 0x00, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x0c, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x00, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x24, /* REG_HS_SEL (0x22) */
  76. 0x0a, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x00, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x00, /* REG_DTMF_TONOFF (0x35) */
  95. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x16, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
  116. };
  117. /* codec private data */
  118. struct twl4030_priv {
  119. struct snd_soc_codec codec;
  120. unsigned int bypass_state;
  121. unsigned int codec_powered;
  122. unsigned int codec_muted;
  123. struct snd_pcm_substream *master_substream;
  124. struct snd_pcm_substream *slave_substream;
  125. unsigned int configured;
  126. unsigned int rate;
  127. unsigned int sample_bits;
  128. unsigned int channels;
  129. unsigned int sysclk;
  130. /* Headset output state handling */
  131. unsigned int hsl_enabled;
  132. unsigned int hsr_enabled;
  133. };
  134. /*
  135. * read twl4030 register cache
  136. */
  137. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  138. unsigned int reg)
  139. {
  140. u8 *cache = codec->reg_cache;
  141. if (reg >= TWL4030_CACHEREGNUM)
  142. return -EIO;
  143. return cache[reg];
  144. }
  145. /*
  146. * write twl4030 register cache
  147. */
  148. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  149. u8 reg, u8 value)
  150. {
  151. u8 *cache = codec->reg_cache;
  152. if (reg >= TWL4030_CACHEREGNUM)
  153. return;
  154. cache[reg] = value;
  155. }
  156. /*
  157. * write to the twl4030 register space
  158. */
  159. static int twl4030_write(struct snd_soc_codec *codec,
  160. unsigned int reg, unsigned int value)
  161. {
  162. twl4030_write_reg_cache(codec, reg, value);
  163. if (likely(reg < TWL4030_REG_SW_SHADOW))
  164. return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value,
  165. reg);
  166. else
  167. return 0;
  168. }
  169. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  170. {
  171. struct twl4030_priv *twl4030 = codec->private_data;
  172. int mode;
  173. if (enable == twl4030->codec_powered)
  174. return;
  175. if (enable)
  176. mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
  177. else
  178. mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
  179. if (mode >= 0) {
  180. twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
  181. twl4030->codec_powered = enable;
  182. }
  183. /* REVISIT: this delay is present in TI sample drivers */
  184. /* but there seems to be no TRM requirement for it */
  185. udelay(10);
  186. }
  187. static void twl4030_init_chip(struct snd_soc_codec *codec)
  188. {
  189. u8 *cache = codec->reg_cache;
  190. int i;
  191. /* clear CODECPDZ prior to setting register defaults */
  192. twl4030_codec_enable(codec, 0);
  193. /* set all audio section registers to reasonable defaults */
  194. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  195. twl4030_write(codec, i, cache[i]);
  196. }
  197. static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
  198. {
  199. struct twl4030_priv *twl4030 = codec->private_data;
  200. int status;
  201. if (mute == twl4030->codec_muted)
  202. return;
  203. if (mute)
  204. /* Disable PLL */
  205. status = twl4030_codec_disable_resource(TWL4030_CODEC_RES_APLL);
  206. else
  207. /* Enable PLL */
  208. status = twl4030_codec_enable_resource(TWL4030_CODEC_RES_APLL);
  209. if (status >= 0)
  210. twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
  211. twl4030->codec_muted = mute;
  212. }
  213. static void twl4030_power_up(struct snd_soc_codec *codec)
  214. {
  215. struct twl4030_priv *twl4030 = codec->private_data;
  216. u8 anamicl, regmisc1, byte;
  217. int i = 0;
  218. if (twl4030->codec_powered)
  219. return;
  220. /* set CODECPDZ to turn on codec */
  221. twl4030_codec_enable(codec, 1);
  222. /* initiate offset cancellation */
  223. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  224. twl4030_write(codec, TWL4030_REG_ANAMICL,
  225. anamicl | TWL4030_CNCL_OFFSET_START);
  226. /* wait for offset cancellation to complete */
  227. do {
  228. /* this takes a little while, so don't slam i2c */
  229. udelay(2000);
  230. twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  231. TWL4030_REG_ANAMICL);
  232. } while ((i++ < 100) &&
  233. ((byte & TWL4030_CNCL_OFFSET_START) ==
  234. TWL4030_CNCL_OFFSET_START));
  235. /* Make sure that the reg_cache has the same value as the HW */
  236. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  237. /* anti-pop when changing analog gain */
  238. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  239. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  240. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  241. /* toggle CODECPDZ as per TRM */
  242. twl4030_codec_enable(codec, 0);
  243. twl4030_codec_enable(codec, 1);
  244. }
  245. /*
  246. * Unconditional power down
  247. */
  248. static void twl4030_power_down(struct snd_soc_codec *codec)
  249. {
  250. /* power down */
  251. twl4030_codec_enable(codec, 0);
  252. }
  253. /* Earpiece */
  254. static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
  255. SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
  256. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
  257. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
  258. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
  259. };
  260. /* PreDrive Left */
  261. static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
  262. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
  263. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
  264. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
  265. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
  266. };
  267. /* PreDrive Right */
  268. static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
  269. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
  270. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
  271. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
  272. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
  273. };
  274. /* Headset Left */
  275. static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
  276. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
  277. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
  278. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
  279. };
  280. /* Headset Right */
  281. static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
  282. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
  283. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
  284. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
  285. };
  286. /* Carkit Left */
  287. static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
  288. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
  289. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
  290. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
  291. };
  292. /* Carkit Right */
  293. static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
  294. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
  295. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
  296. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
  297. };
  298. /* Handsfree Left */
  299. static const char *twl4030_handsfreel_texts[] =
  300. {"Voice", "AudioL1", "AudioL2", "AudioR2"};
  301. static const struct soc_enum twl4030_handsfreel_enum =
  302. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  303. ARRAY_SIZE(twl4030_handsfreel_texts),
  304. twl4030_handsfreel_texts);
  305. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  306. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  307. /* Handsfree Left virtual mute */
  308. static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
  309. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
  310. /* Handsfree Right */
  311. static const char *twl4030_handsfreer_texts[] =
  312. {"Voice", "AudioR1", "AudioR2", "AudioL2"};
  313. static const struct soc_enum twl4030_handsfreer_enum =
  314. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  315. ARRAY_SIZE(twl4030_handsfreer_texts),
  316. twl4030_handsfreer_texts);
  317. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  318. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  319. /* Handsfree Right virtual mute */
  320. static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
  321. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
  322. /* Vibra */
  323. /* Vibra audio path selection */
  324. static const char *twl4030_vibra_texts[] =
  325. {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
  326. static const struct soc_enum twl4030_vibra_enum =
  327. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
  328. ARRAY_SIZE(twl4030_vibra_texts),
  329. twl4030_vibra_texts);
  330. static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
  331. SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
  332. /* Vibra path selection: local vibrator (PWM) or audio driven */
  333. static const char *twl4030_vibrapath_texts[] =
  334. {"Local vibrator", "Audio"};
  335. static const struct soc_enum twl4030_vibrapath_enum =
  336. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
  337. ARRAY_SIZE(twl4030_vibrapath_texts),
  338. twl4030_vibrapath_texts);
  339. static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
  340. SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
  341. /* Left analog microphone selection */
  342. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
  343. SOC_DAPM_SINGLE("Main Mic Capture Switch",
  344. TWL4030_REG_ANAMICL, 0, 1, 0),
  345. SOC_DAPM_SINGLE("Headset Mic Capture Switch",
  346. TWL4030_REG_ANAMICL, 1, 1, 0),
  347. SOC_DAPM_SINGLE("AUXL Capture Switch",
  348. TWL4030_REG_ANAMICL, 2, 1, 0),
  349. SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
  350. TWL4030_REG_ANAMICL, 3, 1, 0),
  351. };
  352. /* Right analog microphone selection */
  353. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
  354. SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
  355. SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
  356. };
  357. /* TX1 L/R Analog/Digital microphone selection */
  358. static const char *twl4030_micpathtx1_texts[] =
  359. {"Analog", "Digimic0"};
  360. static const struct soc_enum twl4030_micpathtx1_enum =
  361. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  362. ARRAY_SIZE(twl4030_micpathtx1_texts),
  363. twl4030_micpathtx1_texts);
  364. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  365. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  366. /* TX2 L/R Analog/Digital microphone selection */
  367. static const char *twl4030_micpathtx2_texts[] =
  368. {"Analog", "Digimic1"};
  369. static const struct soc_enum twl4030_micpathtx2_enum =
  370. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  371. ARRAY_SIZE(twl4030_micpathtx2_texts),
  372. twl4030_micpathtx2_texts);
  373. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  374. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  375. /* Analog bypass for AudioR1 */
  376. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  377. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  378. /* Analog bypass for AudioL1 */
  379. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  380. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  381. /* Analog bypass for AudioR2 */
  382. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  383. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  384. /* Analog bypass for AudioL2 */
  385. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  386. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  387. /* Analog bypass for Voice */
  388. static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
  389. SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
  390. /* Digital bypass gain, 0 mutes the bypass */
  391. static const unsigned int twl4030_dapm_dbypass_tlv[] = {
  392. TLV_DB_RANGE_HEAD(2),
  393. 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
  394. 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
  395. };
  396. /* Digital bypass left (TX1L -> RX2L) */
  397. static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
  398. SOC_DAPM_SINGLE_TLV("Volume",
  399. TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
  400. twl4030_dapm_dbypass_tlv);
  401. /* Digital bypass right (TX1R -> RX2R) */
  402. static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
  403. SOC_DAPM_SINGLE_TLV("Volume",
  404. TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
  405. twl4030_dapm_dbypass_tlv);
  406. /*
  407. * Voice Sidetone GAIN volume control:
  408. * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
  409. */
  410. static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
  411. /* Digital bypass voice: sidetone (VUL -> VDL)*/
  412. static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
  413. SOC_DAPM_SINGLE_TLV("Volume",
  414. TWL4030_REG_VSTPGA, 0, 0x29, 0,
  415. twl4030_dapm_dbypassv_tlv);
  416. static int micpath_event(struct snd_soc_dapm_widget *w,
  417. struct snd_kcontrol *kcontrol, int event)
  418. {
  419. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  420. unsigned char adcmicsel, micbias_ctl;
  421. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  422. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  423. /* Prepare the bits for the given TX path:
  424. * shift_l == 0: TX1 microphone path
  425. * shift_l == 2: TX2 microphone path */
  426. if (e->shift_l) {
  427. /* TX2 microphone path */
  428. if (adcmicsel & TWL4030_TX2IN_SEL)
  429. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  430. else
  431. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  432. } else {
  433. /* TX1 microphone path */
  434. if (adcmicsel & TWL4030_TX1IN_SEL)
  435. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  436. else
  437. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  438. }
  439. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  440. return 0;
  441. }
  442. /*
  443. * Output PGA builder:
  444. * Handle the muting and unmuting of the given output (turning off the
  445. * amplifier associated with the output pin)
  446. * On mute bypass the reg_cache and mute the volume
  447. * On unmute: restore the register content
  448. * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
  449. */
  450. #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
  451. static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
  452. struct snd_kcontrol *kcontrol, int event) \
  453. { \
  454. u8 reg_val; \
  455. \
  456. switch (event) { \
  457. case SND_SOC_DAPM_POST_PMU: \
  458. twl4030_write(w->codec, reg, \
  459. twl4030_read_reg_cache(w->codec, reg)); \
  460. break; \
  461. case SND_SOC_DAPM_POST_PMD: \
  462. reg_val = twl4030_read_reg_cache(w->codec, reg); \
  463. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
  464. reg_val & (~mask), \
  465. reg); \
  466. break; \
  467. } \
  468. return 0; \
  469. }
  470. TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
  471. TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
  472. TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
  473. TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
  474. TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
  475. static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
  476. {
  477. unsigned char hs_ctl;
  478. hs_ctl = twl4030_read_reg_cache(codec, reg);
  479. if (ramp) {
  480. /* HF ramp-up */
  481. hs_ctl |= TWL4030_HF_CTL_REF_EN;
  482. twl4030_write(codec, reg, hs_ctl);
  483. udelay(10);
  484. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  485. twl4030_write(codec, reg, hs_ctl);
  486. udelay(40);
  487. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  488. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  489. twl4030_write(codec, reg, hs_ctl);
  490. } else {
  491. /* HF ramp-down */
  492. hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
  493. hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
  494. twl4030_write(codec, reg, hs_ctl);
  495. hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
  496. twl4030_write(codec, reg, hs_ctl);
  497. udelay(40);
  498. hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
  499. twl4030_write(codec, reg, hs_ctl);
  500. }
  501. }
  502. static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
  503. struct snd_kcontrol *kcontrol, int event)
  504. {
  505. switch (event) {
  506. case SND_SOC_DAPM_POST_PMU:
  507. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
  508. break;
  509. case SND_SOC_DAPM_POST_PMD:
  510. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
  511. break;
  512. }
  513. return 0;
  514. }
  515. static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
  516. struct snd_kcontrol *kcontrol, int event)
  517. {
  518. switch (event) {
  519. case SND_SOC_DAPM_POST_PMU:
  520. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
  521. break;
  522. case SND_SOC_DAPM_POST_PMD:
  523. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
  524. break;
  525. }
  526. return 0;
  527. }
  528. static void headset_ramp(struct snd_soc_codec *codec, int ramp)
  529. {
  530. struct snd_soc_device *socdev = codec->socdev;
  531. struct twl4030_setup_data *setup = socdev->codec_data;
  532. unsigned char hs_gain, hs_pop;
  533. struct twl4030_priv *twl4030 = codec->private_data;
  534. /* Base values for ramp delay calculation: 2^19 - 2^26 */
  535. unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
  536. 8388608, 16777216, 33554432, 67108864};
  537. hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
  538. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  539. /* Enable external mute control, this dramatically reduces
  540. * the pop-noise */
  541. if (setup && setup->hs_extmute) {
  542. if (setup->set_hs_extmute) {
  543. setup->set_hs_extmute(1);
  544. } else {
  545. hs_pop |= TWL4030_EXTMUTE;
  546. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  547. }
  548. }
  549. if (ramp) {
  550. /* Headset ramp-up according to the TRM */
  551. hs_pop |= TWL4030_VMID_EN;
  552. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  553. twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
  554. hs_pop |= TWL4030_RAMP_EN;
  555. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  556. /* Wait ramp delay time + 1, so the VMID can settle */
  557. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  558. twl4030->sysclk) + 1);
  559. } else {
  560. /* Headset ramp-down _not_ according to
  561. * the TRM, but in a way that it is working */
  562. hs_pop &= ~TWL4030_RAMP_EN;
  563. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  564. /* Wait ramp delay time + 1, so the VMID can settle */
  565. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  566. twl4030->sysclk) + 1);
  567. /* Bypass the reg_cache to mute the headset */
  568. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  569. hs_gain & (~0x0f),
  570. TWL4030_REG_HS_GAIN_SET);
  571. hs_pop &= ~TWL4030_VMID_EN;
  572. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  573. }
  574. /* Disable external mute */
  575. if (setup && setup->hs_extmute) {
  576. if (setup->set_hs_extmute) {
  577. setup->set_hs_extmute(0);
  578. } else {
  579. hs_pop &= ~TWL4030_EXTMUTE;
  580. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  581. }
  582. }
  583. }
  584. static int headsetlpga_event(struct snd_soc_dapm_widget *w,
  585. struct snd_kcontrol *kcontrol, int event)
  586. {
  587. struct twl4030_priv *twl4030 = w->codec->private_data;
  588. switch (event) {
  589. case SND_SOC_DAPM_POST_PMU:
  590. /* Do the ramp-up only once */
  591. if (!twl4030->hsr_enabled)
  592. headset_ramp(w->codec, 1);
  593. twl4030->hsl_enabled = 1;
  594. break;
  595. case SND_SOC_DAPM_POST_PMD:
  596. /* Do the ramp-down only if both headsetL/R is disabled */
  597. if (!twl4030->hsr_enabled)
  598. headset_ramp(w->codec, 0);
  599. twl4030->hsl_enabled = 0;
  600. break;
  601. }
  602. return 0;
  603. }
  604. static int headsetrpga_event(struct snd_soc_dapm_widget *w,
  605. struct snd_kcontrol *kcontrol, int event)
  606. {
  607. struct twl4030_priv *twl4030 = w->codec->private_data;
  608. switch (event) {
  609. case SND_SOC_DAPM_POST_PMU:
  610. /* Do the ramp-up only once */
  611. if (!twl4030->hsl_enabled)
  612. headset_ramp(w->codec, 1);
  613. twl4030->hsr_enabled = 1;
  614. break;
  615. case SND_SOC_DAPM_POST_PMD:
  616. /* Do the ramp-down only if both headsetL/R is disabled */
  617. if (!twl4030->hsl_enabled)
  618. headset_ramp(w->codec, 0);
  619. twl4030->hsr_enabled = 0;
  620. break;
  621. }
  622. return 0;
  623. }
  624. static int bypass_event(struct snd_soc_dapm_widget *w,
  625. struct snd_kcontrol *kcontrol, int event)
  626. {
  627. struct soc_mixer_control *m =
  628. (struct soc_mixer_control *)w->kcontrols->private_value;
  629. struct twl4030_priv *twl4030 = w->codec->private_data;
  630. unsigned char reg, misc;
  631. reg = twl4030_read_reg_cache(w->codec, m->reg);
  632. /*
  633. * bypass_state[0:3] - analog HiFi bypass
  634. * bypass_state[4] - analog voice bypass
  635. * bypass_state[5] - digital voice bypass
  636. * bypass_state[6:7] - digital HiFi bypass
  637. */
  638. if (m->reg == TWL4030_REG_VSTPGA) {
  639. /* Voice digital bypass */
  640. if (reg)
  641. twl4030->bypass_state |= (1 << 5);
  642. else
  643. twl4030->bypass_state &= ~(1 << 5);
  644. } else if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
  645. /* Analog bypass */
  646. if (reg & (1 << m->shift))
  647. twl4030->bypass_state |=
  648. (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  649. else
  650. twl4030->bypass_state &=
  651. ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  652. } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) {
  653. /* Analog voice bypass */
  654. if (reg & (1 << m->shift))
  655. twl4030->bypass_state |= (1 << 4);
  656. else
  657. twl4030->bypass_state &= ~(1 << 4);
  658. } else {
  659. /* Digital bypass */
  660. if (reg & (0x7 << m->shift))
  661. twl4030->bypass_state |= (1 << (m->shift ? 7 : 6));
  662. else
  663. twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6));
  664. }
  665. /* Enable master analog loopback mode if any analog switch is enabled*/
  666. misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1);
  667. if (twl4030->bypass_state & 0x1F)
  668. misc |= TWL4030_FMLOOP_EN;
  669. else
  670. misc &= ~TWL4030_FMLOOP_EN;
  671. twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc);
  672. if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
  673. if (twl4030->bypass_state)
  674. twl4030_codec_mute(w->codec, 0);
  675. else
  676. twl4030_codec_mute(w->codec, 1);
  677. }
  678. return 0;
  679. }
  680. /*
  681. * Some of the gain controls in TWL (mostly those which are associated with
  682. * the outputs) are implemented in an interesting way:
  683. * 0x0 : Power down (mute)
  684. * 0x1 : 6dB
  685. * 0x2 : 0 dB
  686. * 0x3 : -6 dB
  687. * Inverting not going to help with these.
  688. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  689. */
  690. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  691. xinvert, tlv_array) \
  692. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  693. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  694. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  695. .tlv.p = (tlv_array), \
  696. .info = snd_soc_info_volsw, \
  697. .get = snd_soc_get_volsw_twl4030, \
  698. .put = snd_soc_put_volsw_twl4030, \
  699. .private_value = (unsigned long)&(struct soc_mixer_control) \
  700. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  701. .max = xmax, .invert = xinvert} }
  702. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  703. xinvert, tlv_array) \
  704. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  705. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  706. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  707. .tlv.p = (tlv_array), \
  708. .info = snd_soc_info_volsw_2r, \
  709. .get = snd_soc_get_volsw_r2_twl4030,\
  710. .put = snd_soc_put_volsw_r2_twl4030, \
  711. .private_value = (unsigned long)&(struct soc_mixer_control) \
  712. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  713. .rshift = xshift, .max = xmax, .invert = xinvert} }
  714. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  715. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  716. xinvert, tlv_array)
  717. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  718. struct snd_ctl_elem_value *ucontrol)
  719. {
  720. struct soc_mixer_control *mc =
  721. (struct soc_mixer_control *)kcontrol->private_value;
  722. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  723. unsigned int reg = mc->reg;
  724. unsigned int shift = mc->shift;
  725. unsigned int rshift = mc->rshift;
  726. int max = mc->max;
  727. int mask = (1 << fls(max)) - 1;
  728. ucontrol->value.integer.value[0] =
  729. (snd_soc_read(codec, reg) >> shift) & mask;
  730. if (ucontrol->value.integer.value[0])
  731. ucontrol->value.integer.value[0] =
  732. max + 1 - ucontrol->value.integer.value[0];
  733. if (shift != rshift) {
  734. ucontrol->value.integer.value[1] =
  735. (snd_soc_read(codec, reg) >> rshift) & mask;
  736. if (ucontrol->value.integer.value[1])
  737. ucontrol->value.integer.value[1] =
  738. max + 1 - ucontrol->value.integer.value[1];
  739. }
  740. return 0;
  741. }
  742. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  743. struct snd_ctl_elem_value *ucontrol)
  744. {
  745. struct soc_mixer_control *mc =
  746. (struct soc_mixer_control *)kcontrol->private_value;
  747. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  748. unsigned int reg = mc->reg;
  749. unsigned int shift = mc->shift;
  750. unsigned int rshift = mc->rshift;
  751. int max = mc->max;
  752. int mask = (1 << fls(max)) - 1;
  753. unsigned short val, val2, val_mask;
  754. val = (ucontrol->value.integer.value[0] & mask);
  755. val_mask = mask << shift;
  756. if (val)
  757. val = max + 1 - val;
  758. val = val << shift;
  759. if (shift != rshift) {
  760. val2 = (ucontrol->value.integer.value[1] & mask);
  761. val_mask |= mask << rshift;
  762. if (val2)
  763. val2 = max + 1 - val2;
  764. val |= val2 << rshift;
  765. }
  766. return snd_soc_update_bits(codec, reg, val_mask, val);
  767. }
  768. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  769. struct snd_ctl_elem_value *ucontrol)
  770. {
  771. struct soc_mixer_control *mc =
  772. (struct soc_mixer_control *)kcontrol->private_value;
  773. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  774. unsigned int reg = mc->reg;
  775. unsigned int reg2 = mc->rreg;
  776. unsigned int shift = mc->shift;
  777. int max = mc->max;
  778. int mask = (1<<fls(max))-1;
  779. ucontrol->value.integer.value[0] =
  780. (snd_soc_read(codec, reg) >> shift) & mask;
  781. ucontrol->value.integer.value[1] =
  782. (snd_soc_read(codec, reg2) >> shift) & mask;
  783. if (ucontrol->value.integer.value[0])
  784. ucontrol->value.integer.value[0] =
  785. max + 1 - ucontrol->value.integer.value[0];
  786. if (ucontrol->value.integer.value[1])
  787. ucontrol->value.integer.value[1] =
  788. max + 1 - ucontrol->value.integer.value[1];
  789. return 0;
  790. }
  791. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  792. struct snd_ctl_elem_value *ucontrol)
  793. {
  794. struct soc_mixer_control *mc =
  795. (struct soc_mixer_control *)kcontrol->private_value;
  796. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  797. unsigned int reg = mc->reg;
  798. unsigned int reg2 = mc->rreg;
  799. unsigned int shift = mc->shift;
  800. int max = mc->max;
  801. int mask = (1 << fls(max)) - 1;
  802. int err;
  803. unsigned short val, val2, val_mask;
  804. val_mask = mask << shift;
  805. val = (ucontrol->value.integer.value[0] & mask);
  806. val2 = (ucontrol->value.integer.value[1] & mask);
  807. if (val)
  808. val = max + 1 - val;
  809. if (val2)
  810. val2 = max + 1 - val2;
  811. val = val << shift;
  812. val2 = val2 << shift;
  813. err = snd_soc_update_bits(codec, reg, val_mask, val);
  814. if (err < 0)
  815. return err;
  816. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  817. return err;
  818. }
  819. /* Codec operation modes */
  820. static const char *twl4030_op_modes_texts[] = {
  821. "Option 2 (voice/audio)", "Option 1 (audio)"
  822. };
  823. static const struct soc_enum twl4030_op_modes_enum =
  824. SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
  825. ARRAY_SIZE(twl4030_op_modes_texts),
  826. twl4030_op_modes_texts);
  827. static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
  828. struct snd_ctl_elem_value *ucontrol)
  829. {
  830. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  831. struct twl4030_priv *twl4030 = codec->private_data;
  832. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  833. unsigned short val;
  834. unsigned short mask, bitmask;
  835. if (twl4030->configured) {
  836. printk(KERN_ERR "twl4030 operation mode cannot be "
  837. "changed on-the-fly\n");
  838. return -EBUSY;
  839. }
  840. for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
  841. ;
  842. if (ucontrol->value.enumerated.item[0] > e->max - 1)
  843. return -EINVAL;
  844. val = ucontrol->value.enumerated.item[0] << e->shift_l;
  845. mask = (bitmask - 1) << e->shift_l;
  846. if (e->shift_l != e->shift_r) {
  847. if (ucontrol->value.enumerated.item[1] > e->max - 1)
  848. return -EINVAL;
  849. val |= ucontrol->value.enumerated.item[1] << e->shift_r;
  850. mask |= (bitmask - 1) << e->shift_r;
  851. }
  852. return snd_soc_update_bits(codec, e->reg, mask, val);
  853. }
  854. /*
  855. * FGAIN volume control:
  856. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  857. */
  858. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  859. /*
  860. * CGAIN volume control:
  861. * 0 dB to 12 dB in 6 dB steps
  862. * value 2 and 3 means 12 dB
  863. */
  864. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  865. /*
  866. * Voice Downlink GAIN volume control:
  867. * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
  868. */
  869. static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
  870. /*
  871. * Analog playback gain
  872. * -24 dB to 12 dB in 2 dB steps
  873. */
  874. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  875. /*
  876. * Gain controls tied to outputs
  877. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  878. */
  879. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  880. /*
  881. * Gain control for earpiece amplifier
  882. * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
  883. */
  884. static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
  885. /*
  886. * Capture gain after the ADCs
  887. * from 0 dB to 31 dB in 1 dB steps
  888. */
  889. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  890. /*
  891. * Gain control for input amplifiers
  892. * 0 dB to 30 dB in 6 dB steps
  893. */
  894. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  895. /* AVADC clock priority */
  896. static const char *twl4030_avadc_clk_priority_texts[] = {
  897. "Voice high priority", "HiFi high priority"
  898. };
  899. static const struct soc_enum twl4030_avadc_clk_priority_enum =
  900. SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
  901. ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
  902. twl4030_avadc_clk_priority_texts);
  903. static const char *twl4030_rampdelay_texts[] = {
  904. "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
  905. "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
  906. "3495/2581/1748 ms"
  907. };
  908. static const struct soc_enum twl4030_rampdelay_enum =
  909. SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
  910. ARRAY_SIZE(twl4030_rampdelay_texts),
  911. twl4030_rampdelay_texts);
  912. /* Vibra H-bridge direction mode */
  913. static const char *twl4030_vibradirmode_texts[] = {
  914. "Vibra H-bridge direction", "Audio data MSB",
  915. };
  916. static const struct soc_enum twl4030_vibradirmode_enum =
  917. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
  918. ARRAY_SIZE(twl4030_vibradirmode_texts),
  919. twl4030_vibradirmode_texts);
  920. /* Vibra H-bridge direction */
  921. static const char *twl4030_vibradir_texts[] = {
  922. "Positive polarity", "Negative polarity",
  923. };
  924. static const struct soc_enum twl4030_vibradir_enum =
  925. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
  926. ARRAY_SIZE(twl4030_vibradir_texts),
  927. twl4030_vibradir_texts);
  928. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  929. /* Codec operation mode control */
  930. SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
  931. snd_soc_get_enum_double,
  932. snd_soc_put_twl4030_opmode_enum_double),
  933. /* Common playback gain controls */
  934. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  935. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  936. 0, 0x3f, 0, digital_fine_tlv),
  937. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  938. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  939. 0, 0x3f, 0, digital_fine_tlv),
  940. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  941. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  942. 6, 0x2, 0, digital_coarse_tlv),
  943. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  944. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  945. 6, 0x2, 0, digital_coarse_tlv),
  946. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  947. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  948. 3, 0x12, 1, analog_tlv),
  949. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  950. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  951. 3, 0x12, 1, analog_tlv),
  952. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  953. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  954. 1, 1, 0),
  955. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  956. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  957. 1, 1, 0),
  958. /* Common voice downlink gain controls */
  959. SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
  960. TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
  961. SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
  962. TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
  963. SOC_SINGLE("DAC Voice Analog Downlink Switch",
  964. TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
  965. /* Separate output gain controls */
  966. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  967. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  968. 4, 3, 0, output_tvl),
  969. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  970. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  971. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  972. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  973. 4, 3, 0, output_tvl),
  974. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  975. TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
  976. /* Common capture gain controls */
  977. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  978. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  979. 0, 0x1f, 0, digital_capture_tlv),
  980. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  981. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  982. 0, 0x1f, 0, digital_capture_tlv),
  983. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  984. 0, 3, 5, 0, input_gain_tlv),
  985. SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
  986. SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
  987. SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
  988. SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
  989. };
  990. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  991. /* Left channel inputs */
  992. SND_SOC_DAPM_INPUT("MAINMIC"),
  993. SND_SOC_DAPM_INPUT("HSMIC"),
  994. SND_SOC_DAPM_INPUT("AUXL"),
  995. SND_SOC_DAPM_INPUT("CARKITMIC"),
  996. /* Right channel inputs */
  997. SND_SOC_DAPM_INPUT("SUBMIC"),
  998. SND_SOC_DAPM_INPUT("AUXR"),
  999. /* Digital microphones (Stereo) */
  1000. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  1001. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  1002. /* Outputs */
  1003. SND_SOC_DAPM_OUTPUT("OUTL"),
  1004. SND_SOC_DAPM_OUTPUT("OUTR"),
  1005. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  1006. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  1007. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  1008. SND_SOC_DAPM_OUTPUT("HSOL"),
  1009. SND_SOC_DAPM_OUTPUT("HSOR"),
  1010. SND_SOC_DAPM_OUTPUT("CARKITL"),
  1011. SND_SOC_DAPM_OUTPUT("CARKITR"),
  1012. SND_SOC_DAPM_OUTPUT("HFL"),
  1013. SND_SOC_DAPM_OUTPUT("HFR"),
  1014. SND_SOC_DAPM_OUTPUT("VIBRA"),
  1015. /* DACs */
  1016. SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
  1017. SND_SOC_NOPM, 0, 0),
  1018. SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
  1019. SND_SOC_NOPM, 0, 0),
  1020. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
  1021. SND_SOC_NOPM, 0, 0),
  1022. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
  1023. SND_SOC_NOPM, 0, 0),
  1024. SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
  1025. SND_SOC_NOPM, 0, 0),
  1026. /* Analog bypasses */
  1027. SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1028. &twl4030_dapm_abypassr1_control, bypass_event,
  1029. SND_SOC_DAPM_POST_REG),
  1030. SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1031. &twl4030_dapm_abypassl1_control,
  1032. bypass_event, SND_SOC_DAPM_POST_REG),
  1033. SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1034. &twl4030_dapm_abypassr2_control,
  1035. bypass_event, SND_SOC_DAPM_POST_REG),
  1036. SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1037. &twl4030_dapm_abypassl2_control,
  1038. bypass_event, SND_SOC_DAPM_POST_REG),
  1039. SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
  1040. &twl4030_dapm_abypassv_control,
  1041. bypass_event, SND_SOC_DAPM_POST_REG),
  1042. /* Digital bypasses */
  1043. SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
  1044. &twl4030_dapm_dbypassl_control, bypass_event,
  1045. SND_SOC_DAPM_POST_REG),
  1046. SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
  1047. &twl4030_dapm_dbypassr_control, bypass_event,
  1048. SND_SOC_DAPM_POST_REG),
  1049. SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
  1050. &twl4030_dapm_dbypassv_control, bypass_event,
  1051. SND_SOC_DAPM_POST_REG),
  1052. /* Digital mixers, power control for the physical DACs */
  1053. SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
  1054. TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
  1055. SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
  1056. TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
  1057. SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
  1058. TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
  1059. SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
  1060. TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
  1061. SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
  1062. TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
  1063. /* Analog mixers, power control for the physical PGAs */
  1064. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
  1065. TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
  1066. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
  1067. TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
  1068. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
  1069. TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
  1070. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
  1071. TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
  1072. SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
  1073. TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
  1074. /* Output MIXER controls */
  1075. /* Earpiece */
  1076. SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
  1077. &twl4030_dapm_earpiece_controls[0],
  1078. ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
  1079. SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
  1080. 0, 0, NULL, 0, earpiecepga_event,
  1081. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1082. /* PreDrivL/R */
  1083. SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
  1084. &twl4030_dapm_predrivel_controls[0],
  1085. ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
  1086. SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
  1087. 0, 0, NULL, 0, predrivelpga_event,
  1088. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1089. SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
  1090. &twl4030_dapm_predriver_controls[0],
  1091. ARRAY_SIZE(twl4030_dapm_predriver_controls)),
  1092. SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
  1093. 0, 0, NULL, 0, predriverpga_event,
  1094. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1095. /* HeadsetL/R */
  1096. SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
  1097. &twl4030_dapm_hsol_controls[0],
  1098. ARRAY_SIZE(twl4030_dapm_hsol_controls)),
  1099. SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
  1100. 0, 0, NULL, 0, headsetlpga_event,
  1101. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1102. SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
  1103. &twl4030_dapm_hsor_controls[0],
  1104. ARRAY_SIZE(twl4030_dapm_hsor_controls)),
  1105. SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
  1106. 0, 0, NULL, 0, headsetrpga_event,
  1107. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1108. /* CarkitL/R */
  1109. SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
  1110. &twl4030_dapm_carkitl_controls[0],
  1111. ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
  1112. SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
  1113. 0, 0, NULL, 0, carkitlpga_event,
  1114. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1115. SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
  1116. &twl4030_dapm_carkitr_controls[0],
  1117. ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
  1118. SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
  1119. 0, 0, NULL, 0, carkitrpga_event,
  1120. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1121. /* Output MUX controls */
  1122. /* HandsfreeL/R */
  1123. SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
  1124. &twl4030_dapm_handsfreel_control),
  1125. SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
  1126. &twl4030_dapm_handsfreelmute_control),
  1127. SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
  1128. 0, 0, NULL, 0, handsfreelpga_event,
  1129. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1130. SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
  1131. &twl4030_dapm_handsfreer_control),
  1132. SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
  1133. &twl4030_dapm_handsfreermute_control),
  1134. SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
  1135. 0, 0, NULL, 0, handsfreerpga_event,
  1136. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1137. /* Vibra */
  1138. SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
  1139. &twl4030_dapm_vibra_control),
  1140. SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
  1141. &twl4030_dapm_vibrapath_control),
  1142. /* Introducing four virtual ADC, since TWL4030 have four channel for
  1143. capture */
  1144. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  1145. SND_SOC_NOPM, 0, 0),
  1146. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  1147. SND_SOC_NOPM, 0, 0),
  1148. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  1149. SND_SOC_NOPM, 0, 0),
  1150. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  1151. SND_SOC_NOPM, 0, 0),
  1152. /* Analog/Digital mic path selection.
  1153. TX1 Left/Right: either analog Left/Right or Digimic0
  1154. TX2 Left/Right: either analog Left/Right or Digimic1 */
  1155. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  1156. &twl4030_dapm_micpathtx1_control, micpath_event,
  1157. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1158. SND_SOC_DAPM_POST_REG),
  1159. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  1160. &twl4030_dapm_micpathtx2_control, micpath_event,
  1161. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1162. SND_SOC_DAPM_POST_REG),
  1163. /* Analog input mixers for the capture amplifiers */
  1164. SND_SOC_DAPM_MIXER("Analog Left",
  1165. TWL4030_REG_ANAMICL, 4, 0,
  1166. &twl4030_dapm_analoglmic_controls[0],
  1167. ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
  1168. SND_SOC_DAPM_MIXER("Analog Right",
  1169. TWL4030_REG_ANAMICR, 4, 0,
  1170. &twl4030_dapm_analogrmic_controls[0],
  1171. ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
  1172. SND_SOC_DAPM_PGA("ADC Physical Left",
  1173. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  1174. SND_SOC_DAPM_PGA("ADC Physical Right",
  1175. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  1176. SND_SOC_DAPM_PGA("Digimic0 Enable",
  1177. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  1178. SND_SOC_DAPM_PGA("Digimic1 Enable",
  1179. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  1180. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  1181. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  1182. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  1183. };
  1184. static const struct snd_soc_dapm_route intercon[] = {
  1185. {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
  1186. {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
  1187. {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
  1188. {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
  1189. {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
  1190. {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
  1191. {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
  1192. {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
  1193. {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
  1194. {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
  1195. /* Internal playback routings */
  1196. /* Earpiece */
  1197. {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
  1198. {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1199. {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1200. {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1201. {"Earpiece PGA", NULL, "Earpiece Mixer"},
  1202. /* PreDrivL */
  1203. {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1204. {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1205. {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1206. {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1207. {"PredriveL PGA", NULL, "PredriveL Mixer"},
  1208. /* PreDrivR */
  1209. {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1210. {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1211. {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1212. {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1213. {"PredriveR PGA", NULL, "PredriveR Mixer"},
  1214. /* HeadsetL */
  1215. {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1216. {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1217. {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1218. {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
  1219. /* HeadsetR */
  1220. {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1221. {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1222. {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1223. {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
  1224. /* CarkitL */
  1225. {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1226. {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1227. {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1228. {"CarkitL PGA", NULL, "CarkitL Mixer"},
  1229. /* CarkitR */
  1230. {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1231. {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1232. {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1233. {"CarkitR PGA", NULL, "CarkitR Mixer"},
  1234. /* HandsfreeL */
  1235. {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
  1236. {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
  1237. {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1238. {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1239. {"HandsfreeL", "Switch", "HandsfreeL Mux"},
  1240. {"HandsfreeL PGA", NULL, "HandsfreeL"},
  1241. /* HandsfreeR */
  1242. {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
  1243. {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
  1244. {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1245. {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1246. {"HandsfreeR", "Switch", "HandsfreeR Mux"},
  1247. {"HandsfreeR PGA", NULL, "HandsfreeR"},
  1248. /* Vibra */
  1249. {"Vibra Mux", "AudioL1", "DAC Left1"},
  1250. {"Vibra Mux", "AudioR1", "DAC Right1"},
  1251. {"Vibra Mux", "AudioL2", "DAC Left2"},
  1252. {"Vibra Mux", "AudioR2", "DAC Right2"},
  1253. /* outputs */
  1254. {"OUTL", NULL, "Analog L2 Playback Mixer"},
  1255. {"OUTR", NULL, "Analog R2 Playback Mixer"},
  1256. {"EARPIECE", NULL, "Earpiece PGA"},
  1257. {"PREDRIVEL", NULL, "PredriveL PGA"},
  1258. {"PREDRIVER", NULL, "PredriveR PGA"},
  1259. {"HSOL", NULL, "HeadsetL PGA"},
  1260. {"HSOR", NULL, "HeadsetR PGA"},
  1261. {"CARKITL", NULL, "CarkitL PGA"},
  1262. {"CARKITR", NULL, "CarkitR PGA"},
  1263. {"HFL", NULL, "HandsfreeL PGA"},
  1264. {"HFR", NULL, "HandsfreeR PGA"},
  1265. {"Vibra Route", "Audio", "Vibra Mux"},
  1266. {"VIBRA", NULL, "Vibra Route"},
  1267. /* Capture path */
  1268. {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
  1269. {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
  1270. {"Analog Left", "AUXL Capture Switch", "AUXL"},
  1271. {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
  1272. {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
  1273. {"Analog Right", "AUXR Capture Switch", "AUXR"},
  1274. {"ADC Physical Left", NULL, "Analog Left"},
  1275. {"ADC Physical Right", NULL, "Analog Right"},
  1276. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  1277. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  1278. /* TX1 Left capture path */
  1279. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  1280. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1281. /* TX1 Right capture path */
  1282. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  1283. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1284. /* TX2 Left capture path */
  1285. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  1286. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1287. /* TX2 Right capture path */
  1288. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  1289. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1290. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  1291. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  1292. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  1293. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  1294. /* Analog bypass routes */
  1295. {"Right1 Analog Loopback", "Switch", "Analog Right"},
  1296. {"Left1 Analog Loopback", "Switch", "Analog Left"},
  1297. {"Right2 Analog Loopback", "Switch", "Analog Right"},
  1298. {"Left2 Analog Loopback", "Switch", "Analog Left"},
  1299. {"Voice Analog Loopback", "Switch", "Analog Left"},
  1300. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  1301. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  1302. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  1303. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  1304. {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
  1305. /* Digital bypass routes */
  1306. {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
  1307. {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
  1308. {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
  1309. {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
  1310. {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
  1311. {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
  1312. };
  1313. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  1314. {
  1315. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  1316. ARRAY_SIZE(twl4030_dapm_widgets));
  1317. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  1318. snd_soc_dapm_new_widgets(codec);
  1319. return 0;
  1320. }
  1321. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  1322. enum snd_soc_bias_level level)
  1323. {
  1324. struct twl4030_priv *twl4030 = codec->private_data;
  1325. switch (level) {
  1326. case SND_SOC_BIAS_ON:
  1327. twl4030_codec_mute(codec, 0);
  1328. break;
  1329. case SND_SOC_BIAS_PREPARE:
  1330. twl4030_power_up(codec);
  1331. if (twl4030->bypass_state)
  1332. twl4030_codec_mute(codec, 0);
  1333. else
  1334. twl4030_codec_mute(codec, 1);
  1335. break;
  1336. case SND_SOC_BIAS_STANDBY:
  1337. twl4030_power_up(codec);
  1338. if (twl4030->bypass_state)
  1339. twl4030_codec_mute(codec, 0);
  1340. else
  1341. twl4030_codec_mute(codec, 1);
  1342. break;
  1343. case SND_SOC_BIAS_OFF:
  1344. twl4030_power_down(codec);
  1345. break;
  1346. }
  1347. codec->bias_level = level;
  1348. return 0;
  1349. }
  1350. static void twl4030_constraints(struct twl4030_priv *twl4030,
  1351. struct snd_pcm_substream *mst_substream)
  1352. {
  1353. struct snd_pcm_substream *slv_substream;
  1354. /* Pick the stream, which need to be constrained */
  1355. if (mst_substream == twl4030->master_substream)
  1356. slv_substream = twl4030->slave_substream;
  1357. else if (mst_substream == twl4030->slave_substream)
  1358. slv_substream = twl4030->master_substream;
  1359. else /* This should not happen.. */
  1360. return;
  1361. /* Set the constraints according to the already configured stream */
  1362. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1363. SNDRV_PCM_HW_PARAM_RATE,
  1364. twl4030->rate,
  1365. twl4030->rate);
  1366. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1367. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1368. twl4030->sample_bits,
  1369. twl4030->sample_bits);
  1370. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1371. SNDRV_PCM_HW_PARAM_CHANNELS,
  1372. twl4030->channels,
  1373. twl4030->channels);
  1374. }
  1375. /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
  1376. * capture has to be enabled/disabled. */
  1377. static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
  1378. int enable)
  1379. {
  1380. u8 reg, mask;
  1381. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1382. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1383. mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
  1384. else
  1385. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1386. if (enable)
  1387. reg |= mask;
  1388. else
  1389. reg &= ~mask;
  1390. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1391. }
  1392. static int twl4030_startup(struct snd_pcm_substream *substream,
  1393. struct snd_soc_dai *dai)
  1394. {
  1395. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1396. struct snd_soc_device *socdev = rtd->socdev;
  1397. struct snd_soc_codec *codec = socdev->card->codec;
  1398. struct twl4030_priv *twl4030 = codec->private_data;
  1399. if (twl4030->master_substream) {
  1400. twl4030->slave_substream = substream;
  1401. /* The DAI has one configuration for playback and capture, so
  1402. * if the DAI has been already configured then constrain this
  1403. * substream to match it. */
  1404. if (twl4030->configured)
  1405. twl4030_constraints(twl4030, twl4030->master_substream);
  1406. } else {
  1407. if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1408. TWL4030_OPTION_1)) {
  1409. /* In option2 4 channel is not supported, set the
  1410. * constraint for the first stream for channels, the
  1411. * second stream will 'inherit' this cosntraint */
  1412. snd_pcm_hw_constraint_minmax(substream->runtime,
  1413. SNDRV_PCM_HW_PARAM_CHANNELS,
  1414. 2, 2);
  1415. }
  1416. twl4030->master_substream = substream;
  1417. }
  1418. return 0;
  1419. }
  1420. static void twl4030_shutdown(struct snd_pcm_substream *substream,
  1421. struct snd_soc_dai *dai)
  1422. {
  1423. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1424. struct snd_soc_device *socdev = rtd->socdev;
  1425. struct snd_soc_codec *codec = socdev->card->codec;
  1426. struct twl4030_priv *twl4030 = codec->private_data;
  1427. if (twl4030->master_substream == substream)
  1428. twl4030->master_substream = twl4030->slave_substream;
  1429. twl4030->slave_substream = NULL;
  1430. /* If all streams are closed, or the remaining stream has not yet
  1431. * been configured than set the DAI as not configured. */
  1432. if (!twl4030->master_substream)
  1433. twl4030->configured = 0;
  1434. else if (!twl4030->master_substream->runtime->channels)
  1435. twl4030->configured = 0;
  1436. /* If the closing substream had 4 channel, do the necessary cleanup */
  1437. if (substream->runtime->channels == 4)
  1438. twl4030_tdm_enable(codec, substream->stream, 0);
  1439. }
  1440. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  1441. struct snd_pcm_hw_params *params,
  1442. struct snd_soc_dai *dai)
  1443. {
  1444. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1445. struct snd_soc_device *socdev = rtd->socdev;
  1446. struct snd_soc_codec *codec = socdev->card->codec;
  1447. struct twl4030_priv *twl4030 = codec->private_data;
  1448. u8 mode, old_mode, format, old_format;
  1449. /* If the substream has 4 channel, do the necessary setup */
  1450. if (params_channels(params) == 4) {
  1451. format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1452. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  1453. /* Safety check: are we in the correct operating mode and
  1454. * the interface is in TDM mode? */
  1455. if ((mode & TWL4030_OPTION_1) &&
  1456. ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
  1457. twl4030_tdm_enable(codec, substream->stream, 1);
  1458. else
  1459. return -EINVAL;
  1460. }
  1461. if (twl4030->configured)
  1462. /* Ignoring hw_params for already configured DAI */
  1463. return 0;
  1464. /* bit rate */
  1465. old_mode = twl4030_read_reg_cache(codec,
  1466. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1467. mode = old_mode & ~TWL4030_APLL_RATE;
  1468. switch (params_rate(params)) {
  1469. case 8000:
  1470. mode |= TWL4030_APLL_RATE_8000;
  1471. break;
  1472. case 11025:
  1473. mode |= TWL4030_APLL_RATE_11025;
  1474. break;
  1475. case 12000:
  1476. mode |= TWL4030_APLL_RATE_12000;
  1477. break;
  1478. case 16000:
  1479. mode |= TWL4030_APLL_RATE_16000;
  1480. break;
  1481. case 22050:
  1482. mode |= TWL4030_APLL_RATE_22050;
  1483. break;
  1484. case 24000:
  1485. mode |= TWL4030_APLL_RATE_24000;
  1486. break;
  1487. case 32000:
  1488. mode |= TWL4030_APLL_RATE_32000;
  1489. break;
  1490. case 44100:
  1491. mode |= TWL4030_APLL_RATE_44100;
  1492. break;
  1493. case 48000:
  1494. mode |= TWL4030_APLL_RATE_48000;
  1495. break;
  1496. case 96000:
  1497. mode |= TWL4030_APLL_RATE_96000;
  1498. break;
  1499. default:
  1500. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1501. params_rate(params));
  1502. return -EINVAL;
  1503. }
  1504. if (mode != old_mode) {
  1505. /* change rate and set CODECPDZ */
  1506. twl4030_codec_enable(codec, 0);
  1507. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1508. twl4030_codec_enable(codec, 1);
  1509. }
  1510. /* sample size */
  1511. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1512. format = old_format;
  1513. format &= ~TWL4030_DATA_WIDTH;
  1514. switch (params_format(params)) {
  1515. case SNDRV_PCM_FORMAT_S16_LE:
  1516. format |= TWL4030_DATA_WIDTH_16S_16W;
  1517. break;
  1518. case SNDRV_PCM_FORMAT_S24_LE:
  1519. format |= TWL4030_DATA_WIDTH_32S_24W;
  1520. break;
  1521. default:
  1522. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1523. params_format(params));
  1524. return -EINVAL;
  1525. }
  1526. if (format != old_format) {
  1527. /* clear CODECPDZ before changing format (codec requirement) */
  1528. twl4030_codec_enable(codec, 0);
  1529. /* change format */
  1530. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1531. /* set CODECPDZ afterwards */
  1532. twl4030_codec_enable(codec, 1);
  1533. }
  1534. /* Store the important parameters for the DAI configuration and set
  1535. * the DAI as configured */
  1536. twl4030->configured = 1;
  1537. twl4030->rate = params_rate(params);
  1538. twl4030->sample_bits = hw_param_interval(params,
  1539. SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
  1540. twl4030->channels = params_channels(params);
  1541. /* If both playback and capture streams are open, and one of them
  1542. * is setting the hw parameters right now (since we are here), set
  1543. * constraints to the other stream to match the current one. */
  1544. if (twl4030->slave_substream)
  1545. twl4030_constraints(twl4030, substream);
  1546. return 0;
  1547. }
  1548. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1549. int clk_id, unsigned int freq, int dir)
  1550. {
  1551. struct snd_soc_codec *codec = codec_dai->codec;
  1552. struct twl4030_priv *twl4030 = codec->private_data;
  1553. u8 apll_ctrl;
  1554. apll_ctrl = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  1555. apll_ctrl &= ~TWL4030_APLL_INFREQ;
  1556. switch (freq) {
  1557. case 19200000:
  1558. apll_ctrl |= TWL4030_APLL_INFREQ_19200KHZ;
  1559. twl4030->sysclk = 19200;
  1560. break;
  1561. case 26000000:
  1562. apll_ctrl |= TWL4030_APLL_INFREQ_26000KHZ;
  1563. twl4030->sysclk = 26000;
  1564. break;
  1565. case 38400000:
  1566. apll_ctrl |= TWL4030_APLL_INFREQ_38400KHZ;
  1567. twl4030->sysclk = 38400;
  1568. break;
  1569. default:
  1570. printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
  1571. freq);
  1572. return -EINVAL;
  1573. }
  1574. twl4030_write(codec, TWL4030_REG_APLL_CTL, apll_ctrl);
  1575. return 0;
  1576. }
  1577. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1578. unsigned int fmt)
  1579. {
  1580. struct snd_soc_codec *codec = codec_dai->codec;
  1581. u8 old_format, format;
  1582. /* get format */
  1583. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1584. format = old_format;
  1585. /* set master/slave audio interface */
  1586. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1587. case SND_SOC_DAIFMT_CBM_CFM:
  1588. format &= ~(TWL4030_AIF_SLAVE_EN);
  1589. format &= ~(TWL4030_CLK256FS_EN);
  1590. break;
  1591. case SND_SOC_DAIFMT_CBS_CFS:
  1592. format |= TWL4030_AIF_SLAVE_EN;
  1593. format |= TWL4030_CLK256FS_EN;
  1594. break;
  1595. default:
  1596. return -EINVAL;
  1597. }
  1598. /* interface format */
  1599. format &= ~TWL4030_AIF_FORMAT;
  1600. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1601. case SND_SOC_DAIFMT_I2S:
  1602. format |= TWL4030_AIF_FORMAT_CODEC;
  1603. break;
  1604. case SND_SOC_DAIFMT_DSP_A:
  1605. format |= TWL4030_AIF_FORMAT_TDM;
  1606. break;
  1607. default:
  1608. return -EINVAL;
  1609. }
  1610. if (format != old_format) {
  1611. /* clear CODECPDZ before changing format (codec requirement) */
  1612. twl4030_codec_enable(codec, 0);
  1613. /* change format */
  1614. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1615. /* set CODECPDZ afterwards */
  1616. twl4030_codec_enable(codec, 1);
  1617. }
  1618. return 0;
  1619. }
  1620. static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
  1621. {
  1622. struct snd_soc_codec *codec = dai->codec;
  1623. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1624. if (tristate)
  1625. reg |= TWL4030_AIF_TRI_EN;
  1626. else
  1627. reg &= ~TWL4030_AIF_TRI_EN;
  1628. return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
  1629. }
  1630. /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
  1631. * (VTXL, VTXR) for uplink has to be enabled/disabled. */
  1632. static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
  1633. int enable)
  1634. {
  1635. u8 reg, mask;
  1636. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1637. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1638. mask = TWL4030_ARXL1_VRX_EN;
  1639. else
  1640. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1641. if (enable)
  1642. reg |= mask;
  1643. else
  1644. reg &= ~mask;
  1645. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1646. }
  1647. static int twl4030_voice_startup(struct snd_pcm_substream *substream,
  1648. struct snd_soc_dai *dai)
  1649. {
  1650. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1651. struct snd_soc_device *socdev = rtd->socdev;
  1652. struct snd_soc_codec *codec = socdev->card->codec;
  1653. u8 infreq;
  1654. u8 mode;
  1655. /* If the system master clock is not 26MHz, the voice PCM interface is
  1656. * not avilable.
  1657. */
  1658. infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
  1659. & TWL4030_APLL_INFREQ;
  1660. if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
  1661. printk(KERN_ERR "TWL4030 voice startup: "
  1662. "MCLK is not 26MHz, call set_sysclk() on init\n");
  1663. return -EINVAL;
  1664. }
  1665. /* If the codec mode is not option2, the voice PCM interface is not
  1666. * avilable.
  1667. */
  1668. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1669. & TWL4030_OPT_MODE;
  1670. if (mode != TWL4030_OPTION_2) {
  1671. printk(KERN_ERR "TWL4030 voice startup: "
  1672. "the codec mode is not option2\n");
  1673. return -EINVAL;
  1674. }
  1675. return 0;
  1676. }
  1677. static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
  1678. struct snd_soc_dai *dai)
  1679. {
  1680. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1681. struct snd_soc_device *socdev = rtd->socdev;
  1682. struct snd_soc_codec *codec = socdev->card->codec;
  1683. /* Enable voice digital filters */
  1684. twl4030_voice_enable(codec, substream->stream, 0);
  1685. }
  1686. static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
  1687. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1688. {
  1689. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1690. struct snd_soc_device *socdev = rtd->socdev;
  1691. struct snd_soc_codec *codec = socdev->card->codec;
  1692. u8 old_mode, mode;
  1693. /* Enable voice digital filters */
  1694. twl4030_voice_enable(codec, substream->stream, 1);
  1695. /* bit rate */
  1696. old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1697. & ~(TWL4030_CODECPDZ);
  1698. mode = old_mode;
  1699. switch (params_rate(params)) {
  1700. case 8000:
  1701. mode &= ~(TWL4030_SEL_16K);
  1702. break;
  1703. case 16000:
  1704. mode |= TWL4030_SEL_16K;
  1705. break;
  1706. default:
  1707. printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
  1708. params_rate(params));
  1709. return -EINVAL;
  1710. }
  1711. if (mode != old_mode) {
  1712. /* change rate and set CODECPDZ */
  1713. twl4030_codec_enable(codec, 0);
  1714. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1715. twl4030_codec_enable(codec, 1);
  1716. }
  1717. return 0;
  1718. }
  1719. static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1720. int clk_id, unsigned int freq, int dir)
  1721. {
  1722. struct snd_soc_codec *codec = codec_dai->codec;
  1723. u8 apll_ctrl;
  1724. apll_ctrl = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  1725. apll_ctrl &= ~TWL4030_APLL_INFREQ;
  1726. switch (freq) {
  1727. case 26000000:
  1728. apll_ctrl |= TWL4030_APLL_INFREQ_26000KHZ;
  1729. break;
  1730. default:
  1731. printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
  1732. freq);
  1733. return -EINVAL;
  1734. }
  1735. twl4030_write(codec, TWL4030_REG_APLL_CTL, apll_ctrl);
  1736. return 0;
  1737. }
  1738. static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1739. unsigned int fmt)
  1740. {
  1741. struct snd_soc_codec *codec = codec_dai->codec;
  1742. u8 old_format, format;
  1743. /* get format */
  1744. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1745. format = old_format;
  1746. /* set master/slave audio interface */
  1747. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1748. case SND_SOC_DAIFMT_CBM_CFM:
  1749. format &= ~(TWL4030_VIF_SLAVE_EN);
  1750. break;
  1751. case SND_SOC_DAIFMT_CBS_CFS:
  1752. format |= TWL4030_VIF_SLAVE_EN;
  1753. break;
  1754. default:
  1755. return -EINVAL;
  1756. }
  1757. /* clock inversion */
  1758. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1759. case SND_SOC_DAIFMT_IB_NF:
  1760. format &= ~(TWL4030_VIF_FORMAT);
  1761. break;
  1762. case SND_SOC_DAIFMT_NB_IF:
  1763. format |= TWL4030_VIF_FORMAT;
  1764. break;
  1765. default:
  1766. return -EINVAL;
  1767. }
  1768. if (format != old_format) {
  1769. /* change format and set CODECPDZ */
  1770. twl4030_codec_enable(codec, 0);
  1771. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1772. twl4030_codec_enable(codec, 1);
  1773. }
  1774. return 0;
  1775. }
  1776. static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
  1777. {
  1778. struct snd_soc_codec *codec = dai->codec;
  1779. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1780. if (tristate)
  1781. reg |= TWL4030_VIF_TRI_EN;
  1782. else
  1783. reg &= ~TWL4030_VIF_TRI_EN;
  1784. return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
  1785. }
  1786. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1787. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1788. static struct snd_soc_dai_ops twl4030_dai_ops = {
  1789. .startup = twl4030_startup,
  1790. .shutdown = twl4030_shutdown,
  1791. .hw_params = twl4030_hw_params,
  1792. .set_sysclk = twl4030_set_dai_sysclk,
  1793. .set_fmt = twl4030_set_dai_fmt,
  1794. .set_tristate = twl4030_set_tristate,
  1795. };
  1796. static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
  1797. .startup = twl4030_voice_startup,
  1798. .shutdown = twl4030_voice_shutdown,
  1799. .hw_params = twl4030_voice_hw_params,
  1800. .set_sysclk = twl4030_voice_set_dai_sysclk,
  1801. .set_fmt = twl4030_voice_set_dai_fmt,
  1802. .set_tristate = twl4030_voice_set_tristate,
  1803. };
  1804. struct snd_soc_dai twl4030_dai[] = {
  1805. {
  1806. .name = "twl4030",
  1807. .playback = {
  1808. .stream_name = "HiFi Playback",
  1809. .channels_min = 2,
  1810. .channels_max = 4,
  1811. .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
  1812. .formats = TWL4030_FORMATS,},
  1813. .capture = {
  1814. .stream_name = "Capture",
  1815. .channels_min = 2,
  1816. .channels_max = 4,
  1817. .rates = TWL4030_RATES,
  1818. .formats = TWL4030_FORMATS,},
  1819. .ops = &twl4030_dai_ops,
  1820. },
  1821. {
  1822. .name = "twl4030 Voice",
  1823. .playback = {
  1824. .stream_name = "Voice Playback",
  1825. .channels_min = 1,
  1826. .channels_max = 1,
  1827. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1828. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1829. .capture = {
  1830. .stream_name = "Capture",
  1831. .channels_min = 1,
  1832. .channels_max = 2,
  1833. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1834. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1835. .ops = &twl4030_dai_voice_ops,
  1836. },
  1837. };
  1838. EXPORT_SYMBOL_GPL(twl4030_dai);
  1839. static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
  1840. {
  1841. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1842. struct snd_soc_codec *codec = socdev->card->codec;
  1843. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1844. return 0;
  1845. }
  1846. static int twl4030_soc_resume(struct platform_device *pdev)
  1847. {
  1848. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1849. struct snd_soc_codec *codec = socdev->card->codec;
  1850. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1851. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  1852. return 0;
  1853. }
  1854. static struct snd_soc_codec *twl4030_codec;
  1855. static int twl4030_soc_probe(struct platform_device *pdev)
  1856. {
  1857. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1858. struct twl4030_setup_data *setup = socdev->codec_data;
  1859. struct snd_soc_codec *codec;
  1860. struct twl4030_priv *twl4030;
  1861. int ret;
  1862. BUG_ON(!twl4030_codec);
  1863. codec = twl4030_codec;
  1864. twl4030 = codec->private_data;
  1865. socdev->card->codec = codec;
  1866. /* Configuration for headset ramp delay from setup data */
  1867. if (setup) {
  1868. unsigned char hs_pop;
  1869. if (setup->sysclk)
  1870. twl4030->sysclk = setup->sysclk;
  1871. else
  1872. twl4030->sysclk = 26000;
  1873. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  1874. hs_pop &= ~TWL4030_RAMP_DELAY;
  1875. hs_pop |= (setup->ramp_delay_value << 2);
  1876. twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  1877. } else {
  1878. twl4030->sysclk = 26000;
  1879. }
  1880. /* register pcms */
  1881. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1882. if (ret < 0) {
  1883. dev_err(&pdev->dev, "failed to create pcms\n");
  1884. return ret;
  1885. }
  1886. snd_soc_add_controls(codec, twl4030_snd_controls,
  1887. ARRAY_SIZE(twl4030_snd_controls));
  1888. twl4030_add_widgets(codec);
  1889. ret = snd_soc_init_card(socdev);
  1890. if (ret < 0) {
  1891. dev_err(&pdev->dev, "failed to register card\n");
  1892. goto card_err;
  1893. }
  1894. return 0;
  1895. card_err:
  1896. snd_soc_free_pcms(socdev);
  1897. snd_soc_dapm_free(socdev);
  1898. return ret;
  1899. }
  1900. static int twl4030_soc_remove(struct platform_device *pdev)
  1901. {
  1902. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1903. struct snd_soc_codec *codec = socdev->card->codec;
  1904. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1905. snd_soc_free_pcms(socdev);
  1906. snd_soc_dapm_free(socdev);
  1907. kfree(codec->private_data);
  1908. kfree(codec);
  1909. return 0;
  1910. }
  1911. static int __devinit twl4030_codec_probe(struct platform_device *pdev)
  1912. {
  1913. struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
  1914. struct snd_soc_codec *codec;
  1915. struct twl4030_priv *twl4030;
  1916. int ret;
  1917. if (!pdata || !(pdata->audio_mclk == 19200000 ||
  1918. pdata->audio_mclk == 26000000 ||
  1919. pdata->audio_mclk == 38400000)) {
  1920. dev_err(&pdev->dev, "Invalid platform_data\n");
  1921. return -EINVAL;
  1922. }
  1923. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  1924. if (twl4030 == NULL) {
  1925. dev_err(&pdev->dev, "Can not allocate memroy\n");
  1926. return -ENOMEM;
  1927. }
  1928. codec = &twl4030->codec;
  1929. codec->private_data = twl4030;
  1930. codec->dev = &pdev->dev;
  1931. twl4030_dai[0].dev = &pdev->dev;
  1932. twl4030_dai[1].dev = &pdev->dev;
  1933. mutex_init(&codec->mutex);
  1934. INIT_LIST_HEAD(&codec->dapm_widgets);
  1935. INIT_LIST_HEAD(&codec->dapm_paths);
  1936. codec->name = "twl4030";
  1937. codec->owner = THIS_MODULE;
  1938. codec->read = twl4030_read_reg_cache;
  1939. codec->write = twl4030_write;
  1940. codec->set_bias_level = twl4030_set_bias_level;
  1941. codec->dai = twl4030_dai;
  1942. codec->num_dai = ARRAY_SIZE(twl4030_dai),
  1943. codec->reg_cache_size = sizeof(twl4030_reg);
  1944. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  1945. GFP_KERNEL);
  1946. if (codec->reg_cache == NULL) {
  1947. ret = -ENOMEM;
  1948. goto error_cache;
  1949. }
  1950. platform_set_drvdata(pdev, twl4030);
  1951. twl4030_codec = codec;
  1952. /* Set the defaults, and power up the codec */
  1953. twl4030_init_chip(codec);
  1954. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1955. ret = snd_soc_register_codec(codec);
  1956. if (ret != 0) {
  1957. dev_err(codec->dev, "Failed to register codec: %d\n", ret);
  1958. goto error_codec;
  1959. }
  1960. ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1961. if (ret != 0) {
  1962. dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
  1963. snd_soc_unregister_codec(codec);
  1964. goto error_codec;
  1965. }
  1966. return 0;
  1967. error_codec:
  1968. twl4030_power_down(codec);
  1969. kfree(codec->reg_cache);
  1970. error_cache:
  1971. kfree(twl4030);
  1972. return ret;
  1973. }
  1974. static int __devexit twl4030_codec_remove(struct platform_device *pdev)
  1975. {
  1976. struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
  1977. kfree(twl4030);
  1978. twl4030_codec = NULL;
  1979. return 0;
  1980. }
  1981. MODULE_ALIAS("platform:twl4030_codec_audio");
  1982. static struct platform_driver twl4030_codec_driver = {
  1983. .probe = twl4030_codec_probe,
  1984. .remove = __devexit_p(twl4030_codec_remove),
  1985. .driver = {
  1986. .name = "twl4030_codec_audio",
  1987. .owner = THIS_MODULE,
  1988. },
  1989. };
  1990. static int __init twl4030_modinit(void)
  1991. {
  1992. return platform_driver_register(&twl4030_codec_driver);
  1993. }
  1994. module_init(twl4030_modinit);
  1995. static void __exit twl4030_exit(void)
  1996. {
  1997. platform_driver_unregister(&twl4030_codec_driver);
  1998. }
  1999. module_exit(twl4030_exit);
  2000. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  2001. .probe = twl4030_soc_probe,
  2002. .remove = twl4030_soc_remove,
  2003. .suspend = twl4030_soc_suspend,
  2004. .resume = twl4030_soc_resume,
  2005. };
  2006. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  2007. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  2008. MODULE_AUTHOR("Steve Sakoman");
  2009. MODULE_LICENSE("GPL");