vmwgfx_drv.c 24 KB

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  1. /**************************************************************************
  2. *
  3. * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
  4. * All Rights Reserved.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the
  8. * "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish,
  10. * distribute, sub license, and/or sell copies of the Software, and to
  11. * permit persons to whom the Software is furnished to do so, subject to
  12. * the following conditions:
  13. *
  14. * The above copyright notice and this permission notice (including the
  15. * next paragraph) shall be included in all copies or substantial portions
  16. * of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. *
  26. **************************************************************************/
  27. #include "drmP.h"
  28. #include "vmwgfx_drv.h"
  29. #include "ttm/ttm_placement.h"
  30. #include "ttm/ttm_bo_driver.h"
  31. #include "ttm/ttm_object.h"
  32. #include "ttm/ttm_module.h"
  33. #define VMWGFX_DRIVER_NAME "vmwgfx"
  34. #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
  35. #define VMWGFX_CHIP_SVGAII 0
  36. #define VMW_FB_RESERVATION 0
  37. /**
  38. * Fully encoded drm commands. Might move to vmw_drm.h
  39. */
  40. #define DRM_IOCTL_VMW_GET_PARAM \
  41. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
  42. struct drm_vmw_getparam_arg)
  43. #define DRM_IOCTL_VMW_ALLOC_DMABUF \
  44. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
  45. union drm_vmw_alloc_dmabuf_arg)
  46. #define DRM_IOCTL_VMW_UNREF_DMABUF \
  47. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
  48. struct drm_vmw_unref_dmabuf_arg)
  49. #define DRM_IOCTL_VMW_CURSOR_BYPASS \
  50. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
  51. struct drm_vmw_cursor_bypass_arg)
  52. #define DRM_IOCTL_VMW_CONTROL_STREAM \
  53. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
  54. struct drm_vmw_control_stream_arg)
  55. #define DRM_IOCTL_VMW_CLAIM_STREAM \
  56. DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
  57. struct drm_vmw_stream_arg)
  58. #define DRM_IOCTL_VMW_UNREF_STREAM \
  59. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
  60. struct drm_vmw_stream_arg)
  61. #define DRM_IOCTL_VMW_CREATE_CONTEXT \
  62. DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
  63. struct drm_vmw_context_arg)
  64. #define DRM_IOCTL_VMW_UNREF_CONTEXT \
  65. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
  66. struct drm_vmw_context_arg)
  67. #define DRM_IOCTL_VMW_CREATE_SURFACE \
  68. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
  69. union drm_vmw_surface_create_arg)
  70. #define DRM_IOCTL_VMW_UNREF_SURFACE \
  71. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
  72. struct drm_vmw_surface_arg)
  73. #define DRM_IOCTL_VMW_REF_SURFACE \
  74. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
  75. union drm_vmw_surface_reference_arg)
  76. #define DRM_IOCTL_VMW_EXECBUF \
  77. DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
  78. struct drm_vmw_execbuf_arg)
  79. #define DRM_IOCTL_VMW_FIFO_DEBUG \
  80. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FIFO_DEBUG, \
  81. struct drm_vmw_fifo_debug_arg)
  82. #define DRM_IOCTL_VMW_FENCE_WAIT \
  83. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
  84. struct drm_vmw_fence_wait_arg)
  85. #define DRM_IOCTL_VMW_UPDATE_LAYOUT \
  86. DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
  87. struct drm_vmw_update_layout_arg)
  88. /**
  89. * The core DRM version of this macro doesn't account for
  90. * DRM_COMMAND_BASE.
  91. */
  92. #define VMW_IOCTL_DEF(ioctl, func, flags) \
  93. [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
  94. /**
  95. * Ioctl definitions.
  96. */
  97. static struct drm_ioctl_desc vmw_ioctls[] = {
  98. VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
  99. DRM_AUTH | DRM_UNLOCKED),
  100. VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
  101. DRM_AUTH | DRM_UNLOCKED),
  102. VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
  103. DRM_AUTH | DRM_UNLOCKED),
  104. VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
  105. vmw_kms_cursor_bypass_ioctl,
  106. DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
  107. VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
  108. DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
  109. VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
  110. DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
  111. VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
  112. DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
  113. VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
  114. DRM_AUTH | DRM_UNLOCKED),
  115. VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
  116. DRM_AUTH | DRM_UNLOCKED),
  117. VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
  118. DRM_AUTH | DRM_UNLOCKED),
  119. VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
  120. DRM_AUTH | DRM_UNLOCKED),
  121. VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
  122. DRM_AUTH | DRM_UNLOCKED),
  123. VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
  124. DRM_AUTH | DRM_UNLOCKED),
  125. VMW_IOCTL_DEF(VMW_FIFO_DEBUG, vmw_fifo_debug_ioctl,
  126. DRM_AUTH | DRM_ROOT_ONLY | DRM_MASTER | DRM_UNLOCKED),
  127. VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_wait_ioctl,
  128. DRM_AUTH | DRM_UNLOCKED),
  129. VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, vmw_kms_update_layout_ioctl,
  130. DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED)
  131. };
  132. static struct pci_device_id vmw_pci_id_list[] = {
  133. {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
  134. {0, 0, 0}
  135. };
  136. static char *vmw_devname = "vmwgfx";
  137. static int enable_fbdev;
  138. static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
  139. static void vmw_master_init(struct vmw_master *);
  140. static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
  141. void *ptr);
  142. MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
  143. module_param_named(enable_fbdev, enable_fbdev, int, 0600);
  144. static void vmw_print_capabilities(uint32_t capabilities)
  145. {
  146. DRM_INFO("Capabilities:\n");
  147. if (capabilities & SVGA_CAP_RECT_COPY)
  148. DRM_INFO(" Rect copy.\n");
  149. if (capabilities & SVGA_CAP_CURSOR)
  150. DRM_INFO(" Cursor.\n");
  151. if (capabilities & SVGA_CAP_CURSOR_BYPASS)
  152. DRM_INFO(" Cursor bypass.\n");
  153. if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
  154. DRM_INFO(" Cursor bypass 2.\n");
  155. if (capabilities & SVGA_CAP_8BIT_EMULATION)
  156. DRM_INFO(" 8bit emulation.\n");
  157. if (capabilities & SVGA_CAP_ALPHA_CURSOR)
  158. DRM_INFO(" Alpha cursor.\n");
  159. if (capabilities & SVGA_CAP_3D)
  160. DRM_INFO(" 3D.\n");
  161. if (capabilities & SVGA_CAP_EXTENDED_FIFO)
  162. DRM_INFO(" Extended Fifo.\n");
  163. if (capabilities & SVGA_CAP_MULTIMON)
  164. DRM_INFO(" Multimon.\n");
  165. if (capabilities & SVGA_CAP_PITCHLOCK)
  166. DRM_INFO(" Pitchlock.\n");
  167. if (capabilities & SVGA_CAP_IRQMASK)
  168. DRM_INFO(" Irq mask.\n");
  169. if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
  170. DRM_INFO(" Display Topology.\n");
  171. if (capabilities & SVGA_CAP_GMR)
  172. DRM_INFO(" GMR.\n");
  173. if (capabilities & SVGA_CAP_TRACES)
  174. DRM_INFO(" Traces.\n");
  175. }
  176. static int vmw_request_device(struct vmw_private *dev_priv)
  177. {
  178. int ret;
  179. ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
  180. if (unlikely(ret != 0)) {
  181. DRM_ERROR("Unable to initialize FIFO.\n");
  182. return ret;
  183. }
  184. return 0;
  185. }
  186. static void vmw_release_device(struct vmw_private *dev_priv)
  187. {
  188. vmw_fifo_release(dev_priv, &dev_priv->fifo);
  189. }
  190. int vmw_3d_resource_inc(struct vmw_private *dev_priv)
  191. {
  192. int ret = 0;
  193. mutex_lock(&dev_priv->release_mutex);
  194. if (unlikely(dev_priv->num_3d_resources++ == 0)) {
  195. ret = vmw_request_device(dev_priv);
  196. if (unlikely(ret != 0))
  197. --dev_priv->num_3d_resources;
  198. }
  199. mutex_unlock(&dev_priv->release_mutex);
  200. return ret;
  201. }
  202. void vmw_3d_resource_dec(struct vmw_private *dev_priv)
  203. {
  204. int32_t n3d;
  205. mutex_lock(&dev_priv->release_mutex);
  206. if (unlikely(--dev_priv->num_3d_resources == 0))
  207. vmw_release_device(dev_priv);
  208. n3d = (int32_t) dev_priv->num_3d_resources;
  209. mutex_unlock(&dev_priv->release_mutex);
  210. BUG_ON(n3d < 0);
  211. }
  212. static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
  213. {
  214. struct vmw_private *dev_priv;
  215. int ret;
  216. uint32_t svga_id;
  217. dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
  218. if (unlikely(dev_priv == NULL)) {
  219. DRM_ERROR("Failed allocating a device private struct.\n");
  220. return -ENOMEM;
  221. }
  222. memset(dev_priv, 0, sizeof(*dev_priv));
  223. dev_priv->dev = dev;
  224. dev_priv->vmw_chipset = chipset;
  225. dev_priv->last_read_sequence = (uint32_t) -100;
  226. mutex_init(&dev_priv->hw_mutex);
  227. mutex_init(&dev_priv->cmdbuf_mutex);
  228. mutex_init(&dev_priv->release_mutex);
  229. rwlock_init(&dev_priv->resource_lock);
  230. idr_init(&dev_priv->context_idr);
  231. idr_init(&dev_priv->surface_idr);
  232. idr_init(&dev_priv->stream_idr);
  233. ida_init(&dev_priv->gmr_ida);
  234. mutex_init(&dev_priv->init_mutex);
  235. init_waitqueue_head(&dev_priv->fence_queue);
  236. init_waitqueue_head(&dev_priv->fifo_queue);
  237. atomic_set(&dev_priv->fence_queue_waiters, 0);
  238. atomic_set(&dev_priv->fifo_queue_waiters, 0);
  239. INIT_LIST_HEAD(&dev_priv->gmr_lru);
  240. dev_priv->io_start = pci_resource_start(dev->pdev, 0);
  241. dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
  242. dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
  243. dev_priv->enable_fb = enable_fbdev;
  244. mutex_lock(&dev_priv->hw_mutex);
  245. vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
  246. svga_id = vmw_read(dev_priv, SVGA_REG_ID);
  247. if (svga_id != SVGA_ID_2) {
  248. ret = -ENOSYS;
  249. DRM_ERROR("Unsuported SVGA ID 0x%x\n", svga_id);
  250. mutex_unlock(&dev_priv->hw_mutex);
  251. goto out_err0;
  252. }
  253. dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
  254. if (dev_priv->capabilities & SVGA_CAP_GMR) {
  255. dev_priv->max_gmr_descriptors =
  256. vmw_read(dev_priv,
  257. SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
  258. dev_priv->max_gmr_ids =
  259. vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
  260. }
  261. dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
  262. dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
  263. dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
  264. dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
  265. mutex_unlock(&dev_priv->hw_mutex);
  266. vmw_print_capabilities(dev_priv->capabilities);
  267. if (dev_priv->capabilities & SVGA_CAP_GMR) {
  268. DRM_INFO("Max GMR ids is %u\n",
  269. (unsigned)dev_priv->max_gmr_ids);
  270. DRM_INFO("Max GMR descriptors is %u\n",
  271. (unsigned)dev_priv->max_gmr_descriptors);
  272. }
  273. DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
  274. dev_priv->vram_start, dev_priv->vram_size / 1024);
  275. DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
  276. dev_priv->mmio_start, dev_priv->mmio_size / 1024);
  277. ret = vmw_ttm_global_init(dev_priv);
  278. if (unlikely(ret != 0))
  279. goto out_err0;
  280. vmw_master_init(&dev_priv->fbdev_master);
  281. ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
  282. dev_priv->active_master = &dev_priv->fbdev_master;
  283. ret = ttm_bo_device_init(&dev_priv->bdev,
  284. dev_priv->bo_global_ref.ref.object,
  285. &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET,
  286. false);
  287. if (unlikely(ret != 0)) {
  288. DRM_ERROR("Failed initializing TTM buffer object driver.\n");
  289. goto out_err1;
  290. }
  291. ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
  292. (dev_priv->vram_size >> PAGE_SHIFT));
  293. if (unlikely(ret != 0)) {
  294. DRM_ERROR("Failed initializing memory manager for VRAM.\n");
  295. goto out_err2;
  296. }
  297. dev_priv->mmio_mtrr = drm_mtrr_add(dev_priv->mmio_start,
  298. dev_priv->mmio_size, DRM_MTRR_WC);
  299. dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
  300. dev_priv->mmio_size);
  301. if (unlikely(dev_priv->mmio_virt == NULL)) {
  302. ret = -ENOMEM;
  303. DRM_ERROR("Failed mapping MMIO.\n");
  304. goto out_err3;
  305. }
  306. /* Need mmio memory to check for fifo pitchlock cap. */
  307. if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
  308. !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
  309. !vmw_fifo_have_pitchlock(dev_priv)) {
  310. ret = -ENOSYS;
  311. DRM_ERROR("Hardware has no pitchlock\n");
  312. goto out_err4;
  313. }
  314. dev_priv->tdev = ttm_object_device_init
  315. (dev_priv->mem_global_ref.object, 12);
  316. if (unlikely(dev_priv->tdev == NULL)) {
  317. DRM_ERROR("Unable to initialize TTM object management.\n");
  318. ret = -ENOMEM;
  319. goto out_err4;
  320. }
  321. dev->dev_private = dev_priv;
  322. ret = pci_request_regions(dev->pdev, "vmwgfx probe");
  323. dev_priv->stealth = (ret != 0);
  324. if (dev_priv->stealth) {
  325. /**
  326. * Request at least the mmio PCI resource.
  327. */
  328. DRM_INFO("It appears like vesafb is loaded. "
  329. "Ignore above error if any.\n");
  330. ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
  331. if (unlikely(ret != 0)) {
  332. DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
  333. goto out_no_device;
  334. }
  335. }
  336. ret = vmw_kms_init(dev_priv);
  337. if (unlikely(ret != 0))
  338. goto out_no_kms;
  339. vmw_overlay_init(dev_priv);
  340. if (dev_priv->enable_fb) {
  341. ret = vmw_3d_resource_inc(dev_priv);
  342. if (unlikely(ret != 0))
  343. goto out_no_fifo;
  344. vmw_kms_save_vga(dev_priv);
  345. vmw_fb_init(dev_priv);
  346. DRM_INFO("%s", vmw_fifo_have_3d(dev_priv) ?
  347. "Detected device 3D availability.\n" :
  348. "Detected no device 3D availability.\n");
  349. } else {
  350. DRM_INFO("Delayed 3D detection since we're not "
  351. "running the device in SVGA mode yet.\n");
  352. }
  353. if (!dev->devname)
  354. dev->devname = vmw_devname;
  355. if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
  356. ret = drm_irq_install(dev);
  357. if (unlikely(ret != 0)) {
  358. DRM_ERROR("Failed installing irq: %d\n", ret);
  359. goto out_no_irq;
  360. }
  361. }
  362. dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
  363. register_pm_notifier(&dev_priv->pm_nb);
  364. return 0;
  365. out_no_irq:
  366. if (dev_priv->enable_fb) {
  367. vmw_fb_close(dev_priv);
  368. vmw_kms_restore_vga(dev_priv);
  369. vmw_3d_resource_dec(dev_priv);
  370. }
  371. out_no_fifo:
  372. vmw_overlay_close(dev_priv);
  373. vmw_kms_close(dev_priv);
  374. out_no_kms:
  375. if (dev_priv->stealth)
  376. pci_release_region(dev->pdev, 2);
  377. else
  378. pci_release_regions(dev->pdev);
  379. out_no_device:
  380. ttm_object_device_release(&dev_priv->tdev);
  381. out_err4:
  382. iounmap(dev_priv->mmio_virt);
  383. out_err3:
  384. drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
  385. dev_priv->mmio_size, DRM_MTRR_WC);
  386. (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
  387. out_err2:
  388. (void)ttm_bo_device_release(&dev_priv->bdev);
  389. out_err1:
  390. vmw_ttm_global_release(dev_priv);
  391. out_err0:
  392. ida_destroy(&dev_priv->gmr_ida);
  393. idr_destroy(&dev_priv->surface_idr);
  394. idr_destroy(&dev_priv->context_idr);
  395. idr_destroy(&dev_priv->stream_idr);
  396. kfree(dev_priv);
  397. return ret;
  398. }
  399. static int vmw_driver_unload(struct drm_device *dev)
  400. {
  401. struct vmw_private *dev_priv = vmw_priv(dev);
  402. unregister_pm_notifier(&dev_priv->pm_nb);
  403. if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
  404. drm_irq_uninstall(dev_priv->dev);
  405. if (dev->devname == vmw_devname)
  406. dev->devname = NULL;
  407. if (dev_priv->enable_fb) {
  408. vmw_fb_close(dev_priv);
  409. vmw_kms_restore_vga(dev_priv);
  410. vmw_3d_resource_dec(dev_priv);
  411. }
  412. vmw_kms_close(dev_priv);
  413. vmw_overlay_close(dev_priv);
  414. if (dev_priv->stealth)
  415. pci_release_region(dev->pdev, 2);
  416. else
  417. pci_release_regions(dev->pdev);
  418. ttm_object_device_release(&dev_priv->tdev);
  419. iounmap(dev_priv->mmio_virt);
  420. drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
  421. dev_priv->mmio_size, DRM_MTRR_WC);
  422. (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
  423. (void)ttm_bo_device_release(&dev_priv->bdev);
  424. vmw_ttm_global_release(dev_priv);
  425. ida_destroy(&dev_priv->gmr_ida);
  426. idr_destroy(&dev_priv->surface_idr);
  427. idr_destroy(&dev_priv->context_idr);
  428. idr_destroy(&dev_priv->stream_idr);
  429. kfree(dev_priv);
  430. return 0;
  431. }
  432. static void vmw_postclose(struct drm_device *dev,
  433. struct drm_file *file_priv)
  434. {
  435. struct vmw_fpriv *vmw_fp;
  436. vmw_fp = vmw_fpriv(file_priv);
  437. ttm_object_file_release(&vmw_fp->tfile);
  438. if (vmw_fp->locked_master)
  439. drm_master_put(&vmw_fp->locked_master);
  440. kfree(vmw_fp);
  441. }
  442. static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
  443. {
  444. struct vmw_private *dev_priv = vmw_priv(dev);
  445. struct vmw_fpriv *vmw_fp;
  446. int ret = -ENOMEM;
  447. vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
  448. if (unlikely(vmw_fp == NULL))
  449. return ret;
  450. vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
  451. if (unlikely(vmw_fp->tfile == NULL))
  452. goto out_no_tfile;
  453. file_priv->driver_priv = vmw_fp;
  454. if (unlikely(dev_priv->bdev.dev_mapping == NULL))
  455. dev_priv->bdev.dev_mapping =
  456. file_priv->filp->f_path.dentry->d_inode->i_mapping;
  457. return 0;
  458. out_no_tfile:
  459. kfree(vmw_fp);
  460. return ret;
  461. }
  462. static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
  463. unsigned long arg)
  464. {
  465. struct drm_file *file_priv = filp->private_data;
  466. struct drm_device *dev = file_priv->minor->dev;
  467. unsigned int nr = DRM_IOCTL_NR(cmd);
  468. /*
  469. * Do extra checking on driver private ioctls.
  470. */
  471. if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
  472. && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
  473. struct drm_ioctl_desc *ioctl =
  474. &vmw_ioctls[nr - DRM_COMMAND_BASE];
  475. if (unlikely(ioctl->cmd_drv != cmd)) {
  476. DRM_ERROR("Invalid command format, ioctl %d\n",
  477. nr - DRM_COMMAND_BASE);
  478. return -EINVAL;
  479. }
  480. }
  481. return drm_ioctl(filp, cmd, arg);
  482. }
  483. static int vmw_firstopen(struct drm_device *dev)
  484. {
  485. struct vmw_private *dev_priv = vmw_priv(dev);
  486. dev_priv->is_opened = true;
  487. return 0;
  488. }
  489. static void vmw_lastclose(struct drm_device *dev)
  490. {
  491. struct vmw_private *dev_priv = vmw_priv(dev);
  492. struct drm_crtc *crtc;
  493. struct drm_mode_set set;
  494. int ret;
  495. /**
  496. * Do nothing on the lastclose call from drm_unload.
  497. */
  498. if (!dev_priv->is_opened)
  499. return;
  500. dev_priv->is_opened = false;
  501. set.x = 0;
  502. set.y = 0;
  503. set.fb = NULL;
  504. set.mode = NULL;
  505. set.connectors = NULL;
  506. set.num_connectors = 0;
  507. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  508. set.crtc = crtc;
  509. ret = crtc->funcs->set_config(&set);
  510. WARN_ON(ret != 0);
  511. }
  512. }
  513. static void vmw_master_init(struct vmw_master *vmaster)
  514. {
  515. ttm_lock_init(&vmaster->lock);
  516. }
  517. static int vmw_master_create(struct drm_device *dev,
  518. struct drm_master *master)
  519. {
  520. struct vmw_master *vmaster;
  521. vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
  522. if (unlikely(vmaster == NULL))
  523. return -ENOMEM;
  524. ttm_lock_init(&vmaster->lock);
  525. ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
  526. master->driver_priv = vmaster;
  527. return 0;
  528. }
  529. static void vmw_master_destroy(struct drm_device *dev,
  530. struct drm_master *master)
  531. {
  532. struct vmw_master *vmaster = vmw_master(master);
  533. master->driver_priv = NULL;
  534. kfree(vmaster);
  535. }
  536. static int vmw_master_set(struct drm_device *dev,
  537. struct drm_file *file_priv,
  538. bool from_open)
  539. {
  540. struct vmw_private *dev_priv = vmw_priv(dev);
  541. struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
  542. struct vmw_master *active = dev_priv->active_master;
  543. struct vmw_master *vmaster = vmw_master(file_priv->master);
  544. int ret = 0;
  545. if (!dev_priv->enable_fb) {
  546. ret = vmw_3d_resource_inc(dev_priv);
  547. if (unlikely(ret != 0))
  548. return ret;
  549. vmw_kms_save_vga(dev_priv);
  550. mutex_lock(&dev_priv->hw_mutex);
  551. vmw_write(dev_priv, SVGA_REG_TRACES, 0);
  552. mutex_unlock(&dev_priv->hw_mutex);
  553. }
  554. if (active) {
  555. BUG_ON(active != &dev_priv->fbdev_master);
  556. ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
  557. if (unlikely(ret != 0))
  558. goto out_no_active_lock;
  559. ttm_lock_set_kill(&active->lock, true, SIGTERM);
  560. ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
  561. if (unlikely(ret != 0)) {
  562. DRM_ERROR("Unable to clean VRAM on "
  563. "master drop.\n");
  564. }
  565. dev_priv->active_master = NULL;
  566. }
  567. ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
  568. if (!from_open) {
  569. ttm_vt_unlock(&vmaster->lock);
  570. BUG_ON(vmw_fp->locked_master != file_priv->master);
  571. drm_master_put(&vmw_fp->locked_master);
  572. }
  573. dev_priv->active_master = vmaster;
  574. return 0;
  575. out_no_active_lock:
  576. if (!dev_priv->enable_fb) {
  577. mutex_lock(&dev_priv->hw_mutex);
  578. vmw_write(dev_priv, SVGA_REG_TRACES, 1);
  579. mutex_unlock(&dev_priv->hw_mutex);
  580. vmw_kms_restore_vga(dev_priv);
  581. vmw_3d_resource_dec(dev_priv);
  582. }
  583. return ret;
  584. }
  585. static void vmw_master_drop(struct drm_device *dev,
  586. struct drm_file *file_priv,
  587. bool from_release)
  588. {
  589. struct vmw_private *dev_priv = vmw_priv(dev);
  590. struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
  591. struct vmw_master *vmaster = vmw_master(file_priv->master);
  592. int ret;
  593. /**
  594. * Make sure the master doesn't disappear while we have
  595. * it locked.
  596. */
  597. vmw_fp->locked_master = drm_master_get(file_priv->master);
  598. ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
  599. if (unlikely((ret != 0))) {
  600. DRM_ERROR("Unable to lock TTM at VT switch.\n");
  601. drm_master_put(&vmw_fp->locked_master);
  602. }
  603. ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
  604. if (!dev_priv->enable_fb) {
  605. ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
  606. if (unlikely(ret != 0))
  607. DRM_ERROR("Unable to clean VRAM on master drop.\n");
  608. mutex_lock(&dev_priv->hw_mutex);
  609. vmw_write(dev_priv, SVGA_REG_TRACES, 1);
  610. mutex_unlock(&dev_priv->hw_mutex);
  611. vmw_kms_restore_vga(dev_priv);
  612. vmw_3d_resource_dec(dev_priv);
  613. }
  614. dev_priv->active_master = &dev_priv->fbdev_master;
  615. ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
  616. ttm_vt_unlock(&dev_priv->fbdev_master.lock);
  617. if (dev_priv->enable_fb)
  618. vmw_fb_on(dev_priv);
  619. }
  620. static void vmw_remove(struct pci_dev *pdev)
  621. {
  622. struct drm_device *dev = pci_get_drvdata(pdev);
  623. drm_put_dev(dev);
  624. }
  625. static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
  626. void *ptr)
  627. {
  628. struct vmw_private *dev_priv =
  629. container_of(nb, struct vmw_private, pm_nb);
  630. struct vmw_master *vmaster = dev_priv->active_master;
  631. switch (val) {
  632. case PM_HIBERNATION_PREPARE:
  633. case PM_SUSPEND_PREPARE:
  634. ttm_suspend_lock(&vmaster->lock);
  635. /**
  636. * This empties VRAM and unbinds all GMR bindings.
  637. * Buffer contents is moved to swappable memory.
  638. */
  639. ttm_bo_swapout_all(&dev_priv->bdev);
  640. break;
  641. case PM_POST_HIBERNATION:
  642. case PM_POST_SUSPEND:
  643. ttm_suspend_unlock(&vmaster->lock);
  644. break;
  645. case PM_RESTORE_PREPARE:
  646. break;
  647. case PM_POST_RESTORE:
  648. break;
  649. default:
  650. break;
  651. }
  652. return 0;
  653. }
  654. /**
  655. * These might not be needed with the virtual SVGA device.
  656. */
  657. int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  658. {
  659. pci_save_state(pdev);
  660. pci_disable_device(pdev);
  661. pci_set_power_state(pdev, PCI_D3hot);
  662. return 0;
  663. }
  664. int vmw_pci_resume(struct pci_dev *pdev)
  665. {
  666. pci_set_power_state(pdev, PCI_D0);
  667. pci_restore_state(pdev);
  668. return pci_enable_device(pdev);
  669. }
  670. static struct drm_driver driver = {
  671. .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
  672. DRIVER_MODESET,
  673. .load = vmw_driver_load,
  674. .unload = vmw_driver_unload,
  675. .firstopen = vmw_firstopen,
  676. .lastclose = vmw_lastclose,
  677. .irq_preinstall = vmw_irq_preinstall,
  678. .irq_postinstall = vmw_irq_postinstall,
  679. .irq_uninstall = vmw_irq_uninstall,
  680. .irq_handler = vmw_irq_handler,
  681. .get_vblank_counter = vmw_get_vblank_counter,
  682. .reclaim_buffers_locked = NULL,
  683. .get_map_ofs = drm_core_get_map_ofs,
  684. .get_reg_ofs = drm_core_get_reg_ofs,
  685. .ioctls = vmw_ioctls,
  686. .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
  687. .dma_quiescent = NULL, /*vmw_dma_quiescent, */
  688. .master_create = vmw_master_create,
  689. .master_destroy = vmw_master_destroy,
  690. .master_set = vmw_master_set,
  691. .master_drop = vmw_master_drop,
  692. .open = vmw_driver_open,
  693. .postclose = vmw_postclose,
  694. .fops = {
  695. .owner = THIS_MODULE,
  696. .open = drm_open,
  697. .release = drm_release,
  698. .unlocked_ioctl = vmw_unlocked_ioctl,
  699. .mmap = vmw_mmap,
  700. .poll = drm_poll,
  701. .fasync = drm_fasync,
  702. #if defined(CONFIG_COMPAT)
  703. .compat_ioctl = drm_compat_ioctl,
  704. #endif
  705. },
  706. .pci_driver = {
  707. .name = VMWGFX_DRIVER_NAME,
  708. .id_table = vmw_pci_id_list,
  709. .probe = vmw_probe,
  710. .remove = vmw_remove,
  711. .suspend = vmw_pci_suspend,
  712. .resume = vmw_pci_resume
  713. },
  714. .name = VMWGFX_DRIVER_NAME,
  715. .desc = VMWGFX_DRIVER_DESC,
  716. .date = VMWGFX_DRIVER_DATE,
  717. .major = VMWGFX_DRIVER_MAJOR,
  718. .minor = VMWGFX_DRIVER_MINOR,
  719. .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
  720. };
  721. static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  722. {
  723. return drm_get_pci_dev(pdev, ent, &driver);
  724. }
  725. static int __init vmwgfx_init(void)
  726. {
  727. int ret;
  728. ret = drm_init(&driver);
  729. if (ret)
  730. DRM_ERROR("Failed initializing DRM.\n");
  731. return ret;
  732. }
  733. static void __exit vmwgfx_exit(void)
  734. {
  735. drm_exit(&driver);
  736. }
  737. module_init(vmwgfx_init);
  738. module_exit(vmwgfx_exit);
  739. MODULE_AUTHOR("VMware Inc. and others");
  740. MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
  741. MODULE_LICENSE("GPL and additional rights");