r8a7791.dtsi 1.5 KB

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  1. /*
  2. * Device Tree Source for the r8a7791 SoC
  3. *
  4. * Copyright (C) 2013 Renesas Electronics Corporation
  5. * Copyright (C) 2013 Renesas Solutions Corp.
  6. *
  7. * This file is licensed under the terms of the GNU General Public License
  8. * version 2. This program is licensed "as is" without any warranty of any
  9. * kind, whether express or implied.
  10. */
  11. / {
  12. compatible = "renesas,r8a7791";
  13. interrupt-parent = <&gic>;
  14. #address-cells = <2>;
  15. #size-cells = <2>;
  16. cpus {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. cpu0: cpu@0 {
  20. device_type = "cpu";
  21. compatible = "arm,cortex-a15";
  22. reg = <0>;
  23. clock-frequency = <1300000000>;
  24. };
  25. cpu1: cpu@1 {
  26. device_type = "cpu";
  27. compatible = "arm,cortex-a15";
  28. reg = <1>;
  29. clock-frequency = <1300000000>;
  30. };
  31. };
  32. gic: interrupt-controller@f1001000 {
  33. compatible = "arm,cortex-a15-gic";
  34. #interrupt-cells = <3>;
  35. #address-cells = <0>;
  36. interrupt-controller;
  37. reg = <0 0xf1001000 0 0x1000>,
  38. <0 0xf1002000 0 0x1000>,
  39. <0 0xf1004000 0 0x2000>,
  40. <0 0xf1006000 0 0x2000>;
  41. interrupts = <1 9 0xf04>;
  42. };
  43. timer {
  44. compatible = "arm,armv7-timer";
  45. interrupts = <1 13 0xf08>,
  46. <1 14 0xf08>,
  47. <1 11 0xf08>,
  48. <1 10 0xf08>;
  49. };
  50. irqc0: interrupt-controller@e61c0000 {
  51. compatible = "renesas,irqc";
  52. #interrupt-cells = <2>;
  53. interrupt-controller;
  54. reg = <0 0xe61c0000 0 0x200>;
  55. interrupt-parent = <&gic>;
  56. interrupts = <0 0 4>,
  57. <0 1 4>,
  58. <0 2 4>,
  59. <0 3 4>,
  60. <0 12 4>,
  61. <0 13 4>,
  62. <0 14 4>,
  63. <0 15 4>,
  64. <0 16 4>,
  65. <0 17 4>;
  66. };
  67. };