ahci.c 62 KB

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  1. /*
  2. * ahci.c - AHCI SATA support
  3. *
  4. * Maintained by: Jeff Garzik <jgarzik@pobox.com>
  5. * Please ALWAYS copy linux-ide@vger.kernel.org
  6. * on emails.
  7. *
  8. * Copyright 2004-2005 Red Hat, Inc.
  9. *
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2, or (at your option)
  14. * any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; see the file COPYING. If not, write to
  23. * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  24. *
  25. *
  26. * libata documentation is available via 'make {ps|pdf}docs',
  27. * as Documentation/DocBook/libata.*
  28. *
  29. * AHCI hardware documentation:
  30. * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
  31. * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
  32. *
  33. */
  34. #include <linux/kernel.h>
  35. #include <linux/module.h>
  36. #include <linux/pci.h>
  37. #include <linux/init.h>
  38. #include <linux/blkdev.h>
  39. #include <linux/delay.h>
  40. #include <linux/interrupt.h>
  41. #include <linux/dma-mapping.h>
  42. #include <linux/device.h>
  43. #include <linux/dmi.h>
  44. #include <scsi/scsi_host.h>
  45. #include <scsi/scsi_cmnd.h>
  46. #include <linux/libata.h>
  47. #define DRV_NAME "ahci"
  48. #define DRV_VERSION "3.0"
  49. static int ahci_skip_host_reset;
  50. module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
  51. MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
  52. static int ahci_enable_alpm(struct ata_port *ap,
  53. enum link_pm policy);
  54. static void ahci_disable_alpm(struct ata_port *ap);
  55. enum {
  56. AHCI_PCI_BAR = 5,
  57. AHCI_MAX_PORTS = 32,
  58. AHCI_MAX_SG = 168, /* hardware max is 64K */
  59. AHCI_DMA_BOUNDARY = 0xffffffff,
  60. AHCI_MAX_CMDS = 32,
  61. AHCI_CMD_SZ = 32,
  62. AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
  63. AHCI_RX_FIS_SZ = 256,
  64. AHCI_CMD_TBL_CDB = 0x40,
  65. AHCI_CMD_TBL_HDR_SZ = 0x80,
  66. AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
  67. AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
  68. AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
  69. AHCI_RX_FIS_SZ,
  70. AHCI_IRQ_ON_SG = (1 << 31),
  71. AHCI_CMD_ATAPI = (1 << 5),
  72. AHCI_CMD_WRITE = (1 << 6),
  73. AHCI_CMD_PREFETCH = (1 << 7),
  74. AHCI_CMD_RESET = (1 << 8),
  75. AHCI_CMD_CLR_BUSY = (1 << 10),
  76. RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
  77. RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
  78. RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
  79. board_ahci = 0,
  80. board_ahci_vt8251 = 1,
  81. board_ahci_ign_iferr = 2,
  82. board_ahci_sb600 = 3,
  83. board_ahci_mv = 4,
  84. board_ahci_sb700 = 5,
  85. /* global controller registers */
  86. HOST_CAP = 0x00, /* host capabilities */
  87. HOST_CTL = 0x04, /* global host control */
  88. HOST_IRQ_STAT = 0x08, /* interrupt status */
  89. HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
  90. HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
  91. /* HOST_CTL bits */
  92. HOST_RESET = (1 << 0), /* reset controller; self-clear */
  93. HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
  94. HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
  95. /* HOST_CAP bits */
  96. HOST_CAP_SSC = (1 << 14), /* Slumber capable */
  97. HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
  98. HOST_CAP_CLO = (1 << 24), /* Command List Override support */
  99. HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
  100. HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
  101. HOST_CAP_SNTF = (1 << 29), /* SNotification register */
  102. HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
  103. HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
  104. /* registers for each SATA port */
  105. PORT_LST_ADDR = 0x00, /* command list DMA addr */
  106. PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
  107. PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
  108. PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
  109. PORT_IRQ_STAT = 0x10, /* interrupt status */
  110. PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
  111. PORT_CMD = 0x18, /* port command */
  112. PORT_TFDATA = 0x20, /* taskfile data */
  113. PORT_SIG = 0x24, /* device TF signature */
  114. PORT_CMD_ISSUE = 0x38, /* command issue */
  115. PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
  116. PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
  117. PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
  118. PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
  119. PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
  120. /* PORT_IRQ_{STAT,MASK} bits */
  121. PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
  122. PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
  123. PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
  124. PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
  125. PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
  126. PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
  127. PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
  128. PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
  129. PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
  130. PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
  131. PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
  132. PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
  133. PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
  134. PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
  135. PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
  136. PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
  137. PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
  138. PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
  139. PORT_IRQ_IF_ERR |
  140. PORT_IRQ_CONNECT |
  141. PORT_IRQ_PHYRDY |
  142. PORT_IRQ_UNK_FIS |
  143. PORT_IRQ_BAD_PMP,
  144. PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
  145. PORT_IRQ_TF_ERR |
  146. PORT_IRQ_HBUS_DATA_ERR,
  147. DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
  148. PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
  149. PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
  150. /* PORT_CMD bits */
  151. PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
  152. PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
  153. PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
  154. PORT_CMD_PMP = (1 << 17), /* PMP attached */
  155. PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
  156. PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
  157. PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
  158. PORT_CMD_CLO = (1 << 3), /* Command list override */
  159. PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
  160. PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
  161. PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
  162. PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
  163. PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
  164. PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
  165. PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
  166. /* hpriv->flags bits */
  167. AHCI_HFLAG_NO_NCQ = (1 << 0),
  168. AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
  169. AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
  170. AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
  171. AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
  172. AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
  173. AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
  174. AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
  175. AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
  176. /* ap->flags bits */
  177. AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
  178. ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
  179. ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
  180. ATA_FLAG_IPM,
  181. ICH_MAP = 0x90, /* ICH MAP register */
  182. };
  183. struct ahci_cmd_hdr {
  184. __le32 opts;
  185. __le32 status;
  186. __le32 tbl_addr;
  187. __le32 tbl_addr_hi;
  188. __le32 reserved[4];
  189. };
  190. struct ahci_sg {
  191. __le32 addr;
  192. __le32 addr_hi;
  193. __le32 reserved;
  194. __le32 flags_size;
  195. };
  196. struct ahci_host_priv {
  197. unsigned int flags; /* AHCI_HFLAG_* */
  198. u32 cap; /* cap to use */
  199. u32 port_map; /* port map to use */
  200. u32 saved_cap; /* saved initial cap */
  201. u32 saved_port_map; /* saved initial port_map */
  202. };
  203. struct ahci_port_priv {
  204. struct ata_link *active_link;
  205. struct ahci_cmd_hdr *cmd_slot;
  206. dma_addr_t cmd_slot_dma;
  207. void *cmd_tbl;
  208. dma_addr_t cmd_tbl_dma;
  209. void *rx_fis;
  210. dma_addr_t rx_fis_dma;
  211. /* for NCQ spurious interrupt analysis */
  212. unsigned int ncq_saw_d2h:1;
  213. unsigned int ncq_saw_dmas:1;
  214. unsigned int ncq_saw_sdb:1;
  215. u32 intr_mask; /* interrupts to enable */
  216. };
  217. static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
  218. static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
  219. static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  220. static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
  221. static int ahci_port_start(struct ata_port *ap);
  222. static void ahci_port_stop(struct ata_port *ap);
  223. static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
  224. static void ahci_qc_prep(struct ata_queued_cmd *qc);
  225. static u8 ahci_check_status(struct ata_port *ap);
  226. static void ahci_freeze(struct ata_port *ap);
  227. static void ahci_thaw(struct ata_port *ap);
  228. static void ahci_pmp_attach(struct ata_port *ap);
  229. static void ahci_pmp_detach(struct ata_port *ap);
  230. static int ahci_softreset(struct ata_link *link, unsigned int *class,
  231. unsigned long deadline);
  232. static int ahci_hardreset(struct ata_link *link, unsigned int *class,
  233. unsigned long deadline);
  234. static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
  235. unsigned long deadline);
  236. static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
  237. unsigned long deadline);
  238. static void ahci_postreset(struct ata_link *link, unsigned int *class);
  239. static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
  240. unsigned long deadline);
  241. static void ahci_error_handler(struct ata_port *ap);
  242. static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
  243. static int ahci_port_resume(struct ata_port *ap);
  244. static void ahci_dev_config(struct ata_device *dev);
  245. static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
  246. static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
  247. u32 opts);
  248. #ifdef CONFIG_PM
  249. static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
  250. static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
  251. static int ahci_pci_device_resume(struct pci_dev *pdev);
  252. #endif
  253. static struct class_device_attribute *ahci_shost_attrs[] = {
  254. &class_device_attr_link_power_management_policy,
  255. NULL
  256. };
  257. static struct scsi_host_template ahci_sht = {
  258. ATA_NCQ_SHT(DRV_NAME),
  259. .can_queue = AHCI_MAX_CMDS - 1,
  260. .sg_tablesize = AHCI_MAX_SG,
  261. .dma_boundary = AHCI_DMA_BOUNDARY,
  262. .shost_attrs = ahci_shost_attrs,
  263. };
  264. static struct ata_port_operations ahci_ops = {
  265. .inherits = &sata_pmp_port_ops,
  266. .sff_check_status = ahci_check_status,
  267. .sff_check_altstatus = ahci_check_status,
  268. .sff_tf_read = ahci_tf_read,
  269. .qc_defer = sata_pmp_qc_defer_cmd_switch,
  270. .qc_prep = ahci_qc_prep,
  271. .qc_issue = ahci_qc_issue,
  272. .freeze = ahci_freeze,
  273. .thaw = ahci_thaw,
  274. .softreset = ahci_softreset,
  275. .hardreset = ahci_hardreset,
  276. .postreset = ahci_postreset,
  277. .pmp_softreset = ahci_pmp_softreset,
  278. .error_handler = ahci_error_handler,
  279. .post_internal_cmd = ahci_post_internal_cmd,
  280. .dev_config = ahci_dev_config,
  281. .scr_read = ahci_scr_read,
  282. .scr_write = ahci_scr_write,
  283. .pmp_attach = ahci_pmp_attach,
  284. .pmp_detach = ahci_pmp_detach,
  285. .enable_pm = ahci_enable_alpm,
  286. .disable_pm = ahci_disable_alpm,
  287. #ifdef CONFIG_PM
  288. .port_suspend = ahci_port_suspend,
  289. .port_resume = ahci_port_resume,
  290. #endif
  291. .port_start = ahci_port_start,
  292. .port_stop = ahci_port_stop,
  293. };
  294. static struct ata_port_operations ahci_vt8251_ops = {
  295. .inherits = &ahci_ops,
  296. .hardreset = ahci_vt8251_hardreset,
  297. };
  298. static struct ata_port_operations ahci_p5wdh_ops = {
  299. .inherits = &ahci_ops,
  300. .hardreset = ahci_p5wdh_hardreset,
  301. };
  302. #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
  303. static const struct ata_port_info ahci_port_info[] = {
  304. /* board_ahci */
  305. {
  306. .flags = AHCI_FLAG_COMMON,
  307. .pio_mask = 0x1f, /* pio0-4 */
  308. .udma_mask = ATA_UDMA6,
  309. .port_ops = &ahci_ops,
  310. },
  311. /* board_ahci_vt8251 */
  312. {
  313. AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
  314. .flags = AHCI_FLAG_COMMON,
  315. .pio_mask = 0x1f, /* pio0-4 */
  316. .udma_mask = ATA_UDMA6,
  317. .port_ops = &ahci_vt8251_ops,
  318. },
  319. /* board_ahci_ign_iferr */
  320. {
  321. AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
  322. .flags = AHCI_FLAG_COMMON,
  323. .pio_mask = 0x1f, /* pio0-4 */
  324. .udma_mask = ATA_UDMA6,
  325. .port_ops = &ahci_ops,
  326. },
  327. /* board_ahci_sb600 */
  328. {
  329. AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
  330. AHCI_HFLAG_32BIT_ONLY |
  331. AHCI_HFLAG_SECT255 | AHCI_HFLAG_NO_PMP),
  332. .flags = AHCI_FLAG_COMMON,
  333. .pio_mask = 0x1f, /* pio0-4 */
  334. .udma_mask = ATA_UDMA6,
  335. .port_ops = &ahci_ops,
  336. },
  337. /* board_ahci_mv */
  338. {
  339. AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
  340. AHCI_HFLAG_MV_PATA),
  341. .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
  342. ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
  343. .pio_mask = 0x1f, /* pio0-4 */
  344. .udma_mask = ATA_UDMA6,
  345. .port_ops = &ahci_ops,
  346. },
  347. /* board_ahci_sb700 */
  348. {
  349. AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
  350. AHCI_HFLAG_NO_PMP),
  351. .flags = AHCI_FLAG_COMMON,
  352. .pio_mask = 0x1f, /* pio0-4 */
  353. .udma_mask = ATA_UDMA6,
  354. .port_ops = &ahci_ops,
  355. },
  356. };
  357. static const struct pci_device_id ahci_pci_tbl[] = {
  358. /* Intel */
  359. { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
  360. { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
  361. { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
  362. { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
  363. { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
  364. { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
  365. { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
  366. { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
  367. { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
  368. { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
  369. { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
  370. { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
  371. { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
  372. { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
  373. { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
  374. { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
  375. { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
  376. { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
  377. { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
  378. { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
  379. { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
  380. { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
  381. { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
  382. { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
  383. { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
  384. { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
  385. { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
  386. { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
  387. { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
  388. { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
  389. { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
  390. /* JMicron 360/1/3/5/6, match class to avoid IDE function */
  391. { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  392. PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
  393. /* ATI */
  394. { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
  395. { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
  396. { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
  397. { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
  398. { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
  399. { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
  400. { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
  401. /* VIA */
  402. { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
  403. { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
  404. /* NVIDIA */
  405. { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
  406. { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
  407. { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
  408. { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
  409. { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
  410. { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
  411. { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
  412. { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
  413. { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
  414. { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
  415. { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
  416. { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
  417. { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
  418. { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
  419. { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
  420. { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
  421. { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
  422. { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
  423. { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
  424. { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
  425. { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
  426. { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
  427. { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
  428. { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
  429. { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
  430. { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
  431. { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
  432. { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
  433. { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
  434. { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
  435. { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
  436. { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
  437. { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
  438. { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
  439. { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
  440. { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
  441. { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
  442. { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
  443. { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
  444. { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
  445. { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
  446. { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
  447. { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
  448. { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
  449. { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
  450. { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
  451. { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
  452. { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
  453. { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
  454. { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
  455. { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
  456. { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
  457. { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
  458. { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
  459. { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
  460. { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
  461. { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
  462. { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
  463. { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
  464. { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
  465. { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
  466. { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
  467. { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
  468. { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
  469. { PCI_VDEVICE(NVIDIA, 0x0bd0), board_ahci }, /* MCP7B */
  470. { PCI_VDEVICE(NVIDIA, 0x0bd1), board_ahci }, /* MCP7B */
  471. { PCI_VDEVICE(NVIDIA, 0x0bd2), board_ahci }, /* MCP7B */
  472. { PCI_VDEVICE(NVIDIA, 0x0bd3), board_ahci }, /* MCP7B */
  473. /* SiS */
  474. { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
  475. { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
  476. { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
  477. /* Marvell */
  478. { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
  479. { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
  480. /* Generic, PCI class code for AHCI */
  481. { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  482. PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
  483. { } /* terminate list */
  484. };
  485. static struct pci_driver ahci_pci_driver = {
  486. .name = DRV_NAME,
  487. .id_table = ahci_pci_tbl,
  488. .probe = ahci_init_one,
  489. .remove = ata_pci_remove_one,
  490. #ifdef CONFIG_PM
  491. .suspend = ahci_pci_device_suspend,
  492. .resume = ahci_pci_device_resume,
  493. #endif
  494. };
  495. static inline int ahci_nr_ports(u32 cap)
  496. {
  497. return (cap & 0x1f) + 1;
  498. }
  499. static inline void __iomem *__ahci_port_base(struct ata_host *host,
  500. unsigned int port_no)
  501. {
  502. void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
  503. return mmio + 0x100 + (port_no * 0x80);
  504. }
  505. static inline void __iomem *ahci_port_base(struct ata_port *ap)
  506. {
  507. return __ahci_port_base(ap->host, ap->port_no);
  508. }
  509. static void ahci_enable_ahci(void __iomem *mmio)
  510. {
  511. u32 tmp;
  512. /* turn on AHCI_EN */
  513. tmp = readl(mmio + HOST_CTL);
  514. if (!(tmp & HOST_AHCI_EN)) {
  515. tmp |= HOST_AHCI_EN;
  516. writel(tmp, mmio + HOST_CTL);
  517. tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
  518. WARN_ON(!(tmp & HOST_AHCI_EN));
  519. }
  520. }
  521. /**
  522. * ahci_save_initial_config - Save and fixup initial config values
  523. * @pdev: target PCI device
  524. * @hpriv: host private area to store config values
  525. *
  526. * Some registers containing configuration info might be setup by
  527. * BIOS and might be cleared on reset. This function saves the
  528. * initial values of those registers into @hpriv such that they
  529. * can be restored after controller reset.
  530. *
  531. * If inconsistent, config values are fixed up by this function.
  532. *
  533. * LOCKING:
  534. * None.
  535. */
  536. static void ahci_save_initial_config(struct pci_dev *pdev,
  537. struct ahci_host_priv *hpriv)
  538. {
  539. void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
  540. u32 cap, port_map;
  541. int i;
  542. int mv;
  543. /* make sure AHCI mode is enabled before accessing CAP */
  544. ahci_enable_ahci(mmio);
  545. /* Values prefixed with saved_ are written back to host after
  546. * reset. Values without are used for driver operation.
  547. */
  548. hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
  549. hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
  550. /* some chips have errata preventing 64bit use */
  551. if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
  552. dev_printk(KERN_INFO, &pdev->dev,
  553. "controller can't do 64bit DMA, forcing 32bit\n");
  554. cap &= ~HOST_CAP_64;
  555. }
  556. if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
  557. dev_printk(KERN_INFO, &pdev->dev,
  558. "controller can't do NCQ, turning off CAP_NCQ\n");
  559. cap &= ~HOST_CAP_NCQ;
  560. }
  561. if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
  562. dev_printk(KERN_INFO, &pdev->dev,
  563. "controller can't do PMP, turning off CAP_PMP\n");
  564. cap &= ~HOST_CAP_PMP;
  565. }
  566. /*
  567. * Temporary Marvell 6145 hack: PATA port presence
  568. * is asserted through the standard AHCI port
  569. * presence register, as bit 4 (counting from 0)
  570. */
  571. if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
  572. if (pdev->device == 0x6121)
  573. mv = 0x3;
  574. else
  575. mv = 0xf;
  576. dev_printk(KERN_ERR, &pdev->dev,
  577. "MV_AHCI HACK: port_map %x -> %x\n",
  578. port_map,
  579. port_map & mv);
  580. port_map &= mv;
  581. }
  582. /* cross check port_map and cap.n_ports */
  583. if (port_map) {
  584. int map_ports = 0;
  585. for (i = 0; i < AHCI_MAX_PORTS; i++)
  586. if (port_map & (1 << i))
  587. map_ports++;
  588. /* If PI has more ports than n_ports, whine, clear
  589. * port_map and let it be generated from n_ports.
  590. */
  591. if (map_ports > ahci_nr_ports(cap)) {
  592. dev_printk(KERN_WARNING, &pdev->dev,
  593. "implemented port map (0x%x) contains more "
  594. "ports than nr_ports (%u), using nr_ports\n",
  595. port_map, ahci_nr_ports(cap));
  596. port_map = 0;
  597. }
  598. }
  599. /* fabricate port_map from cap.nr_ports */
  600. if (!port_map) {
  601. port_map = (1 << ahci_nr_ports(cap)) - 1;
  602. dev_printk(KERN_WARNING, &pdev->dev,
  603. "forcing PORTS_IMPL to 0x%x\n", port_map);
  604. /* write the fixed up value to the PI register */
  605. hpriv->saved_port_map = port_map;
  606. }
  607. /* record values to use during operation */
  608. hpriv->cap = cap;
  609. hpriv->port_map = port_map;
  610. }
  611. /**
  612. * ahci_restore_initial_config - Restore initial config
  613. * @host: target ATA host
  614. *
  615. * Restore initial config stored by ahci_save_initial_config().
  616. *
  617. * LOCKING:
  618. * None.
  619. */
  620. static void ahci_restore_initial_config(struct ata_host *host)
  621. {
  622. struct ahci_host_priv *hpriv = host->private_data;
  623. void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
  624. writel(hpriv->saved_cap, mmio + HOST_CAP);
  625. writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
  626. (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
  627. }
  628. static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
  629. {
  630. static const int offset[] = {
  631. [SCR_STATUS] = PORT_SCR_STAT,
  632. [SCR_CONTROL] = PORT_SCR_CTL,
  633. [SCR_ERROR] = PORT_SCR_ERR,
  634. [SCR_ACTIVE] = PORT_SCR_ACT,
  635. [SCR_NOTIFICATION] = PORT_SCR_NTF,
  636. };
  637. struct ahci_host_priv *hpriv = ap->host->private_data;
  638. if (sc_reg < ARRAY_SIZE(offset) &&
  639. (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
  640. return offset[sc_reg];
  641. return 0;
  642. }
  643. static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
  644. {
  645. void __iomem *port_mmio = ahci_port_base(ap);
  646. int offset = ahci_scr_offset(ap, sc_reg);
  647. if (offset) {
  648. *val = readl(port_mmio + offset);
  649. return 0;
  650. }
  651. return -EINVAL;
  652. }
  653. static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
  654. {
  655. void __iomem *port_mmio = ahci_port_base(ap);
  656. int offset = ahci_scr_offset(ap, sc_reg);
  657. if (offset) {
  658. writel(val, port_mmio + offset);
  659. return 0;
  660. }
  661. return -EINVAL;
  662. }
  663. static void ahci_start_engine(struct ata_port *ap)
  664. {
  665. void __iomem *port_mmio = ahci_port_base(ap);
  666. u32 tmp;
  667. /* start DMA */
  668. tmp = readl(port_mmio + PORT_CMD);
  669. tmp |= PORT_CMD_START;
  670. writel(tmp, port_mmio + PORT_CMD);
  671. readl(port_mmio + PORT_CMD); /* flush */
  672. }
  673. static int ahci_stop_engine(struct ata_port *ap)
  674. {
  675. void __iomem *port_mmio = ahci_port_base(ap);
  676. u32 tmp;
  677. tmp = readl(port_mmio + PORT_CMD);
  678. /* check if the HBA is idle */
  679. if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
  680. return 0;
  681. /* setting HBA to idle */
  682. tmp &= ~PORT_CMD_START;
  683. writel(tmp, port_mmio + PORT_CMD);
  684. /* wait for engine to stop. This could be as long as 500 msec */
  685. tmp = ata_wait_register(port_mmio + PORT_CMD,
  686. PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
  687. if (tmp & PORT_CMD_LIST_ON)
  688. return -EIO;
  689. return 0;
  690. }
  691. static void ahci_start_fis_rx(struct ata_port *ap)
  692. {
  693. void __iomem *port_mmio = ahci_port_base(ap);
  694. struct ahci_host_priv *hpriv = ap->host->private_data;
  695. struct ahci_port_priv *pp = ap->private_data;
  696. u32 tmp;
  697. /* set FIS registers */
  698. if (hpriv->cap & HOST_CAP_64)
  699. writel((pp->cmd_slot_dma >> 16) >> 16,
  700. port_mmio + PORT_LST_ADDR_HI);
  701. writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
  702. if (hpriv->cap & HOST_CAP_64)
  703. writel((pp->rx_fis_dma >> 16) >> 16,
  704. port_mmio + PORT_FIS_ADDR_HI);
  705. writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
  706. /* enable FIS reception */
  707. tmp = readl(port_mmio + PORT_CMD);
  708. tmp |= PORT_CMD_FIS_RX;
  709. writel(tmp, port_mmio + PORT_CMD);
  710. /* flush */
  711. readl(port_mmio + PORT_CMD);
  712. }
  713. static int ahci_stop_fis_rx(struct ata_port *ap)
  714. {
  715. void __iomem *port_mmio = ahci_port_base(ap);
  716. u32 tmp;
  717. /* disable FIS reception */
  718. tmp = readl(port_mmio + PORT_CMD);
  719. tmp &= ~PORT_CMD_FIS_RX;
  720. writel(tmp, port_mmio + PORT_CMD);
  721. /* wait for completion, spec says 500ms, give it 1000 */
  722. tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
  723. PORT_CMD_FIS_ON, 10, 1000);
  724. if (tmp & PORT_CMD_FIS_ON)
  725. return -EBUSY;
  726. return 0;
  727. }
  728. static void ahci_power_up(struct ata_port *ap)
  729. {
  730. struct ahci_host_priv *hpriv = ap->host->private_data;
  731. void __iomem *port_mmio = ahci_port_base(ap);
  732. u32 cmd;
  733. cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
  734. /* spin up device */
  735. if (hpriv->cap & HOST_CAP_SSS) {
  736. cmd |= PORT_CMD_SPIN_UP;
  737. writel(cmd, port_mmio + PORT_CMD);
  738. }
  739. /* wake up link */
  740. writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
  741. }
  742. static void ahci_disable_alpm(struct ata_port *ap)
  743. {
  744. struct ahci_host_priv *hpriv = ap->host->private_data;
  745. void __iomem *port_mmio = ahci_port_base(ap);
  746. u32 cmd;
  747. struct ahci_port_priv *pp = ap->private_data;
  748. /* IPM bits should be disabled by libata-core */
  749. /* get the existing command bits */
  750. cmd = readl(port_mmio + PORT_CMD);
  751. /* disable ALPM and ASP */
  752. cmd &= ~PORT_CMD_ASP;
  753. cmd &= ~PORT_CMD_ALPE;
  754. /* force the interface back to active */
  755. cmd |= PORT_CMD_ICC_ACTIVE;
  756. /* write out new cmd value */
  757. writel(cmd, port_mmio + PORT_CMD);
  758. cmd = readl(port_mmio + PORT_CMD);
  759. /* wait 10ms to be sure we've come out of any low power state */
  760. msleep(10);
  761. /* clear out any PhyRdy stuff from interrupt status */
  762. writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
  763. /* go ahead and clean out PhyRdy Change from Serror too */
  764. ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
  765. /*
  766. * Clear flag to indicate that we should ignore all PhyRdy
  767. * state changes
  768. */
  769. hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
  770. /*
  771. * Enable interrupts on Phy Ready.
  772. */
  773. pp->intr_mask |= PORT_IRQ_PHYRDY;
  774. writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
  775. /*
  776. * don't change the link pm policy - we can be called
  777. * just to turn of link pm temporarily
  778. */
  779. }
  780. static int ahci_enable_alpm(struct ata_port *ap,
  781. enum link_pm policy)
  782. {
  783. struct ahci_host_priv *hpriv = ap->host->private_data;
  784. void __iomem *port_mmio = ahci_port_base(ap);
  785. u32 cmd;
  786. struct ahci_port_priv *pp = ap->private_data;
  787. u32 asp;
  788. /* Make sure the host is capable of link power management */
  789. if (!(hpriv->cap & HOST_CAP_ALPM))
  790. return -EINVAL;
  791. switch (policy) {
  792. case MAX_PERFORMANCE:
  793. case NOT_AVAILABLE:
  794. /*
  795. * if we came here with NOT_AVAILABLE,
  796. * it just means this is the first time we
  797. * have tried to enable - default to max performance,
  798. * and let the user go to lower power modes on request.
  799. */
  800. ahci_disable_alpm(ap);
  801. return 0;
  802. case MIN_POWER:
  803. /* configure HBA to enter SLUMBER */
  804. asp = PORT_CMD_ASP;
  805. break;
  806. case MEDIUM_POWER:
  807. /* configure HBA to enter PARTIAL */
  808. asp = 0;
  809. break;
  810. default:
  811. return -EINVAL;
  812. }
  813. /*
  814. * Disable interrupts on Phy Ready. This keeps us from
  815. * getting woken up due to spurious phy ready interrupts
  816. * TBD - Hot plug should be done via polling now, is
  817. * that even supported?
  818. */
  819. pp->intr_mask &= ~PORT_IRQ_PHYRDY;
  820. writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
  821. /*
  822. * Set a flag to indicate that we should ignore all PhyRdy
  823. * state changes since these can happen now whenever we
  824. * change link state
  825. */
  826. hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
  827. /* get the existing command bits */
  828. cmd = readl(port_mmio + PORT_CMD);
  829. /*
  830. * Set ASP based on Policy
  831. */
  832. cmd |= asp;
  833. /*
  834. * Setting this bit will instruct the HBA to aggressively
  835. * enter a lower power link state when it's appropriate and
  836. * based on the value set above for ASP
  837. */
  838. cmd |= PORT_CMD_ALPE;
  839. /* write out new cmd value */
  840. writel(cmd, port_mmio + PORT_CMD);
  841. cmd = readl(port_mmio + PORT_CMD);
  842. /* IPM bits should be set by libata-core */
  843. return 0;
  844. }
  845. #ifdef CONFIG_PM
  846. static void ahci_power_down(struct ata_port *ap)
  847. {
  848. struct ahci_host_priv *hpriv = ap->host->private_data;
  849. void __iomem *port_mmio = ahci_port_base(ap);
  850. u32 cmd, scontrol;
  851. if (!(hpriv->cap & HOST_CAP_SSS))
  852. return;
  853. /* put device into listen mode, first set PxSCTL.DET to 0 */
  854. scontrol = readl(port_mmio + PORT_SCR_CTL);
  855. scontrol &= ~0xf;
  856. writel(scontrol, port_mmio + PORT_SCR_CTL);
  857. /* then set PxCMD.SUD to 0 */
  858. cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
  859. cmd &= ~PORT_CMD_SPIN_UP;
  860. writel(cmd, port_mmio + PORT_CMD);
  861. }
  862. #endif
  863. static void ahci_start_port(struct ata_port *ap)
  864. {
  865. /* enable FIS reception */
  866. ahci_start_fis_rx(ap);
  867. /* enable DMA */
  868. ahci_start_engine(ap);
  869. }
  870. static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
  871. {
  872. int rc;
  873. /* disable DMA */
  874. rc = ahci_stop_engine(ap);
  875. if (rc) {
  876. *emsg = "failed to stop engine";
  877. return rc;
  878. }
  879. /* disable FIS reception */
  880. rc = ahci_stop_fis_rx(ap);
  881. if (rc) {
  882. *emsg = "failed stop FIS RX";
  883. return rc;
  884. }
  885. return 0;
  886. }
  887. static int ahci_reset_controller(struct ata_host *host)
  888. {
  889. struct pci_dev *pdev = to_pci_dev(host->dev);
  890. struct ahci_host_priv *hpriv = host->private_data;
  891. void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
  892. u32 tmp;
  893. /* we must be in AHCI mode, before using anything
  894. * AHCI-specific, such as HOST_RESET.
  895. */
  896. ahci_enable_ahci(mmio);
  897. /* global controller reset */
  898. if (!ahci_skip_host_reset) {
  899. tmp = readl(mmio + HOST_CTL);
  900. if ((tmp & HOST_RESET) == 0) {
  901. writel(tmp | HOST_RESET, mmio + HOST_CTL);
  902. readl(mmio + HOST_CTL); /* flush */
  903. }
  904. /* reset must complete within 1 second, or
  905. * the hardware should be considered fried.
  906. */
  907. ssleep(1);
  908. tmp = readl(mmio + HOST_CTL);
  909. if (tmp & HOST_RESET) {
  910. dev_printk(KERN_ERR, host->dev,
  911. "controller reset failed (0x%x)\n", tmp);
  912. return -EIO;
  913. }
  914. /* turn on AHCI mode */
  915. ahci_enable_ahci(mmio);
  916. /* Some registers might be cleared on reset. Restore
  917. * initial values.
  918. */
  919. ahci_restore_initial_config(host);
  920. } else
  921. dev_printk(KERN_INFO, host->dev,
  922. "skipping global host reset\n");
  923. if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
  924. u16 tmp16;
  925. /* configure PCS */
  926. pci_read_config_word(pdev, 0x92, &tmp16);
  927. if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
  928. tmp16 |= hpriv->port_map;
  929. pci_write_config_word(pdev, 0x92, tmp16);
  930. }
  931. }
  932. return 0;
  933. }
  934. static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
  935. int port_no, void __iomem *mmio,
  936. void __iomem *port_mmio)
  937. {
  938. const char *emsg = NULL;
  939. int rc;
  940. u32 tmp;
  941. /* make sure port is not active */
  942. rc = ahci_deinit_port(ap, &emsg);
  943. if (rc)
  944. dev_printk(KERN_WARNING, &pdev->dev,
  945. "%s (%d)\n", emsg, rc);
  946. /* clear SError */
  947. tmp = readl(port_mmio + PORT_SCR_ERR);
  948. VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
  949. writel(tmp, port_mmio + PORT_SCR_ERR);
  950. /* clear port IRQ */
  951. tmp = readl(port_mmio + PORT_IRQ_STAT);
  952. VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
  953. if (tmp)
  954. writel(tmp, port_mmio + PORT_IRQ_STAT);
  955. writel(1 << port_no, mmio + HOST_IRQ_STAT);
  956. }
  957. static void ahci_init_controller(struct ata_host *host)
  958. {
  959. struct ahci_host_priv *hpriv = host->private_data;
  960. struct pci_dev *pdev = to_pci_dev(host->dev);
  961. void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
  962. int i;
  963. void __iomem *port_mmio;
  964. u32 tmp;
  965. int mv;
  966. if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
  967. if (pdev->device == 0x6121)
  968. mv = 2;
  969. else
  970. mv = 4;
  971. port_mmio = __ahci_port_base(host, mv);
  972. writel(0, port_mmio + PORT_IRQ_MASK);
  973. /* clear port IRQ */
  974. tmp = readl(port_mmio + PORT_IRQ_STAT);
  975. VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
  976. if (tmp)
  977. writel(tmp, port_mmio + PORT_IRQ_STAT);
  978. }
  979. for (i = 0; i < host->n_ports; i++) {
  980. struct ata_port *ap = host->ports[i];
  981. port_mmio = ahci_port_base(ap);
  982. if (ata_port_is_dummy(ap))
  983. continue;
  984. ahci_port_init(pdev, ap, i, mmio, port_mmio);
  985. }
  986. tmp = readl(mmio + HOST_CTL);
  987. VPRINTK("HOST_CTL 0x%x\n", tmp);
  988. writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
  989. tmp = readl(mmio + HOST_CTL);
  990. VPRINTK("HOST_CTL 0x%x\n", tmp);
  991. }
  992. static void ahci_dev_config(struct ata_device *dev)
  993. {
  994. struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
  995. if (hpriv->flags & AHCI_HFLAG_SECT255) {
  996. dev->max_sectors = 255;
  997. ata_dev_printk(dev, KERN_INFO,
  998. "SB600 AHCI: limiting to 255 sectors per cmd\n");
  999. }
  1000. }
  1001. static unsigned int ahci_dev_classify(struct ata_port *ap)
  1002. {
  1003. void __iomem *port_mmio = ahci_port_base(ap);
  1004. struct ata_taskfile tf;
  1005. u32 tmp;
  1006. tmp = readl(port_mmio + PORT_SIG);
  1007. tf.lbah = (tmp >> 24) & 0xff;
  1008. tf.lbam = (tmp >> 16) & 0xff;
  1009. tf.lbal = (tmp >> 8) & 0xff;
  1010. tf.nsect = (tmp) & 0xff;
  1011. return ata_dev_classify(&tf);
  1012. }
  1013. static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
  1014. u32 opts)
  1015. {
  1016. dma_addr_t cmd_tbl_dma;
  1017. cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
  1018. pp->cmd_slot[tag].opts = cpu_to_le32(opts);
  1019. pp->cmd_slot[tag].status = 0;
  1020. pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
  1021. pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
  1022. }
  1023. static int ahci_kick_engine(struct ata_port *ap, int force_restart)
  1024. {
  1025. void __iomem *port_mmio = ap->ioaddr.cmd_addr;
  1026. struct ahci_host_priv *hpriv = ap->host->private_data;
  1027. u32 tmp;
  1028. int busy, rc;
  1029. /* do we need to kick the port? */
  1030. busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
  1031. if (!busy && !force_restart)
  1032. return 0;
  1033. /* stop engine */
  1034. rc = ahci_stop_engine(ap);
  1035. if (rc)
  1036. goto out_restart;
  1037. /* need to do CLO? */
  1038. if (!busy) {
  1039. rc = 0;
  1040. goto out_restart;
  1041. }
  1042. if (!(hpriv->cap & HOST_CAP_CLO)) {
  1043. rc = -EOPNOTSUPP;
  1044. goto out_restart;
  1045. }
  1046. /* perform CLO */
  1047. tmp = readl(port_mmio + PORT_CMD);
  1048. tmp |= PORT_CMD_CLO;
  1049. writel(tmp, port_mmio + PORT_CMD);
  1050. rc = 0;
  1051. tmp = ata_wait_register(port_mmio + PORT_CMD,
  1052. PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
  1053. if (tmp & PORT_CMD_CLO)
  1054. rc = -EIO;
  1055. /* restart engine */
  1056. out_restart:
  1057. ahci_start_engine(ap);
  1058. return rc;
  1059. }
  1060. static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
  1061. struct ata_taskfile *tf, int is_cmd, u16 flags,
  1062. unsigned long timeout_msec)
  1063. {
  1064. const u32 cmd_fis_len = 5; /* five dwords */
  1065. struct ahci_port_priv *pp = ap->private_data;
  1066. void __iomem *port_mmio = ahci_port_base(ap);
  1067. u8 *fis = pp->cmd_tbl;
  1068. u32 tmp;
  1069. /* prep the command */
  1070. ata_tf_to_fis(tf, pmp, is_cmd, fis);
  1071. ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
  1072. /* issue & wait */
  1073. writel(1, port_mmio + PORT_CMD_ISSUE);
  1074. if (timeout_msec) {
  1075. tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
  1076. 1, timeout_msec);
  1077. if (tmp & 0x1) {
  1078. ahci_kick_engine(ap, 1);
  1079. return -EBUSY;
  1080. }
  1081. } else
  1082. readl(port_mmio + PORT_CMD_ISSUE); /* flush */
  1083. return 0;
  1084. }
  1085. static int ahci_check_ready(struct ata_link *link)
  1086. {
  1087. void __iomem *mmio = link->ap->ioaddr.cmd_addr;
  1088. u8 status = readl(mmio + PORT_TFDATA) & 0xFF;
  1089. if (!(status & ATA_BUSY))
  1090. return 1;
  1091. return 0;
  1092. }
  1093. static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
  1094. int pmp, unsigned long deadline)
  1095. {
  1096. struct ata_port *ap = link->ap;
  1097. const char *reason = NULL;
  1098. unsigned long now, msecs;
  1099. struct ata_taskfile tf;
  1100. int rc;
  1101. DPRINTK("ENTER\n");
  1102. if (ata_link_offline(link)) {
  1103. DPRINTK("PHY reports no device\n");
  1104. *class = ATA_DEV_NONE;
  1105. return 0;
  1106. }
  1107. /* prepare for SRST (AHCI-1.1 10.4.1) */
  1108. rc = ahci_kick_engine(ap, 1);
  1109. if (rc && rc != -EOPNOTSUPP)
  1110. ata_link_printk(link, KERN_WARNING,
  1111. "failed to reset engine (errno=%d)\n", rc);
  1112. ata_tf_init(link->device, &tf);
  1113. /* issue the first D2H Register FIS */
  1114. msecs = 0;
  1115. now = jiffies;
  1116. if (time_after(now, deadline))
  1117. msecs = jiffies_to_msecs(deadline - now);
  1118. tf.ctl |= ATA_SRST;
  1119. if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
  1120. AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
  1121. rc = -EIO;
  1122. reason = "1st FIS failed";
  1123. goto fail;
  1124. }
  1125. /* spec says at least 5us, but be generous and sleep for 1ms */
  1126. msleep(1);
  1127. /* issue the second D2H Register FIS */
  1128. tf.ctl &= ~ATA_SRST;
  1129. ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
  1130. /* wait for link to become ready */
  1131. rc = ata_wait_after_reset(link, deadline, ahci_check_ready);
  1132. /* link occupied, -ENODEV too is an error */
  1133. if (rc) {
  1134. reason = "device not ready";
  1135. goto fail;
  1136. }
  1137. *class = ahci_dev_classify(ap);
  1138. DPRINTK("EXIT, class=%u\n", *class);
  1139. return 0;
  1140. fail:
  1141. ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
  1142. return rc;
  1143. }
  1144. static int ahci_softreset(struct ata_link *link, unsigned int *class,
  1145. unsigned long deadline)
  1146. {
  1147. int pmp = 0;
  1148. if (link->ap->flags & ATA_FLAG_PMP)
  1149. pmp = SATA_PMP_CTRL_PORT;
  1150. return ahci_do_softreset(link, class, pmp, deadline);
  1151. }
  1152. static int ahci_hardreset(struct ata_link *link, unsigned int *class,
  1153. unsigned long deadline)
  1154. {
  1155. const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
  1156. struct ata_port *ap = link->ap;
  1157. struct ahci_port_priv *pp = ap->private_data;
  1158. u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
  1159. struct ata_taskfile tf;
  1160. bool online;
  1161. int rc;
  1162. DPRINTK("ENTER\n");
  1163. ahci_stop_engine(ap);
  1164. /* clear D2H reception area to properly wait for D2H FIS */
  1165. ata_tf_init(link->device, &tf);
  1166. tf.command = 0x80;
  1167. ata_tf_to_fis(&tf, 0, 0, d2h_fis);
  1168. rc = sata_link_hardreset(link, timing, deadline, &online,
  1169. ahci_check_ready);
  1170. ahci_start_engine(ap);
  1171. if (online)
  1172. *class = ahci_dev_classify(ap);
  1173. DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
  1174. return rc;
  1175. }
  1176. static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
  1177. unsigned long deadline)
  1178. {
  1179. struct ata_port *ap = link->ap;
  1180. bool online;
  1181. int rc;
  1182. DPRINTK("ENTER\n");
  1183. ahci_stop_engine(ap);
  1184. rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
  1185. deadline, &online, NULL);
  1186. ahci_start_engine(ap);
  1187. DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
  1188. /* vt8251 doesn't clear BSY on signature FIS reception,
  1189. * request follow-up softreset.
  1190. */
  1191. return online ? -EAGAIN : rc;
  1192. }
  1193. static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
  1194. unsigned long deadline)
  1195. {
  1196. struct ata_port *ap = link->ap;
  1197. struct ahci_port_priv *pp = ap->private_data;
  1198. u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
  1199. struct ata_taskfile tf;
  1200. bool online;
  1201. int rc;
  1202. ahci_stop_engine(ap);
  1203. /* clear D2H reception area to properly wait for D2H FIS */
  1204. ata_tf_init(link->device, &tf);
  1205. tf.command = 0x80;
  1206. ata_tf_to_fis(&tf, 0, 0, d2h_fis);
  1207. rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
  1208. deadline, &online, NULL);
  1209. ahci_start_engine(ap);
  1210. /* The pseudo configuration device on SIMG4726 attached to
  1211. * ASUS P5W-DH Deluxe doesn't send signature FIS after
  1212. * hardreset if no device is attached to the first downstream
  1213. * port && the pseudo device locks up on SRST w/ PMP==0. To
  1214. * work around this, wait for !BSY only briefly. If BSY isn't
  1215. * cleared, perform CLO and proceed to IDENTIFY (achieved by
  1216. * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
  1217. *
  1218. * Wait for two seconds. Devices attached to downstream port
  1219. * which can't process the following IDENTIFY after this will
  1220. * have to be reset again. For most cases, this should
  1221. * suffice while making probing snappish enough.
  1222. */
  1223. if (online) {
  1224. rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
  1225. ahci_check_ready);
  1226. if (rc)
  1227. ahci_kick_engine(ap, 0);
  1228. }
  1229. return rc;
  1230. }
  1231. static void ahci_postreset(struct ata_link *link, unsigned int *class)
  1232. {
  1233. struct ata_port *ap = link->ap;
  1234. void __iomem *port_mmio = ahci_port_base(ap);
  1235. u32 new_tmp, tmp;
  1236. ata_std_postreset(link, class);
  1237. /* Make sure port's ATAPI bit is set appropriately */
  1238. new_tmp = tmp = readl(port_mmio + PORT_CMD);
  1239. if (*class == ATA_DEV_ATAPI)
  1240. new_tmp |= PORT_CMD_ATAPI;
  1241. else
  1242. new_tmp &= ~PORT_CMD_ATAPI;
  1243. if (new_tmp != tmp) {
  1244. writel(new_tmp, port_mmio + PORT_CMD);
  1245. readl(port_mmio + PORT_CMD); /* flush */
  1246. }
  1247. }
  1248. static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
  1249. unsigned long deadline)
  1250. {
  1251. return ahci_do_softreset(link, class, link->pmp, deadline);
  1252. }
  1253. static u8 ahci_check_status(struct ata_port *ap)
  1254. {
  1255. void __iomem *mmio = ap->ioaddr.cmd_addr;
  1256. return readl(mmio + PORT_TFDATA) & 0xFF;
  1257. }
  1258. static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
  1259. {
  1260. struct ahci_port_priv *pp = ap->private_data;
  1261. u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
  1262. ata_tf_from_fis(d2h_fis, tf);
  1263. }
  1264. static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
  1265. {
  1266. struct scatterlist *sg;
  1267. struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
  1268. unsigned int si;
  1269. VPRINTK("ENTER\n");
  1270. /*
  1271. * Next, the S/G list.
  1272. */
  1273. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  1274. dma_addr_t addr = sg_dma_address(sg);
  1275. u32 sg_len = sg_dma_len(sg);
  1276. ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
  1277. ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
  1278. ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
  1279. }
  1280. return si;
  1281. }
  1282. static void ahci_qc_prep(struct ata_queued_cmd *qc)
  1283. {
  1284. struct ata_port *ap = qc->ap;
  1285. struct ahci_port_priv *pp = ap->private_data;
  1286. int is_atapi = ata_is_atapi(qc->tf.protocol);
  1287. void *cmd_tbl;
  1288. u32 opts;
  1289. const u32 cmd_fis_len = 5; /* five dwords */
  1290. unsigned int n_elem;
  1291. /*
  1292. * Fill in command table information. First, the header,
  1293. * a SATA Register - Host to Device command FIS.
  1294. */
  1295. cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
  1296. ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
  1297. if (is_atapi) {
  1298. memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
  1299. memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
  1300. }
  1301. n_elem = 0;
  1302. if (qc->flags & ATA_QCFLAG_DMAMAP)
  1303. n_elem = ahci_fill_sg(qc, cmd_tbl);
  1304. /*
  1305. * Fill in command slot information.
  1306. */
  1307. opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
  1308. if (qc->tf.flags & ATA_TFLAG_WRITE)
  1309. opts |= AHCI_CMD_WRITE;
  1310. if (is_atapi)
  1311. opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
  1312. ahci_fill_cmd_slot(pp, qc->tag, opts);
  1313. }
  1314. static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
  1315. {
  1316. struct ahci_host_priv *hpriv = ap->host->private_data;
  1317. struct ahci_port_priv *pp = ap->private_data;
  1318. struct ata_eh_info *host_ehi = &ap->link.eh_info;
  1319. struct ata_link *link = NULL;
  1320. struct ata_queued_cmd *active_qc;
  1321. struct ata_eh_info *active_ehi;
  1322. u32 serror;
  1323. /* determine active link */
  1324. ata_port_for_each_link(link, ap)
  1325. if (ata_link_active(link))
  1326. break;
  1327. if (!link)
  1328. link = &ap->link;
  1329. active_qc = ata_qc_from_tag(ap, link->active_tag);
  1330. active_ehi = &link->eh_info;
  1331. /* record irq stat */
  1332. ata_ehi_clear_desc(host_ehi);
  1333. ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
  1334. /* AHCI needs SError cleared; otherwise, it might lock up */
  1335. ahci_scr_read(ap, SCR_ERROR, &serror);
  1336. ahci_scr_write(ap, SCR_ERROR, serror);
  1337. host_ehi->serror |= serror;
  1338. /* some controllers set IRQ_IF_ERR on device errors, ignore it */
  1339. if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
  1340. irq_stat &= ~PORT_IRQ_IF_ERR;
  1341. if (irq_stat & PORT_IRQ_TF_ERR) {
  1342. /* If qc is active, charge it; otherwise, the active
  1343. * link. There's no active qc on NCQ errors. It will
  1344. * be determined by EH by reading log page 10h.
  1345. */
  1346. if (active_qc)
  1347. active_qc->err_mask |= AC_ERR_DEV;
  1348. else
  1349. active_ehi->err_mask |= AC_ERR_DEV;
  1350. if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
  1351. host_ehi->serror &= ~SERR_INTERNAL;
  1352. }
  1353. if (irq_stat & PORT_IRQ_UNK_FIS) {
  1354. u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
  1355. active_ehi->err_mask |= AC_ERR_HSM;
  1356. active_ehi->action |= ATA_EH_RESET;
  1357. ata_ehi_push_desc(active_ehi,
  1358. "unknown FIS %08x %08x %08x %08x" ,
  1359. unk[0], unk[1], unk[2], unk[3]);
  1360. }
  1361. if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
  1362. active_ehi->err_mask |= AC_ERR_HSM;
  1363. active_ehi->action |= ATA_EH_RESET;
  1364. ata_ehi_push_desc(active_ehi, "incorrect PMP");
  1365. }
  1366. if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
  1367. host_ehi->err_mask |= AC_ERR_HOST_BUS;
  1368. host_ehi->action |= ATA_EH_RESET;
  1369. ata_ehi_push_desc(host_ehi, "host bus error");
  1370. }
  1371. if (irq_stat & PORT_IRQ_IF_ERR) {
  1372. host_ehi->err_mask |= AC_ERR_ATA_BUS;
  1373. host_ehi->action |= ATA_EH_RESET;
  1374. ata_ehi_push_desc(host_ehi, "interface fatal error");
  1375. }
  1376. if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
  1377. ata_ehi_hotplugged(host_ehi);
  1378. ata_ehi_push_desc(host_ehi, "%s",
  1379. irq_stat & PORT_IRQ_CONNECT ?
  1380. "connection status changed" : "PHY RDY changed");
  1381. }
  1382. /* okay, let's hand over to EH */
  1383. if (irq_stat & PORT_IRQ_FREEZE)
  1384. ata_port_freeze(ap);
  1385. else
  1386. ata_port_abort(ap);
  1387. }
  1388. static void ahci_port_intr(struct ata_port *ap)
  1389. {
  1390. void __iomem *port_mmio = ap->ioaddr.cmd_addr;
  1391. struct ata_eh_info *ehi = &ap->link.eh_info;
  1392. struct ahci_port_priv *pp = ap->private_data;
  1393. struct ahci_host_priv *hpriv = ap->host->private_data;
  1394. int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
  1395. u32 status, qc_active;
  1396. int rc;
  1397. status = readl(port_mmio + PORT_IRQ_STAT);
  1398. writel(status, port_mmio + PORT_IRQ_STAT);
  1399. /* ignore BAD_PMP while resetting */
  1400. if (unlikely(resetting))
  1401. status &= ~PORT_IRQ_BAD_PMP;
  1402. /* If we are getting PhyRdy, this is
  1403. * just a power state change, we should
  1404. * clear out this, plus the PhyRdy/Comm
  1405. * Wake bits from Serror
  1406. */
  1407. if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
  1408. (status & PORT_IRQ_PHYRDY)) {
  1409. status &= ~PORT_IRQ_PHYRDY;
  1410. ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
  1411. }
  1412. if (unlikely(status & PORT_IRQ_ERROR)) {
  1413. ahci_error_intr(ap, status);
  1414. return;
  1415. }
  1416. if (status & PORT_IRQ_SDB_FIS) {
  1417. /* If SNotification is available, leave notification
  1418. * handling to sata_async_notification(). If not,
  1419. * emulate it by snooping SDB FIS RX area.
  1420. *
  1421. * Snooping FIS RX area is probably cheaper than
  1422. * poking SNotification but some constrollers which
  1423. * implement SNotification, ICH9 for example, don't
  1424. * store AN SDB FIS into receive area.
  1425. */
  1426. if (hpriv->cap & HOST_CAP_SNTF)
  1427. sata_async_notification(ap);
  1428. else {
  1429. /* If the 'N' bit in word 0 of the FIS is set,
  1430. * we just received asynchronous notification.
  1431. * Tell libata about it.
  1432. */
  1433. const __le32 *f = pp->rx_fis + RX_FIS_SDB;
  1434. u32 f0 = le32_to_cpu(f[0]);
  1435. if (f0 & (1 << 15))
  1436. sata_async_notification(ap);
  1437. }
  1438. }
  1439. /* pp->active_link is valid iff any command is in flight */
  1440. if (ap->qc_active && pp->active_link->sactive)
  1441. qc_active = readl(port_mmio + PORT_SCR_ACT);
  1442. else
  1443. qc_active = readl(port_mmio + PORT_CMD_ISSUE);
  1444. rc = ata_qc_complete_multiple(ap, qc_active);
  1445. /* while resetting, invalid completions are expected */
  1446. if (unlikely(rc < 0 && !resetting)) {
  1447. ehi->err_mask |= AC_ERR_HSM;
  1448. ehi->action |= ATA_EH_RESET;
  1449. ata_port_freeze(ap);
  1450. }
  1451. }
  1452. static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
  1453. {
  1454. struct ata_host *host = dev_instance;
  1455. struct ahci_host_priv *hpriv;
  1456. unsigned int i, handled = 0;
  1457. void __iomem *mmio;
  1458. u32 irq_stat, irq_ack = 0;
  1459. VPRINTK("ENTER\n");
  1460. hpriv = host->private_data;
  1461. mmio = host->iomap[AHCI_PCI_BAR];
  1462. /* sigh. 0xffffffff is a valid return from h/w */
  1463. irq_stat = readl(mmio + HOST_IRQ_STAT);
  1464. irq_stat &= hpriv->port_map;
  1465. if (!irq_stat)
  1466. return IRQ_NONE;
  1467. spin_lock(&host->lock);
  1468. for (i = 0; i < host->n_ports; i++) {
  1469. struct ata_port *ap;
  1470. if (!(irq_stat & (1 << i)))
  1471. continue;
  1472. ap = host->ports[i];
  1473. if (ap) {
  1474. ahci_port_intr(ap);
  1475. VPRINTK("port %u\n", i);
  1476. } else {
  1477. VPRINTK("port %u (no irq)\n", i);
  1478. if (ata_ratelimit())
  1479. dev_printk(KERN_WARNING, host->dev,
  1480. "interrupt on disabled port %u\n", i);
  1481. }
  1482. irq_ack |= (1 << i);
  1483. }
  1484. if (irq_ack) {
  1485. writel(irq_ack, mmio + HOST_IRQ_STAT);
  1486. handled = 1;
  1487. }
  1488. spin_unlock(&host->lock);
  1489. VPRINTK("EXIT\n");
  1490. return IRQ_RETVAL(handled);
  1491. }
  1492. static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
  1493. {
  1494. struct ata_port *ap = qc->ap;
  1495. void __iomem *port_mmio = ahci_port_base(ap);
  1496. struct ahci_port_priv *pp = ap->private_data;
  1497. /* Keep track of the currently active link. It will be used
  1498. * in completion path to determine whether NCQ phase is in
  1499. * progress.
  1500. */
  1501. pp->active_link = qc->dev->link;
  1502. if (qc->tf.protocol == ATA_PROT_NCQ)
  1503. writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
  1504. writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
  1505. readl(port_mmio + PORT_CMD_ISSUE); /* flush */
  1506. return 0;
  1507. }
  1508. static void ahci_freeze(struct ata_port *ap)
  1509. {
  1510. void __iomem *port_mmio = ahci_port_base(ap);
  1511. /* turn IRQ off */
  1512. writel(0, port_mmio + PORT_IRQ_MASK);
  1513. }
  1514. static void ahci_thaw(struct ata_port *ap)
  1515. {
  1516. void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
  1517. void __iomem *port_mmio = ahci_port_base(ap);
  1518. u32 tmp;
  1519. struct ahci_port_priv *pp = ap->private_data;
  1520. /* clear IRQ */
  1521. tmp = readl(port_mmio + PORT_IRQ_STAT);
  1522. writel(tmp, port_mmio + PORT_IRQ_STAT);
  1523. writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
  1524. /* turn IRQ back on */
  1525. writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
  1526. }
  1527. static void ahci_error_handler(struct ata_port *ap)
  1528. {
  1529. if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
  1530. /* restart engine */
  1531. ahci_stop_engine(ap);
  1532. ahci_start_engine(ap);
  1533. }
  1534. sata_pmp_error_handler(ap);
  1535. }
  1536. static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
  1537. {
  1538. struct ata_port *ap = qc->ap;
  1539. /* make DMA engine forget about the failed command */
  1540. if (qc->flags & ATA_QCFLAG_FAILED)
  1541. ahci_kick_engine(ap, 1);
  1542. }
  1543. static void ahci_pmp_attach(struct ata_port *ap)
  1544. {
  1545. void __iomem *port_mmio = ahci_port_base(ap);
  1546. struct ahci_port_priv *pp = ap->private_data;
  1547. u32 cmd;
  1548. cmd = readl(port_mmio + PORT_CMD);
  1549. cmd |= PORT_CMD_PMP;
  1550. writel(cmd, port_mmio + PORT_CMD);
  1551. pp->intr_mask |= PORT_IRQ_BAD_PMP;
  1552. writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
  1553. }
  1554. static void ahci_pmp_detach(struct ata_port *ap)
  1555. {
  1556. void __iomem *port_mmio = ahci_port_base(ap);
  1557. struct ahci_port_priv *pp = ap->private_data;
  1558. u32 cmd;
  1559. cmd = readl(port_mmio + PORT_CMD);
  1560. cmd &= ~PORT_CMD_PMP;
  1561. writel(cmd, port_mmio + PORT_CMD);
  1562. pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
  1563. writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
  1564. }
  1565. static int ahci_port_resume(struct ata_port *ap)
  1566. {
  1567. ahci_power_up(ap);
  1568. ahci_start_port(ap);
  1569. if (ap->nr_pmp_links)
  1570. ahci_pmp_attach(ap);
  1571. else
  1572. ahci_pmp_detach(ap);
  1573. return 0;
  1574. }
  1575. #ifdef CONFIG_PM
  1576. static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
  1577. {
  1578. const char *emsg = NULL;
  1579. int rc;
  1580. rc = ahci_deinit_port(ap, &emsg);
  1581. if (rc == 0)
  1582. ahci_power_down(ap);
  1583. else {
  1584. ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
  1585. ahci_start_port(ap);
  1586. }
  1587. return rc;
  1588. }
  1589. static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
  1590. {
  1591. struct ata_host *host = dev_get_drvdata(&pdev->dev);
  1592. void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
  1593. u32 ctl;
  1594. if (mesg.event & PM_EVENT_SLEEP) {
  1595. /* AHCI spec rev1.1 section 8.3.3:
  1596. * Software must disable interrupts prior to requesting a
  1597. * transition of the HBA to D3 state.
  1598. */
  1599. ctl = readl(mmio + HOST_CTL);
  1600. ctl &= ~HOST_IRQ_EN;
  1601. writel(ctl, mmio + HOST_CTL);
  1602. readl(mmio + HOST_CTL); /* flush */
  1603. }
  1604. return ata_pci_device_suspend(pdev, mesg);
  1605. }
  1606. static int ahci_pci_device_resume(struct pci_dev *pdev)
  1607. {
  1608. struct ata_host *host = dev_get_drvdata(&pdev->dev);
  1609. int rc;
  1610. rc = ata_pci_device_do_resume(pdev);
  1611. if (rc)
  1612. return rc;
  1613. if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
  1614. rc = ahci_reset_controller(host);
  1615. if (rc)
  1616. return rc;
  1617. ahci_init_controller(host);
  1618. }
  1619. ata_host_resume(host);
  1620. return 0;
  1621. }
  1622. #endif
  1623. static int ahci_port_start(struct ata_port *ap)
  1624. {
  1625. struct device *dev = ap->host->dev;
  1626. struct ahci_port_priv *pp;
  1627. void *mem;
  1628. dma_addr_t mem_dma;
  1629. pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
  1630. if (!pp)
  1631. return -ENOMEM;
  1632. mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
  1633. GFP_KERNEL);
  1634. if (!mem)
  1635. return -ENOMEM;
  1636. memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
  1637. /*
  1638. * First item in chunk of DMA memory: 32-slot command table,
  1639. * 32 bytes each in size
  1640. */
  1641. pp->cmd_slot = mem;
  1642. pp->cmd_slot_dma = mem_dma;
  1643. mem += AHCI_CMD_SLOT_SZ;
  1644. mem_dma += AHCI_CMD_SLOT_SZ;
  1645. /*
  1646. * Second item: Received-FIS area
  1647. */
  1648. pp->rx_fis = mem;
  1649. pp->rx_fis_dma = mem_dma;
  1650. mem += AHCI_RX_FIS_SZ;
  1651. mem_dma += AHCI_RX_FIS_SZ;
  1652. /*
  1653. * Third item: data area for storing a single command
  1654. * and its scatter-gather table
  1655. */
  1656. pp->cmd_tbl = mem;
  1657. pp->cmd_tbl_dma = mem_dma;
  1658. /*
  1659. * Save off initial list of interrupts to be enabled.
  1660. * This could be changed later
  1661. */
  1662. pp->intr_mask = DEF_PORT_IRQ;
  1663. ap->private_data = pp;
  1664. /* engage engines, captain */
  1665. return ahci_port_resume(ap);
  1666. }
  1667. static void ahci_port_stop(struct ata_port *ap)
  1668. {
  1669. const char *emsg = NULL;
  1670. int rc;
  1671. /* de-initialize port */
  1672. rc = ahci_deinit_port(ap, &emsg);
  1673. if (rc)
  1674. ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
  1675. }
  1676. static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
  1677. {
  1678. int rc;
  1679. if (using_dac &&
  1680. !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
  1681. rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  1682. if (rc) {
  1683. rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  1684. if (rc) {
  1685. dev_printk(KERN_ERR, &pdev->dev,
  1686. "64-bit DMA enable failed\n");
  1687. return rc;
  1688. }
  1689. }
  1690. } else {
  1691. rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  1692. if (rc) {
  1693. dev_printk(KERN_ERR, &pdev->dev,
  1694. "32-bit DMA enable failed\n");
  1695. return rc;
  1696. }
  1697. rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  1698. if (rc) {
  1699. dev_printk(KERN_ERR, &pdev->dev,
  1700. "32-bit consistent DMA enable failed\n");
  1701. return rc;
  1702. }
  1703. }
  1704. return 0;
  1705. }
  1706. static void ahci_print_info(struct ata_host *host)
  1707. {
  1708. struct ahci_host_priv *hpriv = host->private_data;
  1709. struct pci_dev *pdev = to_pci_dev(host->dev);
  1710. void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
  1711. u32 vers, cap, impl, speed;
  1712. const char *speed_s;
  1713. u16 cc;
  1714. const char *scc_s;
  1715. vers = readl(mmio + HOST_VERSION);
  1716. cap = hpriv->cap;
  1717. impl = hpriv->port_map;
  1718. speed = (cap >> 20) & 0xf;
  1719. if (speed == 1)
  1720. speed_s = "1.5";
  1721. else if (speed == 2)
  1722. speed_s = "3";
  1723. else
  1724. speed_s = "?";
  1725. pci_read_config_word(pdev, 0x0a, &cc);
  1726. if (cc == PCI_CLASS_STORAGE_IDE)
  1727. scc_s = "IDE";
  1728. else if (cc == PCI_CLASS_STORAGE_SATA)
  1729. scc_s = "SATA";
  1730. else if (cc == PCI_CLASS_STORAGE_RAID)
  1731. scc_s = "RAID";
  1732. else
  1733. scc_s = "unknown";
  1734. dev_printk(KERN_INFO, &pdev->dev,
  1735. "AHCI %02x%02x.%02x%02x "
  1736. "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
  1737. ,
  1738. (vers >> 24) & 0xff,
  1739. (vers >> 16) & 0xff,
  1740. (vers >> 8) & 0xff,
  1741. vers & 0xff,
  1742. ((cap >> 8) & 0x1f) + 1,
  1743. (cap & 0x1f) + 1,
  1744. speed_s,
  1745. impl,
  1746. scc_s);
  1747. dev_printk(KERN_INFO, &pdev->dev,
  1748. "flags: "
  1749. "%s%s%s%s%s%s%s"
  1750. "%s%s%s%s%s%s%s\n"
  1751. ,
  1752. cap & (1 << 31) ? "64bit " : "",
  1753. cap & (1 << 30) ? "ncq " : "",
  1754. cap & (1 << 29) ? "sntf " : "",
  1755. cap & (1 << 28) ? "ilck " : "",
  1756. cap & (1 << 27) ? "stag " : "",
  1757. cap & (1 << 26) ? "pm " : "",
  1758. cap & (1 << 25) ? "led " : "",
  1759. cap & (1 << 24) ? "clo " : "",
  1760. cap & (1 << 19) ? "nz " : "",
  1761. cap & (1 << 18) ? "only " : "",
  1762. cap & (1 << 17) ? "pmp " : "",
  1763. cap & (1 << 15) ? "pio " : "",
  1764. cap & (1 << 14) ? "slum " : "",
  1765. cap & (1 << 13) ? "part " : ""
  1766. );
  1767. }
  1768. /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
  1769. * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
  1770. * support PMP and the 4726 either directly exports the device
  1771. * attached to the first downstream port or acts as a hardware storage
  1772. * controller and emulate a single ATA device (can be RAID 0/1 or some
  1773. * other configuration).
  1774. *
  1775. * When there's no device attached to the first downstream port of the
  1776. * 4726, "Config Disk" appears, which is a pseudo ATA device to
  1777. * configure the 4726. However, ATA emulation of the device is very
  1778. * lame. It doesn't send signature D2H Reg FIS after the initial
  1779. * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
  1780. *
  1781. * The following function works around the problem by always using
  1782. * hardreset on the port and not depending on receiving signature FIS
  1783. * afterward. If signature FIS isn't received soon, ATA class is
  1784. * assumed without follow-up softreset.
  1785. */
  1786. static void ahci_p5wdh_workaround(struct ata_host *host)
  1787. {
  1788. static struct dmi_system_id sysids[] = {
  1789. {
  1790. .ident = "P5W DH Deluxe",
  1791. .matches = {
  1792. DMI_MATCH(DMI_SYS_VENDOR,
  1793. "ASUSTEK COMPUTER INC"),
  1794. DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
  1795. },
  1796. },
  1797. { }
  1798. };
  1799. struct pci_dev *pdev = to_pci_dev(host->dev);
  1800. if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
  1801. dmi_check_system(sysids)) {
  1802. struct ata_port *ap = host->ports[1];
  1803. dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
  1804. "Deluxe on-board SIMG4726 workaround\n");
  1805. ap->ops = &ahci_p5wdh_ops;
  1806. ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
  1807. }
  1808. }
  1809. static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  1810. {
  1811. static int printed_version;
  1812. struct ata_port_info pi = ahci_port_info[ent->driver_data];
  1813. const struct ata_port_info *ppi[] = { &pi, NULL };
  1814. struct device *dev = &pdev->dev;
  1815. struct ahci_host_priv *hpriv;
  1816. struct ata_host *host;
  1817. int n_ports, i, rc;
  1818. VPRINTK("ENTER\n");
  1819. WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
  1820. if (!printed_version++)
  1821. dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
  1822. /* acquire resources */
  1823. rc = pcim_enable_device(pdev);
  1824. if (rc)
  1825. return rc;
  1826. /* AHCI controllers often implement SFF compatible interface.
  1827. * Grab all PCI BARs just in case.
  1828. */
  1829. rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
  1830. if (rc == -EBUSY)
  1831. pcim_pin_device(pdev);
  1832. if (rc)
  1833. return rc;
  1834. if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
  1835. (pdev->device == 0x2652 || pdev->device == 0x2653)) {
  1836. u8 map;
  1837. /* ICH6s share the same PCI ID for both piix and ahci
  1838. * modes. Enabling ahci mode while MAP indicates
  1839. * combined mode is a bad idea. Yield to ata_piix.
  1840. */
  1841. pci_read_config_byte(pdev, ICH_MAP, &map);
  1842. if (map & 0x3) {
  1843. dev_printk(KERN_INFO, &pdev->dev, "controller is in "
  1844. "combined mode, can't enable AHCI mode\n");
  1845. return -ENODEV;
  1846. }
  1847. }
  1848. hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
  1849. if (!hpriv)
  1850. return -ENOMEM;
  1851. hpriv->flags |= (unsigned long)pi.private_data;
  1852. if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
  1853. pci_intx(pdev, 1);
  1854. /* save initial config */
  1855. ahci_save_initial_config(pdev, hpriv);
  1856. /* prepare host */
  1857. if (hpriv->cap & HOST_CAP_NCQ)
  1858. pi.flags |= ATA_FLAG_NCQ;
  1859. if (hpriv->cap & HOST_CAP_PMP)
  1860. pi.flags |= ATA_FLAG_PMP;
  1861. /* CAP.NP sometimes indicate the index of the last enabled
  1862. * port, at other times, that of the last possible port, so
  1863. * determining the maximum port number requires looking at
  1864. * both CAP.NP and port_map.
  1865. */
  1866. n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
  1867. host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
  1868. if (!host)
  1869. return -ENOMEM;
  1870. host->iomap = pcim_iomap_table(pdev);
  1871. host->private_data = hpriv;
  1872. for (i = 0; i < host->n_ports; i++) {
  1873. struct ata_port *ap = host->ports[i];
  1874. void __iomem *port_mmio = ahci_port_base(ap);
  1875. ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
  1876. ata_port_pbar_desc(ap, AHCI_PCI_BAR,
  1877. 0x100 + ap->port_no * 0x80, "port");
  1878. /* set initial link pm policy */
  1879. ap->pm_policy = NOT_AVAILABLE;
  1880. /* standard SATA port setup */
  1881. if (hpriv->port_map & (1 << i))
  1882. ap->ioaddr.cmd_addr = port_mmio;
  1883. /* disabled/not-implemented port */
  1884. else
  1885. ap->ops = &ata_dummy_port_ops;
  1886. }
  1887. /* apply workaround for ASUS P5W DH Deluxe mainboard */
  1888. ahci_p5wdh_workaround(host);
  1889. /* initialize adapter */
  1890. rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
  1891. if (rc)
  1892. return rc;
  1893. rc = ahci_reset_controller(host);
  1894. if (rc)
  1895. return rc;
  1896. ahci_init_controller(host);
  1897. ahci_print_info(host);
  1898. pci_set_master(pdev);
  1899. return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
  1900. &ahci_sht);
  1901. }
  1902. static int __init ahci_init(void)
  1903. {
  1904. return pci_register_driver(&ahci_pci_driver);
  1905. }
  1906. static void __exit ahci_exit(void)
  1907. {
  1908. pci_unregister_driver(&ahci_pci_driver);
  1909. }
  1910. MODULE_AUTHOR("Jeff Garzik");
  1911. MODULE_DESCRIPTION("AHCI SATA low-level driver");
  1912. MODULE_LICENSE("GPL");
  1913. MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
  1914. MODULE_VERSION(DRV_VERSION);
  1915. module_init(ahci_init);
  1916. module_exit(ahci_exit);