bfin_can.c 16 KB

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  1. /*
  2. * Blackfin On-Chip CAN Driver
  3. *
  4. * Copyright 2004-2009 Analog Devices Inc.
  5. *
  6. * Enter bugs at http://blackfin.uclinux.org/
  7. *
  8. * Licensed under the GPL-2 or later.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/init.h>
  12. #include <linux/kernel.h>
  13. #include <linux/bitops.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/errno.h>
  16. #include <linux/netdevice.h>
  17. #include <linux/skbuff.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/can/dev.h>
  20. #include <linux/can/error.h>
  21. #include <asm/bfin_can.h>
  22. #include <asm/portmux.h>
  23. #define DRV_NAME "bfin_can"
  24. #define BFIN_CAN_TIMEOUT 100
  25. #define TX_ECHO_SKB_MAX 1
  26. /*
  27. * bfin can private data
  28. */
  29. struct bfin_can_priv {
  30. struct can_priv can; /* must be the first member */
  31. struct net_device *dev;
  32. void __iomem *membase;
  33. int rx_irq;
  34. int tx_irq;
  35. int err_irq;
  36. unsigned short *pin_list;
  37. };
  38. /*
  39. * bfin can timing parameters
  40. */
  41. static struct can_bittiming_const bfin_can_bittiming_const = {
  42. .name = DRV_NAME,
  43. .tseg1_min = 1,
  44. .tseg1_max = 16,
  45. .tseg2_min = 1,
  46. .tseg2_max = 8,
  47. .sjw_max = 4,
  48. /*
  49. * Although the BRP field can be set to any value, it is recommended
  50. * that the value be greater than or equal to 4, as restrictions
  51. * apply to the bit timing configuration when BRP is less than 4.
  52. */
  53. .brp_min = 4,
  54. .brp_max = 1024,
  55. .brp_inc = 1,
  56. };
  57. static int bfin_can_set_bittiming(struct net_device *dev)
  58. {
  59. struct bfin_can_priv *priv = netdev_priv(dev);
  60. struct bfin_can_regs __iomem *reg = priv->membase;
  61. struct can_bittiming *bt = &priv->can.bittiming;
  62. u16 clk, timing;
  63. clk = bt->brp - 1;
  64. timing = ((bt->sjw - 1) << 8) | (bt->prop_seg + bt->phase_seg1 - 1) |
  65. ((bt->phase_seg2 - 1) << 4);
  66. /*
  67. * If the SAM bit is set, the input signal is oversampled three times
  68. * at the SCLK rate.
  69. */
  70. if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
  71. timing |= SAM;
  72. bfin_write(&reg->clock, clk);
  73. bfin_write(&reg->timing, timing);
  74. dev_info(dev->dev.parent, "setting CLOCK=0x%04x TIMING=0x%04x\n",
  75. clk, timing);
  76. return 0;
  77. }
  78. static void bfin_can_set_reset_mode(struct net_device *dev)
  79. {
  80. struct bfin_can_priv *priv = netdev_priv(dev);
  81. struct bfin_can_regs __iomem *reg = priv->membase;
  82. int timeout = BFIN_CAN_TIMEOUT;
  83. int i;
  84. /* disable interrupts */
  85. bfin_write(&reg->mbim1, 0);
  86. bfin_write(&reg->mbim2, 0);
  87. bfin_write(&reg->gim, 0);
  88. /* reset can and enter configuration mode */
  89. bfin_write(&reg->control, SRS | CCR);
  90. SSYNC();
  91. bfin_write(&reg->control, CCR);
  92. SSYNC();
  93. while (!(bfin_read(&reg->control) & CCA)) {
  94. udelay(10);
  95. if (--timeout == 0) {
  96. dev_err(dev->dev.parent,
  97. "fail to enter configuration mode\n");
  98. BUG();
  99. }
  100. }
  101. /*
  102. * All mailbox configurations are marked as inactive
  103. * by writing to CAN Mailbox Configuration Registers 1 and 2
  104. * For all bits: 0 - Mailbox disabled, 1 - Mailbox enabled
  105. */
  106. bfin_write(&reg->mc1, 0);
  107. bfin_write(&reg->mc2, 0);
  108. /* Set Mailbox Direction */
  109. bfin_write(&reg->md1, 0xFFFF); /* mailbox 1-16 are RX */
  110. bfin_write(&reg->md2, 0); /* mailbox 17-32 are TX */
  111. /* RECEIVE_STD_CHL */
  112. for (i = 0; i < 2; i++) {
  113. bfin_write(&reg->chl[RECEIVE_STD_CHL + i].id0, 0);
  114. bfin_write(&reg->chl[RECEIVE_STD_CHL + i].id1, AME);
  115. bfin_write(&reg->chl[RECEIVE_STD_CHL + i].dlc, 0);
  116. bfin_write(&reg->msk[RECEIVE_STD_CHL + i].amh, 0x1FFF);
  117. bfin_write(&reg->msk[RECEIVE_STD_CHL + i].aml, 0xFFFF);
  118. }
  119. /* RECEIVE_EXT_CHL */
  120. for (i = 0; i < 2; i++) {
  121. bfin_write(&reg->chl[RECEIVE_EXT_CHL + i].id0, 0);
  122. bfin_write(&reg->chl[RECEIVE_EXT_CHL + i].id1, AME | IDE);
  123. bfin_write(&reg->chl[RECEIVE_EXT_CHL + i].dlc, 0);
  124. bfin_write(&reg->msk[RECEIVE_EXT_CHL + i].amh, 0x1FFF);
  125. bfin_write(&reg->msk[RECEIVE_EXT_CHL + i].aml, 0xFFFF);
  126. }
  127. bfin_write(&reg->mc2, BIT(TRANSMIT_CHL - 16));
  128. bfin_write(&reg->mc1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL));
  129. SSYNC();
  130. priv->can.state = CAN_STATE_STOPPED;
  131. }
  132. static void bfin_can_set_normal_mode(struct net_device *dev)
  133. {
  134. struct bfin_can_priv *priv = netdev_priv(dev);
  135. struct bfin_can_regs __iomem *reg = priv->membase;
  136. int timeout = BFIN_CAN_TIMEOUT;
  137. /*
  138. * leave configuration mode
  139. */
  140. bfin_write(&reg->control, bfin_read(&reg->control) & ~CCR);
  141. while (bfin_read(&reg->status) & CCA) {
  142. udelay(10);
  143. if (--timeout == 0) {
  144. dev_err(dev->dev.parent,
  145. "fail to leave configuration mode\n");
  146. BUG();
  147. }
  148. }
  149. /*
  150. * clear _All_ tx and rx interrupts
  151. */
  152. bfin_write(&reg->mbtif1, 0xFFFF);
  153. bfin_write(&reg->mbtif2, 0xFFFF);
  154. bfin_write(&reg->mbrif1, 0xFFFF);
  155. bfin_write(&reg->mbrif2, 0xFFFF);
  156. /*
  157. * clear global interrupt status register
  158. */
  159. bfin_write(&reg->gis, 0x7FF); /* overwrites with '1' */
  160. /*
  161. * Initialize Interrupts
  162. * - set bits in the mailbox interrupt mask register
  163. * - global interrupt mask
  164. */
  165. bfin_write(&reg->mbim1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL));
  166. bfin_write(&reg->mbim2, BIT(TRANSMIT_CHL - 16));
  167. bfin_write(&reg->gim, EPIM | BOIM | RMLIM);
  168. SSYNC();
  169. }
  170. static void bfin_can_start(struct net_device *dev)
  171. {
  172. struct bfin_can_priv *priv = netdev_priv(dev);
  173. /* enter reset mode */
  174. if (priv->can.state != CAN_STATE_STOPPED)
  175. bfin_can_set_reset_mode(dev);
  176. /* leave reset mode */
  177. bfin_can_set_normal_mode(dev);
  178. }
  179. static int bfin_can_set_mode(struct net_device *dev, enum can_mode mode)
  180. {
  181. switch (mode) {
  182. case CAN_MODE_START:
  183. bfin_can_start(dev);
  184. if (netif_queue_stopped(dev))
  185. netif_wake_queue(dev);
  186. break;
  187. default:
  188. return -EOPNOTSUPP;
  189. }
  190. return 0;
  191. }
  192. static int bfin_can_get_berr_counter(const struct net_device *dev,
  193. struct can_berr_counter *bec)
  194. {
  195. struct bfin_can_priv *priv = netdev_priv(dev);
  196. struct bfin_can_regs __iomem *reg = priv->membase;
  197. u16 cec = bfin_read(&reg->cec);
  198. bec->txerr = cec >> 8;
  199. bec->rxerr = cec;
  200. return 0;
  201. }
  202. static int bfin_can_start_xmit(struct sk_buff *skb, struct net_device *dev)
  203. {
  204. struct bfin_can_priv *priv = netdev_priv(dev);
  205. struct bfin_can_regs __iomem *reg = priv->membase;
  206. struct can_frame *cf = (struct can_frame *)skb->data;
  207. u8 dlc = cf->can_dlc;
  208. canid_t id = cf->can_id;
  209. u8 *data = cf->data;
  210. u16 val;
  211. int i;
  212. if (can_dropped_invalid_skb(dev, skb))
  213. return NETDEV_TX_OK;
  214. netif_stop_queue(dev);
  215. /* fill id */
  216. if (id & CAN_EFF_FLAG) {
  217. bfin_write(&reg->chl[TRANSMIT_CHL].id0, id);
  218. val = ((id & 0x1FFF0000) >> 16) | IDE;
  219. } else
  220. val = (id << 2);
  221. if (id & CAN_RTR_FLAG)
  222. val |= RTR;
  223. bfin_write(&reg->chl[TRANSMIT_CHL].id1, val | AME);
  224. /* fill payload */
  225. for (i = 0; i < 8; i += 2) {
  226. val = ((7 - i) < dlc ? (data[7 - i]) : 0) +
  227. ((6 - i) < dlc ? (data[6 - i] << 8) : 0);
  228. bfin_write(&reg->chl[TRANSMIT_CHL].data[i], val);
  229. }
  230. /* fill data length code */
  231. bfin_write(&reg->chl[TRANSMIT_CHL].dlc, dlc);
  232. can_put_echo_skb(skb, dev, 0);
  233. /* set transmit request */
  234. bfin_write(&reg->trs2, BIT(TRANSMIT_CHL - 16));
  235. return 0;
  236. }
  237. static void bfin_can_rx(struct net_device *dev, u16 isrc)
  238. {
  239. struct bfin_can_priv *priv = netdev_priv(dev);
  240. struct net_device_stats *stats = &dev->stats;
  241. struct bfin_can_regs __iomem *reg = priv->membase;
  242. struct can_frame *cf;
  243. struct sk_buff *skb;
  244. int obj;
  245. int i;
  246. u16 val;
  247. skb = alloc_can_skb(dev, &cf);
  248. if (skb == NULL)
  249. return;
  250. /* get id */
  251. if (isrc & BIT(RECEIVE_EXT_CHL)) {
  252. /* extended frame format (EFF) */
  253. cf->can_id = ((bfin_read(&reg->chl[RECEIVE_EXT_CHL].id1)
  254. & 0x1FFF) << 16)
  255. + bfin_read(&reg->chl[RECEIVE_EXT_CHL].id0);
  256. cf->can_id |= CAN_EFF_FLAG;
  257. obj = RECEIVE_EXT_CHL;
  258. } else {
  259. /* standard frame format (SFF) */
  260. cf->can_id = (bfin_read(&reg->chl[RECEIVE_STD_CHL].id1)
  261. & 0x1ffc) >> 2;
  262. obj = RECEIVE_STD_CHL;
  263. }
  264. if (bfin_read(&reg->chl[obj].id1) & RTR)
  265. cf->can_id |= CAN_RTR_FLAG;
  266. /* get data length code */
  267. cf->can_dlc = get_can_dlc(bfin_read(&reg->chl[obj].dlc) & 0xF);
  268. /* get payload */
  269. for (i = 0; i < 8; i += 2) {
  270. val = bfin_read(&reg->chl[obj].data[i]);
  271. cf->data[7 - i] = (7 - i) < cf->can_dlc ? val : 0;
  272. cf->data[6 - i] = (6 - i) < cf->can_dlc ? (val >> 8) : 0;
  273. }
  274. netif_rx(skb);
  275. stats->rx_packets++;
  276. stats->rx_bytes += cf->can_dlc;
  277. }
  278. static int bfin_can_err(struct net_device *dev, u16 isrc, u16 status)
  279. {
  280. struct bfin_can_priv *priv = netdev_priv(dev);
  281. struct bfin_can_regs __iomem *reg = priv->membase;
  282. struct net_device_stats *stats = &dev->stats;
  283. struct can_frame *cf;
  284. struct sk_buff *skb;
  285. enum can_state state = priv->can.state;
  286. skb = alloc_can_err_skb(dev, &cf);
  287. if (skb == NULL)
  288. return -ENOMEM;
  289. if (isrc & RMLIS) {
  290. /* data overrun interrupt */
  291. dev_dbg(dev->dev.parent, "data overrun interrupt\n");
  292. cf->can_id |= CAN_ERR_CRTL;
  293. cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
  294. stats->rx_over_errors++;
  295. stats->rx_errors++;
  296. }
  297. if (isrc & BOIS) {
  298. dev_dbg(dev->dev.parent, "bus-off mode interrupt\n");
  299. state = CAN_STATE_BUS_OFF;
  300. cf->can_id |= CAN_ERR_BUSOFF;
  301. can_bus_off(dev);
  302. }
  303. if (isrc & EPIS) {
  304. /* error passive interrupt */
  305. dev_dbg(dev->dev.parent, "error passive interrupt\n");
  306. state = CAN_STATE_ERROR_PASSIVE;
  307. }
  308. if ((isrc & EWTIS) || (isrc & EWRIS)) {
  309. dev_dbg(dev->dev.parent,
  310. "Error Warning Transmit/Receive Interrupt\n");
  311. state = CAN_STATE_ERROR_WARNING;
  312. }
  313. if (state != priv->can.state && (state == CAN_STATE_ERROR_WARNING ||
  314. state == CAN_STATE_ERROR_PASSIVE)) {
  315. u16 cec = bfin_read(&reg->cec);
  316. u8 rxerr = cec;
  317. u8 txerr = cec >> 8;
  318. cf->can_id |= CAN_ERR_CRTL;
  319. if (state == CAN_STATE_ERROR_WARNING) {
  320. priv->can.can_stats.error_warning++;
  321. cf->data[1] = (txerr > rxerr) ?
  322. CAN_ERR_CRTL_TX_WARNING :
  323. CAN_ERR_CRTL_RX_WARNING;
  324. } else {
  325. priv->can.can_stats.error_passive++;
  326. cf->data[1] = (txerr > rxerr) ?
  327. CAN_ERR_CRTL_TX_PASSIVE :
  328. CAN_ERR_CRTL_RX_PASSIVE;
  329. }
  330. }
  331. if (status) {
  332. priv->can.can_stats.bus_error++;
  333. cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
  334. if (status & BEF)
  335. cf->data[2] |= CAN_ERR_PROT_BIT;
  336. else if (status & FER)
  337. cf->data[2] |= CAN_ERR_PROT_FORM;
  338. else if (status & SER)
  339. cf->data[2] |= CAN_ERR_PROT_STUFF;
  340. else
  341. cf->data[2] |= CAN_ERR_PROT_UNSPEC;
  342. }
  343. priv->can.state = state;
  344. netif_rx(skb);
  345. stats->rx_packets++;
  346. stats->rx_bytes += cf->can_dlc;
  347. return 0;
  348. }
  349. irqreturn_t bfin_can_interrupt(int irq, void *dev_id)
  350. {
  351. struct net_device *dev = dev_id;
  352. struct bfin_can_priv *priv = netdev_priv(dev);
  353. struct bfin_can_regs __iomem *reg = priv->membase;
  354. struct net_device_stats *stats = &dev->stats;
  355. u16 status, isrc;
  356. if ((irq == priv->tx_irq) && bfin_read(&reg->mbtif2)) {
  357. /* transmission complete interrupt */
  358. bfin_write(&reg->mbtif2, 0xFFFF);
  359. stats->tx_packets++;
  360. stats->tx_bytes += bfin_read(&reg->chl[TRANSMIT_CHL].dlc);
  361. can_get_echo_skb(dev, 0);
  362. netif_wake_queue(dev);
  363. } else if ((irq == priv->rx_irq) && bfin_read(&reg->mbrif1)) {
  364. /* receive interrupt */
  365. isrc = bfin_read(&reg->mbrif1);
  366. bfin_write(&reg->mbrif1, 0xFFFF);
  367. bfin_can_rx(dev, isrc);
  368. } else if ((irq == priv->err_irq) && bfin_read(&reg->gis)) {
  369. /* error interrupt */
  370. isrc = bfin_read(&reg->gis);
  371. status = bfin_read(&reg->esr);
  372. bfin_write(&reg->gis, 0x7FF);
  373. bfin_can_err(dev, isrc, status);
  374. } else {
  375. return IRQ_NONE;
  376. }
  377. return IRQ_HANDLED;
  378. }
  379. static int bfin_can_open(struct net_device *dev)
  380. {
  381. struct bfin_can_priv *priv = netdev_priv(dev);
  382. int err;
  383. /* set chip into reset mode */
  384. bfin_can_set_reset_mode(dev);
  385. /* common open */
  386. err = open_candev(dev);
  387. if (err)
  388. goto exit_open;
  389. /* register interrupt handler */
  390. err = request_irq(priv->rx_irq, &bfin_can_interrupt, 0,
  391. "bfin-can-rx", dev);
  392. if (err)
  393. goto exit_rx_irq;
  394. err = request_irq(priv->tx_irq, &bfin_can_interrupt, 0,
  395. "bfin-can-tx", dev);
  396. if (err)
  397. goto exit_tx_irq;
  398. err = request_irq(priv->err_irq, &bfin_can_interrupt, 0,
  399. "bfin-can-err", dev);
  400. if (err)
  401. goto exit_err_irq;
  402. bfin_can_start(dev);
  403. netif_start_queue(dev);
  404. return 0;
  405. exit_err_irq:
  406. free_irq(priv->tx_irq, dev);
  407. exit_tx_irq:
  408. free_irq(priv->rx_irq, dev);
  409. exit_rx_irq:
  410. close_candev(dev);
  411. exit_open:
  412. return err;
  413. }
  414. static int bfin_can_close(struct net_device *dev)
  415. {
  416. struct bfin_can_priv *priv = netdev_priv(dev);
  417. netif_stop_queue(dev);
  418. bfin_can_set_reset_mode(dev);
  419. close_candev(dev);
  420. free_irq(priv->rx_irq, dev);
  421. free_irq(priv->tx_irq, dev);
  422. free_irq(priv->err_irq, dev);
  423. return 0;
  424. }
  425. struct net_device *alloc_bfin_candev(void)
  426. {
  427. struct net_device *dev;
  428. struct bfin_can_priv *priv;
  429. dev = alloc_candev(sizeof(*priv), TX_ECHO_SKB_MAX);
  430. if (!dev)
  431. return NULL;
  432. priv = netdev_priv(dev);
  433. priv->dev = dev;
  434. priv->can.bittiming_const = &bfin_can_bittiming_const;
  435. priv->can.do_set_bittiming = bfin_can_set_bittiming;
  436. priv->can.do_set_mode = bfin_can_set_mode;
  437. priv->can.do_get_berr_counter = bfin_can_get_berr_counter;
  438. priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
  439. return dev;
  440. }
  441. static const struct net_device_ops bfin_can_netdev_ops = {
  442. .ndo_open = bfin_can_open,
  443. .ndo_stop = bfin_can_close,
  444. .ndo_start_xmit = bfin_can_start_xmit,
  445. };
  446. static int __devinit bfin_can_probe(struct platform_device *pdev)
  447. {
  448. int err;
  449. struct net_device *dev;
  450. struct bfin_can_priv *priv;
  451. struct resource *res_mem, *rx_irq, *tx_irq, *err_irq;
  452. unsigned short *pdata;
  453. pdata = pdev->dev.platform_data;
  454. if (!pdata) {
  455. dev_err(&pdev->dev, "No platform data provided!\n");
  456. err = -EINVAL;
  457. goto exit;
  458. }
  459. res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  460. rx_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  461. tx_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
  462. err_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
  463. if (!res_mem || !rx_irq || !tx_irq || !err_irq) {
  464. err = -EINVAL;
  465. goto exit;
  466. }
  467. if (!request_mem_region(res_mem->start, resource_size(res_mem),
  468. dev_name(&pdev->dev))) {
  469. err = -EBUSY;
  470. goto exit;
  471. }
  472. /* request peripheral pins */
  473. err = peripheral_request_list(pdata, dev_name(&pdev->dev));
  474. if (err)
  475. goto exit_mem_release;
  476. dev = alloc_bfin_candev();
  477. if (!dev) {
  478. err = -ENOMEM;
  479. goto exit_peri_pin_free;
  480. }
  481. priv = netdev_priv(dev);
  482. priv->membase = (void __iomem *)res_mem->start;
  483. priv->rx_irq = rx_irq->start;
  484. priv->tx_irq = tx_irq->start;
  485. priv->err_irq = err_irq->start;
  486. priv->pin_list = pdata;
  487. priv->can.clock.freq = get_sclk();
  488. dev_set_drvdata(&pdev->dev, dev);
  489. SET_NETDEV_DEV(dev, &pdev->dev);
  490. dev->flags |= IFF_ECHO; /* we support local echo */
  491. dev->netdev_ops = &bfin_can_netdev_ops;
  492. bfin_can_set_reset_mode(dev);
  493. err = register_candev(dev);
  494. if (err) {
  495. dev_err(&pdev->dev, "registering failed (err=%d)\n", err);
  496. goto exit_candev_free;
  497. }
  498. dev_info(&pdev->dev,
  499. "%s device registered"
  500. "(&reg_base=%p, rx_irq=%d, tx_irq=%d, err_irq=%d, sclk=%d)\n",
  501. DRV_NAME, (void *)priv->membase, priv->rx_irq,
  502. priv->tx_irq, priv->err_irq, priv->can.clock.freq);
  503. return 0;
  504. exit_candev_free:
  505. free_candev(dev);
  506. exit_peri_pin_free:
  507. peripheral_free_list(pdata);
  508. exit_mem_release:
  509. release_mem_region(res_mem->start, resource_size(res_mem));
  510. exit:
  511. return err;
  512. }
  513. static int __devexit bfin_can_remove(struct platform_device *pdev)
  514. {
  515. struct net_device *dev = dev_get_drvdata(&pdev->dev);
  516. struct bfin_can_priv *priv = netdev_priv(dev);
  517. struct resource *res;
  518. bfin_can_set_reset_mode(dev);
  519. unregister_candev(dev);
  520. dev_set_drvdata(&pdev->dev, NULL);
  521. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  522. release_mem_region(res->start, resource_size(res));
  523. peripheral_free_list(priv->pin_list);
  524. free_candev(dev);
  525. return 0;
  526. }
  527. #ifdef CONFIG_PM
  528. static int bfin_can_suspend(struct platform_device *pdev, pm_message_t mesg)
  529. {
  530. struct net_device *dev = dev_get_drvdata(&pdev->dev);
  531. struct bfin_can_priv *priv = netdev_priv(dev);
  532. struct bfin_can_regs __iomem *reg = priv->membase;
  533. int timeout = BFIN_CAN_TIMEOUT;
  534. if (netif_running(dev)) {
  535. /* enter sleep mode */
  536. bfin_write(&reg->control, bfin_read(&reg->control) | SMR);
  537. SSYNC();
  538. while (!(bfin_read(&reg->intr) & SMACK)) {
  539. udelay(10);
  540. if (--timeout == 0) {
  541. dev_err(dev->dev.parent,
  542. "fail to enter sleep mode\n");
  543. BUG();
  544. }
  545. }
  546. }
  547. return 0;
  548. }
  549. static int bfin_can_resume(struct platform_device *pdev)
  550. {
  551. struct net_device *dev = dev_get_drvdata(&pdev->dev);
  552. struct bfin_can_priv *priv = netdev_priv(dev);
  553. struct bfin_can_regs __iomem *reg = priv->membase;
  554. if (netif_running(dev)) {
  555. /* leave sleep mode */
  556. bfin_write(&reg->intr, 0);
  557. SSYNC();
  558. }
  559. return 0;
  560. }
  561. #else
  562. #define bfin_can_suspend NULL
  563. #define bfin_can_resume NULL
  564. #endif /* CONFIG_PM */
  565. static struct platform_driver bfin_can_driver = {
  566. .probe = bfin_can_probe,
  567. .remove = __devexit_p(bfin_can_remove),
  568. .suspend = bfin_can_suspend,
  569. .resume = bfin_can_resume,
  570. .driver = {
  571. .name = DRV_NAME,
  572. .owner = THIS_MODULE,
  573. },
  574. };
  575. module_platform_driver(bfin_can_driver);
  576. MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
  577. MODULE_LICENSE("GPL");
  578. MODULE_DESCRIPTION("Blackfin on-chip CAN netdevice driver");