mcbsp.c 33 KB

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  1. /*
  2. * linux/arch/arm/plat-omap/mcbsp.c
  3. *
  4. * Copyright (C) 2004 Nokia Corporation
  5. * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
  6. *
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * Multichannel mode not supported.
  13. */
  14. #include <linux/module.h>
  15. #include <linux/init.h>
  16. #include <linux/device.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/err.h>
  20. #include <linux/clk.h>
  21. #include <linux/delay.h>
  22. #include <linux/io.h>
  23. #include <linux/slab.h>
  24. #include <plat/mcbsp.h>
  25. #include <linux/pm_runtime.h>
  26. /* XXX These "sideways" includes are a sign that something is wrong */
  27. #include "../mach-omap2/cm2xxx_3xxx.h"
  28. #include "../mach-omap2/cm-regbits-34xx.h"
  29. struct omap_mcbsp **mcbsp_ptr;
  30. int omap_mcbsp_count, omap_mcbsp_cache_size;
  31. static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  32. {
  33. if (cpu_class_is_omap1()) {
  34. ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
  35. __raw_writew((u16)val, mcbsp->io_base + reg);
  36. } else if (cpu_is_omap2420()) {
  37. ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
  38. __raw_writew((u16)val, mcbsp->io_base + reg);
  39. } else {
  40. ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
  41. __raw_writel(val, mcbsp->io_base + reg);
  42. }
  43. }
  44. static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
  45. {
  46. if (cpu_class_is_omap1()) {
  47. return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
  48. ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
  49. } else if (cpu_is_omap2420()) {
  50. return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
  51. ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
  52. } else {
  53. return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
  54. ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
  55. }
  56. }
  57. #ifdef CONFIG_ARCH_OMAP3
  58. static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  59. {
  60. __raw_writel(val, mcbsp->st_data->io_base_st + reg);
  61. }
  62. static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
  63. {
  64. return __raw_readl(mcbsp->st_data->io_base_st + reg);
  65. }
  66. #endif
  67. #define MCBSP_READ(mcbsp, reg) \
  68. omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
  69. #define MCBSP_WRITE(mcbsp, reg, val) \
  70. omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
  71. #define MCBSP_READ_CACHE(mcbsp, reg) \
  72. omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
  73. #define MCBSP_ST_READ(mcbsp, reg) \
  74. omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
  75. #define MCBSP_ST_WRITE(mcbsp, reg, val) \
  76. omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
  77. static void omap_mcbsp_dump_reg(u8 id)
  78. {
  79. struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
  80. dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  81. dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
  82. MCBSP_READ(mcbsp, DRR2));
  83. dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
  84. MCBSP_READ(mcbsp, DRR1));
  85. dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
  86. MCBSP_READ(mcbsp, DXR2));
  87. dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
  88. MCBSP_READ(mcbsp, DXR1));
  89. dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
  90. MCBSP_READ(mcbsp, SPCR2));
  91. dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
  92. MCBSP_READ(mcbsp, SPCR1));
  93. dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
  94. MCBSP_READ(mcbsp, RCR2));
  95. dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
  96. MCBSP_READ(mcbsp, RCR1));
  97. dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
  98. MCBSP_READ(mcbsp, XCR2));
  99. dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
  100. MCBSP_READ(mcbsp, XCR1));
  101. dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
  102. MCBSP_READ(mcbsp, SRGR2));
  103. dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
  104. MCBSP_READ(mcbsp, SRGR1));
  105. dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
  106. MCBSP_READ(mcbsp, PCR0));
  107. dev_dbg(mcbsp->dev, "***********************\n");
  108. }
  109. static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
  110. {
  111. struct omap_mcbsp *mcbsp_tx = dev_id;
  112. u16 irqst_spcr2;
  113. irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
  114. dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
  115. if (irqst_spcr2 & XSYNC_ERR) {
  116. dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
  117. irqst_spcr2);
  118. /* Writing zero to XSYNC_ERR clears the IRQ */
  119. MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
  120. }
  121. return IRQ_HANDLED;
  122. }
  123. static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
  124. {
  125. struct omap_mcbsp *mcbsp_rx = dev_id;
  126. u16 irqst_spcr1;
  127. irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
  128. dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
  129. if (irqst_spcr1 & RSYNC_ERR) {
  130. dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
  131. irqst_spcr1);
  132. /* Writing zero to RSYNC_ERR clears the IRQ */
  133. MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
  134. }
  135. return IRQ_HANDLED;
  136. }
  137. /*
  138. * omap_mcbsp_config simply write a config to the
  139. * appropriate McBSP.
  140. * You either call this function or set the McBSP registers
  141. * by yourself before calling omap_mcbsp_start().
  142. */
  143. void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
  144. {
  145. struct omap_mcbsp *mcbsp;
  146. if (!omap_mcbsp_check_valid_id(id)) {
  147. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  148. return;
  149. }
  150. mcbsp = id_to_mcbsp_ptr(id);
  151. dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
  152. mcbsp->id, mcbsp->phys_base);
  153. /* We write the given config */
  154. MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
  155. MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
  156. MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
  157. MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
  158. MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
  159. MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
  160. MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
  161. MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
  162. MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
  163. MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
  164. MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
  165. if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
  166. MCBSP_WRITE(mcbsp, XCCR, config->xccr);
  167. MCBSP_WRITE(mcbsp, RCCR, config->rccr);
  168. }
  169. }
  170. EXPORT_SYMBOL(omap_mcbsp_config);
  171. /**
  172. * omap_mcbsp_dma_params - returns the dma channel number
  173. * @id - mcbsp id
  174. * @stream - indicates the direction of data flow (rx or tx)
  175. *
  176. * Returns the dma channel number for the rx channel or tx channel
  177. * based on the value of @stream for the requested mcbsp given by @id
  178. */
  179. int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream)
  180. {
  181. struct omap_mcbsp *mcbsp;
  182. if (!omap_mcbsp_check_valid_id(id)) {
  183. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  184. return -ENODEV;
  185. }
  186. mcbsp = id_to_mcbsp_ptr(id);
  187. if (stream)
  188. return mcbsp->dma_rx_sync;
  189. else
  190. return mcbsp->dma_tx_sync;
  191. }
  192. EXPORT_SYMBOL(omap_mcbsp_dma_ch_params);
  193. /**
  194. * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
  195. * @id - mcbsp id
  196. * @stream - indicates the direction of data flow (rx or tx)
  197. *
  198. * Returns the address of mcbsp data transmit register or data receive register
  199. * to be used by DMA for transferring/receiving data based on the value of
  200. * @stream for the requested mcbsp given by @id
  201. */
  202. int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
  203. {
  204. struct omap_mcbsp *mcbsp;
  205. int data_reg;
  206. if (!omap_mcbsp_check_valid_id(id)) {
  207. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  208. return -ENODEV;
  209. }
  210. mcbsp = id_to_mcbsp_ptr(id);
  211. data_reg = mcbsp->phys_dma_base;
  212. if (mcbsp->mcbsp_config_type < MCBSP_CONFIG_TYPE2) {
  213. if (stream)
  214. data_reg += OMAP_MCBSP_REG_DRR1;
  215. else
  216. data_reg += OMAP_MCBSP_REG_DXR1;
  217. } else {
  218. if (stream)
  219. data_reg += OMAP_MCBSP_REG_DRR;
  220. else
  221. data_reg += OMAP_MCBSP_REG_DXR;
  222. }
  223. return data_reg;
  224. }
  225. EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
  226. #ifdef CONFIG_ARCH_OMAP3
  227. static void omap_st_on(struct omap_mcbsp *mcbsp)
  228. {
  229. unsigned int w;
  230. /*
  231. * Sidetone uses McBSP ICLK - which must not idle when sidetones
  232. * are enabled or sidetones start sounding ugly.
  233. */
  234. w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
  235. w &= ~(1 << (mcbsp->id - 2));
  236. omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
  237. /* Enable McBSP Sidetone */
  238. w = MCBSP_READ(mcbsp, SSELCR);
  239. MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
  240. /* Enable Sidetone from Sidetone Core */
  241. w = MCBSP_ST_READ(mcbsp, SSELCR);
  242. MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
  243. }
  244. static void omap_st_off(struct omap_mcbsp *mcbsp)
  245. {
  246. unsigned int w;
  247. w = MCBSP_ST_READ(mcbsp, SSELCR);
  248. MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
  249. w = MCBSP_READ(mcbsp, SSELCR);
  250. MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
  251. w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
  252. w |= 1 << (mcbsp->id - 2);
  253. omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
  254. }
  255. static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
  256. {
  257. u16 val, i;
  258. val = MCBSP_ST_READ(mcbsp, SSELCR);
  259. if (val & ST_COEFFWREN)
  260. MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
  261. MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
  262. for (i = 0; i < 128; i++)
  263. MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
  264. i = 0;
  265. val = MCBSP_ST_READ(mcbsp, SSELCR);
  266. while (!(val & ST_COEFFWRDONE) && (++i < 1000))
  267. val = MCBSP_ST_READ(mcbsp, SSELCR);
  268. MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
  269. if (i == 1000)
  270. dev_err(mcbsp->dev, "McBSP FIR load error!\n");
  271. }
  272. static void omap_st_chgain(struct omap_mcbsp *mcbsp)
  273. {
  274. u16 w;
  275. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  276. w = MCBSP_ST_READ(mcbsp, SSELCR);
  277. MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
  278. ST_CH1GAIN(st_data->ch1gain));
  279. }
  280. int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
  281. {
  282. struct omap_mcbsp *mcbsp;
  283. struct omap_mcbsp_st_data *st_data;
  284. int ret = 0;
  285. if (!omap_mcbsp_check_valid_id(id)) {
  286. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  287. return -ENODEV;
  288. }
  289. mcbsp = id_to_mcbsp_ptr(id);
  290. st_data = mcbsp->st_data;
  291. if (!st_data)
  292. return -ENOENT;
  293. spin_lock_irq(&mcbsp->lock);
  294. if (channel == 0)
  295. st_data->ch0gain = chgain;
  296. else if (channel == 1)
  297. st_data->ch1gain = chgain;
  298. else
  299. ret = -EINVAL;
  300. if (st_data->enabled)
  301. omap_st_chgain(mcbsp);
  302. spin_unlock_irq(&mcbsp->lock);
  303. return ret;
  304. }
  305. EXPORT_SYMBOL(omap_st_set_chgain);
  306. int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
  307. {
  308. struct omap_mcbsp *mcbsp;
  309. struct omap_mcbsp_st_data *st_data;
  310. int ret = 0;
  311. if (!omap_mcbsp_check_valid_id(id)) {
  312. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  313. return -ENODEV;
  314. }
  315. mcbsp = id_to_mcbsp_ptr(id);
  316. st_data = mcbsp->st_data;
  317. if (!st_data)
  318. return -ENOENT;
  319. spin_lock_irq(&mcbsp->lock);
  320. if (channel == 0)
  321. *chgain = st_data->ch0gain;
  322. else if (channel == 1)
  323. *chgain = st_data->ch1gain;
  324. else
  325. ret = -EINVAL;
  326. spin_unlock_irq(&mcbsp->lock);
  327. return ret;
  328. }
  329. EXPORT_SYMBOL(omap_st_get_chgain);
  330. static int omap_st_start(struct omap_mcbsp *mcbsp)
  331. {
  332. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  333. if (st_data && st_data->enabled && !st_data->running) {
  334. omap_st_fir_write(mcbsp, st_data->taps);
  335. omap_st_chgain(mcbsp);
  336. if (!mcbsp->free) {
  337. omap_st_on(mcbsp);
  338. st_data->running = 1;
  339. }
  340. }
  341. return 0;
  342. }
  343. int omap_st_enable(unsigned int id)
  344. {
  345. struct omap_mcbsp *mcbsp;
  346. struct omap_mcbsp_st_data *st_data;
  347. if (!omap_mcbsp_check_valid_id(id)) {
  348. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  349. return -ENODEV;
  350. }
  351. mcbsp = id_to_mcbsp_ptr(id);
  352. st_data = mcbsp->st_data;
  353. if (!st_data)
  354. return -ENODEV;
  355. spin_lock_irq(&mcbsp->lock);
  356. st_data->enabled = 1;
  357. omap_st_start(mcbsp);
  358. spin_unlock_irq(&mcbsp->lock);
  359. return 0;
  360. }
  361. EXPORT_SYMBOL(omap_st_enable);
  362. static int omap_st_stop(struct omap_mcbsp *mcbsp)
  363. {
  364. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  365. if (st_data && st_data->running) {
  366. if (!mcbsp->free) {
  367. omap_st_off(mcbsp);
  368. st_data->running = 0;
  369. }
  370. }
  371. return 0;
  372. }
  373. int omap_st_disable(unsigned int id)
  374. {
  375. struct omap_mcbsp *mcbsp;
  376. struct omap_mcbsp_st_data *st_data;
  377. int ret = 0;
  378. if (!omap_mcbsp_check_valid_id(id)) {
  379. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  380. return -ENODEV;
  381. }
  382. mcbsp = id_to_mcbsp_ptr(id);
  383. st_data = mcbsp->st_data;
  384. if (!st_data)
  385. return -ENODEV;
  386. spin_lock_irq(&mcbsp->lock);
  387. omap_st_stop(mcbsp);
  388. st_data->enabled = 0;
  389. spin_unlock_irq(&mcbsp->lock);
  390. return ret;
  391. }
  392. EXPORT_SYMBOL(omap_st_disable);
  393. int omap_st_is_enabled(unsigned int id)
  394. {
  395. struct omap_mcbsp *mcbsp;
  396. struct omap_mcbsp_st_data *st_data;
  397. if (!omap_mcbsp_check_valid_id(id)) {
  398. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  399. return -ENODEV;
  400. }
  401. mcbsp = id_to_mcbsp_ptr(id);
  402. st_data = mcbsp->st_data;
  403. if (!st_data)
  404. return -ENODEV;
  405. return st_data->enabled;
  406. }
  407. EXPORT_SYMBOL(omap_st_is_enabled);
  408. /*
  409. * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
  410. * The threshold parameter is 1 based, and it is converted (threshold - 1)
  411. * for the THRSH2 register.
  412. */
  413. void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
  414. {
  415. struct omap_mcbsp *mcbsp;
  416. if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
  417. return;
  418. if (!omap_mcbsp_check_valid_id(id)) {
  419. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  420. return;
  421. }
  422. mcbsp = id_to_mcbsp_ptr(id);
  423. if (threshold && threshold <= mcbsp->max_tx_thres)
  424. MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
  425. }
  426. EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
  427. /*
  428. * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
  429. * The threshold parameter is 1 based, and it is converted (threshold - 1)
  430. * for the THRSH1 register.
  431. */
  432. void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
  433. {
  434. struct omap_mcbsp *mcbsp;
  435. if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
  436. return;
  437. if (!omap_mcbsp_check_valid_id(id)) {
  438. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  439. return;
  440. }
  441. mcbsp = id_to_mcbsp_ptr(id);
  442. if (threshold && threshold <= mcbsp->max_rx_thres)
  443. MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
  444. }
  445. EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
  446. /*
  447. * omap_mcbsp_get_max_tx_thres just return the current configured
  448. * maximum threshold for transmission
  449. */
  450. u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
  451. {
  452. struct omap_mcbsp *mcbsp;
  453. if (!omap_mcbsp_check_valid_id(id)) {
  454. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  455. return -ENODEV;
  456. }
  457. mcbsp = id_to_mcbsp_ptr(id);
  458. return mcbsp->max_tx_thres;
  459. }
  460. EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
  461. /*
  462. * omap_mcbsp_get_max_rx_thres just return the current configured
  463. * maximum threshold for reception
  464. */
  465. u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
  466. {
  467. struct omap_mcbsp *mcbsp;
  468. if (!omap_mcbsp_check_valid_id(id)) {
  469. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  470. return -ENODEV;
  471. }
  472. mcbsp = id_to_mcbsp_ptr(id);
  473. return mcbsp->max_rx_thres;
  474. }
  475. EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
  476. u16 omap_mcbsp_get_fifo_size(unsigned int id)
  477. {
  478. struct omap_mcbsp *mcbsp;
  479. if (!omap_mcbsp_check_valid_id(id)) {
  480. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  481. return -ENODEV;
  482. }
  483. mcbsp = id_to_mcbsp_ptr(id);
  484. return mcbsp->pdata->buffer_size;
  485. }
  486. EXPORT_SYMBOL(omap_mcbsp_get_fifo_size);
  487. /*
  488. * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
  489. */
  490. u16 omap_mcbsp_get_tx_delay(unsigned int id)
  491. {
  492. struct omap_mcbsp *mcbsp;
  493. u16 buffstat;
  494. if (!omap_mcbsp_check_valid_id(id)) {
  495. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  496. return -ENODEV;
  497. }
  498. mcbsp = id_to_mcbsp_ptr(id);
  499. /* Returns the number of free locations in the buffer */
  500. buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
  501. /* Number of slots are different in McBSP ports */
  502. return mcbsp->pdata->buffer_size - buffstat;
  503. }
  504. EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
  505. /*
  506. * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
  507. * to reach the threshold value (when the DMA will be triggered to read it)
  508. */
  509. u16 omap_mcbsp_get_rx_delay(unsigned int id)
  510. {
  511. struct omap_mcbsp *mcbsp;
  512. u16 buffstat, threshold;
  513. if (!omap_mcbsp_check_valid_id(id)) {
  514. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  515. return -ENODEV;
  516. }
  517. mcbsp = id_to_mcbsp_ptr(id);
  518. /* Returns the number of used locations in the buffer */
  519. buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
  520. /* RX threshold */
  521. threshold = MCBSP_READ(mcbsp, THRSH1);
  522. /* Return the number of location till we reach the threshold limit */
  523. if (threshold <= buffstat)
  524. return 0;
  525. else
  526. return threshold - buffstat;
  527. }
  528. EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
  529. /*
  530. * omap_mcbsp_get_dma_op_mode just return the current configured
  531. * operating mode for the mcbsp channel
  532. */
  533. int omap_mcbsp_get_dma_op_mode(unsigned int id)
  534. {
  535. struct omap_mcbsp *mcbsp;
  536. int dma_op_mode;
  537. if (!omap_mcbsp_check_valid_id(id)) {
  538. printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
  539. return -ENODEV;
  540. }
  541. mcbsp = id_to_mcbsp_ptr(id);
  542. dma_op_mode = mcbsp->dma_op_mode;
  543. return dma_op_mode;
  544. }
  545. EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
  546. static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
  547. {
  548. /*
  549. * Enable wakup behavior, smart idle and all wakeups
  550. * REVISIT: some wakeups may be unnecessary
  551. */
  552. if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
  553. MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
  554. }
  555. }
  556. static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
  557. {
  558. /*
  559. * Disable wakup behavior, smart idle and all wakeups
  560. */
  561. if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
  562. /*
  563. * HW bug workaround - If no_idle mode is taken, we need to
  564. * go to smart_idle before going to always_idle, or the
  565. * device will not hit retention anymore.
  566. */
  567. MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
  568. }
  569. }
  570. #else
  571. static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
  572. static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
  573. static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
  574. static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
  575. #endif
  576. int omap_mcbsp_request(unsigned int id)
  577. {
  578. struct omap_mcbsp *mcbsp;
  579. void *reg_cache;
  580. int err;
  581. if (!omap_mcbsp_check_valid_id(id)) {
  582. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  583. return -ENODEV;
  584. }
  585. mcbsp = id_to_mcbsp_ptr(id);
  586. reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
  587. if (!reg_cache) {
  588. return -ENOMEM;
  589. }
  590. spin_lock(&mcbsp->lock);
  591. if (!mcbsp->free) {
  592. dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
  593. mcbsp->id);
  594. err = -EBUSY;
  595. goto err_kfree;
  596. }
  597. mcbsp->free = false;
  598. mcbsp->reg_cache = reg_cache;
  599. spin_unlock(&mcbsp->lock);
  600. if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
  601. mcbsp->pdata->ops->request(id);
  602. pm_runtime_get_sync(mcbsp->dev);
  603. /* Do procedure specific to omap34xx arch, if applicable */
  604. omap34xx_mcbsp_request(mcbsp);
  605. /*
  606. * Make sure that transmitter, receiver and sample-rate generator are
  607. * not running before activating IRQs.
  608. */
  609. MCBSP_WRITE(mcbsp, SPCR1, 0);
  610. MCBSP_WRITE(mcbsp, SPCR2, 0);
  611. err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
  612. 0, "McBSP", (void *)mcbsp);
  613. if (err != 0) {
  614. dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
  615. "for McBSP%d\n", mcbsp->tx_irq,
  616. mcbsp->id);
  617. goto err_clk_disable;
  618. }
  619. if (mcbsp->rx_irq) {
  620. err = request_irq(mcbsp->rx_irq,
  621. omap_mcbsp_rx_irq_handler,
  622. 0, "McBSP", (void *)mcbsp);
  623. if (err != 0) {
  624. dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
  625. "for McBSP%d\n", mcbsp->rx_irq,
  626. mcbsp->id);
  627. goto err_free_irq;
  628. }
  629. }
  630. return 0;
  631. err_free_irq:
  632. free_irq(mcbsp->tx_irq, (void *)mcbsp);
  633. err_clk_disable:
  634. if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
  635. mcbsp->pdata->ops->free(id);
  636. /* Do procedure specific to omap34xx arch, if applicable */
  637. omap34xx_mcbsp_free(mcbsp);
  638. pm_runtime_put_sync(mcbsp->dev);
  639. spin_lock(&mcbsp->lock);
  640. mcbsp->free = true;
  641. mcbsp->reg_cache = NULL;
  642. err_kfree:
  643. spin_unlock(&mcbsp->lock);
  644. kfree(reg_cache);
  645. return err;
  646. }
  647. EXPORT_SYMBOL(omap_mcbsp_request);
  648. void omap_mcbsp_free(unsigned int id)
  649. {
  650. struct omap_mcbsp *mcbsp;
  651. void *reg_cache;
  652. if (!omap_mcbsp_check_valid_id(id)) {
  653. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  654. return;
  655. }
  656. mcbsp = id_to_mcbsp_ptr(id);
  657. if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
  658. mcbsp->pdata->ops->free(id);
  659. /* Do procedure specific to omap34xx arch, if applicable */
  660. omap34xx_mcbsp_free(mcbsp);
  661. pm_runtime_put_sync(mcbsp->dev);
  662. if (mcbsp->rx_irq)
  663. free_irq(mcbsp->rx_irq, (void *)mcbsp);
  664. free_irq(mcbsp->tx_irq, (void *)mcbsp);
  665. reg_cache = mcbsp->reg_cache;
  666. spin_lock(&mcbsp->lock);
  667. if (mcbsp->free)
  668. dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
  669. else
  670. mcbsp->free = true;
  671. mcbsp->reg_cache = NULL;
  672. spin_unlock(&mcbsp->lock);
  673. if (reg_cache)
  674. kfree(reg_cache);
  675. }
  676. EXPORT_SYMBOL(omap_mcbsp_free);
  677. /*
  678. * Here we start the McBSP, by enabling transmitter, receiver or both.
  679. * If no transmitter or receiver is active prior calling, then sample-rate
  680. * generator and frame sync are started.
  681. */
  682. void omap_mcbsp_start(unsigned int id, int tx, int rx)
  683. {
  684. struct omap_mcbsp *mcbsp;
  685. int enable_srg = 0;
  686. u16 w;
  687. if (!omap_mcbsp_check_valid_id(id)) {
  688. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  689. return;
  690. }
  691. mcbsp = id_to_mcbsp_ptr(id);
  692. if (cpu_is_omap34xx())
  693. omap_st_start(mcbsp);
  694. /* Only enable SRG, if McBSP is master */
  695. w = MCBSP_READ_CACHE(mcbsp, PCR0);
  696. if (w & (FSXM | FSRM | CLKXM | CLKRM))
  697. enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
  698. MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
  699. if (enable_srg) {
  700. /* Start the sample generator */
  701. w = MCBSP_READ_CACHE(mcbsp, SPCR2);
  702. MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
  703. }
  704. /* Enable transmitter and receiver */
  705. tx &= 1;
  706. w = MCBSP_READ_CACHE(mcbsp, SPCR2);
  707. MCBSP_WRITE(mcbsp, SPCR2, w | tx);
  708. rx &= 1;
  709. w = MCBSP_READ_CACHE(mcbsp, SPCR1);
  710. MCBSP_WRITE(mcbsp, SPCR1, w | rx);
  711. /*
  712. * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
  713. * REVISIT: 100us may give enough time for two CLKSRG, however
  714. * due to some unknown PM related, clock gating etc. reason it
  715. * is now at 500us.
  716. */
  717. udelay(500);
  718. if (enable_srg) {
  719. /* Start frame sync */
  720. w = MCBSP_READ_CACHE(mcbsp, SPCR2);
  721. MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
  722. }
  723. if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
  724. /* Release the transmitter and receiver */
  725. w = MCBSP_READ_CACHE(mcbsp, XCCR);
  726. w &= ~(tx ? XDISABLE : 0);
  727. MCBSP_WRITE(mcbsp, XCCR, w);
  728. w = MCBSP_READ_CACHE(mcbsp, RCCR);
  729. w &= ~(rx ? RDISABLE : 0);
  730. MCBSP_WRITE(mcbsp, RCCR, w);
  731. }
  732. /* Dump McBSP Regs */
  733. omap_mcbsp_dump_reg(id);
  734. }
  735. EXPORT_SYMBOL(omap_mcbsp_start);
  736. void omap_mcbsp_stop(unsigned int id, int tx, int rx)
  737. {
  738. struct omap_mcbsp *mcbsp;
  739. int idle;
  740. u16 w;
  741. if (!omap_mcbsp_check_valid_id(id)) {
  742. printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
  743. return;
  744. }
  745. mcbsp = id_to_mcbsp_ptr(id);
  746. /* Reset transmitter */
  747. tx &= 1;
  748. if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
  749. w = MCBSP_READ_CACHE(mcbsp, XCCR);
  750. w |= (tx ? XDISABLE : 0);
  751. MCBSP_WRITE(mcbsp, XCCR, w);
  752. }
  753. w = MCBSP_READ_CACHE(mcbsp, SPCR2);
  754. MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
  755. /* Reset receiver */
  756. rx &= 1;
  757. if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
  758. w = MCBSP_READ_CACHE(mcbsp, RCCR);
  759. w |= (rx ? RDISABLE : 0);
  760. MCBSP_WRITE(mcbsp, RCCR, w);
  761. }
  762. w = MCBSP_READ_CACHE(mcbsp, SPCR1);
  763. MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
  764. idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
  765. MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
  766. if (idle) {
  767. /* Reset the sample rate generator */
  768. w = MCBSP_READ_CACHE(mcbsp, SPCR2);
  769. MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
  770. }
  771. if (cpu_is_omap34xx())
  772. omap_st_stop(mcbsp);
  773. }
  774. EXPORT_SYMBOL(omap_mcbsp_stop);
  775. /*
  776. * The following functions are only required on an OMAP1-only build.
  777. * mach-omap2/mcbsp.c contains the real functions
  778. */
  779. #ifndef CONFIG_ARCH_OMAP2PLUS
  780. int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
  781. {
  782. WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
  783. __func__);
  784. return -EINVAL;
  785. }
  786. void omap2_mcbsp1_mux_clkr_src(u8 mux)
  787. {
  788. WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
  789. __func__);
  790. return;
  791. }
  792. void omap2_mcbsp1_mux_fsr_src(u8 mux)
  793. {
  794. WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
  795. __func__);
  796. return;
  797. }
  798. #endif
  799. #ifdef CONFIG_ARCH_OMAP3
  800. #define max_thres(m) (mcbsp->pdata->buffer_size)
  801. #define valid_threshold(m, val) ((val) <= max_thres(m))
  802. #define THRESHOLD_PROP_BUILDER(prop) \
  803. static ssize_t prop##_show(struct device *dev, \
  804. struct device_attribute *attr, char *buf) \
  805. { \
  806. struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
  807. \
  808. return sprintf(buf, "%u\n", mcbsp->prop); \
  809. } \
  810. \
  811. static ssize_t prop##_store(struct device *dev, \
  812. struct device_attribute *attr, \
  813. const char *buf, size_t size) \
  814. { \
  815. struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
  816. unsigned long val; \
  817. int status; \
  818. \
  819. status = strict_strtoul(buf, 0, &val); \
  820. if (status) \
  821. return status; \
  822. \
  823. if (!valid_threshold(mcbsp, val)) \
  824. return -EDOM; \
  825. \
  826. mcbsp->prop = val; \
  827. return size; \
  828. } \
  829. \
  830. static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
  831. THRESHOLD_PROP_BUILDER(max_tx_thres);
  832. THRESHOLD_PROP_BUILDER(max_rx_thres);
  833. static const char *dma_op_modes[] = {
  834. "element", "threshold", "frame",
  835. };
  836. static ssize_t dma_op_mode_show(struct device *dev,
  837. struct device_attribute *attr, char *buf)
  838. {
  839. struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
  840. int dma_op_mode, i = 0;
  841. ssize_t len = 0;
  842. const char * const *s;
  843. dma_op_mode = mcbsp->dma_op_mode;
  844. for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
  845. if (dma_op_mode == i)
  846. len += sprintf(buf + len, "[%s] ", *s);
  847. else
  848. len += sprintf(buf + len, "%s ", *s);
  849. }
  850. len += sprintf(buf + len, "\n");
  851. return len;
  852. }
  853. static ssize_t dma_op_mode_store(struct device *dev,
  854. struct device_attribute *attr,
  855. const char *buf, size_t size)
  856. {
  857. struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
  858. const char * const *s;
  859. int i = 0;
  860. for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
  861. if (sysfs_streq(buf, *s))
  862. break;
  863. if (i == ARRAY_SIZE(dma_op_modes))
  864. return -EINVAL;
  865. spin_lock_irq(&mcbsp->lock);
  866. if (!mcbsp->free) {
  867. size = -EBUSY;
  868. goto unlock;
  869. }
  870. mcbsp->dma_op_mode = i;
  871. unlock:
  872. spin_unlock_irq(&mcbsp->lock);
  873. return size;
  874. }
  875. static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
  876. static ssize_t st_taps_show(struct device *dev,
  877. struct device_attribute *attr, char *buf)
  878. {
  879. struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
  880. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  881. ssize_t status = 0;
  882. int i;
  883. spin_lock_irq(&mcbsp->lock);
  884. for (i = 0; i < st_data->nr_taps; i++)
  885. status += sprintf(&buf[status], (i ? ", %d" : "%d"),
  886. st_data->taps[i]);
  887. if (i)
  888. status += sprintf(&buf[status], "\n");
  889. spin_unlock_irq(&mcbsp->lock);
  890. return status;
  891. }
  892. static ssize_t st_taps_store(struct device *dev,
  893. struct device_attribute *attr,
  894. const char *buf, size_t size)
  895. {
  896. struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
  897. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  898. int val, tmp, status, i = 0;
  899. spin_lock_irq(&mcbsp->lock);
  900. memset(st_data->taps, 0, sizeof(st_data->taps));
  901. st_data->nr_taps = 0;
  902. do {
  903. status = sscanf(buf, "%d%n", &val, &tmp);
  904. if (status < 0 || status == 0) {
  905. size = -EINVAL;
  906. goto out;
  907. }
  908. if (val < -32768 || val > 32767) {
  909. size = -EINVAL;
  910. goto out;
  911. }
  912. st_data->taps[i++] = val;
  913. buf += tmp;
  914. if (*buf != ',')
  915. break;
  916. buf++;
  917. } while (1);
  918. st_data->nr_taps = i;
  919. out:
  920. spin_unlock_irq(&mcbsp->lock);
  921. return size;
  922. }
  923. static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
  924. static const struct attribute *additional_attrs[] = {
  925. &dev_attr_max_tx_thres.attr,
  926. &dev_attr_max_rx_thres.attr,
  927. &dev_attr_dma_op_mode.attr,
  928. NULL,
  929. };
  930. static const struct attribute_group additional_attr_group = {
  931. .attrs = (struct attribute **)additional_attrs,
  932. };
  933. static inline int __devinit omap_additional_add(struct device *dev)
  934. {
  935. return sysfs_create_group(&dev->kobj, &additional_attr_group);
  936. }
  937. static inline void __devexit omap_additional_remove(struct device *dev)
  938. {
  939. sysfs_remove_group(&dev->kobj, &additional_attr_group);
  940. }
  941. static const struct attribute *sidetone_attrs[] = {
  942. &dev_attr_st_taps.attr,
  943. NULL,
  944. };
  945. static const struct attribute_group sidetone_attr_group = {
  946. .attrs = (struct attribute **)sidetone_attrs,
  947. };
  948. static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
  949. {
  950. struct platform_device *pdev;
  951. struct resource *res;
  952. struct omap_mcbsp_st_data *st_data;
  953. int err;
  954. st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
  955. if (!st_data) {
  956. err = -ENOMEM;
  957. goto err1;
  958. }
  959. pdev = container_of(mcbsp->dev, struct platform_device, dev);
  960. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
  961. st_data->io_base_st = ioremap(res->start, resource_size(res));
  962. if (!st_data->io_base_st) {
  963. err = -ENOMEM;
  964. goto err2;
  965. }
  966. err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
  967. if (err)
  968. goto err3;
  969. mcbsp->st_data = st_data;
  970. return 0;
  971. err3:
  972. iounmap(st_data->io_base_st);
  973. err2:
  974. kfree(st_data);
  975. err1:
  976. return err;
  977. }
  978. static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
  979. {
  980. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  981. if (st_data) {
  982. sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
  983. iounmap(st_data->io_base_st);
  984. kfree(st_data);
  985. }
  986. }
  987. static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
  988. {
  989. mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
  990. if (cpu_is_omap34xx()) {
  991. /*
  992. * Initially configure the maximum thresholds to a safe value.
  993. * The McBSP FIFO usage with these values should not go under
  994. * 16 locations.
  995. * If the whole FIFO without safety buffer is used, than there
  996. * is a possibility that the DMA will be not able to push the
  997. * new data on time, causing channel shifts in runtime.
  998. */
  999. mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
  1000. mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
  1001. /*
  1002. * REVISIT: Set dmap_op_mode to THRESHOLD as default
  1003. * for mcbsp2 instances.
  1004. */
  1005. if (omap_additional_add(mcbsp->dev))
  1006. dev_warn(mcbsp->dev,
  1007. "Unable to create additional controls\n");
  1008. if (mcbsp->id == 2 || mcbsp->id == 3)
  1009. if (omap_st_add(mcbsp))
  1010. dev_warn(mcbsp->dev,
  1011. "Unable to create sidetone controls\n");
  1012. } else {
  1013. mcbsp->max_tx_thres = -EINVAL;
  1014. mcbsp->max_rx_thres = -EINVAL;
  1015. }
  1016. }
  1017. static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
  1018. {
  1019. if (cpu_is_omap34xx()) {
  1020. omap_additional_remove(mcbsp->dev);
  1021. if (mcbsp->id == 2 || mcbsp->id == 3)
  1022. omap_st_remove(mcbsp);
  1023. }
  1024. }
  1025. #else
  1026. static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
  1027. static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
  1028. #endif /* CONFIG_ARCH_OMAP3 */
  1029. /*
  1030. * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
  1031. * 730 has only 2 McBSP, and both of them are MPU peripherals.
  1032. */
  1033. static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
  1034. {
  1035. struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
  1036. struct omap_mcbsp *mcbsp;
  1037. int id = pdev->id - 1;
  1038. struct resource *res;
  1039. int ret = 0;
  1040. if (!pdata) {
  1041. dev_err(&pdev->dev, "McBSP device initialized without"
  1042. "platform data\n");
  1043. ret = -EINVAL;
  1044. goto exit;
  1045. }
  1046. dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
  1047. if (id >= omap_mcbsp_count) {
  1048. dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
  1049. ret = -EINVAL;
  1050. goto exit;
  1051. }
  1052. mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
  1053. if (!mcbsp) {
  1054. ret = -ENOMEM;
  1055. goto exit;
  1056. }
  1057. spin_lock_init(&mcbsp->lock);
  1058. mcbsp->id = id + 1;
  1059. mcbsp->free = true;
  1060. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
  1061. if (!res) {
  1062. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1063. if (!res) {
  1064. dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
  1065. "resource\n", __func__, pdev->id);
  1066. ret = -ENOMEM;
  1067. goto exit;
  1068. }
  1069. }
  1070. mcbsp->phys_base = res->start;
  1071. omap_mcbsp_cache_size = resource_size(res);
  1072. mcbsp->io_base = ioremap(res->start, resource_size(res));
  1073. if (!mcbsp->io_base) {
  1074. ret = -ENOMEM;
  1075. goto err_ioremap;
  1076. }
  1077. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
  1078. if (!res)
  1079. mcbsp->phys_dma_base = mcbsp->phys_base;
  1080. else
  1081. mcbsp->phys_dma_base = res->start;
  1082. mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
  1083. mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
  1084. /* From OMAP4 there will be a single irq line */
  1085. if (mcbsp->tx_irq == -ENXIO)
  1086. mcbsp->tx_irq = platform_get_irq(pdev, 0);
  1087. res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
  1088. if (!res) {
  1089. dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
  1090. __func__, pdev->id);
  1091. ret = -ENODEV;
  1092. goto err_res;
  1093. }
  1094. mcbsp->dma_rx_sync = res->start;
  1095. res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
  1096. if (!res) {
  1097. dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
  1098. __func__, pdev->id);
  1099. ret = -ENODEV;
  1100. goto err_res;
  1101. }
  1102. mcbsp->dma_tx_sync = res->start;
  1103. mcbsp->fclk = clk_get(&pdev->dev, "fck");
  1104. if (IS_ERR(mcbsp->fclk)) {
  1105. ret = PTR_ERR(mcbsp->fclk);
  1106. dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
  1107. goto err_res;
  1108. }
  1109. mcbsp->pdata = pdata;
  1110. mcbsp->dev = &pdev->dev;
  1111. mcbsp_ptr[id] = mcbsp;
  1112. mcbsp->mcbsp_config_type = pdata->mcbsp_config_type;
  1113. platform_set_drvdata(pdev, mcbsp);
  1114. pm_runtime_enable(mcbsp->dev);
  1115. /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
  1116. omap34xx_device_init(mcbsp);
  1117. return 0;
  1118. err_res:
  1119. iounmap(mcbsp->io_base);
  1120. err_ioremap:
  1121. kfree(mcbsp);
  1122. exit:
  1123. return ret;
  1124. }
  1125. static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
  1126. {
  1127. struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
  1128. platform_set_drvdata(pdev, NULL);
  1129. if (mcbsp) {
  1130. if (mcbsp->pdata && mcbsp->pdata->ops &&
  1131. mcbsp->pdata->ops->free)
  1132. mcbsp->pdata->ops->free(mcbsp->id);
  1133. omap34xx_device_exit(mcbsp);
  1134. clk_put(mcbsp->fclk);
  1135. iounmap(mcbsp->io_base);
  1136. kfree(mcbsp);
  1137. }
  1138. return 0;
  1139. }
  1140. static struct platform_driver omap_mcbsp_driver = {
  1141. .probe = omap_mcbsp_probe,
  1142. .remove = __devexit_p(omap_mcbsp_remove),
  1143. .driver = {
  1144. .name = "omap-mcbsp",
  1145. },
  1146. };
  1147. int __init omap_mcbsp_init(void)
  1148. {
  1149. /* Register the McBSP driver */
  1150. return platform_driver_register(&omap_mcbsp_driver);
  1151. }