dsp_spos_scb_lib.c 48 KB

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  1. /*
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License as published by
  5. * the Free Software Foundation; either version 2 of the License, or
  6. * (at your option) any later version.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  16. *
  17. */
  18. /*
  19. * 2002-07 Benny Sjostrand benny@hostmobility.com
  20. */
  21. #include <sound/driver.h>
  22. #include <asm/io.h>
  23. #include <linux/delay.h>
  24. #include <linux/pm.h>
  25. #include <linux/init.h>
  26. #include <linux/slab.h>
  27. #include <linux/mutex.h>
  28. #include <sound/core.h>
  29. #include <sound/control.h>
  30. #include <sound/info.h>
  31. #include <sound/cs46xx.h>
  32. #include "cs46xx_lib.h"
  33. #include "dsp_spos.h"
  34. struct proc_scb_info {
  35. struct dsp_scb_descriptor * scb_desc;
  36. struct snd_cs46xx *chip;
  37. };
  38. static void remove_symbol (struct snd_cs46xx * chip, struct dsp_symbol_entry * symbol)
  39. {
  40. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  41. int symbol_index = (int)(symbol - ins->symbol_table.symbols);
  42. snd_assert(ins->symbol_table.nsymbols > 0,return);
  43. snd_assert(symbol_index >= 0 && symbol_index < ins->symbol_table.nsymbols, return);
  44. ins->symbol_table.symbols[symbol_index].deleted = 1;
  45. if (symbol_index < ins->symbol_table.highest_frag_index) {
  46. ins->symbol_table.highest_frag_index = symbol_index;
  47. }
  48. if (symbol_index == ins->symbol_table.nsymbols - 1)
  49. ins->symbol_table.nsymbols --;
  50. if (ins->symbol_table.highest_frag_index > ins->symbol_table.nsymbols) {
  51. ins->symbol_table.highest_frag_index = ins->symbol_table.nsymbols;
  52. }
  53. }
  54. #ifdef CONFIG_PROC_FS
  55. static void cs46xx_dsp_proc_scb_info_read (struct snd_info_entry *entry,
  56. struct snd_info_buffer *buffer)
  57. {
  58. struct proc_scb_info * scb_info = entry->private_data;
  59. struct dsp_scb_descriptor * scb = scb_info->scb_desc;
  60. struct dsp_spos_instance * ins;
  61. struct snd_cs46xx *chip = scb_info->chip;
  62. int j,col;
  63. void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
  64. ins = chip->dsp_spos_instance;
  65. mutex_lock(&chip->spos_mutex);
  66. snd_iprintf(buffer,"%04x %s:\n",scb->address,scb->scb_name);
  67. for (col = 0,j = 0;j < 0x10; j++,col++) {
  68. if (col == 4) {
  69. snd_iprintf(buffer,"\n");
  70. col = 0;
  71. }
  72. snd_iprintf(buffer,"%08x ",readl(dst + (scb->address + j) * sizeof(u32)));
  73. }
  74. snd_iprintf(buffer,"\n");
  75. if (scb->parent_scb_ptr != NULL) {
  76. snd_iprintf(buffer,"parent [%s:%04x] ",
  77. scb->parent_scb_ptr->scb_name,
  78. scb->parent_scb_ptr->address);
  79. } else snd_iprintf(buffer,"parent [none] ");
  80. snd_iprintf(buffer,"sub_list_ptr [%s:%04x]\nnext_scb_ptr [%s:%04x] task_entry [%s:%04x]\n",
  81. scb->sub_list_ptr->scb_name,
  82. scb->sub_list_ptr->address,
  83. scb->next_scb_ptr->scb_name,
  84. scb->next_scb_ptr->address,
  85. scb->task_entry->symbol_name,
  86. scb->task_entry->address);
  87. snd_iprintf(buffer,"index [%d] ref_count [%d]\n",scb->index,scb->ref_count);
  88. mutex_unlock(&chip->spos_mutex);
  89. }
  90. #endif
  91. static void _dsp_unlink_scb (struct snd_cs46xx *chip, struct dsp_scb_descriptor * scb)
  92. {
  93. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  94. unsigned long flags;
  95. if ( scb->parent_scb_ptr ) {
  96. /* unlink parent SCB */
  97. snd_assert ((scb->parent_scb_ptr->sub_list_ptr == scb ||
  98. scb->parent_scb_ptr->next_scb_ptr == scb),return);
  99. if (scb->parent_scb_ptr->sub_list_ptr == scb) {
  100. if (scb->next_scb_ptr == ins->the_null_scb) {
  101. /* last and only node in parent sublist */
  102. scb->parent_scb_ptr->sub_list_ptr = scb->sub_list_ptr;
  103. if (scb->sub_list_ptr != ins->the_null_scb) {
  104. scb->sub_list_ptr->parent_scb_ptr = scb->parent_scb_ptr;
  105. }
  106. scb->sub_list_ptr = ins->the_null_scb;
  107. } else {
  108. /* first node in parent sublist */
  109. scb->parent_scb_ptr->sub_list_ptr = scb->next_scb_ptr;
  110. if (scb->next_scb_ptr != ins->the_null_scb) {
  111. /* update next node parent ptr. */
  112. scb->next_scb_ptr->parent_scb_ptr = scb->parent_scb_ptr;
  113. }
  114. scb->next_scb_ptr = ins->the_null_scb;
  115. }
  116. } else {
  117. /* snd_assert ( (scb->sub_list_ptr == ins->the_null_scb), return); */
  118. scb->parent_scb_ptr->next_scb_ptr = scb->next_scb_ptr;
  119. if (scb->next_scb_ptr != ins->the_null_scb) {
  120. /* update next node parent ptr. */
  121. scb->next_scb_ptr->parent_scb_ptr = scb->parent_scb_ptr;
  122. }
  123. scb->next_scb_ptr = ins->the_null_scb;
  124. }
  125. spin_lock_irqsave(&chip->reg_lock, flags);
  126. /* update parent first entry in DSP RAM */
  127. cs46xx_dsp_spos_update_scb(chip,scb->parent_scb_ptr);
  128. /* then update entry in DSP RAM */
  129. cs46xx_dsp_spos_update_scb(chip,scb);
  130. scb->parent_scb_ptr = NULL;
  131. spin_unlock_irqrestore(&chip->reg_lock, flags);
  132. }
  133. }
  134. static void _dsp_clear_sample_buffer (struct snd_cs46xx *chip, u32 sample_buffer_addr,
  135. int dword_count)
  136. {
  137. void __iomem *dst = chip->region.idx[2].remap_addr + sample_buffer_addr;
  138. int i;
  139. for (i = 0; i < dword_count ; ++i ) {
  140. writel(0, dst);
  141. dst += 4;
  142. }
  143. }
  144. void cs46xx_dsp_remove_scb (struct snd_cs46xx *chip, struct dsp_scb_descriptor * scb)
  145. {
  146. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  147. unsigned long flags;
  148. /* check integrety */
  149. snd_assert ( (scb->index >= 0 &&
  150. scb->index < ins->nscb &&
  151. (ins->scbs + scb->index) == scb), return );
  152. #if 0
  153. /* can't remove a SCB with childs before
  154. removing childs first */
  155. snd_assert ( (scb->sub_list_ptr == ins->the_null_scb &&
  156. scb->next_scb_ptr == ins->the_null_scb),
  157. goto _end);
  158. #endif
  159. spin_lock_irqsave(&scb->lock, flags);
  160. _dsp_unlink_scb (chip,scb);
  161. spin_unlock_irqrestore(&scb->lock, flags);
  162. cs46xx_dsp_proc_free_scb_desc(scb);
  163. snd_assert (scb->scb_symbol != NULL, return );
  164. remove_symbol (chip,scb->scb_symbol);
  165. ins->scbs[scb->index].deleted = 1;
  166. if (scb->index < ins->scb_highest_frag_index)
  167. ins->scb_highest_frag_index = scb->index;
  168. if (scb->index == ins->nscb - 1) {
  169. ins->nscb --;
  170. }
  171. if (ins->scb_highest_frag_index > ins->nscb) {
  172. ins->scb_highest_frag_index = ins->nscb;
  173. }
  174. #if 0
  175. /* !!!! THIS IS A PIECE OF SHIT MADE BY ME !!! */
  176. for(i = scb->index + 1;i < ins->nscb; ++i) {
  177. ins->scbs[i - 1].index = i - 1;
  178. }
  179. #endif
  180. }
  181. #ifdef CONFIG_PROC_FS
  182. void cs46xx_dsp_proc_free_scb_desc (struct dsp_scb_descriptor * scb)
  183. {
  184. if (scb->proc_info) {
  185. struct proc_scb_info * scb_info = scb->proc_info->private_data;
  186. snd_printdd("cs46xx_dsp_proc_free_scb_desc: freeing %s\n",scb->scb_name);
  187. snd_info_free_entry(scb->proc_info);
  188. scb->proc_info = NULL;
  189. snd_assert (scb_info != NULL, return);
  190. kfree (scb_info);
  191. }
  192. }
  193. void cs46xx_dsp_proc_register_scb_desc (struct snd_cs46xx *chip,
  194. struct dsp_scb_descriptor * scb)
  195. {
  196. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  197. struct snd_info_entry * entry;
  198. struct proc_scb_info * scb_info;
  199. /* register to proc */
  200. if (ins->snd_card != NULL && ins->proc_dsp_dir != NULL &&
  201. scb->proc_info == NULL) {
  202. if ((entry = snd_info_create_card_entry(ins->snd_card, scb->scb_name,
  203. ins->proc_dsp_dir)) != NULL) {
  204. scb_info = kmalloc(sizeof(struct proc_scb_info), GFP_KERNEL);
  205. if (!scb_info) {
  206. snd_info_free_entry(entry);
  207. entry = NULL;
  208. goto out;
  209. }
  210. scb_info->chip = chip;
  211. scb_info->scb_desc = scb;
  212. entry->content = SNDRV_INFO_CONTENT_TEXT;
  213. entry->private_data = scb_info;
  214. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  215. entry->c.text.read = cs46xx_dsp_proc_scb_info_read;
  216. if (snd_info_register(entry) < 0) {
  217. snd_info_free_entry(entry);
  218. kfree (scb_info);
  219. entry = NULL;
  220. }
  221. }
  222. out:
  223. scb->proc_info = entry;
  224. }
  225. }
  226. #endif /* CONFIG_PROC_FS */
  227. static struct dsp_scb_descriptor *
  228. _dsp_create_generic_scb (struct snd_cs46xx *chip, char * name, u32 * scb_data, u32 dest,
  229. struct dsp_symbol_entry * task_entry,
  230. struct dsp_scb_descriptor * parent_scb,
  231. int scb_child_type)
  232. {
  233. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  234. struct dsp_scb_descriptor * scb;
  235. unsigned long flags;
  236. snd_assert (ins->the_null_scb != NULL,return NULL);
  237. /* fill the data that will be wroten to DSP */
  238. scb_data[SCBsubListPtr] =
  239. (ins->the_null_scb->address << 0x10) | ins->the_null_scb->address;
  240. scb_data[SCBfuncEntryPtr] &= 0xFFFF0000;
  241. scb_data[SCBfuncEntryPtr] |= task_entry->address;
  242. snd_printdd("dsp_spos: creating SCB <%s>\n",name);
  243. scb = cs46xx_dsp_create_scb(chip,name,scb_data,dest);
  244. scb->sub_list_ptr = ins->the_null_scb;
  245. scb->next_scb_ptr = ins->the_null_scb;
  246. scb->parent_scb_ptr = parent_scb;
  247. scb->task_entry = task_entry;
  248. /* update parent SCB */
  249. if (scb->parent_scb_ptr) {
  250. #if 0
  251. printk ("scb->parent_scb_ptr = %s\n",scb->parent_scb_ptr->scb_name);
  252. printk ("scb->parent_scb_ptr->next_scb_ptr = %s\n",scb->parent_scb_ptr->next_scb_ptr->scb_name);
  253. printk ("scb->parent_scb_ptr->sub_list_ptr = %s\n",scb->parent_scb_ptr->sub_list_ptr->scb_name);
  254. #endif
  255. /* link to parent SCB */
  256. if (scb_child_type == SCB_ON_PARENT_NEXT_SCB) {
  257. snd_assert ( (scb->parent_scb_ptr->next_scb_ptr == ins->the_null_scb),
  258. return NULL);
  259. scb->parent_scb_ptr->next_scb_ptr = scb;
  260. } else if (scb_child_type == SCB_ON_PARENT_SUBLIST_SCB) {
  261. snd_assert ( (scb->parent_scb_ptr->sub_list_ptr == ins->the_null_scb),
  262. return NULL);
  263. scb->parent_scb_ptr->sub_list_ptr = scb;
  264. } else {
  265. snd_assert (0,return NULL);
  266. }
  267. spin_lock_irqsave(&chip->reg_lock, flags);
  268. /* update entry in DSP RAM */
  269. cs46xx_dsp_spos_update_scb(chip,scb->parent_scb_ptr);
  270. spin_unlock_irqrestore(&chip->reg_lock, flags);
  271. }
  272. cs46xx_dsp_proc_register_scb_desc (chip,scb);
  273. return scb;
  274. }
  275. static struct dsp_scb_descriptor *
  276. cs46xx_dsp_create_generic_scb (struct snd_cs46xx *chip, char * name, u32 * scb_data,
  277. u32 dest, char * task_entry_name,
  278. struct dsp_scb_descriptor * parent_scb,
  279. int scb_child_type)
  280. {
  281. struct dsp_symbol_entry * task_entry;
  282. task_entry = cs46xx_dsp_lookup_symbol (chip,task_entry_name,
  283. SYMBOL_CODE);
  284. if (task_entry == NULL) {
  285. snd_printk (KERN_ERR "dsp_spos: symbol %s not found\n",task_entry_name);
  286. return NULL;
  287. }
  288. return _dsp_create_generic_scb (chip,name,scb_data,dest,task_entry,
  289. parent_scb,scb_child_type);
  290. }
  291. struct dsp_scb_descriptor *
  292. cs46xx_dsp_create_timing_master_scb (struct snd_cs46xx *chip)
  293. {
  294. struct dsp_scb_descriptor * scb;
  295. struct dsp_timing_master_scb timing_master_scb = {
  296. { 0,
  297. 0,
  298. 0,
  299. 0
  300. },
  301. { 0,
  302. 0,
  303. 0,
  304. 0,
  305. 0
  306. },
  307. 0,0,
  308. 0,NULL_SCB_ADDR,
  309. 0,0, /* extraSampleAccum:TMreserved */
  310. 0,0, /* codecFIFOptr:codecFIFOsyncd */
  311. 0x0001,0x8000, /* fracSampAccumQm1:TMfrmsLeftInGroup */
  312. 0x0001,0x0000, /* fracSampCorrectionQm1:TMfrmGroupLength */
  313. 0x00060000 /* nSampPerFrmQ15 */
  314. };
  315. scb = cs46xx_dsp_create_generic_scb(chip,"TimingMasterSCBInst",(u32 *)&timing_master_scb,
  316. TIMINGMASTER_SCB_ADDR,
  317. "TIMINGMASTER",NULL,SCB_NO_PARENT);
  318. return scb;
  319. }
  320. struct dsp_scb_descriptor *
  321. cs46xx_dsp_create_codec_out_scb(struct snd_cs46xx * chip, char * codec_name,
  322. u16 channel_disp, u16 fifo_addr, u16 child_scb_addr,
  323. u32 dest, struct dsp_scb_descriptor * parent_scb,
  324. int scb_child_type)
  325. {
  326. struct dsp_scb_descriptor * scb;
  327. struct dsp_codec_output_scb codec_out_scb = {
  328. { 0,
  329. 0,
  330. 0,
  331. 0
  332. },
  333. {
  334. 0,
  335. 0,
  336. 0,
  337. 0,
  338. 0
  339. },
  340. 0,0,
  341. 0,NULL_SCB_ADDR,
  342. 0, /* COstrmRsConfig */
  343. 0, /* COstrmBufPtr */
  344. channel_disp,fifo_addr, /* leftChanBaseIOaddr:rightChanIOdisp */
  345. 0x0000,0x0080, /* (!AC97!) COexpVolChangeRate:COscaleShiftCount */
  346. 0,child_scb_addr /* COreserved - need child scb to work with rom code */
  347. };
  348. scb = cs46xx_dsp_create_generic_scb(chip,codec_name,(u32 *)&codec_out_scb,
  349. dest,"S16_CODECOUTPUTTASK",parent_scb,
  350. scb_child_type);
  351. return scb;
  352. }
  353. struct dsp_scb_descriptor *
  354. cs46xx_dsp_create_codec_in_scb(struct snd_cs46xx * chip, char * codec_name,
  355. u16 channel_disp, u16 fifo_addr, u16 sample_buffer_addr,
  356. u32 dest, struct dsp_scb_descriptor * parent_scb,
  357. int scb_child_type)
  358. {
  359. struct dsp_scb_descriptor * scb;
  360. struct dsp_codec_input_scb codec_input_scb = {
  361. { 0,
  362. 0,
  363. 0,
  364. 0
  365. },
  366. {
  367. 0,
  368. 0,
  369. 0,
  370. 0,
  371. 0
  372. },
  373. #if 0 /* cs4620 */
  374. SyncIOSCB,NULL_SCB_ADDR
  375. #else
  376. 0 , 0,
  377. #endif
  378. 0,0,
  379. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64, /* strmRsConfig */
  380. sample_buffer_addr << 0x10, /* strmBufPtr; defined as a dword ptr, used as a byte ptr */
  381. channel_disp,fifo_addr, /* (!AC97!) leftChanBaseINaddr=AC97primary
  382. link input slot 3 :rightChanINdisp=""slot 4 */
  383. 0x0000,0x0000, /* (!AC97!) ????:scaleShiftCount; no shift needed
  384. because AC97 is already 20 bits */
  385. 0x80008000 /* ??clw cwcgame.scb has 0 */
  386. };
  387. scb = cs46xx_dsp_create_generic_scb(chip,codec_name,(u32 *)&codec_input_scb,
  388. dest,"S16_CODECINPUTTASK",parent_scb,
  389. scb_child_type);
  390. return scb;
  391. }
  392. static struct dsp_scb_descriptor *
  393. cs46xx_dsp_create_pcm_reader_scb(struct snd_cs46xx * chip, char * scb_name,
  394. u16 sample_buffer_addr, u32 dest,
  395. int virtual_channel, u32 playback_hw_addr,
  396. struct dsp_scb_descriptor * parent_scb,
  397. int scb_child_type)
  398. {
  399. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  400. struct dsp_scb_descriptor * scb;
  401. struct dsp_generic_scb pcm_reader_scb = {
  402. /*
  403. Play DMA Task xfers data from host buffer to SP buffer
  404. init/runtime variables:
  405. PlayAC: Play Audio Data Conversion - SCB loc: 2nd dword, mask: 0x0000F000L
  406. DATA_FMT_16BIT_ST_LTLEND(0x00000000L) from 16-bit stereo, little-endian
  407. DATA_FMT_8_BIT_ST_SIGNED(0x00001000L) from 8-bit stereo, signed
  408. DATA_FMT_16BIT_MN_LTLEND(0x00002000L) from 16-bit mono, little-endian
  409. DATA_FMT_8_BIT_MN_SIGNED(0x00003000L) from 8-bit mono, signed
  410. DATA_FMT_16BIT_ST_BIGEND(0x00004000L) from 16-bit stereo, big-endian
  411. DATA_FMT_16BIT_MN_BIGEND(0x00006000L) from 16-bit mono, big-endian
  412. DATA_FMT_8_BIT_ST_UNSIGNED(0x00009000L) from 8-bit stereo, unsigned
  413. DATA_FMT_8_BIT_MN_UNSIGNED(0x0000b000L) from 8-bit mono, unsigned
  414. ? Other combinations possible from:
  415. DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000L
  416. DMA_RQ_C2_AC_NONE 0x00000000L
  417. DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000L
  418. DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000L
  419. DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000L
  420. DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000L
  421. HostBuffAddr: Host Buffer Physical Byte Address - SCB loc:3rd dword, Mask: 0xFFFFFFFFL
  422. aligned to dword boundary
  423. */
  424. /* Basic (non scatter/gather) DMA requestor (4 ints) */
  425. { DMA_RQ_C1_SOURCE_ON_HOST + /* source buffer is on the host */
  426. DMA_RQ_C1_SOURCE_MOD1024 + /* source buffer is 1024 dwords (4096 bytes) */
  427. DMA_RQ_C1_DEST_MOD32 + /* dest buffer(PCMreaderBuf) is 32 dwords*/
  428. DMA_RQ_C1_WRITEBACK_SRC_FLAG + /* ?? */
  429. DMA_RQ_C1_WRITEBACK_DEST_FLAG + /* ?? */
  430. 15, /* DwordCount-1: picked 16 for DwordCount because Jim */
  431. /* Barnette said that is what we should use since */
  432. /* we are not running in optimized mode? */
  433. DMA_RQ_C2_AC_NONE +
  434. DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG + /* set play interrupt (bit0) in HISR when source */
  435. /* buffer (on host) crosses half-way point */
  436. virtual_channel, /* Play DMA channel arbitrarily set to 0 */
  437. playback_hw_addr, /* HostBuffAddr (source) */
  438. DMA_RQ_SD_SP_SAMPLE_ADDR + /* destination buffer is in SP Sample Memory */
  439. sample_buffer_addr /* SP Buffer Address (destination) */
  440. },
  441. /* Scatter/gather DMA requestor extension (5 ints) */
  442. {
  443. 0,
  444. 0,
  445. 0,
  446. 0,
  447. 0
  448. },
  449. /* Sublist pointer & next stream control block (SCB) link. */
  450. NULL_SCB_ADDR,NULL_SCB_ADDR,
  451. /* Pointer to this tasks parameter block & stream function pointer */
  452. 0,NULL_SCB_ADDR,
  453. /* rsConfig register for stream buffer (rsDMA reg. is loaded from basicReq.daw */
  454. /* for incoming streams, or basicReq.saw, for outgoing streams) */
  455. RSCONFIG_DMA_ENABLE + /* enable DMA */
  456. (19 << RSCONFIG_MAX_DMA_SIZE_SHIFT) + /* MAX_DMA_SIZE picked to be 19 since SPUD */
  457. /* uses it for some reason */
  458. ((dest >> 4) << RSCONFIG_STREAM_NUM_SHIFT) + /* stream number = SCBaddr/16 */
  459. RSCONFIG_SAMPLE_16STEREO +
  460. RSCONFIG_MODULO_32, /* dest buffer(PCMreaderBuf) is 32 dwords (256 bytes) */
  461. /* Stream sample pointer & MAC-unit mode for this stream */
  462. (sample_buffer_addr << 0x10),
  463. /* Fractional increment per output sample in the input sample buffer */
  464. 0,
  465. {
  466. /* Standard stereo volume control
  467. default muted */
  468. 0xffff,0xffff,
  469. 0xffff,0xffff
  470. }
  471. };
  472. if (ins->null_algorithm == NULL) {
  473. ins->null_algorithm = cs46xx_dsp_lookup_symbol (chip,"NULLALGORITHM",
  474. SYMBOL_CODE);
  475. if (ins->null_algorithm == NULL) {
  476. snd_printk (KERN_ERR "dsp_spos: symbol NULLALGORITHM not found\n");
  477. return NULL;
  478. }
  479. }
  480. scb = _dsp_create_generic_scb(chip,scb_name,(u32 *)&pcm_reader_scb,
  481. dest,ins->null_algorithm,parent_scb,
  482. scb_child_type);
  483. return scb;
  484. }
  485. #define GOF_PER_SEC 200
  486. struct dsp_scb_descriptor *
  487. cs46xx_dsp_create_src_task_scb(struct snd_cs46xx * chip, char * scb_name,
  488. int rate,
  489. u16 src_buffer_addr,
  490. u16 src_delay_buffer_addr, u32 dest,
  491. struct dsp_scb_descriptor * parent_scb,
  492. int scb_child_type,
  493. int pass_through)
  494. {
  495. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  496. struct dsp_scb_descriptor * scb;
  497. unsigned int tmp1, tmp2;
  498. unsigned int phiIncr;
  499. unsigned int correctionPerGOF, correctionPerSec;
  500. snd_printdd( "dsp_spos: setting %s rate to %u\n",scb_name,rate);
  501. /*
  502. * Compute the values used to drive the actual sample rate conversion.
  503. * The following formulas are being computed, using inline assembly
  504. * since we need to use 64 bit arithmetic to compute the values:
  505. *
  506. * phiIncr = floor((Fs,in * 2^26) / Fs,out)
  507. * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
  508. * GOF_PER_SEC)
  509. * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
  510. * GOF_PER_SEC * correctionPerGOF
  511. *
  512. * i.e.
  513. *
  514. * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
  515. * correctionPerGOF:correctionPerSec =
  516. * dividend:remainder(ulOther / GOF_PER_SEC)
  517. */
  518. tmp1 = rate << 16;
  519. phiIncr = tmp1 / 48000;
  520. tmp1 -= phiIncr * 48000;
  521. tmp1 <<= 10;
  522. phiIncr <<= 10;
  523. tmp2 = tmp1 / 48000;
  524. phiIncr += tmp2;
  525. tmp1 -= tmp2 * 48000;
  526. correctionPerGOF = tmp1 / GOF_PER_SEC;
  527. tmp1 -= correctionPerGOF * GOF_PER_SEC;
  528. correctionPerSec = tmp1;
  529. {
  530. struct dsp_src_task_scb src_task_scb = {
  531. 0x0028,0x00c8,
  532. 0x5555,0x0000,
  533. 0x0000,0x0000,
  534. src_buffer_addr,1,
  535. correctionPerGOF,correctionPerSec,
  536. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_32,
  537. 0x0000,src_delay_buffer_addr,
  538. 0x0,
  539. 0x080,(src_delay_buffer_addr + (24 * 4)),
  540. 0,0, /* next_scb, sub_list_ptr */
  541. 0,0, /* entry, this_spb */
  542. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_8,
  543. src_buffer_addr << 0x10,
  544. phiIncr,
  545. {
  546. 0xffff - ins->dac_volume_right,0xffff - ins->dac_volume_left,
  547. 0xffff - ins->dac_volume_right,0xffff - ins->dac_volume_left
  548. }
  549. };
  550. if (ins->s16_up == NULL) {
  551. ins->s16_up = cs46xx_dsp_lookup_symbol (chip,"S16_UPSRC",
  552. SYMBOL_CODE);
  553. if (ins->s16_up == NULL) {
  554. snd_printk (KERN_ERR "dsp_spos: symbol S16_UPSRC not found\n");
  555. return NULL;
  556. }
  557. }
  558. /* clear buffers */
  559. _dsp_clear_sample_buffer (chip,src_buffer_addr,8);
  560. _dsp_clear_sample_buffer (chip,src_delay_buffer_addr,32);
  561. if (pass_through) {
  562. /* wont work with any other rate than
  563. the native DSP rate */
  564. snd_assert (rate == 48000);
  565. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&src_task_scb,
  566. dest,"DMAREADER",parent_scb,
  567. scb_child_type);
  568. } else {
  569. scb = _dsp_create_generic_scb(chip,scb_name,(u32 *)&src_task_scb,
  570. dest,ins->s16_up,parent_scb,
  571. scb_child_type);
  572. }
  573. }
  574. return scb;
  575. }
  576. #if 0 /* not used */
  577. struct dsp_scb_descriptor *
  578. cs46xx_dsp_create_filter_scb(struct snd_cs46xx * chip, char * scb_name,
  579. u16 buffer_addr, u32 dest,
  580. struct dsp_scb_descriptor * parent_scb,
  581. int scb_child_type) {
  582. struct dsp_scb_descriptor * scb;
  583. struct dsp_filter_scb filter_scb = {
  584. .a0_right = 0x41a9,
  585. .a0_left = 0x41a9,
  586. .a1_right = 0xb8e4,
  587. .a1_left = 0xb8e4,
  588. .a2_right = 0x3e55,
  589. .a2_left = 0x3e55,
  590. .filter_unused3 = 0x0000,
  591. .filter_unused2 = 0x0000,
  592. .output_buf_ptr = buffer_addr,
  593. .init = 0x000,
  594. .prev_sample_output1 = 0x00000000,
  595. .prev_sample_output2 = 0x00000000,
  596. .prev_sample_input1 = 0x00000000,
  597. .prev_sample_input2 = 0x00000000,
  598. .next_scb_ptr = 0x0000,
  599. .sub_list_ptr = 0x0000,
  600. .entry_point = 0x0000,
  601. .spb_ptr = 0x0000,
  602. .b0_right = 0x0e38,
  603. .b0_left = 0x0e38,
  604. .b1_right = 0x1c71,
  605. .b1_left = 0x1c71,
  606. .b2_right = 0x0e38,
  607. .b2_left = 0x0e38,
  608. };
  609. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&filter_scb,
  610. dest,"FILTERTASK",parent_scb,
  611. scb_child_type);
  612. return scb;
  613. }
  614. #endif /* not used */
  615. struct dsp_scb_descriptor *
  616. cs46xx_dsp_create_mix_only_scb(struct snd_cs46xx * chip, char * scb_name,
  617. u16 mix_buffer_addr, u32 dest,
  618. struct dsp_scb_descriptor * parent_scb,
  619. int scb_child_type)
  620. {
  621. struct dsp_scb_descriptor * scb;
  622. struct dsp_mix_only_scb master_mix_scb = {
  623. /* 0 */ { 0,
  624. /* 1 */ 0,
  625. /* 2 */ mix_buffer_addr,
  626. /* 3 */ 0
  627. /* */ },
  628. {
  629. /* 4 */ 0,
  630. /* 5 */ 0,
  631. /* 6 */ 0,
  632. /* 7 */ 0,
  633. /* 8 */ 0x00000080
  634. },
  635. /* 9 */ 0,0,
  636. /* A */ 0,0,
  637. /* B */ RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_32,
  638. /* C */ (mix_buffer_addr + (16 * 4)) << 0x10,
  639. /* D */ 0,
  640. {
  641. /* E */ 0x8000,0x8000,
  642. /* F */ 0x8000,0x8000
  643. }
  644. };
  645. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&master_mix_scb,
  646. dest,"S16_MIX",parent_scb,
  647. scb_child_type);
  648. return scb;
  649. }
  650. struct dsp_scb_descriptor *
  651. cs46xx_dsp_create_mix_to_ostream_scb(struct snd_cs46xx * chip, char * scb_name,
  652. u16 mix_buffer_addr, u16 writeback_spb, u32 dest,
  653. struct dsp_scb_descriptor * parent_scb,
  654. int scb_child_type)
  655. {
  656. struct dsp_scb_descriptor * scb;
  657. struct dsp_mix2_ostream_scb mix2_ostream_scb = {
  658. /* Basic (non scatter/gather) DMA requestor (4 ints) */
  659. {
  660. DMA_RQ_C1_SOURCE_MOD64 +
  661. DMA_RQ_C1_DEST_ON_HOST +
  662. DMA_RQ_C1_DEST_MOD1024 +
  663. DMA_RQ_C1_WRITEBACK_SRC_FLAG +
  664. DMA_RQ_C1_WRITEBACK_DEST_FLAG +
  665. 15,
  666. DMA_RQ_C2_AC_NONE +
  667. DMA_RQ_C2_SIGNAL_DEST_PINGPONG +
  668. CS46XX_DSP_CAPTURE_CHANNEL,
  669. DMA_RQ_SD_SP_SAMPLE_ADDR +
  670. mix_buffer_addr,
  671. 0x0
  672. },
  673. { 0, 0, 0, 0, 0, },
  674. 0,0,
  675. 0,writeback_spb,
  676. RSCONFIG_DMA_ENABLE +
  677. (19 << RSCONFIG_MAX_DMA_SIZE_SHIFT) +
  678. ((dest >> 4) << RSCONFIG_STREAM_NUM_SHIFT) +
  679. RSCONFIG_DMA_TO_HOST +
  680. RSCONFIG_SAMPLE_16STEREO +
  681. RSCONFIG_MODULO_64,
  682. (mix_buffer_addr + (32 * 4)) << 0x10,
  683. 1,0,
  684. 0x0001,0x0080,
  685. 0xFFFF,0
  686. };
  687. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&mix2_ostream_scb,
  688. dest,"S16_MIX_TO_OSTREAM",parent_scb,
  689. scb_child_type);
  690. return scb;
  691. }
  692. struct dsp_scb_descriptor *
  693. cs46xx_dsp_create_vari_decimate_scb(struct snd_cs46xx * chip,char * scb_name,
  694. u16 vari_buffer_addr0,
  695. u16 vari_buffer_addr1,
  696. u32 dest,
  697. struct dsp_scb_descriptor * parent_scb,
  698. int scb_child_type)
  699. {
  700. struct dsp_scb_descriptor * scb;
  701. struct dsp_vari_decimate_scb vari_decimate_scb = {
  702. 0x0028,0x00c8,
  703. 0x5555,0x0000,
  704. 0x0000,0x0000,
  705. vari_buffer_addr0,vari_buffer_addr1,
  706. 0x0028,0x00c8,
  707. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_256,
  708. 0xFF800000,
  709. 0,
  710. 0x0080,vari_buffer_addr1 + (25 * 4),
  711. 0,0,
  712. 0,0,
  713. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_8,
  714. vari_buffer_addr0 << 0x10,
  715. 0x04000000,
  716. {
  717. 0x8000,0x8000,
  718. 0xFFFF,0xFFFF
  719. }
  720. };
  721. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&vari_decimate_scb,
  722. dest,"VARIDECIMATE",parent_scb,
  723. scb_child_type);
  724. return scb;
  725. }
  726. static struct dsp_scb_descriptor *
  727. cs46xx_dsp_create_pcm_serial_input_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  728. struct dsp_scb_descriptor * input_scb,
  729. struct dsp_scb_descriptor * parent_scb,
  730. int scb_child_type)
  731. {
  732. struct dsp_scb_descriptor * scb;
  733. struct dsp_pcm_serial_input_scb pcm_serial_input_scb = {
  734. { 0,
  735. 0,
  736. 0,
  737. 0
  738. },
  739. {
  740. 0,
  741. 0,
  742. 0,
  743. 0,
  744. 0
  745. },
  746. 0,0,
  747. 0,0,
  748. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_16,
  749. 0,
  750. /* 0xD */ 0,input_scb->address,
  751. {
  752. /* 0xE */ 0x8000,0x8000,
  753. /* 0xF */ 0x8000,0x8000
  754. }
  755. };
  756. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&pcm_serial_input_scb,
  757. dest,"PCMSERIALINPUTTASK",parent_scb,
  758. scb_child_type);
  759. return scb;
  760. }
  761. static struct dsp_scb_descriptor *
  762. cs46xx_dsp_create_asynch_fg_tx_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  763. u16 hfg_scb_address,
  764. u16 asynch_buffer_address,
  765. struct dsp_scb_descriptor * parent_scb,
  766. int scb_child_type)
  767. {
  768. struct dsp_scb_descriptor * scb;
  769. struct dsp_asynch_fg_tx_scb asynch_fg_tx_scb = {
  770. 0xfc00,0x03ff, /* Prototype sample buffer size of 256 dwords */
  771. 0x0058,0x0028, /* Min Delta 7 dwords == 28 bytes */
  772. /* : Max delta 25 dwords == 100 bytes */
  773. 0,hfg_scb_address, /* Point to HFG task SCB */
  774. 0,0, /* Initialize current Delta and Consumer ptr adjustment count */
  775. 0, /* Initialize accumulated Phi to 0 */
  776. 0,0x2aab, /* Const 1/3 */
  777. {
  778. 0, /* Define the unused elements */
  779. 0,
  780. 0
  781. },
  782. 0,0,
  783. 0,dest + AFGTxAccumPhi,
  784. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_256, /* Stereo, 256 dword */
  785. (asynch_buffer_address) << 0x10, /* This should be automagically synchronized
  786. to the producer pointer */
  787. /* There is no correct initial value, it will depend upon the detected
  788. rate etc */
  789. 0x18000000, /* Phi increment for approx 32k operation */
  790. 0x8000,0x8000, /* Volume controls are unused at this time */
  791. 0x8000,0x8000
  792. };
  793. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&asynch_fg_tx_scb,
  794. dest,"ASYNCHFGTXCODE",parent_scb,
  795. scb_child_type);
  796. return scb;
  797. }
  798. struct dsp_scb_descriptor *
  799. cs46xx_dsp_create_asynch_fg_rx_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  800. u16 hfg_scb_address,
  801. u16 asynch_buffer_address,
  802. struct dsp_scb_descriptor * parent_scb,
  803. int scb_child_type)
  804. {
  805. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  806. struct dsp_scb_descriptor * scb;
  807. struct dsp_asynch_fg_rx_scb asynch_fg_rx_scb = {
  808. 0xfe00,0x01ff, /* Prototype sample buffer size of 128 dwords */
  809. 0x0064,0x001c, /* Min Delta 7 dwords == 28 bytes */
  810. /* : Max delta 25 dwords == 100 bytes */
  811. 0,hfg_scb_address, /* Point to HFG task SCB */
  812. 0,0, /* Initialize current Delta and Consumer ptr adjustment count */
  813. {
  814. 0, /* Define the unused elements */
  815. 0,
  816. 0,
  817. 0,
  818. 0
  819. },
  820. 0,0,
  821. 0,dest,
  822. RSCONFIG_MODULO_128 |
  823. RSCONFIG_SAMPLE_16STEREO, /* Stereo, 128 dword */
  824. ( (asynch_buffer_address + (16 * 4)) << 0x10), /* This should be automagically
  825. synchrinized to the producer pointer */
  826. /* There is no correct initial value, it will depend upon the detected
  827. rate etc */
  828. 0x18000000,
  829. /* Set IEC958 input volume */
  830. 0xffff - ins->spdif_input_volume_right,0xffff - ins->spdif_input_volume_left,
  831. 0xffff - ins->spdif_input_volume_right,0xffff - ins->spdif_input_volume_left,
  832. };
  833. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&asynch_fg_rx_scb,
  834. dest,"ASYNCHFGRXCODE",parent_scb,
  835. scb_child_type);
  836. return scb;
  837. }
  838. #if 0 /* not used */
  839. struct dsp_scb_descriptor *
  840. cs46xx_dsp_create_output_snoop_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  841. u16 snoop_buffer_address,
  842. struct dsp_scb_descriptor * snoop_scb,
  843. struct dsp_scb_descriptor * parent_scb,
  844. int scb_child_type)
  845. {
  846. struct dsp_scb_descriptor * scb;
  847. struct dsp_output_snoop_scb output_snoop_scb = {
  848. { 0, /* not used. Zero */
  849. 0,
  850. 0,
  851. 0,
  852. },
  853. {
  854. 0, /* not used. Zero */
  855. 0,
  856. 0,
  857. 0,
  858. 0
  859. },
  860. 0,0,
  861. 0,0,
  862. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64,
  863. snoop_buffer_address << 0x10,
  864. 0,0,
  865. 0,
  866. 0,snoop_scb->address
  867. };
  868. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&output_snoop_scb,
  869. dest,"OUTPUTSNOOP",parent_scb,
  870. scb_child_type);
  871. return scb;
  872. }
  873. #endif /* not used */
  874. struct dsp_scb_descriptor *
  875. cs46xx_dsp_create_spio_write_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  876. struct dsp_scb_descriptor * parent_scb,
  877. int scb_child_type)
  878. {
  879. struct dsp_scb_descriptor * scb;
  880. struct dsp_spio_write_scb spio_write_scb = {
  881. 0,0, /* SPIOWAddress2:SPIOWAddress1; */
  882. 0, /* SPIOWData1; */
  883. 0, /* SPIOWData2; */
  884. 0,0, /* SPIOWAddress4:SPIOWAddress3; */
  885. 0, /* SPIOWData3; */
  886. 0, /* SPIOWData4; */
  887. 0,0, /* SPIOWDataPtr:Unused1; */
  888. { 0,0 }, /* Unused2[2]; */
  889. 0,0, /* SPIOWChildPtr:SPIOWSiblingPtr; */
  890. 0,0, /* SPIOWThisPtr:SPIOWEntryPoint; */
  891. {
  892. 0,
  893. 0,
  894. 0,
  895. 0,
  896. 0 /* Unused3[5]; */
  897. }
  898. };
  899. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&spio_write_scb,
  900. dest,"SPIOWRITE",parent_scb,
  901. scb_child_type);
  902. return scb;
  903. }
  904. struct dsp_scb_descriptor *
  905. cs46xx_dsp_create_magic_snoop_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  906. u16 snoop_buffer_address,
  907. struct dsp_scb_descriptor * snoop_scb,
  908. struct dsp_scb_descriptor * parent_scb,
  909. int scb_child_type)
  910. {
  911. struct dsp_scb_descriptor * scb;
  912. struct dsp_magic_snoop_task magic_snoop_scb = {
  913. /* 0 */ 0, /* i0 */
  914. /* 1 */ 0, /* i1 */
  915. /* 2 */ snoop_buffer_address << 0x10,
  916. /* 3 */ 0,snoop_scb->address,
  917. /* 4 */ 0, /* i3 */
  918. /* 5 */ 0, /* i4 */
  919. /* 6 */ 0, /* i5 */
  920. /* 7 */ 0, /* i6 */
  921. /* 8 */ 0, /* i7 */
  922. /* 9 */ 0,0, /* next_scb, sub_list_ptr */
  923. /* A */ 0,0, /* entry_point, this_ptr */
  924. /* B */ RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64,
  925. /* C */ snoop_buffer_address << 0x10,
  926. /* D */ 0,
  927. /* E */ { 0x8000,0x8000,
  928. /* F */ 0xffff,0xffff
  929. }
  930. };
  931. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&magic_snoop_scb,
  932. dest,"MAGICSNOOPTASK",parent_scb,
  933. scb_child_type);
  934. return scb;
  935. }
  936. static struct dsp_scb_descriptor *
  937. find_next_free_scb (struct snd_cs46xx * chip, struct dsp_scb_descriptor * from)
  938. {
  939. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  940. struct dsp_scb_descriptor * scb = from;
  941. while (scb->next_scb_ptr != ins->the_null_scb) {
  942. snd_assert (scb->next_scb_ptr != NULL, return NULL);
  943. scb = scb->next_scb_ptr;
  944. }
  945. return scb;
  946. }
  947. static u32 pcm_reader_buffer_addr[DSP_MAX_PCM_CHANNELS] = {
  948. 0x0600, /* 1 */
  949. 0x1500, /* 2 */
  950. 0x1580, /* 3 */
  951. 0x1600, /* 4 */
  952. 0x1680, /* 5 */
  953. 0x1700, /* 6 */
  954. 0x1780, /* 7 */
  955. 0x1800, /* 8 */
  956. 0x1880, /* 9 */
  957. 0x1900, /* 10 */
  958. 0x1980, /* 11 */
  959. 0x1A00, /* 12 */
  960. 0x1A80, /* 13 */
  961. 0x1B00, /* 14 */
  962. 0x1B80, /* 15 */
  963. 0x1C00, /* 16 */
  964. 0x1C80, /* 17 */
  965. 0x1D00, /* 18 */
  966. 0x1D80, /* 19 */
  967. 0x1E00, /* 20 */
  968. 0x1E80, /* 21 */
  969. 0x1F00, /* 22 */
  970. 0x1F80, /* 23 */
  971. 0x2000, /* 24 */
  972. 0x2080, /* 25 */
  973. 0x2100, /* 26 */
  974. 0x2180, /* 27 */
  975. 0x2200, /* 28 */
  976. 0x2280, /* 29 */
  977. 0x2300, /* 30 */
  978. 0x2380, /* 31 */
  979. 0x2400, /* 32 */
  980. };
  981. static u32 src_output_buffer_addr[DSP_MAX_SRC_NR] = {
  982. 0x2B80,
  983. 0x2BA0,
  984. 0x2BC0,
  985. 0x2BE0,
  986. 0x2D00,
  987. 0x2D20,
  988. 0x2D40,
  989. 0x2D60,
  990. 0x2D80,
  991. 0x2DA0,
  992. 0x2DC0,
  993. 0x2DE0,
  994. 0x2E00,
  995. 0x2E20
  996. };
  997. static u32 src_delay_buffer_addr[DSP_MAX_SRC_NR] = {
  998. 0x2480,
  999. 0x2500,
  1000. 0x2580,
  1001. 0x2600,
  1002. 0x2680,
  1003. 0x2700,
  1004. 0x2780,
  1005. 0x2800,
  1006. 0x2880,
  1007. 0x2900,
  1008. 0x2980,
  1009. 0x2A00,
  1010. 0x2A80,
  1011. 0x2B00
  1012. };
  1013. struct dsp_pcm_channel_descriptor *
  1014. cs46xx_dsp_create_pcm_channel (struct snd_cs46xx * chip,
  1015. u32 sample_rate, void * private_data,
  1016. u32 hw_dma_addr,
  1017. int pcm_channel_id)
  1018. {
  1019. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1020. struct dsp_scb_descriptor * src_scb = NULL, * pcm_scb, * mixer_scb = NULL;
  1021. struct dsp_scb_descriptor * src_parent_scb = NULL;
  1022. /* struct dsp_scb_descriptor * pcm_parent_scb; */
  1023. char scb_name[DSP_MAX_SCB_NAME];
  1024. int i, pcm_index = -1, insert_point, src_index = -1, pass_through = 0;
  1025. unsigned long flags;
  1026. switch (pcm_channel_id) {
  1027. case DSP_PCM_MAIN_CHANNEL:
  1028. mixer_scb = ins->master_mix_scb;
  1029. break;
  1030. case DSP_PCM_REAR_CHANNEL:
  1031. mixer_scb = ins->rear_mix_scb;
  1032. break;
  1033. case DSP_PCM_CENTER_LFE_CHANNEL:
  1034. mixer_scb = ins->center_lfe_mix_scb;
  1035. break;
  1036. case DSP_PCM_S71_CHANNEL:
  1037. /* TODO */
  1038. snd_assert(0);
  1039. break;
  1040. case DSP_IEC958_CHANNEL:
  1041. snd_assert (ins->asynch_tx_scb != NULL, return NULL);
  1042. mixer_scb = ins->asynch_tx_scb;
  1043. /* if sample rate is set to 48khz we pass
  1044. the Sample Rate Converted (which could
  1045. alter the raw data stream ...) */
  1046. if (sample_rate == 48000) {
  1047. snd_printdd ("IEC958 pass through\n");
  1048. /* Hack to bypass creating a new SRC */
  1049. pass_through = 1;
  1050. }
  1051. break;
  1052. default:
  1053. snd_assert (0);
  1054. return NULL;
  1055. }
  1056. /* default sample rate is 44100 */
  1057. if (!sample_rate) sample_rate = 44100;
  1058. /* search for a already created SRC SCB with the same sample rate */
  1059. for (i = 0; i < DSP_MAX_PCM_CHANNELS &&
  1060. (pcm_index == -1 || src_scb == NULL); ++i) {
  1061. /* virtual channel reserved
  1062. for capture */
  1063. if (i == CS46XX_DSP_CAPTURE_CHANNEL) continue;
  1064. if (ins->pcm_channels[i].active) {
  1065. if (!src_scb &&
  1066. ins->pcm_channels[i].sample_rate == sample_rate &&
  1067. ins->pcm_channels[i].mixer_scb == mixer_scb) {
  1068. src_scb = ins->pcm_channels[i].src_scb;
  1069. ins->pcm_channels[i].src_scb->ref_count ++;
  1070. src_index = ins->pcm_channels[i].src_slot;
  1071. }
  1072. } else if (pcm_index == -1) {
  1073. pcm_index = i;
  1074. }
  1075. }
  1076. if (pcm_index == -1) {
  1077. snd_printk (KERN_ERR "dsp_spos: no free PCM channel\n");
  1078. return NULL;
  1079. }
  1080. if (src_scb == NULL) {
  1081. if (ins->nsrc_scb >= DSP_MAX_SRC_NR) {
  1082. snd_printk(KERN_ERR "dsp_spos: to many SRC instances\n!");
  1083. return NULL;
  1084. }
  1085. /* find a free slot */
  1086. for (i = 0; i < DSP_MAX_SRC_NR; ++i) {
  1087. if (ins->src_scb_slots[i] == 0) {
  1088. src_index = i;
  1089. ins->src_scb_slots[i] = 1;
  1090. break;
  1091. }
  1092. }
  1093. snd_assert (src_index != -1,return NULL);
  1094. /* we need to create a new SRC SCB */
  1095. if (mixer_scb->sub_list_ptr == ins->the_null_scb) {
  1096. src_parent_scb = mixer_scb;
  1097. insert_point = SCB_ON_PARENT_SUBLIST_SCB;
  1098. } else {
  1099. src_parent_scb = find_next_free_scb(chip,mixer_scb->sub_list_ptr);
  1100. insert_point = SCB_ON_PARENT_NEXT_SCB;
  1101. }
  1102. snprintf (scb_name,DSP_MAX_SCB_NAME,"SrcTask_SCB%d",src_index);
  1103. snd_printdd( "dsp_spos: creating SRC \"%s\"\n",scb_name);
  1104. src_scb = cs46xx_dsp_create_src_task_scb(chip,scb_name,
  1105. sample_rate,
  1106. src_output_buffer_addr[src_index],
  1107. src_delay_buffer_addr[src_index],
  1108. /* 0x400 - 0x600 source SCBs */
  1109. 0x400 + (src_index * 0x10) ,
  1110. src_parent_scb,
  1111. insert_point,
  1112. pass_through);
  1113. if (!src_scb) {
  1114. snd_printk (KERN_ERR "dsp_spos: failed to create SRCtaskSCB\n");
  1115. return NULL;
  1116. }
  1117. /* cs46xx_dsp_set_src_sample_rate(chip,src_scb,sample_rate); */
  1118. ins->nsrc_scb ++;
  1119. }
  1120. snprintf (scb_name,DSP_MAX_SCB_NAME,"PCMReader_SCB%d",pcm_index);
  1121. snd_printdd( "dsp_spos: creating PCM \"%s\" (%d)\n",scb_name,
  1122. pcm_channel_id);
  1123. pcm_scb = cs46xx_dsp_create_pcm_reader_scb(chip,scb_name,
  1124. pcm_reader_buffer_addr[pcm_index],
  1125. /* 0x200 - 400 PCMreader SCBs */
  1126. (pcm_index * 0x10) + 0x200,
  1127. pcm_index, /* virtual channel 0-31 */
  1128. hw_dma_addr, /* pcm hw addr */
  1129. NULL, /* parent SCB ptr */
  1130. 0 /* insert point */
  1131. );
  1132. if (!pcm_scb) {
  1133. snd_printk (KERN_ERR "dsp_spos: failed to create PCMreaderSCB\n");
  1134. return NULL;
  1135. }
  1136. spin_lock_irqsave(&chip->reg_lock, flags);
  1137. ins->pcm_channels[pcm_index].sample_rate = sample_rate;
  1138. ins->pcm_channels[pcm_index].pcm_reader_scb = pcm_scb;
  1139. ins->pcm_channels[pcm_index].src_scb = src_scb;
  1140. ins->pcm_channels[pcm_index].unlinked = 1;
  1141. ins->pcm_channels[pcm_index].private_data = private_data;
  1142. ins->pcm_channels[pcm_index].src_slot = src_index;
  1143. ins->pcm_channels[pcm_index].active = 1;
  1144. ins->pcm_channels[pcm_index].pcm_slot = pcm_index;
  1145. ins->pcm_channels[pcm_index].mixer_scb = mixer_scb;
  1146. ins->npcm_channels ++;
  1147. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1148. return (ins->pcm_channels + pcm_index);
  1149. }
  1150. int cs46xx_dsp_pcm_channel_set_period (struct snd_cs46xx * chip,
  1151. struct dsp_pcm_channel_descriptor * pcm_channel,
  1152. int period_size)
  1153. {
  1154. u32 temp = snd_cs46xx_peek (chip,pcm_channel->pcm_reader_scb->address << 2);
  1155. temp &= ~DMA_RQ_C1_SOURCE_SIZE_MASK;
  1156. switch (period_size) {
  1157. case 2048:
  1158. temp |= DMA_RQ_C1_SOURCE_MOD1024;
  1159. break;
  1160. case 1024:
  1161. temp |= DMA_RQ_C1_SOURCE_MOD512;
  1162. break;
  1163. case 512:
  1164. temp |= DMA_RQ_C1_SOURCE_MOD256;
  1165. break;
  1166. case 256:
  1167. temp |= DMA_RQ_C1_SOURCE_MOD128;
  1168. break;
  1169. case 128:
  1170. temp |= DMA_RQ_C1_SOURCE_MOD64;
  1171. break;
  1172. case 64:
  1173. temp |= DMA_RQ_C1_SOURCE_MOD32;
  1174. break;
  1175. case 32:
  1176. temp |= DMA_RQ_C1_SOURCE_MOD16;
  1177. break;
  1178. default:
  1179. snd_printdd ("period size (%d) not supported by HW\n", period_size);
  1180. return -EINVAL;
  1181. }
  1182. snd_cs46xx_poke (chip,pcm_channel->pcm_reader_scb->address << 2,temp);
  1183. return 0;
  1184. }
  1185. int cs46xx_dsp_pcm_ostream_set_period (struct snd_cs46xx * chip,
  1186. int period_size)
  1187. {
  1188. u32 temp = snd_cs46xx_peek (chip,WRITEBACK_SCB_ADDR << 2);
  1189. temp &= ~DMA_RQ_C1_DEST_SIZE_MASK;
  1190. switch (period_size) {
  1191. case 2048:
  1192. temp |= DMA_RQ_C1_DEST_MOD1024;
  1193. break;
  1194. case 1024:
  1195. temp |= DMA_RQ_C1_DEST_MOD512;
  1196. break;
  1197. case 512:
  1198. temp |= DMA_RQ_C1_DEST_MOD256;
  1199. break;
  1200. case 256:
  1201. temp |= DMA_RQ_C1_DEST_MOD128;
  1202. break;
  1203. case 128:
  1204. temp |= DMA_RQ_C1_DEST_MOD64;
  1205. break;
  1206. case 64:
  1207. temp |= DMA_RQ_C1_DEST_MOD32;
  1208. break;
  1209. case 32:
  1210. temp |= DMA_RQ_C1_DEST_MOD16;
  1211. break;
  1212. default:
  1213. snd_printdd ("period size (%d) not supported by HW\n", period_size);
  1214. return -EINVAL;
  1215. }
  1216. snd_cs46xx_poke (chip,WRITEBACK_SCB_ADDR << 2,temp);
  1217. return 0;
  1218. }
  1219. void cs46xx_dsp_destroy_pcm_channel (struct snd_cs46xx * chip,
  1220. struct dsp_pcm_channel_descriptor * pcm_channel)
  1221. {
  1222. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1223. unsigned long flags;
  1224. snd_assert(pcm_channel->active, return );
  1225. snd_assert(ins->npcm_channels > 0, return );
  1226. snd_assert(pcm_channel->src_scb->ref_count > 0, return );
  1227. spin_lock_irqsave(&chip->reg_lock, flags);
  1228. pcm_channel->unlinked = 1;
  1229. pcm_channel->active = 0;
  1230. pcm_channel->private_data = NULL;
  1231. pcm_channel->src_scb->ref_count --;
  1232. ins->npcm_channels --;
  1233. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1234. cs46xx_dsp_remove_scb(chip,pcm_channel->pcm_reader_scb);
  1235. if (!pcm_channel->src_scb->ref_count) {
  1236. cs46xx_dsp_remove_scb(chip,pcm_channel->src_scb);
  1237. snd_assert (pcm_channel->src_slot >= 0 && pcm_channel->src_slot < DSP_MAX_SRC_NR,
  1238. return );
  1239. ins->src_scb_slots[pcm_channel->src_slot] = 0;
  1240. ins->nsrc_scb --;
  1241. }
  1242. }
  1243. int cs46xx_dsp_pcm_unlink (struct snd_cs46xx * chip,
  1244. struct dsp_pcm_channel_descriptor * pcm_channel)
  1245. {
  1246. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1247. unsigned long flags;
  1248. snd_assert(pcm_channel->active,return -EIO);
  1249. snd_assert(ins->npcm_channels > 0,return -EIO);
  1250. spin_lock(&pcm_channel->src_scb->lock);
  1251. if (pcm_channel->unlinked) {
  1252. spin_unlock(&pcm_channel->src_scb->lock);
  1253. return -EIO;
  1254. }
  1255. spin_lock_irqsave(&chip->reg_lock, flags);
  1256. pcm_channel->unlinked = 1;
  1257. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1258. _dsp_unlink_scb (chip,pcm_channel->pcm_reader_scb);
  1259. spin_unlock(&pcm_channel->src_scb->lock);
  1260. return 0;
  1261. }
  1262. int cs46xx_dsp_pcm_link (struct snd_cs46xx * chip,
  1263. struct dsp_pcm_channel_descriptor * pcm_channel)
  1264. {
  1265. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1266. struct dsp_scb_descriptor * parent_scb;
  1267. struct dsp_scb_descriptor * src_scb = pcm_channel->src_scb;
  1268. unsigned long flags;
  1269. spin_lock(&pcm_channel->src_scb->lock);
  1270. if (pcm_channel->unlinked == 0) {
  1271. spin_unlock(&pcm_channel->src_scb->lock);
  1272. return -EIO;
  1273. }
  1274. parent_scb = src_scb;
  1275. if (src_scb->sub_list_ptr != ins->the_null_scb) {
  1276. src_scb->sub_list_ptr->parent_scb_ptr = pcm_channel->pcm_reader_scb;
  1277. pcm_channel->pcm_reader_scb->next_scb_ptr = src_scb->sub_list_ptr;
  1278. }
  1279. src_scb->sub_list_ptr = pcm_channel->pcm_reader_scb;
  1280. snd_assert (pcm_channel->pcm_reader_scb->parent_scb_ptr == NULL, ; );
  1281. pcm_channel->pcm_reader_scb->parent_scb_ptr = parent_scb;
  1282. spin_lock_irqsave(&chip->reg_lock, flags);
  1283. /* update SCB entry in DSP RAM */
  1284. cs46xx_dsp_spos_update_scb(chip,pcm_channel->pcm_reader_scb);
  1285. /* update parent SCB entry */
  1286. cs46xx_dsp_spos_update_scb(chip,parent_scb);
  1287. pcm_channel->unlinked = 0;
  1288. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1289. spin_unlock(&pcm_channel->src_scb->lock);
  1290. return 0;
  1291. }
  1292. struct dsp_scb_descriptor *
  1293. cs46xx_add_record_source (struct snd_cs46xx *chip, struct dsp_scb_descriptor * source,
  1294. u16 addr, char * scb_name)
  1295. {
  1296. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1297. struct dsp_scb_descriptor * parent;
  1298. struct dsp_scb_descriptor * pcm_input;
  1299. int insert_point;
  1300. snd_assert (ins->record_mixer_scb != NULL,return NULL);
  1301. if (ins->record_mixer_scb->sub_list_ptr != ins->the_null_scb) {
  1302. parent = find_next_free_scb (chip,ins->record_mixer_scb->sub_list_ptr);
  1303. insert_point = SCB_ON_PARENT_NEXT_SCB;
  1304. } else {
  1305. parent = ins->record_mixer_scb;
  1306. insert_point = SCB_ON_PARENT_SUBLIST_SCB;
  1307. }
  1308. pcm_input = cs46xx_dsp_create_pcm_serial_input_scb(chip,scb_name,addr,
  1309. source, parent,
  1310. insert_point);
  1311. return pcm_input;
  1312. }
  1313. int cs46xx_src_unlink(struct snd_cs46xx *chip, struct dsp_scb_descriptor * src)
  1314. {
  1315. snd_assert (src->parent_scb_ptr != NULL, return -EINVAL );
  1316. /* mute SCB */
  1317. cs46xx_dsp_scb_set_volume (chip,src,0,0);
  1318. _dsp_unlink_scb (chip,src);
  1319. return 0;
  1320. }
  1321. int cs46xx_src_link(struct snd_cs46xx *chip, struct dsp_scb_descriptor * src)
  1322. {
  1323. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1324. struct dsp_scb_descriptor * parent_scb;
  1325. snd_assert (src->parent_scb_ptr == NULL, return -EINVAL );
  1326. snd_assert(ins->master_mix_scb !=NULL, return -EINVAL );
  1327. if (ins->master_mix_scb->sub_list_ptr != ins->the_null_scb) {
  1328. parent_scb = find_next_free_scb (chip,ins->master_mix_scb->sub_list_ptr);
  1329. parent_scb->next_scb_ptr = src;
  1330. } else {
  1331. parent_scb = ins->master_mix_scb;
  1332. parent_scb->sub_list_ptr = src;
  1333. }
  1334. src->parent_scb_ptr = parent_scb;
  1335. /* update entry in DSP RAM */
  1336. cs46xx_dsp_spos_update_scb(chip,parent_scb);
  1337. return 0;
  1338. }
  1339. int cs46xx_dsp_enable_spdif_out (struct snd_cs46xx *chip)
  1340. {
  1341. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1342. if ( ! (ins->spdif_status_out & DSP_SPDIF_STATUS_HW_ENABLED) ) {
  1343. cs46xx_dsp_enable_spdif_hw (chip);
  1344. }
  1345. /* dont touch anything if SPDIF is open */
  1346. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) {
  1347. /* when cs46xx_iec958_post_close(...) is called it
  1348. will call this function if necessary depending on
  1349. this bit */
  1350. ins->spdif_status_out |= DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1351. return -EBUSY;
  1352. }
  1353. snd_assert (ins->asynch_tx_scb == NULL, return -EINVAL);
  1354. snd_assert (ins->master_mix_scb->next_scb_ptr == ins->the_null_scb, return -EINVAL);
  1355. /* reset output snooper sample buffer pointer */
  1356. snd_cs46xx_poke (chip, (ins->ref_snoop_scb->address + 2) << 2,
  1357. (OUTPUT_SNOOP_BUFFER + 0x10) << 0x10 );
  1358. /* The asynch. transfer task */
  1359. ins->asynch_tx_scb = cs46xx_dsp_create_asynch_fg_tx_scb(chip,"AsynchFGTxSCB",ASYNCTX_SCB_ADDR,
  1360. SPDIFO_SCB_INST,
  1361. SPDIFO_IP_OUTPUT_BUFFER1,
  1362. ins->master_mix_scb,
  1363. SCB_ON_PARENT_NEXT_SCB);
  1364. if (!ins->asynch_tx_scb) return -ENOMEM;
  1365. ins->spdif_pcm_input_scb = cs46xx_dsp_create_pcm_serial_input_scb(chip,"PCMSerialInput_II",
  1366. PCMSERIALINII_SCB_ADDR,
  1367. ins->ref_snoop_scb,
  1368. ins->asynch_tx_scb,
  1369. SCB_ON_PARENT_SUBLIST_SCB);
  1370. if (!ins->spdif_pcm_input_scb) return -ENOMEM;
  1371. /* monitor state */
  1372. ins->spdif_status_out |= DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1373. return 0;
  1374. }
  1375. int cs46xx_dsp_disable_spdif_out (struct snd_cs46xx *chip)
  1376. {
  1377. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1378. /* dont touch anything if SPDIF is open */
  1379. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) {
  1380. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1381. return -EBUSY;
  1382. }
  1383. /* check integrety */
  1384. snd_assert (ins->asynch_tx_scb != NULL, return -EINVAL);
  1385. snd_assert (ins->spdif_pcm_input_scb != NULL,return -EINVAL);
  1386. snd_assert (ins->master_mix_scb->next_scb_ptr == ins->asynch_tx_scb, return -EINVAL);
  1387. snd_assert (ins->asynch_tx_scb->parent_scb_ptr == ins->master_mix_scb, return -EINVAL);
  1388. cs46xx_dsp_remove_scb (chip,ins->spdif_pcm_input_scb);
  1389. cs46xx_dsp_remove_scb (chip,ins->asynch_tx_scb);
  1390. ins->spdif_pcm_input_scb = NULL;
  1391. ins->asynch_tx_scb = NULL;
  1392. /* clear buffer to prevent any undesired noise */
  1393. _dsp_clear_sample_buffer(chip,SPDIFO_IP_OUTPUT_BUFFER1,256);
  1394. /* monitor state */
  1395. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1396. return 0;
  1397. }
  1398. int cs46xx_iec958_pre_open (struct snd_cs46xx *chip)
  1399. {
  1400. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1401. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED ) {
  1402. /* remove AsynchFGTxSCB and and PCMSerialInput_II */
  1403. cs46xx_dsp_disable_spdif_out (chip);
  1404. /* save state */
  1405. ins->spdif_status_out |= DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1406. }
  1407. /* if not enabled already */
  1408. if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_HW_ENABLED) ) {
  1409. cs46xx_dsp_enable_spdif_hw (chip);
  1410. }
  1411. /* Create the asynch. transfer task for playback */
  1412. ins->asynch_tx_scb = cs46xx_dsp_create_asynch_fg_tx_scb(chip,"AsynchFGTxSCB",ASYNCTX_SCB_ADDR,
  1413. SPDIFO_SCB_INST,
  1414. SPDIFO_IP_OUTPUT_BUFFER1,
  1415. ins->master_mix_scb,
  1416. SCB_ON_PARENT_NEXT_SCB);
  1417. /* set spdif channel status value for streaming */
  1418. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_stream);
  1419. ins->spdif_status_out |= DSP_SPDIF_STATUS_PLAYBACK_OPEN;
  1420. return 0;
  1421. }
  1422. int cs46xx_iec958_post_close (struct snd_cs46xx *chip)
  1423. {
  1424. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1425. snd_assert (ins->asynch_tx_scb != NULL, return -EINVAL);
  1426. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_PLAYBACK_OPEN;
  1427. /* restore settings */
  1428. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);
  1429. /* deallocate stuff */
  1430. if (ins->spdif_pcm_input_scb != NULL) {
  1431. cs46xx_dsp_remove_scb (chip,ins->spdif_pcm_input_scb);
  1432. ins->spdif_pcm_input_scb = NULL;
  1433. }
  1434. cs46xx_dsp_remove_scb (chip,ins->asynch_tx_scb);
  1435. ins->asynch_tx_scb = NULL;
  1436. /* clear buffer to prevent any undesired noise */
  1437. _dsp_clear_sample_buffer(chip,SPDIFO_IP_OUTPUT_BUFFER1,256);
  1438. /* restore state */
  1439. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED ) {
  1440. cs46xx_dsp_enable_spdif_out (chip);
  1441. }
  1442. return 0;
  1443. }