dsp_spos.c 54 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify
  3. * it under the terms of the GNU General Public License as published by
  4. * the Free Software Foundation; either version 2 of the License, or
  5. * (at your option) any later version.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. * You should have received a copy of the GNU General Public License
  13. * along with this program; if not, write to the Free Software
  14. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  15. *
  16. */
  17. /*
  18. * 2002-07 Benny Sjostrand benny@hostmobility.com
  19. */
  20. #include <sound/driver.h>
  21. #include <asm/io.h>
  22. #include <linux/delay.h>
  23. #include <linux/pm.h>
  24. #include <linux/init.h>
  25. #include <linux/slab.h>
  26. #include <linux/vmalloc.h>
  27. #include <linux/mutex.h>
  28. #include <sound/core.h>
  29. #include <sound/control.h>
  30. #include <sound/info.h>
  31. #include <sound/asoundef.h>
  32. #include <sound/cs46xx.h>
  33. #include "cs46xx_lib.h"
  34. #include "dsp_spos.h"
  35. static int cs46xx_dsp_async_init (struct snd_cs46xx *chip,
  36. struct dsp_scb_descriptor * fg_entry);
  37. static enum wide_opcode wide_opcodes[] = {
  38. WIDE_FOR_BEGIN_LOOP,
  39. WIDE_FOR_BEGIN_LOOP2,
  40. WIDE_COND_GOTO_ADDR,
  41. WIDE_COND_GOTO_CALL,
  42. WIDE_TBEQ_COND_GOTO_ADDR,
  43. WIDE_TBEQ_COND_CALL_ADDR,
  44. WIDE_TBEQ_NCOND_GOTO_ADDR,
  45. WIDE_TBEQ_NCOND_CALL_ADDR,
  46. WIDE_TBEQ_COND_GOTO1_ADDR,
  47. WIDE_TBEQ_COND_CALL1_ADDR,
  48. WIDE_TBEQ_NCOND_GOTOI_ADDR,
  49. WIDE_TBEQ_NCOND_CALL1_ADDR
  50. };
  51. static int shadow_and_reallocate_code (struct snd_cs46xx * chip, u32 * data, u32 size,
  52. u32 overlay_begin_address)
  53. {
  54. unsigned int i = 0, j, nreallocated = 0;
  55. u32 hival,loval,address;
  56. u32 mop_operands,mop_type,wide_op;
  57. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  58. snd_assert( ((size % 2) == 0), return -EINVAL);
  59. while (i < size) {
  60. loval = data[i++];
  61. hival = data[i++];
  62. if (ins->code.offset > 0) {
  63. mop_operands = (hival >> 6) & 0x03fff;
  64. mop_type = mop_operands >> 10;
  65. /* check for wide type instruction */
  66. if (mop_type == 0 &&
  67. (mop_operands & WIDE_LADD_INSTR_MASK) == 0 &&
  68. (mop_operands & WIDE_INSTR_MASK) != 0) {
  69. wide_op = loval & 0x7f;
  70. for (j = 0;j < ARRAY_SIZE(wide_opcodes); ++j) {
  71. if (wide_opcodes[j] == wide_op) {
  72. /* need to reallocate instruction */
  73. address = (hival & 0x00FFF) << 5;
  74. address |= loval >> 15;
  75. snd_printdd("handle_wideop[1]: %05x:%05x addr %04x\n",hival,loval,address);
  76. if ( !(address & 0x8000) ) {
  77. address += (ins->code.offset / 2) - overlay_begin_address;
  78. } else {
  79. snd_printdd("handle_wideop[1]: ROM symbol not reallocated\n");
  80. }
  81. hival &= 0xFF000;
  82. loval &= 0x07FFF;
  83. hival |= ( (address >> 5) & 0x00FFF);
  84. loval |= ( (address << 15) & 0xF8000);
  85. address = (hival & 0x00FFF) << 5;
  86. address |= loval >> 15;
  87. snd_printdd("handle_wideop:[2] %05x:%05x addr %04x\n",hival,loval,address);
  88. nreallocated ++;
  89. } /* wide_opcodes[j] == wide_op */
  90. } /* for */
  91. } /* mod_type == 0 ... */
  92. } /* ins->code.offset > 0 */
  93. ins->code.data[ins->code.size++] = loval;
  94. ins->code.data[ins->code.size++] = hival;
  95. }
  96. snd_printdd("dsp_spos: %d instructions reallocated\n",nreallocated);
  97. return nreallocated;
  98. }
  99. static struct dsp_segment_desc * get_segment_desc (struct dsp_module_desc * module, int seg_type)
  100. {
  101. int i;
  102. for (i = 0;i < module->nsegments; ++i) {
  103. if (module->segments[i].segment_type == seg_type) {
  104. return (module->segments + i);
  105. }
  106. }
  107. return NULL;
  108. };
  109. static int find_free_symbol_index (struct dsp_spos_instance * ins)
  110. {
  111. int index = ins->symbol_table.nsymbols,i;
  112. for (i = ins->symbol_table.highest_frag_index; i < ins->symbol_table.nsymbols; ++i) {
  113. if (ins->symbol_table.symbols[i].deleted) {
  114. index = i;
  115. break;
  116. }
  117. }
  118. return index;
  119. }
  120. static int add_symbols (struct snd_cs46xx * chip, struct dsp_module_desc * module)
  121. {
  122. int i;
  123. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  124. if (module->symbol_table.nsymbols > 0) {
  125. if (!strcmp(module->symbol_table.symbols[0].symbol_name, "OVERLAYBEGINADDRESS") &&
  126. module->symbol_table.symbols[0].symbol_type == SYMBOL_CONSTANT ) {
  127. module->overlay_begin_address = module->symbol_table.symbols[0].address;
  128. }
  129. }
  130. for (i = 0;i < module->symbol_table.nsymbols; ++i) {
  131. if (ins->symbol_table.nsymbols == (DSP_MAX_SYMBOLS - 1)) {
  132. snd_printk(KERN_ERR "dsp_spos: symbol table is full\n");
  133. return -ENOMEM;
  134. }
  135. if (cs46xx_dsp_lookup_symbol(chip,
  136. module->symbol_table.symbols[i].symbol_name,
  137. module->symbol_table.symbols[i].symbol_type) == NULL) {
  138. ins->symbol_table.symbols[ins->symbol_table.nsymbols] = module->symbol_table.symbols[i];
  139. ins->symbol_table.symbols[ins->symbol_table.nsymbols].address += ((ins->code.offset / 2) - module->overlay_begin_address);
  140. ins->symbol_table.symbols[ins->symbol_table.nsymbols].module = module;
  141. ins->symbol_table.symbols[ins->symbol_table.nsymbols].deleted = 0;
  142. if (ins->symbol_table.nsymbols > ins->symbol_table.highest_frag_index)
  143. ins->symbol_table.highest_frag_index = ins->symbol_table.nsymbols;
  144. ins->symbol_table.nsymbols++;
  145. } else {
  146. /* if (0) printk ("dsp_spos: symbol <%s> duplicated, probably nothing wrong with that (Cirrus?)\n",
  147. module->symbol_table.symbols[i].symbol_name); */
  148. }
  149. }
  150. return 0;
  151. }
  152. static struct dsp_symbol_entry *
  153. add_symbol (struct snd_cs46xx * chip, char * symbol_name, u32 address, int type)
  154. {
  155. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  156. struct dsp_symbol_entry * symbol = NULL;
  157. int index;
  158. if (ins->symbol_table.nsymbols == (DSP_MAX_SYMBOLS - 1)) {
  159. snd_printk(KERN_ERR "dsp_spos: symbol table is full\n");
  160. return NULL;
  161. }
  162. if (cs46xx_dsp_lookup_symbol(chip,
  163. symbol_name,
  164. type) != NULL) {
  165. snd_printk(KERN_ERR "dsp_spos: symbol <%s> duplicated\n", symbol_name);
  166. return NULL;
  167. }
  168. index = find_free_symbol_index (ins);
  169. strcpy (ins->symbol_table.symbols[index].symbol_name, symbol_name);
  170. ins->symbol_table.symbols[index].address = address;
  171. ins->symbol_table.symbols[index].symbol_type = type;
  172. ins->symbol_table.symbols[index].module = NULL;
  173. ins->symbol_table.symbols[index].deleted = 0;
  174. symbol = (ins->symbol_table.symbols + index);
  175. if (index > ins->symbol_table.highest_frag_index)
  176. ins->symbol_table.highest_frag_index = index;
  177. if (index == ins->symbol_table.nsymbols)
  178. ins->symbol_table.nsymbols++; /* no frag. in list */
  179. return symbol;
  180. }
  181. struct dsp_spos_instance *cs46xx_dsp_spos_create (struct snd_cs46xx * chip)
  182. {
  183. struct dsp_spos_instance * ins = kzalloc(sizeof(struct dsp_spos_instance), GFP_KERNEL);
  184. if (ins == NULL)
  185. return NULL;
  186. /* better to use vmalloc for this big table */
  187. ins->symbol_table.nsymbols = 0;
  188. ins->symbol_table.symbols = vmalloc(sizeof(struct dsp_symbol_entry) *
  189. DSP_MAX_SYMBOLS);
  190. ins->symbol_table.highest_frag_index = 0;
  191. if (ins->symbol_table.symbols == NULL) {
  192. cs46xx_dsp_spos_destroy(chip);
  193. goto error;
  194. }
  195. ins->code.offset = 0;
  196. ins->code.size = 0;
  197. ins->code.data = kmalloc(DSP_CODE_BYTE_SIZE, GFP_KERNEL);
  198. if (ins->code.data == NULL) {
  199. cs46xx_dsp_spos_destroy(chip);
  200. goto error;
  201. }
  202. ins->nscb = 0;
  203. ins->ntask = 0;
  204. ins->nmodules = 0;
  205. ins->modules = kmalloc(sizeof(struct dsp_module_desc) * DSP_MAX_MODULES, GFP_KERNEL);
  206. if (ins->modules == NULL) {
  207. cs46xx_dsp_spos_destroy(chip);
  208. goto error;
  209. }
  210. /* default SPDIF input sample rate
  211. to 48000 khz */
  212. ins->spdif_in_sample_rate = 48000;
  213. /* maximize volume */
  214. ins->dac_volume_right = 0x8000;
  215. ins->dac_volume_left = 0x8000;
  216. ins->spdif_input_volume_right = 0x8000;
  217. ins->spdif_input_volume_left = 0x8000;
  218. /* set left and right validity bits and
  219. default channel status */
  220. ins->spdif_csuv_default =
  221. ins->spdif_csuv_stream =
  222. /* byte 0 */ ((unsigned int)_wrap_all_bits( (SNDRV_PCM_DEFAULT_CON_SPDIF & 0xff)) << 24) |
  223. /* byte 1 */ ((unsigned int)_wrap_all_bits( ((SNDRV_PCM_DEFAULT_CON_SPDIF >> 8) & 0xff)) << 16) |
  224. /* byte 3 */ (unsigned int)_wrap_all_bits( (SNDRV_PCM_DEFAULT_CON_SPDIF >> 24) & 0xff) |
  225. /* left and right validity bits */ (1 << 13) | (1 << 12);
  226. return ins;
  227. error:
  228. kfree(ins);
  229. return NULL;
  230. }
  231. void cs46xx_dsp_spos_destroy (struct snd_cs46xx * chip)
  232. {
  233. int i;
  234. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  235. snd_assert(ins != NULL, return);
  236. mutex_lock(&chip->spos_mutex);
  237. for (i = 0; i < ins->nscb; ++i) {
  238. if (ins->scbs[i].deleted) continue;
  239. cs46xx_dsp_proc_free_scb_desc ( (ins->scbs + i) );
  240. }
  241. kfree(ins->code.data);
  242. vfree(ins->symbol_table.symbols);
  243. kfree(ins->modules);
  244. kfree(ins);
  245. mutex_unlock(&chip->spos_mutex);
  246. }
  247. static int dsp_load_parameter(struct snd_cs46xx *chip,
  248. struct dsp_segment_desc *parameter)
  249. {
  250. u32 doffset, dsize;
  251. if (!parameter) {
  252. snd_printdd("dsp_spos: module got no parameter segment\n");
  253. return 0;
  254. }
  255. doffset = (parameter->offset * 4 + DSP_PARAMETER_BYTE_OFFSET);
  256. dsize = parameter->size * 4;
  257. snd_printdd("dsp_spos: "
  258. "downloading parameter data to chip (%08x-%08x)\n",
  259. doffset,doffset + dsize);
  260. if (snd_cs46xx_download (chip, parameter->data, doffset, dsize)) {
  261. snd_printk(KERN_ERR "dsp_spos: "
  262. "failed to download parameter data to DSP\n");
  263. return -EINVAL;
  264. }
  265. return 0;
  266. }
  267. static int dsp_load_sample(struct snd_cs46xx *chip,
  268. struct dsp_segment_desc *sample)
  269. {
  270. u32 doffset, dsize;
  271. if (!sample) {
  272. snd_printdd("dsp_spos: module got no sample segment\n");
  273. return 0;
  274. }
  275. doffset = (sample->offset * 4 + DSP_SAMPLE_BYTE_OFFSET);
  276. dsize = sample->size * 4;
  277. snd_printdd("dsp_spos: downloading sample data to chip (%08x-%08x)\n",
  278. doffset,doffset + dsize);
  279. if (snd_cs46xx_download (chip,sample->data,doffset,dsize)) {
  280. snd_printk(KERN_ERR "dsp_spos: failed to sample data to DSP\n");
  281. return -EINVAL;
  282. }
  283. return 0;
  284. }
  285. int cs46xx_dsp_load_module (struct snd_cs46xx * chip, struct dsp_module_desc * module)
  286. {
  287. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  288. struct dsp_segment_desc * code = get_segment_desc (module,SEGTYPE_SP_PROGRAM);
  289. u32 doffset, dsize;
  290. int err;
  291. if (ins->nmodules == DSP_MAX_MODULES - 1) {
  292. snd_printk(KERN_ERR "dsp_spos: to many modules loaded into DSP\n");
  293. return -ENOMEM;
  294. }
  295. snd_printdd("dsp_spos: loading module %s into DSP\n", module->module_name);
  296. if (ins->nmodules == 0) {
  297. snd_printdd("dsp_spos: clearing parameter area\n");
  298. snd_cs46xx_clear_BA1(chip, DSP_PARAMETER_BYTE_OFFSET, DSP_PARAMETER_BYTE_SIZE);
  299. }
  300. err = dsp_load_parameter(chip, get_segment_desc(module,
  301. SEGTYPE_SP_PARAMETER));
  302. if (err < 0)
  303. return err;
  304. if (ins->nmodules == 0) {
  305. snd_printdd("dsp_spos: clearing sample area\n");
  306. snd_cs46xx_clear_BA1(chip, DSP_SAMPLE_BYTE_OFFSET, DSP_SAMPLE_BYTE_SIZE);
  307. }
  308. err = dsp_load_sample(chip, get_segment_desc(module,
  309. SEGTYPE_SP_SAMPLE));
  310. if (err < 0)
  311. return err;
  312. if (ins->nmodules == 0) {
  313. snd_printdd("dsp_spos: clearing code area\n");
  314. snd_cs46xx_clear_BA1(chip, DSP_CODE_BYTE_OFFSET, DSP_CODE_BYTE_SIZE);
  315. }
  316. if (code == NULL) {
  317. snd_printdd("dsp_spos: module got no code segment\n");
  318. } else {
  319. if (ins->code.offset + code->size > DSP_CODE_BYTE_SIZE) {
  320. snd_printk(KERN_ERR "dsp_spos: no space available in DSP\n");
  321. return -ENOMEM;
  322. }
  323. module->load_address = ins->code.offset;
  324. module->overlay_begin_address = 0x000;
  325. /* if module has a code segment it must have
  326. symbol table */
  327. snd_assert(module->symbol_table.symbols != NULL ,return -ENOMEM);
  328. if (add_symbols(chip,module)) {
  329. snd_printk(KERN_ERR "dsp_spos: failed to load symbol table\n");
  330. return -ENOMEM;
  331. }
  332. doffset = (code->offset * 4 + ins->code.offset * 4 + DSP_CODE_BYTE_OFFSET);
  333. dsize = code->size * 4;
  334. snd_printdd("dsp_spos: downloading code to chip (%08x-%08x)\n",
  335. doffset,doffset + dsize);
  336. module->nfixups = shadow_and_reallocate_code(chip,code->data,code->size,module->overlay_begin_address);
  337. if (snd_cs46xx_download (chip,(ins->code.data + ins->code.offset),doffset,dsize)) {
  338. snd_printk(KERN_ERR "dsp_spos: failed to download code to DSP\n");
  339. return -EINVAL;
  340. }
  341. ins->code.offset += code->size;
  342. }
  343. /* NOTE: module segments and symbol table must be
  344. statically allocated. Case that module data is
  345. not generated by the ospparser */
  346. ins->modules[ins->nmodules] = *module;
  347. ins->nmodules++;
  348. return 0;
  349. }
  350. struct dsp_symbol_entry *
  351. cs46xx_dsp_lookup_symbol (struct snd_cs46xx * chip, char * symbol_name, int symbol_type)
  352. {
  353. int i;
  354. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  355. for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
  356. if (ins->symbol_table.symbols[i].deleted)
  357. continue;
  358. if (!strcmp(ins->symbol_table.symbols[i].symbol_name,symbol_name) &&
  359. ins->symbol_table.symbols[i].symbol_type == symbol_type) {
  360. return (ins->symbol_table.symbols + i);
  361. }
  362. }
  363. #if 0
  364. printk ("dsp_spos: symbol <%s> type %02x not found\n",
  365. symbol_name,symbol_type);
  366. #endif
  367. return NULL;
  368. }
  369. #ifdef CONFIG_PROC_FS
  370. static struct dsp_symbol_entry *
  371. cs46xx_dsp_lookup_symbol_addr (struct snd_cs46xx * chip, u32 address, int symbol_type)
  372. {
  373. int i;
  374. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  375. for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
  376. if (ins->symbol_table.symbols[i].deleted)
  377. continue;
  378. if (ins->symbol_table.symbols[i].address == address &&
  379. ins->symbol_table.symbols[i].symbol_type == symbol_type) {
  380. return (ins->symbol_table.symbols + i);
  381. }
  382. }
  383. return NULL;
  384. }
  385. static void cs46xx_dsp_proc_symbol_table_read (struct snd_info_entry *entry,
  386. struct snd_info_buffer *buffer)
  387. {
  388. struct snd_cs46xx *chip = entry->private_data;
  389. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  390. int i;
  391. snd_iprintf(buffer, "SYMBOLS:\n");
  392. for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
  393. char *module_str = "system";
  394. if (ins->symbol_table.symbols[i].deleted)
  395. continue;
  396. if (ins->symbol_table.symbols[i].module != NULL) {
  397. module_str = ins->symbol_table.symbols[i].module->module_name;
  398. }
  399. snd_iprintf(buffer, "%04X <%02X> %s [%s]\n",
  400. ins->symbol_table.symbols[i].address,
  401. ins->symbol_table.symbols[i].symbol_type,
  402. ins->symbol_table.symbols[i].symbol_name,
  403. module_str);
  404. }
  405. }
  406. static void cs46xx_dsp_proc_modules_read (struct snd_info_entry *entry,
  407. struct snd_info_buffer *buffer)
  408. {
  409. struct snd_cs46xx *chip = entry->private_data;
  410. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  411. int i,j;
  412. mutex_lock(&chip->spos_mutex);
  413. snd_iprintf(buffer, "MODULES:\n");
  414. for ( i = 0; i < ins->nmodules; ++i ) {
  415. snd_iprintf(buffer, "\n%s:\n", ins->modules[i].module_name);
  416. snd_iprintf(buffer, " %d symbols\n", ins->modules[i].symbol_table.nsymbols);
  417. snd_iprintf(buffer, " %d fixups\n", ins->modules[i].nfixups);
  418. for (j = 0; j < ins->modules[i].nsegments; ++ j) {
  419. struct dsp_segment_desc * desc = (ins->modules[i].segments + j);
  420. snd_iprintf(buffer, " segment %02x offset %08x size %08x\n",
  421. desc->segment_type,desc->offset, desc->size);
  422. }
  423. }
  424. mutex_unlock(&chip->spos_mutex);
  425. }
  426. static void cs46xx_dsp_proc_task_tree_read (struct snd_info_entry *entry,
  427. struct snd_info_buffer *buffer)
  428. {
  429. struct snd_cs46xx *chip = entry->private_data;
  430. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  431. int i, j, col;
  432. void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
  433. mutex_lock(&chip->spos_mutex);
  434. snd_iprintf(buffer, "TASK TREES:\n");
  435. for ( i = 0; i < ins->ntask; ++i) {
  436. snd_iprintf(buffer,"\n%04x %s:\n",ins->tasks[i].address,ins->tasks[i].task_name);
  437. for (col = 0,j = 0;j < ins->tasks[i].size; j++,col++) {
  438. u32 val;
  439. if (col == 4) {
  440. snd_iprintf(buffer,"\n");
  441. col = 0;
  442. }
  443. val = readl(dst + (ins->tasks[i].address + j) * sizeof(u32));
  444. snd_iprintf(buffer,"%08x ",val);
  445. }
  446. }
  447. snd_iprintf(buffer,"\n");
  448. mutex_unlock(&chip->spos_mutex);
  449. }
  450. static void cs46xx_dsp_proc_scb_read (struct snd_info_entry *entry,
  451. struct snd_info_buffer *buffer)
  452. {
  453. struct snd_cs46xx *chip = entry->private_data;
  454. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  455. int i;
  456. mutex_lock(&chip->spos_mutex);
  457. snd_iprintf(buffer, "SCB's:\n");
  458. for ( i = 0; i < ins->nscb; ++i) {
  459. if (ins->scbs[i].deleted)
  460. continue;
  461. snd_iprintf(buffer,"\n%04x %s:\n\n",ins->scbs[i].address,ins->scbs[i].scb_name);
  462. if (ins->scbs[i].parent_scb_ptr != NULL) {
  463. snd_iprintf(buffer,"parent [%s:%04x] ",
  464. ins->scbs[i].parent_scb_ptr->scb_name,
  465. ins->scbs[i].parent_scb_ptr->address);
  466. } else snd_iprintf(buffer,"parent [none] ");
  467. snd_iprintf(buffer,"sub_list_ptr [%s:%04x]\nnext_scb_ptr [%s:%04x] task_entry [%s:%04x]\n",
  468. ins->scbs[i].sub_list_ptr->scb_name,
  469. ins->scbs[i].sub_list_ptr->address,
  470. ins->scbs[i].next_scb_ptr->scb_name,
  471. ins->scbs[i].next_scb_ptr->address,
  472. ins->scbs[i].task_entry->symbol_name,
  473. ins->scbs[i].task_entry->address);
  474. }
  475. snd_iprintf(buffer,"\n");
  476. mutex_unlock(&chip->spos_mutex);
  477. }
  478. static void cs46xx_dsp_proc_parameter_dump_read (struct snd_info_entry *entry,
  479. struct snd_info_buffer *buffer)
  480. {
  481. struct snd_cs46xx *chip = entry->private_data;
  482. /*struct dsp_spos_instance * ins = chip->dsp_spos_instance; */
  483. unsigned int i, col = 0;
  484. void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
  485. struct dsp_symbol_entry * symbol;
  486. for (i = 0;i < DSP_PARAMETER_BYTE_SIZE; i += sizeof(u32),col ++) {
  487. if (col == 4) {
  488. snd_iprintf(buffer,"\n");
  489. col = 0;
  490. }
  491. if ( (symbol = cs46xx_dsp_lookup_symbol_addr (chip,i / sizeof(u32), SYMBOL_PARAMETER)) != NULL) {
  492. col = 0;
  493. snd_iprintf (buffer,"\n%s:\n",symbol->symbol_name);
  494. }
  495. if (col == 0) {
  496. snd_iprintf(buffer, "%04X ", i / (unsigned int)sizeof(u32));
  497. }
  498. snd_iprintf(buffer,"%08X ",readl(dst + i));
  499. }
  500. }
  501. static void cs46xx_dsp_proc_sample_dump_read (struct snd_info_entry *entry,
  502. struct snd_info_buffer *buffer)
  503. {
  504. struct snd_cs46xx *chip = entry->private_data;
  505. int i,col = 0;
  506. void __iomem *dst = chip->region.idx[2].remap_addr;
  507. snd_iprintf(buffer,"PCMREADER:\n");
  508. for (i = PCM_READER_BUF1;i < PCM_READER_BUF1 + 0x30; i += sizeof(u32),col ++) {
  509. if (col == 4) {
  510. snd_iprintf(buffer,"\n");
  511. col = 0;
  512. }
  513. if (col == 0) {
  514. snd_iprintf(buffer, "%04X ",i);
  515. }
  516. snd_iprintf(buffer,"%08X ",readl(dst + i));
  517. }
  518. snd_iprintf(buffer,"\nMIX_SAMPLE_BUF1:\n");
  519. col = 0;
  520. for (i = MIX_SAMPLE_BUF1;i < MIX_SAMPLE_BUF1 + 0x40; i += sizeof(u32),col ++) {
  521. if (col == 4) {
  522. snd_iprintf(buffer,"\n");
  523. col = 0;
  524. }
  525. if (col == 0) {
  526. snd_iprintf(buffer, "%04X ",i);
  527. }
  528. snd_iprintf(buffer,"%08X ",readl(dst + i));
  529. }
  530. snd_iprintf(buffer,"\nSRC_TASK_SCB1:\n");
  531. col = 0;
  532. for (i = 0x2480 ; i < 0x2480 + 0x40 ; i += sizeof(u32),col ++) {
  533. if (col == 4) {
  534. snd_iprintf(buffer,"\n");
  535. col = 0;
  536. }
  537. if (col == 0) {
  538. snd_iprintf(buffer, "%04X ",i);
  539. }
  540. snd_iprintf(buffer,"%08X ",readl(dst + i));
  541. }
  542. snd_iprintf(buffer,"\nSPDIFO_BUFFER:\n");
  543. col = 0;
  544. for (i = SPDIFO_IP_OUTPUT_BUFFER1;i < SPDIFO_IP_OUTPUT_BUFFER1 + 0x30; i += sizeof(u32),col ++) {
  545. if (col == 4) {
  546. snd_iprintf(buffer,"\n");
  547. col = 0;
  548. }
  549. if (col == 0) {
  550. snd_iprintf(buffer, "%04X ",i);
  551. }
  552. snd_iprintf(buffer,"%08X ",readl(dst + i));
  553. }
  554. snd_iprintf(buffer,"\n...\n");
  555. col = 0;
  556. for (i = SPDIFO_IP_OUTPUT_BUFFER1+0xD0;i < SPDIFO_IP_OUTPUT_BUFFER1 + 0x110; i += sizeof(u32),col ++) {
  557. if (col == 4) {
  558. snd_iprintf(buffer,"\n");
  559. col = 0;
  560. }
  561. if (col == 0) {
  562. snd_iprintf(buffer, "%04X ",i);
  563. }
  564. snd_iprintf(buffer,"%08X ",readl(dst + i));
  565. }
  566. snd_iprintf(buffer,"\nOUTPUT_SNOOP:\n");
  567. col = 0;
  568. for (i = OUTPUT_SNOOP_BUFFER;i < OUTPUT_SNOOP_BUFFER + 0x40; i += sizeof(u32),col ++) {
  569. if (col == 4) {
  570. snd_iprintf(buffer,"\n");
  571. col = 0;
  572. }
  573. if (col == 0) {
  574. snd_iprintf(buffer, "%04X ",i);
  575. }
  576. snd_iprintf(buffer,"%08X ",readl(dst + i));
  577. }
  578. snd_iprintf(buffer,"\nCODEC_INPUT_BUF1: \n");
  579. col = 0;
  580. for (i = CODEC_INPUT_BUF1;i < CODEC_INPUT_BUF1 + 0x40; i += sizeof(u32),col ++) {
  581. if (col == 4) {
  582. snd_iprintf(buffer,"\n");
  583. col = 0;
  584. }
  585. if (col == 0) {
  586. snd_iprintf(buffer, "%04X ",i);
  587. }
  588. snd_iprintf(buffer,"%08X ",readl(dst + i));
  589. }
  590. #if 0
  591. snd_iprintf(buffer,"\nWRITE_BACK_BUF1: \n");
  592. col = 0;
  593. for (i = WRITE_BACK_BUF1;i < WRITE_BACK_BUF1 + 0x40; i += sizeof(u32),col ++) {
  594. if (col == 4) {
  595. snd_iprintf(buffer,"\n");
  596. col = 0;
  597. }
  598. if (col == 0) {
  599. snd_iprintf(buffer, "%04X ",i);
  600. }
  601. snd_iprintf(buffer,"%08X ",readl(dst + i));
  602. }
  603. #endif
  604. snd_iprintf(buffer,"\nSPDIFI_IP_OUTPUT_BUFFER1: \n");
  605. col = 0;
  606. for (i = SPDIFI_IP_OUTPUT_BUFFER1;i < SPDIFI_IP_OUTPUT_BUFFER1 + 0x80; i += sizeof(u32),col ++) {
  607. if (col == 4) {
  608. snd_iprintf(buffer,"\n");
  609. col = 0;
  610. }
  611. if (col == 0) {
  612. snd_iprintf(buffer, "%04X ",i);
  613. }
  614. snd_iprintf(buffer,"%08X ",readl(dst + i));
  615. }
  616. snd_iprintf(buffer,"\n");
  617. }
  618. int cs46xx_dsp_proc_init (struct snd_card *card, struct snd_cs46xx *chip)
  619. {
  620. struct snd_info_entry *entry;
  621. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  622. int i;
  623. ins->snd_card = card;
  624. if ((entry = snd_info_create_card_entry(card, "dsp", card->proc_root)) != NULL) {
  625. entry->content = SNDRV_INFO_CONTENT_TEXT;
  626. entry->mode = S_IFDIR | S_IRUGO | S_IXUGO;
  627. if (snd_info_register(entry) < 0) {
  628. snd_info_free_entry(entry);
  629. entry = NULL;
  630. }
  631. }
  632. ins->proc_dsp_dir = entry;
  633. if (!ins->proc_dsp_dir)
  634. return -ENOMEM;
  635. if ((entry = snd_info_create_card_entry(card, "spos_symbols", ins->proc_dsp_dir)) != NULL) {
  636. entry->content = SNDRV_INFO_CONTENT_TEXT;
  637. entry->private_data = chip;
  638. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  639. entry->c.text.read = cs46xx_dsp_proc_symbol_table_read;
  640. if (snd_info_register(entry) < 0) {
  641. snd_info_free_entry(entry);
  642. entry = NULL;
  643. }
  644. }
  645. ins->proc_sym_info_entry = entry;
  646. if ((entry = snd_info_create_card_entry(card, "spos_modules", ins->proc_dsp_dir)) != NULL) {
  647. entry->content = SNDRV_INFO_CONTENT_TEXT;
  648. entry->private_data = chip;
  649. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  650. entry->c.text.read = cs46xx_dsp_proc_modules_read;
  651. if (snd_info_register(entry) < 0) {
  652. snd_info_free_entry(entry);
  653. entry = NULL;
  654. }
  655. }
  656. ins->proc_modules_info_entry = entry;
  657. if ((entry = snd_info_create_card_entry(card, "parameter", ins->proc_dsp_dir)) != NULL) {
  658. entry->content = SNDRV_INFO_CONTENT_TEXT;
  659. entry->private_data = chip;
  660. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  661. entry->c.text.read = cs46xx_dsp_proc_parameter_dump_read;
  662. if (snd_info_register(entry) < 0) {
  663. snd_info_free_entry(entry);
  664. entry = NULL;
  665. }
  666. }
  667. ins->proc_parameter_dump_info_entry = entry;
  668. if ((entry = snd_info_create_card_entry(card, "sample", ins->proc_dsp_dir)) != NULL) {
  669. entry->content = SNDRV_INFO_CONTENT_TEXT;
  670. entry->private_data = chip;
  671. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  672. entry->c.text.read = cs46xx_dsp_proc_sample_dump_read;
  673. if (snd_info_register(entry) < 0) {
  674. snd_info_free_entry(entry);
  675. entry = NULL;
  676. }
  677. }
  678. ins->proc_sample_dump_info_entry = entry;
  679. if ((entry = snd_info_create_card_entry(card, "task_tree", ins->proc_dsp_dir)) != NULL) {
  680. entry->content = SNDRV_INFO_CONTENT_TEXT;
  681. entry->private_data = chip;
  682. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  683. entry->c.text.read = cs46xx_dsp_proc_task_tree_read;
  684. if (snd_info_register(entry) < 0) {
  685. snd_info_free_entry(entry);
  686. entry = NULL;
  687. }
  688. }
  689. ins->proc_task_info_entry = entry;
  690. if ((entry = snd_info_create_card_entry(card, "scb_info", ins->proc_dsp_dir)) != NULL) {
  691. entry->content = SNDRV_INFO_CONTENT_TEXT;
  692. entry->private_data = chip;
  693. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  694. entry->c.text.read = cs46xx_dsp_proc_scb_read;
  695. if (snd_info_register(entry) < 0) {
  696. snd_info_free_entry(entry);
  697. entry = NULL;
  698. }
  699. }
  700. ins->proc_scb_info_entry = entry;
  701. mutex_lock(&chip->spos_mutex);
  702. /* register/update SCB's entries on proc */
  703. for (i = 0; i < ins->nscb; ++i) {
  704. if (ins->scbs[i].deleted) continue;
  705. cs46xx_dsp_proc_register_scb_desc (chip, (ins->scbs + i));
  706. }
  707. mutex_unlock(&chip->spos_mutex);
  708. return 0;
  709. }
  710. int cs46xx_dsp_proc_done (struct snd_cs46xx *chip)
  711. {
  712. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  713. int i;
  714. snd_info_free_entry(ins->proc_sym_info_entry);
  715. ins->proc_sym_info_entry = NULL;
  716. snd_info_free_entry(ins->proc_modules_info_entry);
  717. ins->proc_modules_info_entry = NULL;
  718. snd_info_free_entry(ins->proc_parameter_dump_info_entry);
  719. ins->proc_parameter_dump_info_entry = NULL;
  720. snd_info_free_entry(ins->proc_sample_dump_info_entry);
  721. ins->proc_sample_dump_info_entry = NULL;
  722. snd_info_free_entry(ins->proc_scb_info_entry);
  723. ins->proc_scb_info_entry = NULL;
  724. snd_info_free_entry(ins->proc_task_info_entry);
  725. ins->proc_task_info_entry = NULL;
  726. mutex_lock(&chip->spos_mutex);
  727. for (i = 0; i < ins->nscb; ++i) {
  728. if (ins->scbs[i].deleted) continue;
  729. cs46xx_dsp_proc_free_scb_desc ( (ins->scbs + i) );
  730. }
  731. mutex_unlock(&chip->spos_mutex);
  732. snd_info_free_entry(ins->proc_dsp_dir);
  733. ins->proc_dsp_dir = NULL;
  734. return 0;
  735. }
  736. #endif /* CONFIG_PROC_FS */
  737. static int debug_tree;
  738. static void _dsp_create_task_tree (struct snd_cs46xx *chip, u32 * task_data,
  739. u32 dest, int size)
  740. {
  741. void __iomem *spdst = chip->region.idx[1].remap_addr +
  742. DSP_PARAMETER_BYTE_OFFSET + dest * sizeof(u32);
  743. int i;
  744. for (i = 0; i < size; ++i) {
  745. if (debug_tree) printk ("addr %p, val %08x\n",spdst,task_data[i]);
  746. writel(task_data[i],spdst);
  747. spdst += sizeof(u32);
  748. }
  749. }
  750. static int debug_scb;
  751. static void _dsp_create_scb (struct snd_cs46xx *chip, u32 * scb_data, u32 dest)
  752. {
  753. void __iomem *spdst = chip->region.idx[1].remap_addr +
  754. DSP_PARAMETER_BYTE_OFFSET + dest * sizeof(u32);
  755. int i;
  756. for (i = 0; i < 0x10; ++i) {
  757. if (debug_scb) printk ("addr %p, val %08x\n",spdst,scb_data[i]);
  758. writel(scb_data[i],spdst);
  759. spdst += sizeof(u32);
  760. }
  761. }
  762. static int find_free_scb_index (struct dsp_spos_instance * ins)
  763. {
  764. int index = ins->nscb, i;
  765. for (i = ins->scb_highest_frag_index; i < ins->nscb; ++i) {
  766. if (ins->scbs[i].deleted) {
  767. index = i;
  768. break;
  769. }
  770. }
  771. return index;
  772. }
  773. static struct dsp_scb_descriptor * _map_scb (struct snd_cs46xx *chip, char * name, u32 dest)
  774. {
  775. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  776. struct dsp_scb_descriptor * desc = NULL;
  777. int index;
  778. if (ins->nscb == DSP_MAX_SCB_DESC - 1) {
  779. snd_printk(KERN_ERR "dsp_spos: got no place for other SCB\n");
  780. return NULL;
  781. }
  782. index = find_free_scb_index (ins);
  783. strcpy(ins->scbs[index].scb_name, name);
  784. ins->scbs[index].address = dest;
  785. ins->scbs[index].index = index;
  786. ins->scbs[index].proc_info = NULL;
  787. ins->scbs[index].ref_count = 1;
  788. ins->scbs[index].deleted = 0;
  789. spin_lock_init(&ins->scbs[index].lock);
  790. desc = (ins->scbs + index);
  791. ins->scbs[index].scb_symbol = add_symbol (chip, name, dest, SYMBOL_PARAMETER);
  792. if (index > ins->scb_highest_frag_index)
  793. ins->scb_highest_frag_index = index;
  794. if (index == ins->nscb)
  795. ins->nscb++;
  796. return desc;
  797. }
  798. static struct dsp_task_descriptor *
  799. _map_task_tree (struct snd_cs46xx *chip, char * name, u32 dest, u32 size)
  800. {
  801. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  802. struct dsp_task_descriptor * desc = NULL;
  803. if (ins->ntask == DSP_MAX_TASK_DESC - 1) {
  804. snd_printk(KERN_ERR "dsp_spos: got no place for other TASK\n");
  805. return NULL;
  806. }
  807. if (name)
  808. strcpy(ins->tasks[ins->ntask].task_name, name);
  809. else
  810. strcpy(ins->tasks[ins->ntask].task_name, "(NULL)");
  811. ins->tasks[ins->ntask].address = dest;
  812. ins->tasks[ins->ntask].size = size;
  813. /* quick find in list */
  814. ins->tasks[ins->ntask].index = ins->ntask;
  815. desc = (ins->tasks + ins->ntask);
  816. ins->ntask++;
  817. if (name)
  818. add_symbol (chip,name,dest,SYMBOL_PARAMETER);
  819. return desc;
  820. }
  821. struct dsp_scb_descriptor *
  822. cs46xx_dsp_create_scb (struct snd_cs46xx *chip, char * name, u32 * scb_data, u32 dest)
  823. {
  824. struct dsp_scb_descriptor * desc;
  825. desc = _map_scb (chip,name,dest);
  826. if (desc) {
  827. desc->data = scb_data;
  828. _dsp_create_scb(chip,scb_data,dest);
  829. } else {
  830. snd_printk(KERN_ERR "dsp_spos: failed to map SCB\n");
  831. }
  832. return desc;
  833. }
  834. static struct dsp_task_descriptor *
  835. cs46xx_dsp_create_task_tree (struct snd_cs46xx *chip, char * name, u32 * task_data,
  836. u32 dest, int size)
  837. {
  838. struct dsp_task_descriptor * desc;
  839. desc = _map_task_tree (chip,name,dest,size);
  840. if (desc) {
  841. desc->data = task_data;
  842. _dsp_create_task_tree(chip,task_data,dest,size);
  843. } else {
  844. snd_printk(KERN_ERR "dsp_spos: failed to map TASK\n");
  845. }
  846. return desc;
  847. }
  848. int cs46xx_dsp_scb_and_task_init (struct snd_cs46xx *chip)
  849. {
  850. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  851. struct dsp_symbol_entry * fg_task_tree_header_code;
  852. struct dsp_symbol_entry * task_tree_header_code;
  853. struct dsp_symbol_entry * task_tree_thread;
  854. struct dsp_symbol_entry * null_algorithm;
  855. struct dsp_symbol_entry * magic_snoop_task;
  856. struct dsp_scb_descriptor * timing_master_scb;
  857. struct dsp_scb_descriptor * codec_out_scb;
  858. struct dsp_scb_descriptor * codec_in_scb;
  859. struct dsp_scb_descriptor * src_task_scb;
  860. struct dsp_scb_descriptor * master_mix_scb;
  861. struct dsp_scb_descriptor * rear_mix_scb;
  862. struct dsp_scb_descriptor * record_mix_scb;
  863. struct dsp_scb_descriptor * write_back_scb;
  864. struct dsp_scb_descriptor * vari_decimate_scb;
  865. struct dsp_scb_descriptor * rear_codec_out_scb;
  866. struct dsp_scb_descriptor * clfe_codec_out_scb;
  867. struct dsp_scb_descriptor * magic_snoop_scb;
  868. int fifo_addr, fifo_span, valid_slots;
  869. static struct dsp_spos_control_block sposcb = {
  870. /* 0 */ HFG_TREE_SCB,HFG_STACK,
  871. /* 1 */ SPOSCB_ADDR,BG_TREE_SCB_ADDR,
  872. /* 2 */ DSP_SPOS_DC,0,
  873. /* 3 */ DSP_SPOS_DC,DSP_SPOS_DC,
  874. /* 4 */ 0,0,
  875. /* 5 */ DSP_SPOS_UU,0,
  876. /* 6 */ FG_TASK_HEADER_ADDR,0,
  877. /* 7 */ 0,0,
  878. /* 8 */ DSP_SPOS_UU,DSP_SPOS_DC,
  879. /* 9 */ 0,
  880. /* A */ 0,HFG_FIRST_EXECUTE_MODE,
  881. /* B */ DSP_SPOS_UU,DSP_SPOS_UU,
  882. /* C */ DSP_SPOS_DC_DC,
  883. /* D */ DSP_SPOS_DC_DC,
  884. /* E */ DSP_SPOS_DC_DC,
  885. /* F */ DSP_SPOS_DC_DC
  886. };
  887. cs46xx_dsp_create_task_tree(chip, "sposCB", (u32 *)&sposcb, SPOSCB_ADDR, 0x10);
  888. null_algorithm = cs46xx_dsp_lookup_symbol(chip, "NULLALGORITHM", SYMBOL_CODE);
  889. if (null_algorithm == NULL) {
  890. snd_printk(KERN_ERR "dsp_spos: symbol NULLALGORITHM not found\n");
  891. return -EIO;
  892. }
  893. fg_task_tree_header_code = cs46xx_dsp_lookup_symbol(chip, "FGTASKTREEHEADERCODE", SYMBOL_CODE);
  894. if (fg_task_tree_header_code == NULL) {
  895. snd_printk(KERN_ERR "dsp_spos: symbol FGTASKTREEHEADERCODE not found\n");
  896. return -EIO;
  897. }
  898. task_tree_header_code = cs46xx_dsp_lookup_symbol(chip, "TASKTREEHEADERCODE", SYMBOL_CODE);
  899. if (task_tree_header_code == NULL) {
  900. snd_printk(KERN_ERR "dsp_spos: symbol TASKTREEHEADERCODE not found\n");
  901. return -EIO;
  902. }
  903. task_tree_thread = cs46xx_dsp_lookup_symbol(chip, "TASKTREETHREAD", SYMBOL_CODE);
  904. if (task_tree_thread == NULL) {
  905. snd_printk(KERN_ERR "dsp_spos: symbol TASKTREETHREAD not found\n");
  906. return -EIO;
  907. }
  908. magic_snoop_task = cs46xx_dsp_lookup_symbol(chip, "MAGICSNOOPTASK", SYMBOL_CODE);
  909. if (magic_snoop_task == NULL) {
  910. snd_printk(KERN_ERR "dsp_spos: symbol MAGICSNOOPTASK not found\n");
  911. return -EIO;
  912. }
  913. {
  914. /* create the null SCB */
  915. static struct dsp_generic_scb null_scb = {
  916. { 0, 0, 0, 0 },
  917. { 0, 0, 0, 0, 0 },
  918. NULL_SCB_ADDR, NULL_SCB_ADDR,
  919. 0, 0, 0, 0, 0,
  920. {
  921. 0,0,
  922. 0,0,
  923. }
  924. };
  925. null_scb.entry_point = null_algorithm->address;
  926. ins->the_null_scb = cs46xx_dsp_create_scb(chip, "nullSCB", (u32 *)&null_scb, NULL_SCB_ADDR);
  927. ins->the_null_scb->task_entry = null_algorithm;
  928. ins->the_null_scb->sub_list_ptr = ins->the_null_scb;
  929. ins->the_null_scb->next_scb_ptr = ins->the_null_scb;
  930. ins->the_null_scb->parent_scb_ptr = NULL;
  931. cs46xx_dsp_proc_register_scb_desc (chip,ins->the_null_scb);
  932. }
  933. {
  934. /* setup foreground task tree */
  935. static struct dsp_task_tree_control_block fg_task_tree_hdr = {
  936. { FG_TASK_HEADER_ADDR | (DSP_SPOS_DC << 0x10),
  937. DSP_SPOS_DC_DC,
  938. DSP_SPOS_DC_DC,
  939. 0x0000,DSP_SPOS_DC,
  940. DSP_SPOS_DC, DSP_SPOS_DC,
  941. DSP_SPOS_DC_DC,
  942. DSP_SPOS_DC_DC,
  943. DSP_SPOS_DC_DC,
  944. DSP_SPOS_DC,DSP_SPOS_DC },
  945. {
  946. BG_TREE_SCB_ADDR,TIMINGMASTER_SCB_ADDR,
  947. 0,
  948. FG_TASK_HEADER_ADDR + TCBData,
  949. },
  950. {
  951. 4,0,
  952. 1,0,
  953. 2,SPOSCB_ADDR + HFGFlags,
  954. 0,0,
  955. FG_TASK_HEADER_ADDR + TCBContextBlk,FG_STACK
  956. },
  957. {
  958. DSP_SPOS_DC,0,
  959. DSP_SPOS_DC,DSP_SPOS_DC,
  960. DSP_SPOS_DC,DSP_SPOS_DC,
  961. DSP_SPOS_DC,DSP_SPOS_DC,
  962. DSP_SPOS_DC,DSP_SPOS_DC,
  963. DSP_SPOS_DCDC,
  964. DSP_SPOS_UU,1,
  965. DSP_SPOS_DCDC,
  966. DSP_SPOS_DCDC,
  967. DSP_SPOS_DCDC,
  968. DSP_SPOS_DCDC,
  969. DSP_SPOS_DCDC,
  970. DSP_SPOS_DCDC,
  971. DSP_SPOS_DCDC,
  972. DSP_SPOS_DCDC,
  973. DSP_SPOS_DCDC,
  974. DSP_SPOS_DCDC,
  975. DSP_SPOS_DCDC,
  976. DSP_SPOS_DCDC,
  977. DSP_SPOS_DCDC,
  978. DSP_SPOS_DCDC,
  979. DSP_SPOS_DCDC,
  980. DSP_SPOS_DCDC,
  981. DSP_SPOS_DCDC,
  982. DSP_SPOS_DCDC,
  983. DSP_SPOS_DCDC,
  984. DSP_SPOS_DCDC,
  985. DSP_SPOS_DCDC,
  986. DSP_SPOS_DCDC,
  987. DSP_SPOS_DCDC,
  988. DSP_SPOS_DCDC,
  989. DSP_SPOS_DCDC,
  990. DSP_SPOS_DCDC,
  991. DSP_SPOS_DCDC,
  992. DSP_SPOS_DCDC
  993. },
  994. {
  995. FG_INTERVAL_TIMER_PERIOD,DSP_SPOS_UU,
  996. 0,0
  997. }
  998. };
  999. fg_task_tree_hdr.links.entry_point = fg_task_tree_header_code->address;
  1000. fg_task_tree_hdr.context_blk.stack0 = task_tree_thread->address;
  1001. cs46xx_dsp_create_task_tree(chip,"FGtaskTreeHdr",(u32 *)&fg_task_tree_hdr,FG_TASK_HEADER_ADDR,0x35);
  1002. }
  1003. {
  1004. /* setup foreground task tree */
  1005. static struct dsp_task_tree_control_block bg_task_tree_hdr = {
  1006. { DSP_SPOS_DC_DC,
  1007. DSP_SPOS_DC_DC,
  1008. DSP_SPOS_DC_DC,
  1009. DSP_SPOS_DC, DSP_SPOS_DC,
  1010. DSP_SPOS_DC, DSP_SPOS_DC,
  1011. DSP_SPOS_DC_DC,
  1012. DSP_SPOS_DC_DC,
  1013. DSP_SPOS_DC_DC,
  1014. DSP_SPOS_DC,DSP_SPOS_DC },
  1015. {
  1016. NULL_SCB_ADDR,NULL_SCB_ADDR, /* Set up the background to do nothing */
  1017. 0,
  1018. BG_TREE_SCB_ADDR + TCBData,
  1019. },
  1020. {
  1021. 9999,0,
  1022. 0,1,
  1023. 0,SPOSCB_ADDR + HFGFlags,
  1024. 0,0,
  1025. BG_TREE_SCB_ADDR + TCBContextBlk,BG_STACK
  1026. },
  1027. {
  1028. DSP_SPOS_DC,0,
  1029. DSP_SPOS_DC,DSP_SPOS_DC,
  1030. DSP_SPOS_DC,DSP_SPOS_DC,
  1031. DSP_SPOS_DC,DSP_SPOS_DC,
  1032. DSP_SPOS_DC,DSP_SPOS_DC,
  1033. DSP_SPOS_DCDC,
  1034. DSP_SPOS_UU,1,
  1035. DSP_SPOS_DCDC,
  1036. DSP_SPOS_DCDC,
  1037. DSP_SPOS_DCDC,
  1038. DSP_SPOS_DCDC,
  1039. DSP_SPOS_DCDC,
  1040. DSP_SPOS_DCDC,
  1041. DSP_SPOS_DCDC,
  1042. DSP_SPOS_DCDC,
  1043. DSP_SPOS_DCDC,
  1044. DSP_SPOS_DCDC,
  1045. DSP_SPOS_DCDC,
  1046. DSP_SPOS_DCDC,
  1047. DSP_SPOS_DCDC,
  1048. DSP_SPOS_DCDC,
  1049. DSP_SPOS_DCDC,
  1050. DSP_SPOS_DCDC,
  1051. DSP_SPOS_DCDC,
  1052. DSP_SPOS_DCDC,
  1053. DSP_SPOS_DCDC,
  1054. DSP_SPOS_DCDC,
  1055. DSP_SPOS_DCDC,
  1056. DSP_SPOS_DCDC,
  1057. DSP_SPOS_DCDC,
  1058. DSP_SPOS_DCDC,
  1059. DSP_SPOS_DCDC,
  1060. DSP_SPOS_DCDC,
  1061. DSP_SPOS_DCDC,
  1062. DSP_SPOS_DCDC
  1063. },
  1064. {
  1065. BG_INTERVAL_TIMER_PERIOD,DSP_SPOS_UU,
  1066. 0,0
  1067. }
  1068. };
  1069. bg_task_tree_hdr.links.entry_point = task_tree_header_code->address;
  1070. bg_task_tree_hdr.context_blk.stack0 = task_tree_thread->address;
  1071. cs46xx_dsp_create_task_tree(chip,"BGtaskTreeHdr",(u32 *)&bg_task_tree_hdr,BG_TREE_SCB_ADDR,0x35);
  1072. }
  1073. /* create timing master SCB */
  1074. timing_master_scb = cs46xx_dsp_create_timing_master_scb(chip);
  1075. /* create the CODEC output task */
  1076. codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_I",0x0010,0x0000,
  1077. MASTERMIX_SCB_ADDR,
  1078. CODECOUT_SCB_ADDR,timing_master_scb,
  1079. SCB_ON_PARENT_SUBLIST_SCB);
  1080. if (!codec_out_scb) goto _fail_end;
  1081. /* create the master mix SCB */
  1082. master_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"MasterMixSCB",
  1083. MIX_SAMPLE_BUF1,MASTERMIX_SCB_ADDR,
  1084. codec_out_scb,
  1085. SCB_ON_PARENT_SUBLIST_SCB);
  1086. ins->master_mix_scb = master_mix_scb;
  1087. if (!master_mix_scb) goto _fail_end;
  1088. /* create codec in */
  1089. codec_in_scb = cs46xx_dsp_create_codec_in_scb(chip,"CodecInSCB",0x0010,0x00A0,
  1090. CODEC_INPUT_BUF1,
  1091. CODECIN_SCB_ADDR,codec_out_scb,
  1092. SCB_ON_PARENT_NEXT_SCB);
  1093. if (!codec_in_scb) goto _fail_end;
  1094. ins->codec_in_scb = codec_in_scb;
  1095. /* create write back scb */
  1096. write_back_scb = cs46xx_dsp_create_mix_to_ostream_scb(chip,"WriteBackSCB",
  1097. WRITE_BACK_BUF1,WRITE_BACK_SPB,
  1098. WRITEBACK_SCB_ADDR,
  1099. timing_master_scb,
  1100. SCB_ON_PARENT_NEXT_SCB);
  1101. if (!write_back_scb) goto _fail_end;
  1102. {
  1103. static struct dsp_mix2_ostream_spb mix2_ostream_spb = {
  1104. 0x00020000,
  1105. 0x0000ffff
  1106. };
  1107. if (!cs46xx_dsp_create_task_tree(chip, NULL,
  1108. (u32 *)&mix2_ostream_spb,
  1109. WRITE_BACK_SPB, 2))
  1110. goto _fail_end;
  1111. }
  1112. /* input sample converter */
  1113. vari_decimate_scb = cs46xx_dsp_create_vari_decimate_scb(chip,"VariDecimateSCB",
  1114. VARI_DECIMATE_BUF0,
  1115. VARI_DECIMATE_BUF1,
  1116. VARIDECIMATE_SCB_ADDR,
  1117. write_back_scb,
  1118. SCB_ON_PARENT_SUBLIST_SCB);
  1119. if (!vari_decimate_scb) goto _fail_end;
  1120. /* create the record mixer SCB */
  1121. record_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"RecordMixerSCB",
  1122. MIX_SAMPLE_BUF2,
  1123. RECORD_MIXER_SCB_ADDR,
  1124. vari_decimate_scb,
  1125. SCB_ON_PARENT_SUBLIST_SCB);
  1126. ins->record_mixer_scb = record_mix_scb;
  1127. if (!record_mix_scb) goto _fail_end;
  1128. valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
  1129. snd_assert (chip->nr_ac97_codecs == 1 || chip->nr_ac97_codecs == 2);
  1130. if (chip->nr_ac97_codecs == 1) {
  1131. /* output on slot 5 and 11
  1132. on primary CODEC */
  1133. fifo_addr = 0x20;
  1134. fifo_span = 0x60;
  1135. /* enable slot 5 and 11 */
  1136. valid_slots |= ACOSV_SLV5 | ACOSV_SLV11;
  1137. } else {
  1138. /* output on slot 7 and 8
  1139. on secondary CODEC */
  1140. fifo_addr = 0x40;
  1141. fifo_span = 0x10;
  1142. /* enable slot 7 and 8 */
  1143. valid_slots |= ACOSV_SLV7 | ACOSV_SLV8;
  1144. }
  1145. /* create CODEC tasklet for rear speakers output*/
  1146. rear_codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_Rear",fifo_span,fifo_addr,
  1147. REAR_MIXER_SCB_ADDR,
  1148. REAR_CODECOUT_SCB_ADDR,codec_in_scb,
  1149. SCB_ON_PARENT_NEXT_SCB);
  1150. if (!rear_codec_out_scb) goto _fail_end;
  1151. /* create the rear PCM channel mixer SCB */
  1152. rear_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"RearMixerSCB",
  1153. MIX_SAMPLE_BUF3,
  1154. REAR_MIXER_SCB_ADDR,
  1155. rear_codec_out_scb,
  1156. SCB_ON_PARENT_SUBLIST_SCB);
  1157. ins->rear_mix_scb = rear_mix_scb;
  1158. if (!rear_mix_scb) goto _fail_end;
  1159. if (chip->nr_ac97_codecs == 2) {
  1160. /* create CODEC tasklet for rear Center/LFE output
  1161. slot 6 and 9 on seconadry CODEC */
  1162. clfe_codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_CLFE",0x0030,0x0030,
  1163. CLFE_MIXER_SCB_ADDR,
  1164. CLFE_CODEC_SCB_ADDR,
  1165. rear_codec_out_scb,
  1166. SCB_ON_PARENT_NEXT_SCB);
  1167. if (!clfe_codec_out_scb) goto _fail_end;
  1168. /* create the rear PCM channel mixer SCB */
  1169. ins->center_lfe_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"CLFEMixerSCB",
  1170. MIX_SAMPLE_BUF4,
  1171. CLFE_MIXER_SCB_ADDR,
  1172. clfe_codec_out_scb,
  1173. SCB_ON_PARENT_SUBLIST_SCB);
  1174. if (!ins->center_lfe_mix_scb) goto _fail_end;
  1175. /* enable slot 6 and 9 */
  1176. valid_slots |= ACOSV_SLV6 | ACOSV_SLV9;
  1177. } else {
  1178. clfe_codec_out_scb = rear_codec_out_scb;
  1179. ins->center_lfe_mix_scb = rear_mix_scb;
  1180. }
  1181. /* enable slots depending on CODEC configuration */
  1182. snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
  1183. /* the magic snooper */
  1184. magic_snoop_scb = cs46xx_dsp_create_magic_snoop_scb (chip,"MagicSnoopSCB_I",OUTPUTSNOOP_SCB_ADDR,
  1185. OUTPUT_SNOOP_BUFFER,
  1186. codec_out_scb,
  1187. clfe_codec_out_scb,
  1188. SCB_ON_PARENT_NEXT_SCB);
  1189. if (!magic_snoop_scb) goto _fail_end;
  1190. ins->ref_snoop_scb = magic_snoop_scb;
  1191. /* SP IO access */
  1192. if (!cs46xx_dsp_create_spio_write_scb(chip,"SPIOWriteSCB",SPIOWRITE_SCB_ADDR,
  1193. magic_snoop_scb,
  1194. SCB_ON_PARENT_NEXT_SCB))
  1195. goto _fail_end;
  1196. /* SPDIF input sampel rate converter */
  1197. src_task_scb = cs46xx_dsp_create_src_task_scb(chip,"SrcTaskSCB_SPDIFI",
  1198. ins->spdif_in_sample_rate,
  1199. SRC_OUTPUT_BUF1,
  1200. SRC_DELAY_BUF1,SRCTASK_SCB_ADDR,
  1201. master_mix_scb,
  1202. SCB_ON_PARENT_SUBLIST_SCB,1);
  1203. if (!src_task_scb) goto _fail_end;
  1204. cs46xx_src_unlink(chip,src_task_scb);
  1205. /* NOTE: when we now how to detect the SPDIF input
  1206. sample rate we will use this SRC to adjust it */
  1207. ins->spdif_in_src = src_task_scb;
  1208. cs46xx_dsp_async_init(chip,timing_master_scb);
  1209. return 0;
  1210. _fail_end:
  1211. snd_printk(KERN_ERR "dsp_spos: failed to setup SCB's in DSP\n");
  1212. return -EINVAL;
  1213. }
  1214. static int cs46xx_dsp_async_init (struct snd_cs46xx *chip,
  1215. struct dsp_scb_descriptor * fg_entry)
  1216. {
  1217. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1218. struct dsp_symbol_entry * s16_async_codec_input_task;
  1219. struct dsp_symbol_entry * spdifo_task;
  1220. struct dsp_symbol_entry * spdifi_task;
  1221. struct dsp_scb_descriptor * spdifi_scb_desc, * spdifo_scb_desc, * async_codec_scb_desc;
  1222. s16_async_codec_input_task = cs46xx_dsp_lookup_symbol(chip, "S16_ASYNCCODECINPUTTASK", SYMBOL_CODE);
  1223. if (s16_async_codec_input_task == NULL) {
  1224. snd_printk(KERN_ERR "dsp_spos: symbol S16_ASYNCCODECINPUTTASK not found\n");
  1225. return -EIO;
  1226. }
  1227. spdifo_task = cs46xx_dsp_lookup_symbol(chip, "SPDIFOTASK", SYMBOL_CODE);
  1228. if (spdifo_task == NULL) {
  1229. snd_printk(KERN_ERR "dsp_spos: symbol SPDIFOTASK not found\n");
  1230. return -EIO;
  1231. }
  1232. spdifi_task = cs46xx_dsp_lookup_symbol(chip, "SPDIFITASK", SYMBOL_CODE);
  1233. if (spdifi_task == NULL) {
  1234. snd_printk(KERN_ERR "dsp_spos: symbol SPDIFITASK not found\n");
  1235. return -EIO;
  1236. }
  1237. {
  1238. /* 0xBC0 */
  1239. struct dsp_spdifoscb spdifo_scb = {
  1240. /* 0 */ DSP_SPOS_UUUU,
  1241. {
  1242. /* 1 */ 0xb0,
  1243. /* 2 */ 0,
  1244. /* 3 */ 0,
  1245. /* 4 */ 0,
  1246. },
  1247. /* NOTE: the SPDIF output task read samples in mono
  1248. format, the AsynchFGTxSCB task writes to buffer
  1249. in stereo format
  1250. */
  1251. /* 5 */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_256,
  1252. /* 6 */ ( SPDIFO_IP_OUTPUT_BUFFER1 << 0x10 ) | 0xFFFC,
  1253. /* 7 */ 0,0,
  1254. /* 8 */ 0,
  1255. /* 9 */ FG_TASK_HEADER_ADDR, NULL_SCB_ADDR,
  1256. /* A */ spdifo_task->address,
  1257. SPDIFO_SCB_INST + SPDIFOFIFOPointer,
  1258. {
  1259. /* B */ 0x0040, /*DSP_SPOS_UUUU,*/
  1260. /* C */ 0x20ff, /*DSP_SPOS_UUUU,*/
  1261. },
  1262. /* D */ 0x804c,0, /* SPDIFOFIFOPointer:SPDIFOStatRegAddr; */
  1263. /* E */ 0x0108,0x0001, /* SPDIFOStMoFormat:SPDIFOFIFOBaseAddr; */
  1264. /* F */ DSP_SPOS_UUUU /* SPDIFOFree; */
  1265. };
  1266. /* 0xBB0 */
  1267. struct dsp_spdifiscb spdifi_scb = {
  1268. /* 0 */ DSP_SPOS_UULO,DSP_SPOS_UUHI,
  1269. /* 1 */ 0,
  1270. /* 2 */ 0,
  1271. /* 3 */ 1,4000, /* SPDIFICountLimit SPDIFICount */
  1272. /* 4 */ DSP_SPOS_UUUU, /* SPDIFIStatusData */
  1273. /* 5 */ 0,DSP_SPOS_UUHI, /* StatusData, Free4 */
  1274. /* 6 */ DSP_SPOS_UUUU, /* Free3 */
  1275. /* 7 */ DSP_SPOS_UU,DSP_SPOS_DC, /* Free2 BitCount*/
  1276. /* 8 */ DSP_SPOS_UUUU, /* TempStatus */
  1277. /* 9 */ SPDIFO_SCB_INST, NULL_SCB_ADDR,
  1278. /* A */ spdifi_task->address,
  1279. SPDIFI_SCB_INST + SPDIFIFIFOPointer,
  1280. /* NOTE: The SPDIF input task write the sample in mono
  1281. format from the HW FIFO, the AsynchFGRxSCB task reads
  1282. them in stereo
  1283. */
  1284. /* B */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_128,
  1285. /* C */ (SPDIFI_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,
  1286. /* D */ 0x8048,0,
  1287. /* E */ 0x01f0,0x0001,
  1288. /* F */ DSP_SPOS_UUUU /* SPDIN_STATUS monitor */
  1289. };
  1290. /* 0xBA0 */
  1291. struct dsp_async_codec_input_scb async_codec_input_scb = {
  1292. /* 0 */ DSP_SPOS_UUUU,
  1293. /* 1 */ 0,
  1294. /* 2 */ 0,
  1295. /* 3 */ 1,4000,
  1296. /* 4 */ 0x0118,0x0001,
  1297. /* 5 */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_64,
  1298. /* 6 */ (ASYNC_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,
  1299. /* 7 */ DSP_SPOS_UU,0x3,
  1300. /* 8 */ DSP_SPOS_UUUU,
  1301. /* 9 */ SPDIFI_SCB_INST,NULL_SCB_ADDR,
  1302. /* A */ s16_async_codec_input_task->address,
  1303. HFG_TREE_SCB + AsyncCIOFIFOPointer,
  1304. /* B */ RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64,
  1305. /* C */ (ASYNC_IP_OUTPUT_BUFFER1 << 0x10), /*(ASYNC_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,*/
  1306. #ifdef UseASER1Input
  1307. /* short AsyncCIFIFOPointer:AsyncCIStatRegAddr;
  1308. Init. 0000:8042: for ASER1
  1309. 0000:8044: for ASER2 */
  1310. /* D */ 0x8042,0,
  1311. /* short AsyncCIStMoFormat:AsyncCIFIFOBaseAddr;
  1312. Init 1 stero:8050 ASER1
  1313. Init 0 mono:8070 ASER2
  1314. Init 1 Stereo : 0100 ASER1 (Set by script) */
  1315. /* E */ 0x0100,0x0001,
  1316. #endif
  1317. #ifdef UseASER2Input
  1318. /* short AsyncCIFIFOPointer:AsyncCIStatRegAddr;
  1319. Init. 0000:8042: for ASER1
  1320. 0000:8044: for ASER2 */
  1321. /* D */ 0x8044,0,
  1322. /* short AsyncCIStMoFormat:AsyncCIFIFOBaseAddr;
  1323. Init 1 stero:8050 ASER1
  1324. Init 0 mono:8070 ASER2
  1325. Init 1 Stereo : 0100 ASER1 (Set by script) */
  1326. /* E */ 0x0110,0x0001,
  1327. #endif
  1328. /* short AsyncCIOutputBufModulo:AsyncCIFree;
  1329. AsyncCIOutputBufModulo: The modulo size for
  1330. the output buffer of this task */
  1331. /* F */ 0, /* DSP_SPOS_UUUU */
  1332. };
  1333. spdifo_scb_desc = cs46xx_dsp_create_scb(chip,"SPDIFOSCB",(u32 *)&spdifo_scb,SPDIFO_SCB_INST);
  1334. snd_assert(spdifo_scb_desc, return -EIO);
  1335. spdifi_scb_desc = cs46xx_dsp_create_scb(chip,"SPDIFISCB",(u32 *)&spdifi_scb,SPDIFI_SCB_INST);
  1336. snd_assert(spdifi_scb_desc, return -EIO);
  1337. async_codec_scb_desc = cs46xx_dsp_create_scb(chip,"AsynCodecInputSCB",(u32 *)&async_codec_input_scb, HFG_TREE_SCB);
  1338. snd_assert(async_codec_scb_desc, return -EIO);
  1339. async_codec_scb_desc->parent_scb_ptr = NULL;
  1340. async_codec_scb_desc->next_scb_ptr = spdifi_scb_desc;
  1341. async_codec_scb_desc->sub_list_ptr = ins->the_null_scb;
  1342. async_codec_scb_desc->task_entry = s16_async_codec_input_task;
  1343. spdifi_scb_desc->parent_scb_ptr = async_codec_scb_desc;
  1344. spdifi_scb_desc->next_scb_ptr = spdifo_scb_desc;
  1345. spdifi_scb_desc->sub_list_ptr = ins->the_null_scb;
  1346. spdifi_scb_desc->task_entry = spdifi_task;
  1347. spdifo_scb_desc->parent_scb_ptr = spdifi_scb_desc;
  1348. spdifo_scb_desc->next_scb_ptr = fg_entry;
  1349. spdifo_scb_desc->sub_list_ptr = ins->the_null_scb;
  1350. spdifo_scb_desc->task_entry = spdifo_task;
  1351. /* this one is faked, as the parnet of SPDIFO task
  1352. is the FG task tree */
  1353. fg_entry->parent_scb_ptr = spdifo_scb_desc;
  1354. /* for proc fs */
  1355. cs46xx_dsp_proc_register_scb_desc (chip,spdifo_scb_desc);
  1356. cs46xx_dsp_proc_register_scb_desc (chip,spdifi_scb_desc);
  1357. cs46xx_dsp_proc_register_scb_desc (chip,async_codec_scb_desc);
  1358. /* Async MASTER ENABLE, affects both SPDIF input and output */
  1359. snd_cs46xx_pokeBA0(chip, BA0_ASER_MASTER, 0x1 );
  1360. }
  1361. return 0;
  1362. }
  1363. static void cs46xx_dsp_disable_spdif_hw (struct snd_cs46xx *chip)
  1364. {
  1365. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1366. /* set SPDIF output FIFO slot */
  1367. snd_cs46xx_pokeBA0(chip, BA0_ASER_FADDR, 0);
  1368. /* SPDIF output MASTER ENABLE */
  1369. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CONTROL, 0);
  1370. /* right and left validate bit */
  1371. /*cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);*/
  1372. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, 0x0);
  1373. /* clear fifo pointer */
  1374. cs46xx_poke_via_dsp (chip,SP_SPDIN_FIFOPTR, 0x0);
  1375. /* monitor state */
  1376. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_HW_ENABLED;
  1377. }
  1378. int cs46xx_dsp_enable_spdif_hw (struct snd_cs46xx *chip)
  1379. {
  1380. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1381. /* if hw-ctrl already enabled, turn off to reset logic ... */
  1382. cs46xx_dsp_disable_spdif_hw (chip);
  1383. udelay(50);
  1384. /* set SPDIF output FIFO slot */
  1385. snd_cs46xx_pokeBA0(chip, BA0_ASER_FADDR, ( 0x8000 | ((SP_SPDOUT_FIFO >> 4) << 4) ));
  1386. /* SPDIF output MASTER ENABLE */
  1387. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CONTROL, 0x80000000);
  1388. /* right and left validate bit */
  1389. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);
  1390. /* monitor state */
  1391. ins->spdif_status_out |= DSP_SPDIF_STATUS_HW_ENABLED;
  1392. return 0;
  1393. }
  1394. int cs46xx_dsp_enable_spdif_in (struct snd_cs46xx *chip)
  1395. {
  1396. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1397. /* turn on amplifier */
  1398. chip->active_ctrl(chip, 1);
  1399. chip->amplifier_ctrl(chip, 1);
  1400. snd_assert (ins->asynch_rx_scb == NULL,return -EINVAL);
  1401. snd_assert (ins->spdif_in_src != NULL,return -EINVAL);
  1402. mutex_lock(&chip->spos_mutex);
  1403. if ( ! (ins->spdif_status_out & DSP_SPDIF_STATUS_INPUT_CTRL_ENABLED) ) {
  1404. /* time countdown enable */
  1405. cs46xx_poke_via_dsp (chip,SP_ASER_COUNTDOWN, 0x80000005);
  1406. /* NOTE: 80000005 value is just magic. With all values
  1407. that I've tested this one seem to give the best result.
  1408. Got no explication why. (Benny) */
  1409. /* SPDIF input MASTER ENABLE */
  1410. cs46xx_poke_via_dsp (chip,SP_SPDIN_CONTROL, 0x800003ff);
  1411. ins->spdif_status_out |= DSP_SPDIF_STATUS_INPUT_CTRL_ENABLED;
  1412. }
  1413. /* create and start the asynchronous receiver SCB */
  1414. ins->asynch_rx_scb = cs46xx_dsp_create_asynch_fg_rx_scb(chip,"AsynchFGRxSCB",
  1415. ASYNCRX_SCB_ADDR,
  1416. SPDIFI_SCB_INST,
  1417. SPDIFI_IP_OUTPUT_BUFFER1,
  1418. ins->spdif_in_src,
  1419. SCB_ON_PARENT_SUBLIST_SCB);
  1420. spin_lock_irq(&chip->reg_lock);
  1421. /* reset SPDIF input sample buffer pointer */
  1422. /*snd_cs46xx_poke (chip, (SPDIFI_SCB_INST + 0x0c) << 2,
  1423. (SPDIFI_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC);*/
  1424. /* reset FIFO ptr */
  1425. /*cs46xx_poke_via_dsp (chip,SP_SPDIN_FIFOPTR, 0x0);*/
  1426. cs46xx_src_link(chip,ins->spdif_in_src);
  1427. /* unmute SRC volume */
  1428. cs46xx_dsp_scb_set_volume (chip,ins->spdif_in_src,0x7fff,0x7fff);
  1429. spin_unlock_irq(&chip->reg_lock);
  1430. /* set SPDIF input sample rate and unmute
  1431. NOTE: only 48khz support for SPDIF input this time */
  1432. /* cs46xx_dsp_set_src_sample_rate(chip,ins->spdif_in_src,48000); */
  1433. /* monitor state */
  1434. ins->spdif_status_in = 1;
  1435. mutex_unlock(&chip->spos_mutex);
  1436. return 0;
  1437. }
  1438. int cs46xx_dsp_disable_spdif_in (struct snd_cs46xx *chip)
  1439. {
  1440. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1441. snd_assert (ins->asynch_rx_scb != NULL, return -EINVAL);
  1442. snd_assert (ins->spdif_in_src != NULL,return -EINVAL);
  1443. mutex_lock(&chip->spos_mutex);
  1444. /* Remove the asynchronous receiver SCB */
  1445. cs46xx_dsp_remove_scb (chip,ins->asynch_rx_scb);
  1446. ins->asynch_rx_scb = NULL;
  1447. cs46xx_src_unlink(chip,ins->spdif_in_src);
  1448. /* monitor state */
  1449. ins->spdif_status_in = 0;
  1450. mutex_unlock(&chip->spos_mutex);
  1451. /* restore amplifier */
  1452. chip->active_ctrl(chip, -1);
  1453. chip->amplifier_ctrl(chip, -1);
  1454. return 0;
  1455. }
  1456. int cs46xx_dsp_enable_pcm_capture (struct snd_cs46xx *chip)
  1457. {
  1458. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1459. snd_assert (ins->pcm_input == NULL,return -EINVAL);
  1460. snd_assert (ins->ref_snoop_scb != NULL,return -EINVAL);
  1461. mutex_lock(&chip->spos_mutex);
  1462. ins->pcm_input = cs46xx_add_record_source(chip,ins->ref_snoop_scb,PCMSERIALIN_PCM_SCB_ADDR,
  1463. "PCMSerialInput_Wave");
  1464. mutex_unlock(&chip->spos_mutex);
  1465. return 0;
  1466. }
  1467. int cs46xx_dsp_disable_pcm_capture (struct snd_cs46xx *chip)
  1468. {
  1469. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1470. snd_assert (ins->pcm_input != NULL,return -EINVAL);
  1471. mutex_lock(&chip->spos_mutex);
  1472. cs46xx_dsp_remove_scb (chip,ins->pcm_input);
  1473. ins->pcm_input = NULL;
  1474. mutex_unlock(&chip->spos_mutex);
  1475. return 0;
  1476. }
  1477. int cs46xx_dsp_enable_adc_capture (struct snd_cs46xx *chip)
  1478. {
  1479. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1480. snd_assert (ins->adc_input == NULL,return -EINVAL);
  1481. snd_assert (ins->codec_in_scb != NULL,return -EINVAL);
  1482. mutex_lock(&chip->spos_mutex);
  1483. ins->adc_input = cs46xx_add_record_source(chip,ins->codec_in_scb,PCMSERIALIN_SCB_ADDR,
  1484. "PCMSerialInput_ADC");
  1485. mutex_unlock(&chip->spos_mutex);
  1486. return 0;
  1487. }
  1488. int cs46xx_dsp_disable_adc_capture (struct snd_cs46xx *chip)
  1489. {
  1490. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1491. snd_assert (ins->adc_input != NULL,return -EINVAL);
  1492. mutex_lock(&chip->spos_mutex);
  1493. cs46xx_dsp_remove_scb (chip,ins->adc_input);
  1494. ins->adc_input = NULL;
  1495. mutex_unlock(&chip->spos_mutex);
  1496. return 0;
  1497. }
  1498. int cs46xx_poke_via_dsp (struct snd_cs46xx *chip, u32 address, u32 data)
  1499. {
  1500. u32 temp;
  1501. int i;
  1502. /* santiy check the parameters. (These numbers are not 100% correct. They are
  1503. a rough guess from looking at the controller spec.) */
  1504. if (address < 0x8000 || address >= 0x9000)
  1505. return -EINVAL;
  1506. /* initialize the SP_IO_WRITE SCB with the data. */
  1507. temp = ( address << 16 ) | ( address & 0x0000FFFF); /* offset 0 <-- address2 : address1 */
  1508. snd_cs46xx_poke(chip,( SPIOWRITE_SCB_ADDR << 2), temp);
  1509. snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 1) << 2), data); /* offset 1 <-- data1 */
  1510. snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 2) << 2), data); /* offset 1 <-- data2 */
  1511. /* Poke this location to tell the task to start */
  1512. snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 6) << 2), SPIOWRITE_SCB_ADDR << 0x10);
  1513. /* Verify that the task ran */
  1514. for (i=0; i<25; i++) {
  1515. udelay(125);
  1516. temp = snd_cs46xx_peek(chip,((SPIOWRITE_SCB_ADDR + 6) << 2));
  1517. if (temp == 0x00000000)
  1518. break;
  1519. }
  1520. if (i == 25) {
  1521. snd_printk(KERN_ERR "dsp_spos: SPIOWriteTask not responding\n");
  1522. return -EBUSY;
  1523. }
  1524. return 0;
  1525. }
  1526. int cs46xx_dsp_set_dac_volume (struct snd_cs46xx * chip, u16 left, u16 right)
  1527. {
  1528. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1529. struct dsp_scb_descriptor * scb;
  1530. mutex_lock(&chip->spos_mutex);
  1531. /* main output */
  1532. scb = ins->master_mix_scb->sub_list_ptr;
  1533. while (scb != ins->the_null_scb) {
  1534. cs46xx_dsp_scb_set_volume (chip,scb,left,right);
  1535. scb = scb->next_scb_ptr;
  1536. }
  1537. /* rear output */
  1538. scb = ins->rear_mix_scb->sub_list_ptr;
  1539. while (scb != ins->the_null_scb) {
  1540. cs46xx_dsp_scb_set_volume (chip,scb,left,right);
  1541. scb = scb->next_scb_ptr;
  1542. }
  1543. ins->dac_volume_left = left;
  1544. ins->dac_volume_right = right;
  1545. mutex_unlock(&chip->spos_mutex);
  1546. return 0;
  1547. }
  1548. int cs46xx_dsp_set_iec958_volume (struct snd_cs46xx * chip, u16 left, u16 right)
  1549. {
  1550. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1551. mutex_lock(&chip->spos_mutex);
  1552. if (ins->asynch_rx_scb != NULL)
  1553. cs46xx_dsp_scb_set_volume (chip,ins->asynch_rx_scb,
  1554. left,right);
  1555. ins->spdif_input_volume_left = left;
  1556. ins->spdif_input_volume_right = right;
  1557. mutex_unlock(&chip->spos_mutex);
  1558. return 0;
  1559. }
  1560. #ifdef CONFIG_PM
  1561. int cs46xx_dsp_resume(struct snd_cs46xx * chip)
  1562. {
  1563. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1564. int i, err;
  1565. /* clear parameter, sample and code areas */
  1566. snd_cs46xx_clear_BA1(chip, DSP_PARAMETER_BYTE_OFFSET,
  1567. DSP_PARAMETER_BYTE_SIZE);
  1568. snd_cs46xx_clear_BA1(chip, DSP_SAMPLE_BYTE_OFFSET,
  1569. DSP_SAMPLE_BYTE_SIZE);
  1570. snd_cs46xx_clear_BA1(chip, DSP_CODE_BYTE_OFFSET, DSP_CODE_BYTE_SIZE);
  1571. for (i = 0; i < ins->nmodules; i++) {
  1572. struct dsp_module_desc *module = &ins->modules[i];
  1573. struct dsp_segment_desc *seg;
  1574. u32 doffset, dsize;
  1575. seg = get_segment_desc(module, SEGTYPE_SP_PARAMETER);
  1576. err = dsp_load_parameter(chip, seg);
  1577. if (err < 0)
  1578. return err;
  1579. seg = get_segment_desc(module, SEGTYPE_SP_SAMPLE);
  1580. err = dsp_load_sample(chip, seg);
  1581. if (err < 0)
  1582. return err;
  1583. seg = get_segment_desc(module, SEGTYPE_SP_PROGRAM);
  1584. if (!seg)
  1585. continue;
  1586. doffset = seg->offset * 4 + module->load_address * 4
  1587. + DSP_CODE_BYTE_OFFSET;
  1588. dsize = seg->size * 4;
  1589. err = snd_cs46xx_download(chip,
  1590. ins->code.data + module->load_address,
  1591. doffset, dsize);
  1592. if (err < 0)
  1593. return err;
  1594. }
  1595. for (i = 0; i < ins->ntask; i++) {
  1596. struct dsp_task_descriptor *t = &ins->tasks[i];
  1597. _dsp_create_task_tree(chip, t->data, t->address, t->size);
  1598. }
  1599. for (i = 0; i < ins->nscb; i++) {
  1600. struct dsp_scb_descriptor *s = &ins->scbs[i];
  1601. if (s->deleted)
  1602. continue;
  1603. _dsp_create_scb(chip, s->data, s->address);
  1604. }
  1605. return 0;
  1606. }
  1607. #endif