cs4231_lib.c 57 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  3. * Routines for control of CS4231(A)/CS4232/InterWave & compatible chips
  4. *
  5. * Bugs:
  6. * - sometimes record brokes playback with WSS portion of
  7. * Yamaha OPL3-SA3 chip
  8. * - CS4231 (GUS MAX) - still trouble with occasional noises
  9. * - broken initialization?
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. *
  25. */
  26. #include <sound/driver.h>
  27. #include <linux/delay.h>
  28. #include <linux/pm.h>
  29. #include <linux/init.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/slab.h>
  32. #include <linux/ioport.h>
  33. #include <sound/core.h>
  34. #include <sound/cs4231.h>
  35. #include <sound/pcm_params.h>
  36. #include <asm/io.h>
  37. #include <asm/dma.h>
  38. #include <asm/irq.h>
  39. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  40. MODULE_DESCRIPTION("Routines for control of CS4231(A)/CS4232/InterWave & compatible chips");
  41. MODULE_LICENSE("GPL");
  42. #if 0
  43. #define SNDRV_DEBUG_MCE
  44. #endif
  45. /*
  46. * Some variables
  47. */
  48. static unsigned char freq_bits[14] = {
  49. /* 5510 */ 0x00 | CS4231_XTAL2,
  50. /* 6620 */ 0x0E | CS4231_XTAL2,
  51. /* 8000 */ 0x00 | CS4231_XTAL1,
  52. /* 9600 */ 0x0E | CS4231_XTAL1,
  53. /* 11025 */ 0x02 | CS4231_XTAL2,
  54. /* 16000 */ 0x02 | CS4231_XTAL1,
  55. /* 18900 */ 0x04 | CS4231_XTAL2,
  56. /* 22050 */ 0x06 | CS4231_XTAL2,
  57. /* 27042 */ 0x04 | CS4231_XTAL1,
  58. /* 32000 */ 0x06 | CS4231_XTAL1,
  59. /* 33075 */ 0x0C | CS4231_XTAL2,
  60. /* 37800 */ 0x08 | CS4231_XTAL2,
  61. /* 44100 */ 0x0A | CS4231_XTAL2,
  62. /* 48000 */ 0x0C | CS4231_XTAL1
  63. };
  64. static unsigned int rates[14] = {
  65. 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
  66. 27042, 32000, 33075, 37800, 44100, 48000
  67. };
  68. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  69. .count = ARRAY_SIZE(rates),
  70. .list = rates,
  71. .mask = 0,
  72. };
  73. static int snd_cs4231_xrate(struct snd_pcm_runtime *runtime)
  74. {
  75. return snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  76. }
  77. static unsigned char snd_cs4231_original_image[32] =
  78. {
  79. 0x00, /* 00/00 - lic */
  80. 0x00, /* 01/01 - ric */
  81. 0x9f, /* 02/02 - la1ic */
  82. 0x9f, /* 03/03 - ra1ic */
  83. 0x9f, /* 04/04 - la2ic */
  84. 0x9f, /* 05/05 - ra2ic */
  85. 0xbf, /* 06/06 - loc */
  86. 0xbf, /* 07/07 - roc */
  87. 0x20, /* 08/08 - pdfr */
  88. CS4231_AUTOCALIB, /* 09/09 - ic */
  89. 0x00, /* 0a/10 - pc */
  90. 0x00, /* 0b/11 - ti */
  91. CS4231_MODE2, /* 0c/12 - mi */
  92. 0xfc, /* 0d/13 - lbc */
  93. 0x00, /* 0e/14 - pbru */
  94. 0x00, /* 0f/15 - pbrl */
  95. 0x80, /* 10/16 - afei */
  96. 0x01, /* 11/17 - afeii */
  97. 0x9f, /* 12/18 - llic */
  98. 0x9f, /* 13/19 - rlic */
  99. 0x00, /* 14/20 - tlb */
  100. 0x00, /* 15/21 - thb */
  101. 0x00, /* 16/22 - la3mic/reserved */
  102. 0x00, /* 17/23 - ra3mic/reserved */
  103. 0x00, /* 18/24 - afs */
  104. 0x00, /* 19/25 - lamoc/version */
  105. 0xcf, /* 1a/26 - mioc */
  106. 0x00, /* 1b/27 - ramoc/reserved */
  107. 0x20, /* 1c/28 - cdfr */
  108. 0x00, /* 1d/29 - res4 */
  109. 0x00, /* 1e/30 - cbru */
  110. 0x00, /* 1f/31 - cbrl */
  111. };
  112. /*
  113. * Basic I/O functions
  114. */
  115. static inline void cs4231_outb(struct snd_cs4231 *chip, u8 offset, u8 val)
  116. {
  117. outb(val, chip->port + offset);
  118. }
  119. static inline u8 cs4231_inb(struct snd_cs4231 *chip, u8 offset)
  120. {
  121. return inb(chip->port + offset);
  122. }
  123. static void snd_cs4231_wait(struct snd_cs4231 *chip)
  124. {
  125. int timeout;
  126. for (timeout = 250;
  127. timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
  128. timeout--)
  129. udelay(100);
  130. }
  131. static void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg,
  132. unsigned char mask, unsigned char value)
  133. {
  134. unsigned char tmp = (chip->image[reg] & mask) | value;
  135. snd_cs4231_wait(chip);
  136. #ifdef CONFIG_SND_DEBUG
  137. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  138. snd_printk("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
  139. #endif
  140. chip->image[reg] = tmp;
  141. if (!chip->calibrate_mute) {
  142. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  143. wmb();
  144. cs4231_outb(chip, CS4231P(REG), tmp);
  145. mb();
  146. }
  147. }
  148. static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg, unsigned char value)
  149. {
  150. int timeout;
  151. for (timeout = 250;
  152. timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
  153. timeout--)
  154. udelay(10);
  155. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  156. cs4231_outb(chip, CS4231P(REG), value);
  157. mb();
  158. }
  159. void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char value)
  160. {
  161. snd_cs4231_wait(chip);
  162. #ifdef CONFIG_SND_DEBUG
  163. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  164. snd_printk("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
  165. #endif
  166. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  167. cs4231_outb(chip, CS4231P(REG), value);
  168. chip->image[reg] = value;
  169. mb();
  170. snd_printdd("codec out - reg 0x%x = 0x%x\n",
  171. chip->mce_bit | reg, value);
  172. }
  173. unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg)
  174. {
  175. snd_cs4231_wait(chip);
  176. #ifdef CONFIG_SND_DEBUG
  177. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  178. snd_printk("in: auto calibration time out - reg = 0x%x\n", reg);
  179. #endif
  180. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
  181. mb();
  182. return cs4231_inb(chip, CS4231P(REG));
  183. }
  184. void snd_cs4236_ext_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char val)
  185. {
  186. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
  187. cs4231_outb(chip, CS4231P(REG), reg | (chip->image[CS4236_EXT_REG] & 0x01));
  188. cs4231_outb(chip, CS4231P(REG), val);
  189. chip->eimage[CS4236_REG(reg)] = val;
  190. #if 0
  191. printk("ext out : reg = 0x%x, val = 0x%x\n", reg, val);
  192. #endif
  193. }
  194. unsigned char snd_cs4236_ext_in(struct snd_cs4231 *chip, unsigned char reg)
  195. {
  196. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
  197. cs4231_outb(chip, CS4231P(REG), reg | (chip->image[CS4236_EXT_REG] & 0x01));
  198. #if 1
  199. return cs4231_inb(chip, CS4231P(REG));
  200. #else
  201. {
  202. unsigned char res;
  203. res = cs4231_inb(chip, CS4231P(REG));
  204. printk("ext in : reg = 0x%x, val = 0x%x\n", reg, res);
  205. return res;
  206. }
  207. #endif
  208. }
  209. #if 0
  210. static void snd_cs4231_debug(struct snd_cs4231 *chip)
  211. {
  212. printk("CS4231 REGS: INDEX = 0x%02x ", cs4231_inb(chip, CS4231P(REGSEL)));
  213. printk(" STATUS = 0x%02x\n", cs4231_inb(chip, CS4231P(STATUS)));
  214. printk(" 0x00: left input = 0x%02x ", snd_cs4231_in(chip, 0x00));
  215. printk(" 0x10: alt 1 (CFIG 2) = 0x%02x\n", snd_cs4231_in(chip, 0x10));
  216. printk(" 0x01: right input = 0x%02x ", snd_cs4231_in(chip, 0x01));
  217. printk(" 0x11: alt 2 (CFIG 3) = 0x%02x\n", snd_cs4231_in(chip, 0x11));
  218. printk(" 0x02: GF1 left input = 0x%02x ", snd_cs4231_in(chip, 0x02));
  219. printk(" 0x12: left line in = 0x%02x\n", snd_cs4231_in(chip, 0x12));
  220. printk(" 0x03: GF1 right input = 0x%02x ", snd_cs4231_in(chip, 0x03));
  221. printk(" 0x13: right line in = 0x%02x\n", snd_cs4231_in(chip, 0x13));
  222. printk(" 0x04: CD left input = 0x%02x ", snd_cs4231_in(chip, 0x04));
  223. printk(" 0x14: timer low = 0x%02x\n", snd_cs4231_in(chip, 0x14));
  224. printk(" 0x05: CD right input = 0x%02x ", snd_cs4231_in(chip, 0x05));
  225. printk(" 0x15: timer high = 0x%02x\n", snd_cs4231_in(chip, 0x15));
  226. printk(" 0x06: left output = 0x%02x ", snd_cs4231_in(chip, 0x06));
  227. printk(" 0x16: left MIC (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x16));
  228. printk(" 0x07: right output = 0x%02x ", snd_cs4231_in(chip, 0x07));
  229. printk(" 0x17: right MIC (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x17));
  230. printk(" 0x08: playback format = 0x%02x ", snd_cs4231_in(chip, 0x08));
  231. printk(" 0x18: IRQ status = 0x%02x\n", snd_cs4231_in(chip, 0x18));
  232. printk(" 0x09: iface (CFIG 1) = 0x%02x ", snd_cs4231_in(chip, 0x09));
  233. printk(" 0x19: left line out = 0x%02x\n", snd_cs4231_in(chip, 0x19));
  234. printk(" 0x0a: pin control = 0x%02x ", snd_cs4231_in(chip, 0x0a));
  235. printk(" 0x1a: mono control = 0x%02x\n", snd_cs4231_in(chip, 0x1a));
  236. printk(" 0x0b: init & status = 0x%02x ", snd_cs4231_in(chip, 0x0b));
  237. printk(" 0x1b: right line out = 0x%02x\n", snd_cs4231_in(chip, 0x1b));
  238. printk(" 0x0c: revision & mode = 0x%02x ", snd_cs4231_in(chip, 0x0c));
  239. printk(" 0x1c: record format = 0x%02x\n", snd_cs4231_in(chip, 0x1c));
  240. printk(" 0x0d: loopback = 0x%02x ", snd_cs4231_in(chip, 0x0d));
  241. printk(" 0x1d: var freq (PnP) = 0x%02x\n", snd_cs4231_in(chip, 0x1d));
  242. printk(" 0x0e: ply upr count = 0x%02x ", snd_cs4231_in(chip, 0x0e));
  243. printk(" 0x1e: ply lwr count = 0x%02x\n", snd_cs4231_in(chip, 0x1e));
  244. printk(" 0x0f: rec upr count = 0x%02x ", snd_cs4231_in(chip, 0x0f));
  245. printk(" 0x1f: rec lwr count = 0x%02x\n", snd_cs4231_in(chip, 0x1f));
  246. }
  247. #endif
  248. /*
  249. * CS4231 detection / MCE routines
  250. */
  251. static void snd_cs4231_busy_wait(struct snd_cs4231 *chip)
  252. {
  253. int timeout;
  254. /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
  255. for (timeout = 5; timeout > 0; timeout--)
  256. cs4231_inb(chip, CS4231P(REGSEL));
  257. /* end of cleanup sequence */
  258. for (timeout = 250;
  259. timeout > 0 && (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
  260. timeout--)
  261. udelay(10);
  262. }
  263. void snd_cs4231_mce_up(struct snd_cs4231 *chip)
  264. {
  265. unsigned long flags;
  266. int timeout;
  267. snd_cs4231_wait(chip);
  268. #ifdef CONFIG_SND_DEBUG
  269. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  270. snd_printk("mce_up - auto calibration time out (0)\n");
  271. #endif
  272. spin_lock_irqsave(&chip->reg_lock, flags);
  273. chip->mce_bit |= CS4231_MCE;
  274. timeout = cs4231_inb(chip, CS4231P(REGSEL));
  275. if (timeout == 0x80)
  276. snd_printk("mce_up [0x%lx]: serious init problem - codec still busy\n", chip->port);
  277. if (!(timeout & CS4231_MCE))
  278. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
  279. spin_unlock_irqrestore(&chip->reg_lock, flags);
  280. }
  281. void snd_cs4231_mce_down(struct snd_cs4231 *chip)
  282. {
  283. unsigned long flags;
  284. unsigned long end_time;
  285. int timeout;
  286. snd_cs4231_busy_wait(chip);
  287. #ifdef CONFIG_SND_DEBUG
  288. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  289. snd_printk("mce_down [0x%lx] - auto calibration time out (0)\n", (long)CS4231P(REGSEL));
  290. #endif
  291. spin_lock_irqsave(&chip->reg_lock, flags);
  292. chip->mce_bit &= ~CS4231_MCE;
  293. timeout = cs4231_inb(chip, CS4231P(REGSEL));
  294. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
  295. spin_unlock_irqrestore(&chip->reg_lock, flags);
  296. if (timeout == 0x80)
  297. snd_printk("mce_down [0x%lx]: serious init problem - codec still busy\n", chip->port);
  298. if ((timeout & CS4231_MCE) == 0 ||
  299. !(chip->hardware & (CS4231_HW_CS4231_MASK | CS4231_HW_CS4232_MASK))) {
  300. return;
  301. }
  302. snd_cs4231_busy_wait(chip);
  303. /*
  304. * Wait for (possible -- during init auto-calibration may not be set)
  305. * calibration process to start. Needs upto 5 sample periods on AD1848
  306. * which at the slowest possible rate of 5.5125 kHz means 907 us.
  307. */
  308. msleep(1);
  309. snd_printdd("(1) jiffies = %lu\n", jiffies);
  310. /* check condition up to 250 ms */
  311. end_time = jiffies + msecs_to_jiffies(250);
  312. while (snd_cs4231_in(chip, CS4231_TEST_INIT) &
  313. CS4231_CALIB_IN_PROGRESS) {
  314. if (time_after(jiffies, end_time)) {
  315. snd_printk(KERN_ERR "mce_down - "
  316. "auto calibration time out (2)\n");
  317. return;
  318. }
  319. msleep(1);
  320. }
  321. snd_printdd("(2) jiffies = %lu\n", jiffies);
  322. /* check condition up to 100 ms */
  323. end_time = jiffies + msecs_to_jiffies(100);
  324. while (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {
  325. if (time_after(jiffies, end_time)) {
  326. snd_printk(KERN_ERR "mce_down - auto calibration time out (3)\n");
  327. return;
  328. }
  329. msleep(1);
  330. }
  331. snd_printdd("(3) jiffies = %lu\n", jiffies);
  332. snd_printd("mce_down - exit = 0x%x\n", cs4231_inb(chip, CS4231P(REGSEL)));
  333. }
  334. static unsigned int snd_cs4231_get_count(unsigned char format, unsigned int size)
  335. {
  336. switch (format & 0xe0) {
  337. case CS4231_LINEAR_16:
  338. case CS4231_LINEAR_16_BIG:
  339. size >>= 1;
  340. break;
  341. case CS4231_ADPCM_16:
  342. return size >> 2;
  343. }
  344. if (format & CS4231_STEREO)
  345. size >>= 1;
  346. return size;
  347. }
  348. static int snd_cs4231_trigger(struct snd_pcm_substream *substream,
  349. int cmd)
  350. {
  351. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  352. int result = 0;
  353. unsigned int what;
  354. struct snd_pcm_substream *s;
  355. int do_start;
  356. #if 0
  357. printk("codec trigger!!! - what = %i, enable = %i, status = 0x%x\n", what, enable, cs4231_inb(chip, CS4231P(STATUS)));
  358. #endif
  359. switch (cmd) {
  360. case SNDRV_PCM_TRIGGER_START:
  361. case SNDRV_PCM_TRIGGER_RESUME:
  362. do_start = 1; break;
  363. case SNDRV_PCM_TRIGGER_STOP:
  364. case SNDRV_PCM_TRIGGER_SUSPEND:
  365. do_start = 0; break;
  366. default:
  367. return -EINVAL;
  368. }
  369. what = 0;
  370. snd_pcm_group_for_each_entry(s, substream) {
  371. if (s == chip->playback_substream) {
  372. what |= CS4231_PLAYBACK_ENABLE;
  373. snd_pcm_trigger_done(s, substream);
  374. } else if (s == chip->capture_substream) {
  375. what |= CS4231_RECORD_ENABLE;
  376. snd_pcm_trigger_done(s, substream);
  377. }
  378. }
  379. spin_lock(&chip->reg_lock);
  380. if (do_start) {
  381. chip->image[CS4231_IFACE_CTRL] |= what;
  382. if (chip->trigger)
  383. chip->trigger(chip, what, 1);
  384. } else {
  385. chip->image[CS4231_IFACE_CTRL] &= ~what;
  386. if (chip->trigger)
  387. chip->trigger(chip, what, 0);
  388. }
  389. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  390. spin_unlock(&chip->reg_lock);
  391. #if 0
  392. snd_cs4231_debug(chip);
  393. #endif
  394. return result;
  395. }
  396. /*
  397. * CODEC I/O
  398. */
  399. static unsigned char snd_cs4231_get_rate(unsigned int rate)
  400. {
  401. int i;
  402. for (i = 0; i < ARRAY_SIZE(rates); i++)
  403. if (rate == rates[i])
  404. return freq_bits[i];
  405. // snd_BUG();
  406. return freq_bits[ARRAY_SIZE(rates) - 1];
  407. }
  408. static unsigned char snd_cs4231_get_format(struct snd_cs4231 *chip,
  409. int format,
  410. int channels)
  411. {
  412. unsigned char rformat;
  413. rformat = CS4231_LINEAR_8;
  414. switch (format) {
  415. case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break;
  416. case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break;
  417. case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break;
  418. case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break;
  419. case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break;
  420. }
  421. if (channels > 1)
  422. rformat |= CS4231_STEREO;
  423. #if 0
  424. snd_printk("get_format: 0x%x (mode=0x%x)\n", format, mode);
  425. #endif
  426. return rformat;
  427. }
  428. static void snd_cs4231_calibrate_mute(struct snd_cs4231 *chip, int mute)
  429. {
  430. unsigned long flags;
  431. mute = mute ? 1 : 0;
  432. spin_lock_irqsave(&chip->reg_lock, flags);
  433. if (chip->calibrate_mute == mute) {
  434. spin_unlock_irqrestore(&chip->reg_lock, flags);
  435. return;
  436. }
  437. if (!mute) {
  438. snd_cs4231_dout(chip, CS4231_LEFT_INPUT, chip->image[CS4231_LEFT_INPUT]);
  439. snd_cs4231_dout(chip, CS4231_RIGHT_INPUT, chip->image[CS4231_RIGHT_INPUT]);
  440. snd_cs4231_dout(chip, CS4231_LOOPBACK, chip->image[CS4231_LOOPBACK]);
  441. }
  442. snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
  443. snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
  444. snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
  445. snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT, mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
  446. snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
  447. snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT, mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
  448. snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN, mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
  449. snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN, mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
  450. snd_cs4231_dout(chip, CS4231_MONO_CTRL, mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
  451. if (chip->hardware == CS4231_HW_INTERWAVE) {
  452. snd_cs4231_dout(chip, CS4231_LEFT_MIC_INPUT, mute ? 0x80 : chip->image[CS4231_LEFT_MIC_INPUT]);
  453. snd_cs4231_dout(chip, CS4231_RIGHT_MIC_INPUT, mute ? 0x80 : chip->image[CS4231_RIGHT_MIC_INPUT]);
  454. snd_cs4231_dout(chip, CS4231_LINE_LEFT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LINE_LEFT_OUTPUT]);
  455. snd_cs4231_dout(chip, CS4231_LINE_RIGHT_OUTPUT, mute ? 0x80 : chip->image[CS4231_LINE_RIGHT_OUTPUT]);
  456. }
  457. chip->calibrate_mute = mute;
  458. spin_unlock_irqrestore(&chip->reg_lock, flags);
  459. }
  460. static void snd_cs4231_playback_format(struct snd_cs4231 *chip,
  461. struct snd_pcm_hw_params *params,
  462. unsigned char pdfr)
  463. {
  464. unsigned long flags;
  465. int full_calib = 1;
  466. mutex_lock(&chip->mce_mutex);
  467. snd_cs4231_calibrate_mute(chip, 1);
  468. if (chip->hardware == CS4231_HW_CS4231A ||
  469. (chip->hardware & CS4231_HW_CS4232_MASK)) {
  470. spin_lock_irqsave(&chip->reg_lock, flags);
  471. if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (pdfr & 0x0f)) { /* rate is same? */
  472. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | 0x10);
  473. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT] = pdfr);
  474. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~0x10);
  475. udelay(100); /* Fixes audible clicks at least on GUS MAX */
  476. full_calib = 0;
  477. }
  478. spin_unlock_irqrestore(&chip->reg_lock, flags);
  479. }
  480. if (full_calib) {
  481. snd_cs4231_mce_up(chip);
  482. spin_lock_irqsave(&chip->reg_lock, flags);
  483. if (chip->hardware != CS4231_HW_INTERWAVE && !chip->single_dma) {
  484. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  485. (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
  486. (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
  487. pdfr);
  488. } else {
  489. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT] = pdfr);
  490. }
  491. spin_unlock_irqrestore(&chip->reg_lock, flags);
  492. if (chip->hardware == CS4231_HW_OPL3SA2)
  493. udelay(100); /* this seems to help */
  494. snd_cs4231_mce_down(chip);
  495. }
  496. snd_cs4231_calibrate_mute(chip, 0);
  497. mutex_unlock(&chip->mce_mutex);
  498. }
  499. static void snd_cs4231_capture_format(struct snd_cs4231 *chip,
  500. struct snd_pcm_hw_params *params,
  501. unsigned char cdfr)
  502. {
  503. unsigned long flags;
  504. int full_calib = 1;
  505. mutex_lock(&chip->mce_mutex);
  506. snd_cs4231_calibrate_mute(chip, 1);
  507. if (chip->hardware == CS4231_HW_CS4231A ||
  508. (chip->hardware & CS4231_HW_CS4232_MASK)) {
  509. spin_lock_irqsave(&chip->reg_lock, flags);
  510. if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (cdfr & 0x0f) || /* rate is same? */
  511. (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
  512. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | 0x20);
  513. snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT] = cdfr);
  514. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~0x20);
  515. full_calib = 0;
  516. }
  517. spin_unlock_irqrestore(&chip->reg_lock, flags);
  518. }
  519. if (full_calib) {
  520. snd_cs4231_mce_up(chip);
  521. spin_lock_irqsave(&chip->reg_lock, flags);
  522. if (chip->hardware != CS4231_HW_INTERWAVE) {
  523. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
  524. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  525. ((chip->single_dma ? cdfr : chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
  526. (cdfr & 0x0f));
  527. spin_unlock_irqrestore(&chip->reg_lock, flags);
  528. snd_cs4231_mce_down(chip);
  529. snd_cs4231_mce_up(chip);
  530. spin_lock_irqsave(&chip->reg_lock, flags);
  531. }
  532. }
  533. snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
  534. spin_unlock_irqrestore(&chip->reg_lock, flags);
  535. snd_cs4231_mce_down(chip);
  536. }
  537. snd_cs4231_calibrate_mute(chip, 0);
  538. mutex_unlock(&chip->mce_mutex);
  539. }
  540. /*
  541. * Timer interface
  542. */
  543. static unsigned long snd_cs4231_timer_resolution(struct snd_timer * timer)
  544. {
  545. struct snd_cs4231 *chip = snd_timer_chip(timer);
  546. if (chip->hardware & CS4231_HW_CS4236B_MASK)
  547. return 14467;
  548. else
  549. return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
  550. }
  551. static int snd_cs4231_timer_start(struct snd_timer * timer)
  552. {
  553. unsigned long flags;
  554. unsigned int ticks;
  555. struct snd_cs4231 *chip = snd_timer_chip(timer);
  556. spin_lock_irqsave(&chip->reg_lock, flags);
  557. ticks = timer->sticks;
  558. if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
  559. (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
  560. (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
  561. snd_cs4231_out(chip, CS4231_TIMER_HIGH, chip->image[CS4231_TIMER_HIGH] = (unsigned char) (ticks >> 8));
  562. snd_cs4231_out(chip, CS4231_TIMER_LOW, chip->image[CS4231_TIMER_LOW] = (unsigned char) ticks);
  563. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] | CS4231_TIMER_ENABLE);
  564. }
  565. spin_unlock_irqrestore(&chip->reg_lock, flags);
  566. return 0;
  567. }
  568. static int snd_cs4231_timer_stop(struct snd_timer * timer)
  569. {
  570. unsigned long flags;
  571. struct snd_cs4231 *chip = snd_timer_chip(timer);
  572. spin_lock_irqsave(&chip->reg_lock, flags);
  573. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE);
  574. spin_unlock_irqrestore(&chip->reg_lock, flags);
  575. return 0;
  576. }
  577. static void snd_cs4231_init(struct snd_cs4231 *chip)
  578. {
  579. unsigned long flags;
  580. snd_cs4231_mce_down(chip);
  581. #ifdef SNDRV_DEBUG_MCE
  582. snd_printk("init: (1)\n");
  583. #endif
  584. snd_cs4231_mce_up(chip);
  585. spin_lock_irqsave(&chip->reg_lock, flags);
  586. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  587. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO |
  588. CS4231_CALIB_MODE);
  589. chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
  590. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  591. spin_unlock_irqrestore(&chip->reg_lock, flags);
  592. snd_cs4231_mce_down(chip);
  593. #ifdef SNDRV_DEBUG_MCE
  594. snd_printk("init: (2)\n");
  595. #endif
  596. snd_cs4231_mce_up(chip);
  597. spin_lock_irqsave(&chip->reg_lock, flags);
  598. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
  599. spin_unlock_irqrestore(&chip->reg_lock, flags);
  600. snd_cs4231_mce_down(chip);
  601. #ifdef SNDRV_DEBUG_MCE
  602. snd_printk("init: (3) - afei = 0x%x\n", chip->image[CS4231_ALT_FEATURE_1]);
  603. #endif
  604. spin_lock_irqsave(&chip->reg_lock, flags);
  605. snd_cs4231_out(chip, CS4231_ALT_FEATURE_2, chip->image[CS4231_ALT_FEATURE_2]);
  606. spin_unlock_irqrestore(&chip->reg_lock, flags);
  607. snd_cs4231_mce_up(chip);
  608. spin_lock_irqsave(&chip->reg_lock, flags);
  609. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT]);
  610. spin_unlock_irqrestore(&chip->reg_lock, flags);
  611. snd_cs4231_mce_down(chip);
  612. #ifdef SNDRV_DEBUG_MCE
  613. snd_printk("init: (4)\n");
  614. #endif
  615. snd_cs4231_mce_up(chip);
  616. spin_lock_irqsave(&chip->reg_lock, flags);
  617. snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
  618. spin_unlock_irqrestore(&chip->reg_lock, flags);
  619. snd_cs4231_mce_down(chip);
  620. #ifdef SNDRV_DEBUG_MCE
  621. snd_printk("init: (5)\n");
  622. #endif
  623. }
  624. static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode)
  625. {
  626. unsigned long flags;
  627. mutex_lock(&chip->open_mutex);
  628. if ((chip->mode & mode) ||
  629. ((chip->mode & CS4231_MODE_OPEN) && chip->single_dma)) {
  630. mutex_unlock(&chip->open_mutex);
  631. return -EAGAIN;
  632. }
  633. if (chip->mode & CS4231_MODE_OPEN) {
  634. chip->mode |= mode;
  635. mutex_unlock(&chip->open_mutex);
  636. return 0;
  637. }
  638. /* ok. now enable and ack CODEC IRQ */
  639. spin_lock_irqsave(&chip->reg_lock, flags);
  640. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  641. CS4231_RECORD_IRQ |
  642. CS4231_TIMER_IRQ);
  643. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  644. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  645. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  646. chip->image[CS4231_PIN_CTRL] |= CS4231_IRQ_ENABLE;
  647. snd_cs4231_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
  648. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  649. CS4231_RECORD_IRQ |
  650. CS4231_TIMER_IRQ);
  651. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  652. spin_unlock_irqrestore(&chip->reg_lock, flags);
  653. chip->mode = mode;
  654. mutex_unlock(&chip->open_mutex);
  655. return 0;
  656. }
  657. static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode)
  658. {
  659. unsigned long flags;
  660. mutex_lock(&chip->open_mutex);
  661. chip->mode &= ~mode;
  662. if (chip->mode & CS4231_MODE_OPEN) {
  663. mutex_unlock(&chip->open_mutex);
  664. return;
  665. }
  666. snd_cs4231_calibrate_mute(chip, 1);
  667. /* disable IRQ */
  668. spin_lock_irqsave(&chip->reg_lock, flags);
  669. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  670. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  671. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  672. chip->image[CS4231_PIN_CTRL] &= ~CS4231_IRQ_ENABLE;
  673. snd_cs4231_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
  674. /* now disable record & playback */
  675. if (chip->image[CS4231_IFACE_CTRL] & (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  676. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
  677. spin_unlock_irqrestore(&chip->reg_lock, flags);
  678. snd_cs4231_mce_up(chip);
  679. spin_lock_irqsave(&chip->reg_lock, flags);
  680. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  681. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
  682. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  683. spin_unlock_irqrestore(&chip->reg_lock, flags);
  684. snd_cs4231_mce_down(chip);
  685. spin_lock_irqsave(&chip->reg_lock, flags);
  686. }
  687. /* clear IRQ again */
  688. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  689. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  690. cs4231_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
  691. spin_unlock_irqrestore(&chip->reg_lock, flags);
  692. snd_cs4231_calibrate_mute(chip, 0);
  693. chip->mode = 0;
  694. mutex_unlock(&chip->open_mutex);
  695. }
  696. /*
  697. * timer open/close
  698. */
  699. static int snd_cs4231_timer_open(struct snd_timer * timer)
  700. {
  701. struct snd_cs4231 *chip = snd_timer_chip(timer);
  702. snd_cs4231_open(chip, CS4231_MODE_TIMER);
  703. return 0;
  704. }
  705. static int snd_cs4231_timer_close(struct snd_timer * timer)
  706. {
  707. struct snd_cs4231 *chip = snd_timer_chip(timer);
  708. snd_cs4231_close(chip, CS4231_MODE_TIMER);
  709. return 0;
  710. }
  711. static struct snd_timer_hardware snd_cs4231_timer_table =
  712. {
  713. .flags = SNDRV_TIMER_HW_AUTO,
  714. .resolution = 9945,
  715. .ticks = 65535,
  716. .open = snd_cs4231_timer_open,
  717. .close = snd_cs4231_timer_close,
  718. .c_resolution = snd_cs4231_timer_resolution,
  719. .start = snd_cs4231_timer_start,
  720. .stop = snd_cs4231_timer_stop,
  721. };
  722. /*
  723. * ok.. exported functions..
  724. */
  725. static int snd_cs4231_playback_hw_params(struct snd_pcm_substream *substream,
  726. struct snd_pcm_hw_params *hw_params)
  727. {
  728. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  729. unsigned char new_pdfr;
  730. int err;
  731. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  732. return err;
  733. new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params), params_channels(hw_params)) |
  734. snd_cs4231_get_rate(params_rate(hw_params));
  735. chip->set_playback_format(chip, hw_params, new_pdfr);
  736. return 0;
  737. }
  738. static int snd_cs4231_playback_hw_free(struct snd_pcm_substream *substream)
  739. {
  740. return snd_pcm_lib_free_pages(substream);
  741. }
  742. static int snd_cs4231_playback_prepare(struct snd_pcm_substream *substream)
  743. {
  744. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  745. struct snd_pcm_runtime *runtime = substream->runtime;
  746. unsigned long flags;
  747. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  748. unsigned int count = snd_pcm_lib_period_bytes(substream);
  749. spin_lock_irqsave(&chip->reg_lock, flags);
  750. chip->p_dma_size = size;
  751. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO);
  752. snd_dma_program(chip->dma1, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT);
  753. count = snd_cs4231_get_count(chip->image[CS4231_PLAYBK_FORMAT], count) - 1;
  754. snd_cs4231_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
  755. snd_cs4231_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));
  756. spin_unlock_irqrestore(&chip->reg_lock, flags);
  757. #if 0
  758. snd_cs4231_debug(chip);
  759. #endif
  760. return 0;
  761. }
  762. static int snd_cs4231_capture_hw_params(struct snd_pcm_substream *substream,
  763. struct snd_pcm_hw_params *hw_params)
  764. {
  765. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  766. unsigned char new_cdfr;
  767. int err;
  768. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  769. return err;
  770. new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params), params_channels(hw_params)) |
  771. snd_cs4231_get_rate(params_rate(hw_params));
  772. chip->set_capture_format(chip, hw_params, new_cdfr);
  773. return 0;
  774. }
  775. static int snd_cs4231_capture_hw_free(struct snd_pcm_substream *substream)
  776. {
  777. return snd_pcm_lib_free_pages(substream);
  778. }
  779. static int snd_cs4231_capture_prepare(struct snd_pcm_substream *substream)
  780. {
  781. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  782. struct snd_pcm_runtime *runtime = substream->runtime;
  783. unsigned long flags;
  784. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  785. unsigned int count = snd_pcm_lib_period_bytes(substream);
  786. spin_lock_irqsave(&chip->reg_lock, flags);
  787. chip->c_dma_size = size;
  788. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
  789. snd_dma_program(chip->dma2, runtime->dma_addr, size, DMA_MODE_READ | DMA_AUTOINIT);
  790. count = snd_cs4231_get_count(chip->image[CS4231_REC_FORMAT], count) - 1;
  791. if (chip->single_dma && chip->hardware != CS4231_HW_INTERWAVE) {
  792. snd_cs4231_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
  793. snd_cs4231_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));
  794. } else {
  795. snd_cs4231_out(chip, CS4231_REC_LWR_CNT, (unsigned char) count);
  796. snd_cs4231_out(chip, CS4231_REC_UPR_CNT, (unsigned char) (count >> 8));
  797. }
  798. spin_unlock_irqrestore(&chip->reg_lock, flags);
  799. return 0;
  800. }
  801. static void snd_cs4231_overrange(struct snd_cs4231 *chip)
  802. {
  803. unsigned long flags;
  804. unsigned char res;
  805. spin_lock_irqsave(&chip->reg_lock, flags);
  806. res = snd_cs4231_in(chip, CS4231_TEST_INIT);
  807. spin_unlock_irqrestore(&chip->reg_lock, flags);
  808. if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */
  809. chip->capture_substream->runtime->overrange++;
  810. }
  811. irqreturn_t snd_cs4231_interrupt(int irq, void *dev_id)
  812. {
  813. struct snd_cs4231 *chip = dev_id;
  814. unsigned char status;
  815. status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
  816. if (status & CS4231_TIMER_IRQ) {
  817. if (chip->timer)
  818. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  819. }
  820. if (chip->single_dma && chip->hardware != CS4231_HW_INTERWAVE) {
  821. if (status & CS4231_PLAYBACK_IRQ) {
  822. if (chip->mode & CS4231_MODE_PLAY) {
  823. if (chip->playback_substream)
  824. snd_pcm_period_elapsed(chip->playback_substream);
  825. }
  826. if (chip->mode & CS4231_MODE_RECORD) {
  827. if (chip->capture_substream) {
  828. snd_cs4231_overrange(chip);
  829. snd_pcm_period_elapsed(chip->capture_substream);
  830. }
  831. }
  832. }
  833. } else {
  834. if (status & CS4231_PLAYBACK_IRQ) {
  835. if (chip->playback_substream)
  836. snd_pcm_period_elapsed(chip->playback_substream);
  837. }
  838. if (status & CS4231_RECORD_IRQ) {
  839. if (chip->capture_substream) {
  840. snd_cs4231_overrange(chip);
  841. snd_pcm_period_elapsed(chip->capture_substream);
  842. }
  843. }
  844. }
  845. spin_lock(&chip->reg_lock);
  846. snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
  847. spin_unlock(&chip->reg_lock);
  848. return IRQ_HANDLED;
  849. }
  850. static snd_pcm_uframes_t snd_cs4231_playback_pointer(struct snd_pcm_substream *substream)
  851. {
  852. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  853. size_t ptr;
  854. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
  855. return 0;
  856. ptr = snd_dma_pointer(chip->dma1, chip->p_dma_size);
  857. return bytes_to_frames(substream->runtime, ptr);
  858. }
  859. static snd_pcm_uframes_t snd_cs4231_capture_pointer(struct snd_pcm_substream *substream)
  860. {
  861. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  862. size_t ptr;
  863. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
  864. return 0;
  865. ptr = snd_dma_pointer(chip->dma2, chip->c_dma_size);
  866. return bytes_to_frames(substream->runtime, ptr);
  867. }
  868. /*
  869. */
  870. static int snd_cs4231_probe(struct snd_cs4231 *chip)
  871. {
  872. unsigned long flags;
  873. int i, id, rev;
  874. unsigned char *ptr;
  875. unsigned int hw;
  876. #if 0
  877. snd_cs4231_debug(chip);
  878. #endif
  879. id = 0;
  880. for (i = 0; i < 50; i++) {
  881. mb();
  882. if (cs4231_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
  883. udelay(2000);
  884. else {
  885. spin_lock_irqsave(&chip->reg_lock, flags);
  886. snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
  887. id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
  888. spin_unlock_irqrestore(&chip->reg_lock, flags);
  889. if (id == 0x0a)
  890. break; /* this is valid value */
  891. }
  892. }
  893. snd_printdd("cs4231: port = 0x%lx, id = 0x%x\n", chip->port, id);
  894. if (id != 0x0a)
  895. return -ENODEV; /* no valid device found */
  896. if (((hw = chip->hardware) & CS4231_HW_TYPE_MASK) == CS4231_HW_DETECT) {
  897. rev = snd_cs4231_in(chip, CS4231_VERSION) & 0xe7;
  898. snd_printdd("CS4231: VERSION (I25) = 0x%x\n", rev);
  899. if (rev == 0x80) {
  900. unsigned char tmp = snd_cs4231_in(chip, 23);
  901. snd_cs4231_out(chip, 23, ~tmp);
  902. if (snd_cs4231_in(chip, 23) != tmp)
  903. chip->hardware = CS4231_HW_AD1845;
  904. else
  905. chip->hardware = CS4231_HW_CS4231;
  906. } else if (rev == 0xa0) {
  907. chip->hardware = CS4231_HW_CS4231A;
  908. } else if (rev == 0xa2) {
  909. chip->hardware = CS4231_HW_CS4232;
  910. } else if (rev == 0xb2) {
  911. chip->hardware = CS4231_HW_CS4232A;
  912. } else if (rev == 0x83) {
  913. chip->hardware = CS4231_HW_CS4236;
  914. } else if (rev == 0x03) {
  915. chip->hardware = CS4231_HW_CS4236B;
  916. } else {
  917. snd_printk("unknown CS chip with version 0x%x\n", rev);
  918. return -ENODEV; /* unknown CS4231 chip? */
  919. }
  920. }
  921. spin_lock_irqsave(&chip->reg_lock, flags);
  922. cs4231_inb(chip, CS4231P(STATUS)); /* clear any pendings IRQ */
  923. cs4231_outb(chip, CS4231P(STATUS), 0);
  924. mb();
  925. spin_unlock_irqrestore(&chip->reg_lock, flags);
  926. chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
  927. switch (chip->hardware) {
  928. case CS4231_HW_INTERWAVE:
  929. chip->image[CS4231_MISC_INFO] = CS4231_IW_MODE3;
  930. break;
  931. case CS4231_HW_CS4235:
  932. case CS4231_HW_CS4236B:
  933. case CS4231_HW_CS4237B:
  934. case CS4231_HW_CS4238B:
  935. case CS4231_HW_CS4239:
  936. if (hw == CS4231_HW_DETECT3)
  937. chip->image[CS4231_MISC_INFO] = CS4231_4236_MODE3;
  938. else
  939. chip->hardware = CS4231_HW_CS4236;
  940. break;
  941. }
  942. chip->image[CS4231_IFACE_CTRL] =
  943. (chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA) |
  944. (chip->single_dma ? CS4231_SINGLE_DMA : 0);
  945. chip->image[CS4231_ALT_FEATURE_1] = 0x80;
  946. chip->image[CS4231_ALT_FEATURE_2] = chip->hardware == CS4231_HW_INTERWAVE ? 0xc2 : 0x01;
  947. ptr = (unsigned char *) &chip->image;
  948. snd_cs4231_mce_down(chip);
  949. spin_lock_irqsave(&chip->reg_lock, flags);
  950. for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */
  951. snd_cs4231_out(chip, i, *ptr++);
  952. spin_unlock_irqrestore(&chip->reg_lock, flags);
  953. snd_cs4231_mce_up(chip);
  954. snd_cs4231_mce_down(chip);
  955. mdelay(2);
  956. /* ok.. try check hardware version for CS4236+ chips */
  957. if ((hw & CS4231_HW_TYPE_MASK) == CS4231_HW_DETECT) {
  958. if (chip->hardware == CS4231_HW_CS4236B) {
  959. rev = snd_cs4236_ext_in(chip, CS4236_VERSION);
  960. snd_cs4236_ext_out(chip, CS4236_VERSION, 0xff);
  961. id = snd_cs4236_ext_in(chip, CS4236_VERSION);
  962. snd_cs4236_ext_out(chip, CS4236_VERSION, rev);
  963. snd_printdd("CS4231: ext version; rev = 0x%x, id = 0x%x\n", rev, id);
  964. if ((id & 0x1f) == 0x1d) { /* CS4235 */
  965. chip->hardware = CS4231_HW_CS4235;
  966. switch (id >> 5) {
  967. case 4:
  968. case 5:
  969. case 6:
  970. break;
  971. default:
  972. snd_printk("unknown CS4235 chip (enhanced version = 0x%x)\n", id);
  973. }
  974. } else if ((id & 0x1f) == 0x0b) { /* CS4236/B */
  975. switch (id >> 5) {
  976. case 4:
  977. case 5:
  978. case 6:
  979. case 7:
  980. chip->hardware = CS4231_HW_CS4236B;
  981. break;
  982. default:
  983. snd_printk("unknown CS4236 chip (enhanced version = 0x%x)\n", id);
  984. }
  985. } else if ((id & 0x1f) == 0x08) { /* CS4237B */
  986. chip->hardware = CS4231_HW_CS4237B;
  987. switch (id >> 5) {
  988. case 4:
  989. case 5:
  990. case 6:
  991. case 7:
  992. break;
  993. default:
  994. snd_printk("unknown CS4237B chip (enhanced version = 0x%x)\n", id);
  995. }
  996. } else if ((id & 0x1f) == 0x09) { /* CS4238B */
  997. chip->hardware = CS4231_HW_CS4238B;
  998. switch (id >> 5) {
  999. case 5:
  1000. case 6:
  1001. case 7:
  1002. break;
  1003. default:
  1004. snd_printk("unknown CS4238B chip (enhanced version = 0x%x)\n", id);
  1005. }
  1006. } else if ((id & 0x1f) == 0x1e) { /* CS4239 */
  1007. chip->hardware = CS4231_HW_CS4239;
  1008. switch (id >> 5) {
  1009. case 4:
  1010. case 5:
  1011. case 6:
  1012. break;
  1013. default:
  1014. snd_printk("unknown CS4239 chip (enhanced version = 0x%x)\n", id);
  1015. }
  1016. } else {
  1017. snd_printk("unknown CS4236/CS423xB chip (enhanced version = 0x%x)\n", id);
  1018. }
  1019. }
  1020. }
  1021. return 0; /* all things are ok.. */
  1022. }
  1023. /*
  1024. */
  1025. static struct snd_pcm_hardware snd_cs4231_playback =
  1026. {
  1027. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1028. SNDRV_PCM_INFO_MMAP_VALID |
  1029. SNDRV_PCM_INFO_RESUME |
  1030. SNDRV_PCM_INFO_SYNC_START),
  1031. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
  1032. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
  1033. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  1034. .rate_min = 5510,
  1035. .rate_max = 48000,
  1036. .channels_min = 1,
  1037. .channels_max = 2,
  1038. .buffer_bytes_max = (128*1024),
  1039. .period_bytes_min = 64,
  1040. .period_bytes_max = (128*1024),
  1041. .periods_min = 1,
  1042. .periods_max = 1024,
  1043. .fifo_size = 0,
  1044. };
  1045. static struct snd_pcm_hardware snd_cs4231_capture =
  1046. {
  1047. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1048. SNDRV_PCM_INFO_MMAP_VALID |
  1049. SNDRV_PCM_INFO_RESUME |
  1050. SNDRV_PCM_INFO_SYNC_START),
  1051. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
  1052. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
  1053. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  1054. .rate_min = 5510,
  1055. .rate_max = 48000,
  1056. .channels_min = 1,
  1057. .channels_max = 2,
  1058. .buffer_bytes_max = (128*1024),
  1059. .period_bytes_min = 64,
  1060. .period_bytes_max = (128*1024),
  1061. .periods_min = 1,
  1062. .periods_max = 1024,
  1063. .fifo_size = 0,
  1064. };
  1065. /*
  1066. */
  1067. static int snd_cs4231_playback_open(struct snd_pcm_substream *substream)
  1068. {
  1069. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1070. struct snd_pcm_runtime *runtime = substream->runtime;
  1071. int err;
  1072. runtime->hw = snd_cs4231_playback;
  1073. /* hardware bug in InterWave chipset */
  1074. if (chip->hardware == CS4231_HW_INTERWAVE && chip->dma1 > 3)
  1075. runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_MU_LAW;
  1076. /* hardware limitation of cheap chips */
  1077. if (chip->hardware == CS4231_HW_CS4235 ||
  1078. chip->hardware == CS4231_HW_CS4239)
  1079. runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;
  1080. snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.buffer_bytes_max);
  1081. snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.period_bytes_max);
  1082. if (chip->claim_dma) {
  1083. if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma1)) < 0)
  1084. return err;
  1085. }
  1086. if ((err = snd_cs4231_open(chip, CS4231_MODE_PLAY)) < 0) {
  1087. if (chip->release_dma)
  1088. chip->release_dma(chip, chip->dma_private_data, chip->dma1);
  1089. snd_free_pages(runtime->dma_area, runtime->dma_bytes);
  1090. return err;
  1091. }
  1092. chip->playback_substream = substream;
  1093. snd_pcm_set_sync(substream);
  1094. chip->rate_constraint(runtime);
  1095. return 0;
  1096. }
  1097. static int snd_cs4231_capture_open(struct snd_pcm_substream *substream)
  1098. {
  1099. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1100. struct snd_pcm_runtime *runtime = substream->runtime;
  1101. int err;
  1102. runtime->hw = snd_cs4231_capture;
  1103. /* hardware limitation of cheap chips */
  1104. if (chip->hardware == CS4231_HW_CS4235 ||
  1105. chip->hardware == CS4231_HW_CS4239)
  1106. runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;
  1107. snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.buffer_bytes_max);
  1108. snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.period_bytes_max);
  1109. if (chip->claim_dma) {
  1110. if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma2)) < 0)
  1111. return err;
  1112. }
  1113. if ((err = snd_cs4231_open(chip, CS4231_MODE_RECORD)) < 0) {
  1114. if (chip->release_dma)
  1115. chip->release_dma(chip, chip->dma_private_data, chip->dma2);
  1116. snd_free_pages(runtime->dma_area, runtime->dma_bytes);
  1117. return err;
  1118. }
  1119. chip->capture_substream = substream;
  1120. snd_pcm_set_sync(substream);
  1121. chip->rate_constraint(runtime);
  1122. return 0;
  1123. }
  1124. static int snd_cs4231_playback_close(struct snd_pcm_substream *substream)
  1125. {
  1126. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1127. chip->playback_substream = NULL;
  1128. snd_cs4231_close(chip, CS4231_MODE_PLAY);
  1129. return 0;
  1130. }
  1131. static int snd_cs4231_capture_close(struct snd_pcm_substream *substream)
  1132. {
  1133. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1134. chip->capture_substream = NULL;
  1135. snd_cs4231_close(chip, CS4231_MODE_RECORD);
  1136. return 0;
  1137. }
  1138. #ifdef CONFIG_PM
  1139. /* lowlevel suspend callback for CS4231 */
  1140. static void snd_cs4231_suspend(struct snd_cs4231 *chip)
  1141. {
  1142. int reg;
  1143. unsigned long flags;
  1144. snd_pcm_suspend_all(chip->pcm);
  1145. spin_lock_irqsave(&chip->reg_lock, flags);
  1146. for (reg = 0; reg < 32; reg++)
  1147. chip->image[reg] = snd_cs4231_in(chip, reg);
  1148. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1149. }
  1150. /* lowlevel resume callback for CS4231 */
  1151. static void snd_cs4231_resume(struct snd_cs4231 *chip)
  1152. {
  1153. int reg;
  1154. unsigned long flags;
  1155. /* int timeout; */
  1156. snd_cs4231_mce_up(chip);
  1157. spin_lock_irqsave(&chip->reg_lock, flags);
  1158. for (reg = 0; reg < 32; reg++) {
  1159. switch (reg) {
  1160. case CS4231_VERSION:
  1161. break;
  1162. default:
  1163. snd_cs4231_out(chip, reg, chip->image[reg]);
  1164. break;
  1165. }
  1166. }
  1167. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1168. #if 1
  1169. snd_cs4231_mce_down(chip);
  1170. #else
  1171. /* The following is a workaround to avoid freeze after resume on TP600E.
  1172. This is the first half of copy of snd_cs4231_mce_down(), but doesn't
  1173. include rescheduling. -- iwai
  1174. */
  1175. snd_cs4231_busy_wait(chip);
  1176. spin_lock_irqsave(&chip->reg_lock, flags);
  1177. chip->mce_bit &= ~CS4231_MCE;
  1178. timeout = cs4231_inb(chip, CS4231P(REGSEL));
  1179. cs4231_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
  1180. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1181. if (timeout == 0x80)
  1182. snd_printk("down [0x%lx]: serious init problem - codec still busy\n", chip->port);
  1183. if ((timeout & CS4231_MCE) == 0 ||
  1184. !(chip->hardware & (CS4231_HW_CS4231_MASK | CS4231_HW_CS4232_MASK))) {
  1185. return;
  1186. }
  1187. snd_cs4231_busy_wait(chip);
  1188. #endif
  1189. }
  1190. #endif /* CONFIG_PM */
  1191. static int snd_cs4231_free(struct snd_cs4231 *chip)
  1192. {
  1193. release_and_free_resource(chip->res_port);
  1194. release_and_free_resource(chip->res_cport);
  1195. if (chip->irq >= 0) {
  1196. disable_irq(chip->irq);
  1197. if (!(chip->hwshare & CS4231_HWSHARE_IRQ))
  1198. free_irq(chip->irq, (void *) chip);
  1199. }
  1200. if (!(chip->hwshare & CS4231_HWSHARE_DMA1) && chip->dma1 >= 0) {
  1201. snd_dma_disable(chip->dma1);
  1202. free_dma(chip->dma1);
  1203. }
  1204. if (!(chip->hwshare & CS4231_HWSHARE_DMA2) && chip->dma2 >= 0 && chip->dma2 != chip->dma1) {
  1205. snd_dma_disable(chip->dma2);
  1206. free_dma(chip->dma2);
  1207. }
  1208. if (chip->timer)
  1209. snd_device_free(chip->card, chip->timer);
  1210. kfree(chip);
  1211. return 0;
  1212. }
  1213. static int snd_cs4231_dev_free(struct snd_device *device)
  1214. {
  1215. struct snd_cs4231 *chip = device->device_data;
  1216. return snd_cs4231_free(chip);
  1217. }
  1218. const char *snd_cs4231_chip_id(struct snd_cs4231 *chip)
  1219. {
  1220. switch (chip->hardware) {
  1221. case CS4231_HW_CS4231: return "CS4231";
  1222. case CS4231_HW_CS4231A: return "CS4231A";
  1223. case CS4231_HW_CS4232: return "CS4232";
  1224. case CS4231_HW_CS4232A: return "CS4232A";
  1225. case CS4231_HW_CS4235: return "CS4235";
  1226. case CS4231_HW_CS4236: return "CS4236";
  1227. case CS4231_HW_CS4236B: return "CS4236B";
  1228. case CS4231_HW_CS4237B: return "CS4237B";
  1229. case CS4231_HW_CS4238B: return "CS4238B";
  1230. case CS4231_HW_CS4239: return "CS4239";
  1231. case CS4231_HW_INTERWAVE: return "AMD InterWave";
  1232. case CS4231_HW_OPL3SA2: return chip->card->shortname;
  1233. case CS4231_HW_AD1845: return "AD1845";
  1234. default: return "???";
  1235. }
  1236. }
  1237. static int snd_cs4231_new(struct snd_card *card,
  1238. unsigned short hardware,
  1239. unsigned short hwshare,
  1240. struct snd_cs4231 ** rchip)
  1241. {
  1242. struct snd_cs4231 *chip;
  1243. *rchip = NULL;
  1244. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  1245. if (chip == NULL)
  1246. return -ENOMEM;
  1247. chip->hardware = hardware;
  1248. chip->hwshare = hwshare;
  1249. spin_lock_init(&chip->reg_lock);
  1250. mutex_init(&chip->mce_mutex);
  1251. mutex_init(&chip->open_mutex);
  1252. chip->card = card;
  1253. chip->rate_constraint = snd_cs4231_xrate;
  1254. chip->set_playback_format = snd_cs4231_playback_format;
  1255. chip->set_capture_format = snd_cs4231_capture_format;
  1256. memcpy(&chip->image, &snd_cs4231_original_image, sizeof(snd_cs4231_original_image));
  1257. *rchip = chip;
  1258. return 0;
  1259. }
  1260. int snd_cs4231_create(struct snd_card *card,
  1261. unsigned long port,
  1262. unsigned long cport,
  1263. int irq, int dma1, int dma2,
  1264. unsigned short hardware,
  1265. unsigned short hwshare,
  1266. struct snd_cs4231 ** rchip)
  1267. {
  1268. static struct snd_device_ops ops = {
  1269. .dev_free = snd_cs4231_dev_free,
  1270. };
  1271. struct snd_cs4231 *chip;
  1272. int err;
  1273. err = snd_cs4231_new(card, hardware, hwshare, &chip);
  1274. if (err < 0)
  1275. return err;
  1276. chip->irq = -1;
  1277. chip->dma1 = -1;
  1278. chip->dma2 = -1;
  1279. if ((chip->res_port = request_region(port, 4, "CS4231")) == NULL) {
  1280. snd_printk(KERN_ERR "cs4231: can't grab port 0x%lx\n", port);
  1281. snd_cs4231_free(chip);
  1282. return -EBUSY;
  1283. }
  1284. chip->port = port;
  1285. if ((long)cport >= 0 && (chip->res_cport = request_region(cport, 8, "CS4232 Control")) == NULL) {
  1286. snd_printk(KERN_ERR "cs4231: can't grab control port 0x%lx\n", cport);
  1287. snd_cs4231_free(chip);
  1288. return -ENODEV;
  1289. }
  1290. chip->cport = cport;
  1291. if (!(hwshare & CS4231_HWSHARE_IRQ) && request_irq(irq, snd_cs4231_interrupt, IRQF_DISABLED, "CS4231", (void *) chip)) {
  1292. snd_printk(KERN_ERR "cs4231: can't grab IRQ %d\n", irq);
  1293. snd_cs4231_free(chip);
  1294. return -EBUSY;
  1295. }
  1296. chip->irq = irq;
  1297. if (!(hwshare & CS4231_HWSHARE_DMA1) && request_dma(dma1, "CS4231 - 1")) {
  1298. snd_printk(KERN_ERR "cs4231: can't grab DMA1 %d\n", dma1);
  1299. snd_cs4231_free(chip);
  1300. return -EBUSY;
  1301. }
  1302. chip->dma1 = dma1;
  1303. if (!(hwshare & CS4231_HWSHARE_DMA2) && dma1 != dma2 && dma2 >= 0 && request_dma(dma2, "CS4231 - 2")) {
  1304. snd_printk(KERN_ERR "cs4231: can't grab DMA2 %d\n", dma2);
  1305. snd_cs4231_free(chip);
  1306. return -EBUSY;
  1307. }
  1308. if (dma1 == dma2 || dma2 < 0) {
  1309. chip->single_dma = 1;
  1310. chip->dma2 = chip->dma1;
  1311. } else
  1312. chip->dma2 = dma2;
  1313. /* global setup */
  1314. if (snd_cs4231_probe(chip) < 0) {
  1315. snd_cs4231_free(chip);
  1316. return -ENODEV;
  1317. }
  1318. snd_cs4231_init(chip);
  1319. #if 0
  1320. if (chip->hardware & CS4231_HW_CS4232_MASK) {
  1321. if (chip->res_cport == NULL)
  1322. snd_printk("CS4232 control port features are not accessible\n");
  1323. }
  1324. #endif
  1325. /* Register device */
  1326. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  1327. snd_cs4231_free(chip);
  1328. return err;
  1329. }
  1330. #ifdef CONFIG_PM
  1331. /* Power Management */
  1332. chip->suspend = snd_cs4231_suspend;
  1333. chip->resume = snd_cs4231_resume;
  1334. #endif
  1335. *rchip = chip;
  1336. return 0;
  1337. }
  1338. static struct snd_pcm_ops snd_cs4231_playback_ops = {
  1339. .open = snd_cs4231_playback_open,
  1340. .close = snd_cs4231_playback_close,
  1341. .ioctl = snd_pcm_lib_ioctl,
  1342. .hw_params = snd_cs4231_playback_hw_params,
  1343. .hw_free = snd_cs4231_playback_hw_free,
  1344. .prepare = snd_cs4231_playback_prepare,
  1345. .trigger = snd_cs4231_trigger,
  1346. .pointer = snd_cs4231_playback_pointer,
  1347. };
  1348. static struct snd_pcm_ops snd_cs4231_capture_ops = {
  1349. .open = snd_cs4231_capture_open,
  1350. .close = snd_cs4231_capture_close,
  1351. .ioctl = snd_pcm_lib_ioctl,
  1352. .hw_params = snd_cs4231_capture_hw_params,
  1353. .hw_free = snd_cs4231_capture_hw_free,
  1354. .prepare = snd_cs4231_capture_prepare,
  1355. .trigger = snd_cs4231_trigger,
  1356. .pointer = snd_cs4231_capture_pointer,
  1357. };
  1358. int snd_cs4231_pcm(struct snd_cs4231 *chip, int device, struct snd_pcm **rpcm)
  1359. {
  1360. struct snd_pcm *pcm;
  1361. int err;
  1362. if ((err = snd_pcm_new(chip->card, "CS4231", device, 1, 1, &pcm)) < 0)
  1363. return err;
  1364. spin_lock_init(&chip->reg_lock);
  1365. mutex_init(&chip->mce_mutex);
  1366. mutex_init(&chip->open_mutex);
  1367. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4231_playback_ops);
  1368. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4231_capture_ops);
  1369. /* global setup */
  1370. pcm->private_data = chip;
  1371. pcm->info_flags = 0;
  1372. if (chip->single_dma)
  1373. pcm->info_flags |= SNDRV_PCM_INFO_HALF_DUPLEX;
  1374. if (chip->hardware != CS4231_HW_INTERWAVE)
  1375. pcm->info_flags |= SNDRV_PCM_INFO_JOINT_DUPLEX;
  1376. strcpy(pcm->name, snd_cs4231_chip_id(chip));
  1377. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1378. snd_dma_isa_data(),
  1379. 64*1024, chip->dma1 > 3 || chip->dma2 > 3 ? 128*1024 : 64*1024);
  1380. chip->pcm = pcm;
  1381. if (rpcm)
  1382. *rpcm = pcm;
  1383. return 0;
  1384. }
  1385. static void snd_cs4231_timer_free(struct snd_timer *timer)
  1386. {
  1387. struct snd_cs4231 *chip = timer->private_data;
  1388. chip->timer = NULL;
  1389. }
  1390. int snd_cs4231_timer(struct snd_cs4231 *chip, int device, struct snd_timer **rtimer)
  1391. {
  1392. struct snd_timer *timer;
  1393. struct snd_timer_id tid;
  1394. int err;
  1395. /* Timer initialization */
  1396. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1397. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1398. tid.card = chip->card->number;
  1399. tid.device = device;
  1400. tid.subdevice = 0;
  1401. if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0)
  1402. return err;
  1403. strcpy(timer->name, snd_cs4231_chip_id(chip));
  1404. timer->private_data = chip;
  1405. timer->private_free = snd_cs4231_timer_free;
  1406. timer->hw = snd_cs4231_timer_table;
  1407. chip->timer = timer;
  1408. if (rtimer)
  1409. *rtimer = timer;
  1410. return 0;
  1411. }
  1412. /*
  1413. * MIXER part
  1414. */
  1415. static int snd_cs4231_info_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1416. {
  1417. static char *texts[4] = {
  1418. "Line", "Aux", "Mic", "Mix"
  1419. };
  1420. static char *opl3sa_texts[4] = {
  1421. "Line", "CD", "Mic", "Mix"
  1422. };
  1423. static char *gusmax_texts[4] = {
  1424. "Line", "Synth", "Mic", "Mix"
  1425. };
  1426. char **ptexts = texts;
  1427. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1428. snd_assert(chip->card != NULL, return -EINVAL);
  1429. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1430. uinfo->count = 2;
  1431. uinfo->value.enumerated.items = 4;
  1432. if (uinfo->value.enumerated.item > 3)
  1433. uinfo->value.enumerated.item = 3;
  1434. if (!strcmp(chip->card->driver, "GUS MAX"))
  1435. ptexts = gusmax_texts;
  1436. switch (chip->hardware) {
  1437. case CS4231_HW_INTERWAVE: ptexts = gusmax_texts; break;
  1438. case CS4231_HW_OPL3SA2: ptexts = opl3sa_texts; break;
  1439. }
  1440. strcpy(uinfo->value.enumerated.name, ptexts[uinfo->value.enumerated.item]);
  1441. return 0;
  1442. }
  1443. static int snd_cs4231_get_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1444. {
  1445. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1446. unsigned long flags;
  1447. spin_lock_irqsave(&chip->reg_lock, flags);
  1448. ucontrol->value.enumerated.item[0] = (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1449. ucontrol->value.enumerated.item[1] = (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1450. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1451. return 0;
  1452. }
  1453. static int snd_cs4231_put_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1454. {
  1455. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1456. unsigned long flags;
  1457. unsigned short left, right;
  1458. int change;
  1459. if (ucontrol->value.enumerated.item[0] > 3 ||
  1460. ucontrol->value.enumerated.item[1] > 3)
  1461. return -EINVAL;
  1462. left = ucontrol->value.enumerated.item[0] << 6;
  1463. right = ucontrol->value.enumerated.item[1] << 6;
  1464. spin_lock_irqsave(&chip->reg_lock, flags);
  1465. left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
  1466. right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
  1467. change = left != chip->image[CS4231_LEFT_INPUT] ||
  1468. right != chip->image[CS4231_RIGHT_INPUT];
  1469. snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
  1470. snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
  1471. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1472. return change;
  1473. }
  1474. int snd_cs4231_info_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1475. {
  1476. int mask = (kcontrol->private_value >> 16) & 0xff;
  1477. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1478. uinfo->count = 1;
  1479. uinfo->value.integer.min = 0;
  1480. uinfo->value.integer.max = mask;
  1481. return 0;
  1482. }
  1483. int snd_cs4231_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1484. {
  1485. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1486. unsigned long flags;
  1487. int reg = kcontrol->private_value & 0xff;
  1488. int shift = (kcontrol->private_value >> 8) & 0xff;
  1489. int mask = (kcontrol->private_value >> 16) & 0xff;
  1490. int invert = (kcontrol->private_value >> 24) & 0xff;
  1491. spin_lock_irqsave(&chip->reg_lock, flags);
  1492. ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
  1493. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1494. if (invert)
  1495. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  1496. return 0;
  1497. }
  1498. int snd_cs4231_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1499. {
  1500. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1501. unsigned long flags;
  1502. int reg = kcontrol->private_value & 0xff;
  1503. int shift = (kcontrol->private_value >> 8) & 0xff;
  1504. int mask = (kcontrol->private_value >> 16) & 0xff;
  1505. int invert = (kcontrol->private_value >> 24) & 0xff;
  1506. int change;
  1507. unsigned short val;
  1508. val = (ucontrol->value.integer.value[0] & mask);
  1509. if (invert)
  1510. val = mask - val;
  1511. val <<= shift;
  1512. spin_lock_irqsave(&chip->reg_lock, flags);
  1513. val = (chip->image[reg] & ~(mask << shift)) | val;
  1514. change = val != chip->image[reg];
  1515. snd_cs4231_out(chip, reg, val);
  1516. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1517. return change;
  1518. }
  1519. int snd_cs4231_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1520. {
  1521. int mask = (kcontrol->private_value >> 24) & 0xff;
  1522. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1523. uinfo->count = 2;
  1524. uinfo->value.integer.min = 0;
  1525. uinfo->value.integer.max = mask;
  1526. return 0;
  1527. }
  1528. int snd_cs4231_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1529. {
  1530. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1531. unsigned long flags;
  1532. int left_reg = kcontrol->private_value & 0xff;
  1533. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1534. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1535. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1536. int mask = (kcontrol->private_value >> 24) & 0xff;
  1537. int invert = (kcontrol->private_value >> 22) & 1;
  1538. spin_lock_irqsave(&chip->reg_lock, flags);
  1539. ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
  1540. ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
  1541. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1542. if (invert) {
  1543. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  1544. ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
  1545. }
  1546. return 0;
  1547. }
  1548. int snd_cs4231_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1549. {
  1550. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1551. unsigned long flags;
  1552. int left_reg = kcontrol->private_value & 0xff;
  1553. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1554. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1555. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1556. int mask = (kcontrol->private_value >> 24) & 0xff;
  1557. int invert = (kcontrol->private_value >> 22) & 1;
  1558. int change;
  1559. unsigned short val1, val2;
  1560. val1 = ucontrol->value.integer.value[0] & mask;
  1561. val2 = ucontrol->value.integer.value[1] & mask;
  1562. if (invert) {
  1563. val1 = mask - val1;
  1564. val2 = mask - val2;
  1565. }
  1566. val1 <<= shift_left;
  1567. val2 <<= shift_right;
  1568. spin_lock_irqsave(&chip->reg_lock, flags);
  1569. val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
  1570. val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
  1571. change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg];
  1572. snd_cs4231_out(chip, left_reg, val1);
  1573. snd_cs4231_out(chip, right_reg, val2);
  1574. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1575. return change;
  1576. }
  1577. static struct snd_kcontrol_new snd_cs4231_controls[] = {
  1578. CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
  1579. CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
  1580. CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
  1581. CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
  1582. CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
  1583. CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
  1584. CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
  1585. CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
  1586. CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
  1587. CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
  1588. CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
  1589. CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
  1590. CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
  1591. {
  1592. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1593. .name = "Capture Source",
  1594. .info = snd_cs4231_info_mux,
  1595. .get = snd_cs4231_get_mux,
  1596. .put = snd_cs4231_put_mux,
  1597. },
  1598. CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
  1599. CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
  1600. CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1)
  1601. };
  1602. int snd_cs4231_mixer(struct snd_cs4231 *chip)
  1603. {
  1604. struct snd_card *card;
  1605. unsigned int idx;
  1606. int err;
  1607. snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
  1608. card = chip->card;
  1609. strcpy(card->mixername, chip->pcm->name);
  1610. for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) {
  1611. if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4231_controls[idx], chip))) < 0)
  1612. return err;
  1613. }
  1614. return 0;
  1615. }
  1616. EXPORT_SYMBOL(snd_cs4231_out);
  1617. EXPORT_SYMBOL(snd_cs4231_in);
  1618. EXPORT_SYMBOL(snd_cs4236_ext_out);
  1619. EXPORT_SYMBOL(snd_cs4236_ext_in);
  1620. EXPORT_SYMBOL(snd_cs4231_mce_up);
  1621. EXPORT_SYMBOL(snd_cs4231_mce_down);
  1622. EXPORT_SYMBOL(snd_cs4231_interrupt);
  1623. EXPORT_SYMBOL(snd_cs4231_chip_id);
  1624. EXPORT_SYMBOL(snd_cs4231_create);
  1625. EXPORT_SYMBOL(snd_cs4231_pcm);
  1626. EXPORT_SYMBOL(snd_cs4231_mixer);
  1627. EXPORT_SYMBOL(snd_cs4231_timer);
  1628. EXPORT_SYMBOL(snd_cs4231_info_single);
  1629. EXPORT_SYMBOL(snd_cs4231_get_single);
  1630. EXPORT_SYMBOL(snd_cs4231_put_single);
  1631. EXPORT_SYMBOL(snd_cs4231_info_double);
  1632. EXPORT_SYMBOL(snd_cs4231_get_double);
  1633. EXPORT_SYMBOL(snd_cs4231_put_double);
  1634. /*
  1635. * INIT part
  1636. */
  1637. static int __init alsa_cs4231_init(void)
  1638. {
  1639. return 0;
  1640. }
  1641. static void __exit alsa_cs4231_exit(void)
  1642. {
  1643. }
  1644. module_init(alsa_cs4231_init)
  1645. module_exit(alsa_cs4231_exit)