defBF54x_base.h 243 KB

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  1. /*
  2. * File: include/asm-blackfin/mach-bf548/defBF54x_base.h
  3. * Based on:
  4. * Author:
  5. *
  6. * Created:
  7. * Description:
  8. *
  9. * Rev:
  10. *
  11. * Modified:
  12. *
  13. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2, or (at your option)
  18. * any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; see the file COPYING.
  27. * If not, write to the Free Software Foundation,
  28. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  29. */
  30. #ifndef _DEF_BF54X_H
  31. #define _DEF_BF54X_H
  32. /* ************************************************************** */
  33. /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
  34. /* ************************************************************** */
  35. /* PLL Registers */
  36. #define PLL_CTL 0xffc00000 /* PLL Control Register */
  37. #define PLL_DIV 0xffc00004 /* PLL Divisor Register */
  38. #define VR_CTL 0xffc00008 /* Voltage Regulator Control Register */
  39. #define PLL_STAT 0xffc0000c /* PLL Status Register */
  40. #define PLL_LOCKCNT 0xffc00010 /* PLL Lock Count Register */
  41. /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
  42. #define CHIPID 0xffc00014
  43. /* CHIPID Masks */
  44. #define CHIPID_VERSION 0xF0000000
  45. #define CHIPID_FAMILY 0x0FFFF000
  46. #define CHIPID_MANUFACTURE 0x00000FFE
  47. /* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
  48. #define SWRST 0xffc00100 /* Software Reset Register */
  49. #define SYSCR 0xffc00104 /* System Configuration register */
  50. /* SIC Registers */
  51. #define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */
  52. #define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */
  53. #define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */
  54. #define SIC_ISR0 0xffc00118 /* System Interrupt Status Register 0 */
  55. #define SIC_ISR1 0xffc0011c /* System Interrupt Status Register 1 */
  56. #define SIC_ISR2 0xffc00120 /* System Interrupt Status Register 2 */
  57. #define SIC_IWR0 0xffc00124 /* System Interrupt Wakeup Register 0 */
  58. #define SIC_IWR1 0xffc00128 /* System Interrupt Wakeup Register 1 */
  59. #define SIC_IWR2 0xffc0012c /* System Interrupt Wakeup Register 2 */
  60. #define SIC_IAR0 0xffc00130 /* System Interrupt Assignment Register 0 */
  61. #define SIC_IAR1 0xffc00134 /* System Interrupt Assignment Register 1 */
  62. #define SIC_IAR2 0xffc00138 /* System Interrupt Assignment Register 2 */
  63. #define SIC_IAR3 0xffc0013c /* System Interrupt Assignment Register 3 */
  64. #define SIC_IAR4 0xffc00140 /* System Interrupt Assignment Register 4 */
  65. #define SIC_IAR5 0xffc00144 /* System Interrupt Assignment Register 5 */
  66. #define SIC_IAR6 0xffc00148 /* System Interrupt Assignment Register 6 */
  67. #define SIC_IAR7 0xffc0014c /* System Interrupt Assignment Register 7 */
  68. #define SIC_IAR8 0xffc00150 /* System Interrupt Assignment Register 8 */
  69. #define SIC_IAR9 0xffc00154 /* System Interrupt Assignment Register 9 */
  70. #define SIC_IAR10 0xffc00158 /* System Interrupt Assignment Register 10 */
  71. #define SIC_IAR11 0xffc0015c /* System Interrupt Assignment Register 11 */
  72. /* Watchdog Timer Registers */
  73. #define WDOG_CTL 0xffc00200 /* Watchdog Control Register */
  74. #define WDOG_CNT 0xffc00204 /* Watchdog Count Register */
  75. #define WDOG_STAT 0xffc00208 /* Watchdog Status Register */
  76. /* RTC Registers */
  77. #define RTC_STAT 0xffc00300 /* RTC Status Register */
  78. #define RTC_ICTL 0xffc00304 /* RTC Interrupt Control Register */
  79. #define RTC_ISTAT 0xffc00308 /* RTC Interrupt Status Register */
  80. #define RTC_SWCNT 0xffc0030c /* RTC Stopwatch Count Register */
  81. #define RTC_ALARM 0xffc00310 /* RTC Alarm Register */
  82. #define RTC_PREN 0xffc00314 /* RTC Prescaler Enable Register */
  83. /* UART0 Registers */
  84. #define UART0_DLL 0xffc00400 /* Divisor Latch Low Byte */
  85. #define UART0_DLH 0xffc00404 /* Divisor Latch High Byte */
  86. #define UART0_GCTL 0xffc00408 /* Global Control Register */
  87. #define UART0_LCR 0xffc0040c /* Line Control Register */
  88. #define UART0_MCR 0xffc00410 /* Modem Control Register */
  89. #define UART0_LSR 0xffc00414 /* Line Status Register */
  90. #define UART0_MSR 0xffc00418 /* Modem Status Register */
  91. #define UART0_SCR 0xffc0041c /* Scratch Register */
  92. #define UART0_IER_SET 0xffc00420 /* Interrupt Enable Register Set */
  93. #define UART0_IER_CLEAR 0xffc00424 /* Interrupt Enable Register Clear */
  94. #define UART0_THR 0xffc00428 /* Transmit Hold Register */
  95. #define UART0_RBR 0xffc0042c /* Receive Buffer Register */
  96. /* SPI0 Registers */
  97. #define SPI0_REGBASE 0xffc00500
  98. #define SPI0_CTL 0xffc00500 /* SPI0 Control Register */
  99. #define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */
  100. #define SPI0_STAT 0xffc00508 /* SPI0 Status Register */
  101. #define SPI0_TDBR 0xffc0050c /* SPI0 Transmit Data Buffer Register */
  102. #define SPI0_RDBR 0xffc00510 /* SPI0 Receive Data Buffer Register */
  103. #define SPI0_BAUD 0xffc00514 /* SPI0 Baud Rate Register */
  104. #define SPI0_SHADOW 0xffc00518 /* SPI0 Receive Data Buffer Shadow Register */
  105. /* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
  106. /* Two Wire Interface Registers (TWI0) */
  107. #define TWI0_REGBASE 0xffc00700
  108. #define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */
  109. #define TWI0_CONTROL 0xffc00704 /* TWI Control Register */
  110. #define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */
  111. #define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */
  112. #define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */
  113. #define TWI0_MASTER_CTRL 0xffc00714 /* TWI Master Mode Control Register */
  114. #define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */
  115. #define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */
  116. #define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */
  117. #define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */
  118. #define TWI0_FIFO_CTRL 0xffc00728 /* TWI FIFO Control Register */
  119. #define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */
  120. #define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */
  121. #define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */
  122. #define TWI0_RCV_DATA8 0xffc00788 /* TWI FIFO Receive Data Single Byte Register */
  123. #define TWI0_RCV_DATA16 0xffc0078c /* TWI FIFO Receive Data Double Byte Register */
  124. /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
  125. /* SPORT1 Registers */
  126. #define SPORT1_TCR1 0xffc00900 /* SPORT1 Transmit Configuration 1 Register */
  127. #define SPORT1_TCR2 0xffc00904 /* SPORT1 Transmit Configuration 2 Register */
  128. #define SPORT1_TCLKDIV 0xffc00908 /* SPORT1 Transmit Serial Clock Divider Register */
  129. #define SPORT1_TFSDIV 0xffc0090c /* SPORT1 Transmit Frame Sync Divider Register */
  130. #define SPORT1_TX 0xffc00910 /* SPORT1 Transmit Data Register */
  131. #define SPORT1_RX 0xffc00918 /* SPORT1 Receive Data Register */
  132. #define SPORT1_RCR1 0xffc00920 /* SPORT1 Receive Configuration 1 Register */
  133. #define SPORT1_RCR2 0xffc00924 /* SPORT1 Receive Configuration 2 Register */
  134. #define SPORT1_RCLKDIV 0xffc00928 /* SPORT1 Receive Serial Clock Divider Register */
  135. #define SPORT1_RFSDIV 0xffc0092c /* SPORT1 Receive Frame Sync Divider Register */
  136. #define SPORT1_STAT 0xffc00930 /* SPORT1 Status Register */
  137. #define SPORT1_CHNL 0xffc00934 /* SPORT1 Current Channel Register */
  138. #define SPORT1_MCMC1 0xffc00938 /* SPORT1 Multi channel Configuration Register 1 */
  139. #define SPORT1_MCMC2 0xffc0093c /* SPORT1 Multi channel Configuration Register 2 */
  140. #define SPORT1_MTCS0 0xffc00940 /* SPORT1 Multi channel Transmit Select Register 0 */
  141. #define SPORT1_MTCS1 0xffc00944 /* SPORT1 Multi channel Transmit Select Register 1 */
  142. #define SPORT1_MTCS2 0xffc00948 /* SPORT1 Multi channel Transmit Select Register 2 */
  143. #define SPORT1_MTCS3 0xffc0094c /* SPORT1 Multi channel Transmit Select Register 3 */
  144. #define SPORT1_MRCS0 0xffc00950 /* SPORT1 Multi channel Receive Select Register 0 */
  145. #define SPORT1_MRCS1 0xffc00954 /* SPORT1 Multi channel Receive Select Register 1 */
  146. #define SPORT1_MRCS2 0xffc00958 /* SPORT1 Multi channel Receive Select Register 2 */
  147. #define SPORT1_MRCS3 0xffc0095c /* SPORT1 Multi channel Receive Select Register 3 */
  148. /* Asynchronous Memory Control Registers */
  149. #define EBIU_AMGCTL 0xffc00a00 /* Asynchronous Memory Global Control Register */
  150. #define EBIU_AMBCTL0 0xffc00a04 /* Asynchronous Memory Bank Control Register */
  151. #define EBIU_AMBCTL1 0xffc00a08 /* Asynchronous Memory Bank Control Register */
  152. #define EBIU_MBSCTL 0xffc00a0c /* Asynchronous Memory Bank Select Control Register */
  153. #define EBIU_ARBSTAT 0xffc00a10 /* Asynchronous Memory Arbiter Status Register */
  154. #define EBIU_MODE 0xffc00a14 /* Asynchronous Mode Control Register */
  155. #define EBIU_FCTL 0xffc00a18 /* Asynchronous Memory Flash Control Register */
  156. /* DDR Memory Control Registers */
  157. #define EBIU_DDRCTL0 0xffc00a20 /* DDR Memory Control 0 Register */
  158. #define EBIU_DDRCTL1 0xffc00a24 /* DDR Memory Control 1 Register */
  159. #define EBIU_DDRCTL2 0xffc00a28 /* DDR Memory Control 2 Register */
  160. #define EBIU_DDRCTL3 0xffc00a2c /* DDR Memory Control 3 Register */
  161. #define EBIU_DDRQUE 0xffc00a30 /* DDR Queue Configuration Register */
  162. #define EBIU_ERRADD 0xffc00a34 /* DDR Error Address Register */
  163. #define EBIU_ERRMST 0xffc00a38 /* DDR Error Master Register */
  164. #define EBIU_RSTCTL 0xffc00a3c /* DDR Reset Control Register */
  165. /* DDR BankRead and Write Count Registers */
  166. #define EBIU_DDRBRC0 0xffc00a60 /* DDR Bank0 Read Count Register */
  167. #define EBIU_DDRBRC1 0xffc00a64 /* DDR Bank1 Read Count Register */
  168. #define EBIU_DDRBRC2 0xffc00a68 /* DDR Bank2 Read Count Register */
  169. #define EBIU_DDRBRC3 0xffc00a6c /* DDR Bank3 Read Count Register */
  170. #define EBIU_DDRBRC4 0xffc00a70 /* DDR Bank4 Read Count Register */
  171. #define EBIU_DDRBRC5 0xffc00a74 /* DDR Bank5 Read Count Register */
  172. #define EBIU_DDRBRC6 0xffc00a78 /* DDR Bank6 Read Count Register */
  173. #define EBIU_DDRBRC7 0xffc00a7c /* DDR Bank7 Read Count Register */
  174. #define EBIU_DDRBWC0 0xffc00a80 /* DDR Bank0 Write Count Register */
  175. #define EBIU_DDRBWC1 0xffc00a84 /* DDR Bank1 Write Count Register */
  176. #define EBIU_DDRBWC2 0xffc00a88 /* DDR Bank2 Write Count Register */
  177. #define EBIU_DDRBWC3 0xffc00a8c /* DDR Bank3 Write Count Register */
  178. #define EBIU_DDRBWC4 0xffc00a90 /* DDR Bank4 Write Count Register */
  179. #define EBIU_DDRBWC5 0xffc00a94 /* DDR Bank5 Write Count Register */
  180. #define EBIU_DDRBWC6 0xffc00a98 /* DDR Bank6 Write Count Register */
  181. #define EBIU_DDRBWC7 0xffc00a9c /* DDR Bank7 Write Count Register */
  182. #define EBIU_DDRACCT 0xffc00aa0 /* DDR Activation Count Register */
  183. #define EBIU_DDRTACT 0xffc00aa8 /* DDR Turn Around Count Register */
  184. #define EBIU_DDRARCT 0xffc00aac /* DDR Auto-refresh Count Register */
  185. #define EBIU_DDRGC0 0xffc00ab0 /* DDR Grant Count 0 Register */
  186. #define EBIU_DDRGC1 0xffc00ab4 /* DDR Grant Count 1 Register */
  187. #define EBIU_DDRGC2 0xffc00ab8 /* DDR Grant Count 2 Register */
  188. #define EBIU_DDRGC3 0xffc00abc /* DDR Grant Count 3 Register */
  189. #define EBIU_DDRMCEN 0xffc00ac0 /* DDR Metrics Counter Enable Register */
  190. #define EBIU_DDRMCCL 0xffc00ac4 /* DDR Metrics Counter Clear Register */
  191. /* DMAC0 Registers */
  192. #define DMAC0_TCPER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */
  193. #define DMAC0_TCCNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */
  194. /* DMA Channel 0 Registers */
  195. #define DMA0_NEXT_DESC_PTR 0xffc00c00 /* DMA Channel 0 Next Descriptor Pointer Register */
  196. #define DMA0_START_ADDR 0xffc00c04 /* DMA Channel 0 Start Address Register */
  197. #define DMA0_CONFIG 0xffc00c08 /* DMA Channel 0 Configuration Register */
  198. #define DMA0_X_COUNT 0xffc00c10 /* DMA Channel 0 X Count Register */
  199. #define DMA0_X_MODIFY 0xffc00c14 /* DMA Channel 0 X Modify Register */
  200. #define DMA0_Y_COUNT 0xffc00c18 /* DMA Channel 0 Y Count Register */
  201. #define DMA0_Y_MODIFY 0xffc00c1c /* DMA Channel 0 Y Modify Register */
  202. #define DMA0_CURR_DESC_PTR 0xffc00c20 /* DMA Channel 0 Current Descriptor Pointer Register */
  203. #define DMA0_CURR_ADDR 0xffc00c24 /* DMA Channel 0 Current Address Register */
  204. #define DMA0_IRQ_STATUS 0xffc00c28 /* DMA Channel 0 Interrupt/Status Register */
  205. #define DMA0_PERIPHERAL_MAP 0xffc00c2c /* DMA Channel 0 Peripheral Map Register */
  206. #define DMA0_CURR_X_COUNT 0xffc00c30 /* DMA Channel 0 Current X Count Register */
  207. #define DMA0_CURR_Y_COUNT 0xffc00c38 /* DMA Channel 0 Current Y Count Register */
  208. /* DMA Channel 1 Registers */
  209. #define DMA1_NEXT_DESC_PTR 0xffc00c40 /* DMA Channel 1 Next Descriptor Pointer Register */
  210. #define DMA1_START_ADDR 0xffc00c44 /* DMA Channel 1 Start Address Register */
  211. #define DMA1_CONFIG 0xffc00c48 /* DMA Channel 1 Configuration Register */
  212. #define DMA1_X_COUNT 0xffc00c50 /* DMA Channel 1 X Count Register */
  213. #define DMA1_X_MODIFY 0xffc00c54 /* DMA Channel 1 X Modify Register */
  214. #define DMA1_Y_COUNT 0xffc00c58 /* DMA Channel 1 Y Count Register */
  215. #define DMA1_Y_MODIFY 0xffc00c5c /* DMA Channel 1 Y Modify Register */
  216. #define DMA1_CURR_DESC_PTR 0xffc00c60 /* DMA Channel 1 Current Descriptor Pointer Register */
  217. #define DMA1_CURR_ADDR 0xffc00c64 /* DMA Channel 1 Current Address Register */
  218. #define DMA1_IRQ_STATUS 0xffc00c68 /* DMA Channel 1 Interrupt/Status Register */
  219. #define DMA1_PERIPHERAL_MAP 0xffc00c6c /* DMA Channel 1 Peripheral Map Register */
  220. #define DMA1_CURR_X_COUNT 0xffc00c70 /* DMA Channel 1 Current X Count Register */
  221. #define DMA1_CURR_Y_COUNT 0xffc00c78 /* DMA Channel 1 Current Y Count Register */
  222. /* DMA Channel 2 Registers */
  223. #define DMA2_NEXT_DESC_PTR 0xffc00c80 /* DMA Channel 2 Next Descriptor Pointer Register */
  224. #define DMA2_START_ADDR 0xffc00c84 /* DMA Channel 2 Start Address Register */
  225. #define DMA2_CONFIG 0xffc00c88 /* DMA Channel 2 Configuration Register */
  226. #define DMA2_X_COUNT 0xffc00c90 /* DMA Channel 2 X Count Register */
  227. #define DMA2_X_MODIFY 0xffc00c94 /* DMA Channel 2 X Modify Register */
  228. #define DMA2_Y_COUNT 0xffc00c98 /* DMA Channel 2 Y Count Register */
  229. #define DMA2_Y_MODIFY 0xffc00c9c /* DMA Channel 2 Y Modify Register */
  230. #define DMA2_CURR_DESC_PTR 0xffc00ca0 /* DMA Channel 2 Current Descriptor Pointer Register */
  231. #define DMA2_CURR_ADDR 0xffc00ca4 /* DMA Channel 2 Current Address Register */
  232. #define DMA2_IRQ_STATUS 0xffc00ca8 /* DMA Channel 2 Interrupt/Status Register */
  233. #define DMA2_PERIPHERAL_MAP 0xffc00cac /* DMA Channel 2 Peripheral Map Register */
  234. #define DMA2_CURR_X_COUNT 0xffc00cb0 /* DMA Channel 2 Current X Count Register */
  235. #define DMA2_CURR_Y_COUNT 0xffc00cb8 /* DMA Channel 2 Current Y Count Register */
  236. /* DMA Channel 3 Registers */
  237. #define DMA3_NEXT_DESC_PTR 0xffc00cc0 /* DMA Channel 3 Next Descriptor Pointer Register */
  238. #define DMA3_START_ADDR 0xffc00cc4 /* DMA Channel 3 Start Address Register */
  239. #define DMA3_CONFIG 0xffc00cc8 /* DMA Channel 3 Configuration Register */
  240. #define DMA3_X_COUNT 0xffc00cd0 /* DMA Channel 3 X Count Register */
  241. #define DMA3_X_MODIFY 0xffc00cd4 /* DMA Channel 3 X Modify Register */
  242. #define DMA3_Y_COUNT 0xffc00cd8 /* DMA Channel 3 Y Count Register */
  243. #define DMA3_Y_MODIFY 0xffc00cdc /* DMA Channel 3 Y Modify Register */
  244. #define DMA3_CURR_DESC_PTR 0xffc00ce0 /* DMA Channel 3 Current Descriptor Pointer Register */
  245. #define DMA3_CURR_ADDR 0xffc00ce4 /* DMA Channel 3 Current Address Register */
  246. #define DMA3_IRQ_STATUS 0xffc00ce8 /* DMA Channel 3 Interrupt/Status Register */
  247. #define DMA3_PERIPHERAL_MAP 0xffc00cec /* DMA Channel 3 Peripheral Map Register */
  248. #define DMA3_CURR_X_COUNT 0xffc00cf0 /* DMA Channel 3 Current X Count Register */
  249. #define DMA3_CURR_Y_COUNT 0xffc00cf8 /* DMA Channel 3 Current Y Count Register */
  250. /* DMA Channel 4 Registers */
  251. #define DMA4_NEXT_DESC_PTR 0xffc00d00 /* DMA Channel 4 Next Descriptor Pointer Register */
  252. #define DMA4_START_ADDR 0xffc00d04 /* DMA Channel 4 Start Address Register */
  253. #define DMA4_CONFIG 0xffc00d08 /* DMA Channel 4 Configuration Register */
  254. #define DMA4_X_COUNT 0xffc00d10 /* DMA Channel 4 X Count Register */
  255. #define DMA4_X_MODIFY 0xffc00d14 /* DMA Channel 4 X Modify Register */
  256. #define DMA4_Y_COUNT 0xffc00d18 /* DMA Channel 4 Y Count Register */
  257. #define DMA4_Y_MODIFY 0xffc00d1c /* DMA Channel 4 Y Modify Register */
  258. #define DMA4_CURR_DESC_PTR 0xffc00d20 /* DMA Channel 4 Current Descriptor Pointer Register */
  259. #define DMA4_CURR_ADDR 0xffc00d24 /* DMA Channel 4 Current Address Register */
  260. #define DMA4_IRQ_STATUS 0xffc00d28 /* DMA Channel 4 Interrupt/Status Register */
  261. #define DMA4_PERIPHERAL_MAP 0xffc00d2c /* DMA Channel 4 Peripheral Map Register */
  262. #define DMA4_CURR_X_COUNT 0xffc00d30 /* DMA Channel 4 Current X Count Register */
  263. #define DMA4_CURR_Y_COUNT 0xffc00d38 /* DMA Channel 4 Current Y Count Register */
  264. /* DMA Channel 5 Registers */
  265. #define DMA5_NEXT_DESC_PTR 0xffc00d40 /* DMA Channel 5 Next Descriptor Pointer Register */
  266. #define DMA5_START_ADDR 0xffc00d44 /* DMA Channel 5 Start Address Register */
  267. #define DMA5_CONFIG 0xffc00d48 /* DMA Channel 5 Configuration Register */
  268. #define DMA5_X_COUNT 0xffc00d50 /* DMA Channel 5 X Count Register */
  269. #define DMA5_X_MODIFY 0xffc00d54 /* DMA Channel 5 X Modify Register */
  270. #define DMA5_Y_COUNT 0xffc00d58 /* DMA Channel 5 Y Count Register */
  271. #define DMA5_Y_MODIFY 0xffc00d5c /* DMA Channel 5 Y Modify Register */
  272. #define DMA5_CURR_DESC_PTR 0xffc00d60 /* DMA Channel 5 Current Descriptor Pointer Register */
  273. #define DMA5_CURR_ADDR 0xffc00d64 /* DMA Channel 5 Current Address Register */
  274. #define DMA5_IRQ_STATUS 0xffc00d68 /* DMA Channel 5 Interrupt/Status Register */
  275. #define DMA5_PERIPHERAL_MAP 0xffc00d6c /* DMA Channel 5 Peripheral Map Register */
  276. #define DMA5_CURR_X_COUNT 0xffc00d70 /* DMA Channel 5 Current X Count Register */
  277. #define DMA5_CURR_Y_COUNT 0xffc00d78 /* DMA Channel 5 Current Y Count Register */
  278. /* DMA Channel 6 Registers */
  279. #define DMA6_NEXT_DESC_PTR 0xffc00d80 /* DMA Channel 6 Next Descriptor Pointer Register */
  280. #define DMA6_START_ADDR 0xffc00d84 /* DMA Channel 6 Start Address Register */
  281. #define DMA6_CONFIG 0xffc00d88 /* DMA Channel 6 Configuration Register */
  282. #define DMA6_X_COUNT 0xffc00d90 /* DMA Channel 6 X Count Register */
  283. #define DMA6_X_MODIFY 0xffc00d94 /* DMA Channel 6 X Modify Register */
  284. #define DMA6_Y_COUNT 0xffc00d98 /* DMA Channel 6 Y Count Register */
  285. #define DMA6_Y_MODIFY 0xffc00d9c /* DMA Channel 6 Y Modify Register */
  286. #define DMA6_CURR_DESC_PTR 0xffc00da0 /* DMA Channel 6 Current Descriptor Pointer Register */
  287. #define DMA6_CURR_ADDR 0xffc00da4 /* DMA Channel 6 Current Address Register */
  288. #define DMA6_IRQ_STATUS 0xffc00da8 /* DMA Channel 6 Interrupt/Status Register */
  289. #define DMA6_PERIPHERAL_MAP 0xffc00dac /* DMA Channel 6 Peripheral Map Register */
  290. #define DMA6_CURR_X_COUNT 0xffc00db0 /* DMA Channel 6 Current X Count Register */
  291. #define DMA6_CURR_Y_COUNT 0xffc00db8 /* DMA Channel 6 Current Y Count Register */
  292. /* DMA Channel 7 Registers */
  293. #define DMA7_NEXT_DESC_PTR 0xffc00dc0 /* DMA Channel 7 Next Descriptor Pointer Register */
  294. #define DMA7_START_ADDR 0xffc00dc4 /* DMA Channel 7 Start Address Register */
  295. #define DMA7_CONFIG 0xffc00dc8 /* DMA Channel 7 Configuration Register */
  296. #define DMA7_X_COUNT 0xffc00dd0 /* DMA Channel 7 X Count Register */
  297. #define DMA7_X_MODIFY 0xffc00dd4 /* DMA Channel 7 X Modify Register */
  298. #define DMA7_Y_COUNT 0xffc00dd8 /* DMA Channel 7 Y Count Register */
  299. #define DMA7_Y_MODIFY 0xffc00ddc /* DMA Channel 7 Y Modify Register */
  300. #define DMA7_CURR_DESC_PTR 0xffc00de0 /* DMA Channel 7 Current Descriptor Pointer Register */
  301. #define DMA7_CURR_ADDR 0xffc00de4 /* DMA Channel 7 Current Address Register */
  302. #define DMA7_IRQ_STATUS 0xffc00de8 /* DMA Channel 7 Interrupt/Status Register */
  303. #define DMA7_PERIPHERAL_MAP 0xffc00dec /* DMA Channel 7 Peripheral Map Register */
  304. #define DMA7_CURR_X_COUNT 0xffc00df0 /* DMA Channel 7 Current X Count Register */
  305. #define DMA7_CURR_Y_COUNT 0xffc00df8 /* DMA Channel 7 Current Y Count Register */
  306. /* DMA Channel 8 Registers */
  307. #define DMA8_NEXT_DESC_PTR 0xffc00e00 /* DMA Channel 8 Next Descriptor Pointer Register */
  308. #define DMA8_START_ADDR 0xffc00e04 /* DMA Channel 8 Start Address Register */
  309. #define DMA8_CONFIG 0xffc00e08 /* DMA Channel 8 Configuration Register */
  310. #define DMA8_X_COUNT 0xffc00e10 /* DMA Channel 8 X Count Register */
  311. #define DMA8_X_MODIFY 0xffc00e14 /* DMA Channel 8 X Modify Register */
  312. #define DMA8_Y_COUNT 0xffc00e18 /* DMA Channel 8 Y Count Register */
  313. #define DMA8_Y_MODIFY 0xffc00e1c /* DMA Channel 8 Y Modify Register */
  314. #define DMA8_CURR_DESC_PTR 0xffc00e20 /* DMA Channel 8 Current Descriptor Pointer Register */
  315. #define DMA8_CURR_ADDR 0xffc00e24 /* DMA Channel 8 Current Address Register */
  316. #define DMA8_IRQ_STATUS 0xffc00e28 /* DMA Channel 8 Interrupt/Status Register */
  317. #define DMA8_PERIPHERAL_MAP 0xffc00e2c /* DMA Channel 8 Peripheral Map Register */
  318. #define DMA8_CURR_X_COUNT 0xffc00e30 /* DMA Channel 8 Current X Count Register */
  319. #define DMA8_CURR_Y_COUNT 0xffc00e38 /* DMA Channel 8 Current Y Count Register */
  320. /* DMA Channel 9 Registers */
  321. #define DMA9_NEXT_DESC_PTR 0xffc00e40 /* DMA Channel 9 Next Descriptor Pointer Register */
  322. #define DMA9_START_ADDR 0xffc00e44 /* DMA Channel 9 Start Address Register */
  323. #define DMA9_CONFIG 0xffc00e48 /* DMA Channel 9 Configuration Register */
  324. #define DMA9_X_COUNT 0xffc00e50 /* DMA Channel 9 X Count Register */
  325. #define DMA9_X_MODIFY 0xffc00e54 /* DMA Channel 9 X Modify Register */
  326. #define DMA9_Y_COUNT 0xffc00e58 /* DMA Channel 9 Y Count Register */
  327. #define DMA9_Y_MODIFY 0xffc00e5c /* DMA Channel 9 Y Modify Register */
  328. #define DMA9_CURR_DESC_PTR 0xffc00e60 /* DMA Channel 9 Current Descriptor Pointer Register */
  329. #define DMA9_CURR_ADDR 0xffc00e64 /* DMA Channel 9 Current Address Register */
  330. #define DMA9_IRQ_STATUS 0xffc00e68 /* DMA Channel 9 Interrupt/Status Register */
  331. #define DMA9_PERIPHERAL_MAP 0xffc00e6c /* DMA Channel 9 Peripheral Map Register */
  332. #define DMA9_CURR_X_COUNT 0xffc00e70 /* DMA Channel 9 Current X Count Register */
  333. #define DMA9_CURR_Y_COUNT 0xffc00e78 /* DMA Channel 9 Current Y Count Register */
  334. /* DMA Channel 10 Registers */
  335. #define DMA10_NEXT_DESC_PTR 0xffc00e80 /* DMA Channel 10 Next Descriptor Pointer Register */
  336. #define DMA10_START_ADDR 0xffc00e84 /* DMA Channel 10 Start Address Register */
  337. #define DMA10_CONFIG 0xffc00e88 /* DMA Channel 10 Configuration Register */
  338. #define DMA10_X_COUNT 0xffc00e90 /* DMA Channel 10 X Count Register */
  339. #define DMA10_X_MODIFY 0xffc00e94 /* DMA Channel 10 X Modify Register */
  340. #define DMA10_Y_COUNT 0xffc00e98 /* DMA Channel 10 Y Count Register */
  341. #define DMA10_Y_MODIFY 0xffc00e9c /* DMA Channel 10 Y Modify Register */
  342. #define DMA10_CURR_DESC_PTR 0xffc00ea0 /* DMA Channel 10 Current Descriptor Pointer Register */
  343. #define DMA10_CURR_ADDR 0xffc00ea4 /* DMA Channel 10 Current Address Register */
  344. #define DMA10_IRQ_STATUS 0xffc00ea8 /* DMA Channel 10 Interrupt/Status Register */
  345. #define DMA10_PERIPHERAL_MAP 0xffc00eac /* DMA Channel 10 Peripheral Map Register */
  346. #define DMA10_CURR_X_COUNT 0xffc00eb0 /* DMA Channel 10 Current X Count Register */
  347. #define DMA10_CURR_Y_COUNT 0xffc00eb8 /* DMA Channel 10 Current Y Count Register */
  348. /* DMA Channel 11 Registers */
  349. #define DMA11_NEXT_DESC_PTR 0xffc00ec0 /* DMA Channel 11 Next Descriptor Pointer Register */
  350. #define DMA11_START_ADDR 0xffc00ec4 /* DMA Channel 11 Start Address Register */
  351. #define DMA11_CONFIG 0xffc00ec8 /* DMA Channel 11 Configuration Register */
  352. #define DMA11_X_COUNT 0xffc00ed0 /* DMA Channel 11 X Count Register */
  353. #define DMA11_X_MODIFY 0xffc00ed4 /* DMA Channel 11 X Modify Register */
  354. #define DMA11_Y_COUNT 0xffc00ed8 /* DMA Channel 11 Y Count Register */
  355. #define DMA11_Y_MODIFY 0xffc00edc /* DMA Channel 11 Y Modify Register */
  356. #define DMA11_CURR_DESC_PTR 0xffc00ee0 /* DMA Channel 11 Current Descriptor Pointer Register */
  357. #define DMA11_CURR_ADDR 0xffc00ee4 /* DMA Channel 11 Current Address Register */
  358. #define DMA11_IRQ_STATUS 0xffc00ee8 /* DMA Channel 11 Interrupt/Status Register */
  359. #define DMA11_PERIPHERAL_MAP 0xffc00eec /* DMA Channel 11 Peripheral Map Register */
  360. #define DMA11_CURR_X_COUNT 0xffc00ef0 /* DMA Channel 11 Current X Count Register */
  361. #define DMA11_CURR_Y_COUNT 0xffc00ef8 /* DMA Channel 11 Current Y Count Register */
  362. /* MDMA Stream 0 Registers */
  363. #define MDMA_D0_NEXT_DESC_PTR 0xffc00f00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
  364. #define MDMA_D0_START_ADDR 0xffc00f04 /* Memory DMA Stream 0 Destination Start Address Register */
  365. #define MDMA_D0_CONFIG 0xffc00f08 /* Memory DMA Stream 0 Destination Configuration Register */
  366. #define MDMA_D0_X_COUNT 0xffc00f10 /* Memory DMA Stream 0 Destination X Count Register */
  367. #define MDMA_D0_X_MODIFY 0xffc00f14 /* Memory DMA Stream 0 Destination X Modify Register */
  368. #define MDMA_D0_Y_COUNT 0xffc00f18 /* Memory DMA Stream 0 Destination Y Count Register */
  369. #define MDMA_D0_Y_MODIFY 0xffc00f1c /* Memory DMA Stream 0 Destination Y Modify Register */
  370. #define MDMA_D0_CURR_DESC_PTR 0xffc00f20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
  371. #define MDMA_D0_CURR_ADDR 0xffc00f24 /* Memory DMA Stream 0 Destination Current Address Register */
  372. #define MDMA_D0_IRQ_STATUS 0xffc00f28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
  373. #define MDMA_D0_PERIPHERAL_MAP 0xffc00f2c /* Memory DMA Stream 0 Destination Peripheral Map Register */
  374. #define MDMA_D0_CURR_X_COUNT 0xffc00f30 /* Memory DMA Stream 0 Destination Current X Count Register */
  375. #define MDMA_D0_CURR_Y_COUNT 0xffc00f38 /* Memory DMA Stream 0 Destination Current Y Count Register */
  376. #define MDMA_S0_NEXT_DESC_PTR 0xffc00f40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
  377. #define MDMA_S0_START_ADDR 0xffc00f44 /* Memory DMA Stream 0 Source Start Address Register */
  378. #define MDMA_S0_CONFIG 0xffc00f48 /* Memory DMA Stream 0 Source Configuration Register */
  379. #define MDMA_S0_X_COUNT 0xffc00f50 /* Memory DMA Stream 0 Source X Count Register */
  380. #define MDMA_S0_X_MODIFY 0xffc00f54 /* Memory DMA Stream 0 Source X Modify Register */
  381. #define MDMA_S0_Y_COUNT 0xffc00f58 /* Memory DMA Stream 0 Source Y Count Register */
  382. #define MDMA_S0_Y_MODIFY 0xffc00f5c /* Memory DMA Stream 0 Source Y Modify Register */
  383. #define MDMA_S0_CURR_DESC_PTR 0xffc00f60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
  384. #define MDMA_S0_CURR_ADDR 0xffc00f64 /* Memory DMA Stream 0 Source Current Address Register */
  385. #define MDMA_S0_IRQ_STATUS 0xffc00f68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
  386. #define MDMA_S0_PERIPHERAL_MAP 0xffc00f6c /* Memory DMA Stream 0 Source Peripheral Map Register */
  387. #define MDMA_S0_CURR_X_COUNT 0xffc00f70 /* Memory DMA Stream 0 Source Current X Count Register */
  388. #define MDMA_S0_CURR_Y_COUNT 0xffc00f78 /* Memory DMA Stream 0 Source Current Y Count Register */
  389. /* MDMA Stream 1 Registers */
  390. #define MDMA_D1_NEXT_DESC_PTR 0xffc00f80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
  391. #define MDMA_D1_START_ADDR 0xffc00f84 /* Memory DMA Stream 1 Destination Start Address Register */
  392. #define MDMA_D1_CONFIG 0xffc00f88 /* Memory DMA Stream 1 Destination Configuration Register */
  393. #define MDMA_D1_X_COUNT 0xffc00f90 /* Memory DMA Stream 1 Destination X Count Register */
  394. #define MDMA_D1_X_MODIFY 0xffc00f94 /* Memory DMA Stream 1 Destination X Modify Register */
  395. #define MDMA_D1_Y_COUNT 0xffc00f98 /* Memory DMA Stream 1 Destination Y Count Register */
  396. #define MDMA_D1_Y_MODIFY 0xffc00f9c /* Memory DMA Stream 1 Destination Y Modify Register */
  397. #define MDMA_D1_CURR_DESC_PTR 0xffc00fa0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
  398. #define MDMA_D1_CURR_ADDR 0xffc00fa4 /* Memory DMA Stream 1 Destination Current Address Register */
  399. #define MDMA_D1_IRQ_STATUS 0xffc00fa8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
  400. #define MDMA_D1_PERIPHERAL_MAP 0xffc00fac /* Memory DMA Stream 1 Destination Peripheral Map Register */
  401. #define MDMA_D1_CURR_X_COUNT 0xffc00fb0 /* Memory DMA Stream 1 Destination Current X Count Register */
  402. #define MDMA_D1_CURR_Y_COUNT 0xffc00fb8 /* Memory DMA Stream 1 Destination Current Y Count Register */
  403. #define MDMA_S1_NEXT_DESC_PTR 0xffc00fc0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
  404. #define MDMA_S1_START_ADDR 0xffc00fc4 /* Memory DMA Stream 1 Source Start Address Register */
  405. #define MDMA_S1_CONFIG 0xffc00fc8 /* Memory DMA Stream 1 Source Configuration Register */
  406. #define MDMA_S1_X_COUNT 0xffc00fd0 /* Memory DMA Stream 1 Source X Count Register */
  407. #define MDMA_S1_X_MODIFY 0xffc00fd4 /* Memory DMA Stream 1 Source X Modify Register */
  408. #define MDMA_S1_Y_COUNT 0xffc00fd8 /* Memory DMA Stream 1 Source Y Count Register */
  409. #define MDMA_S1_Y_MODIFY 0xffc00fdc /* Memory DMA Stream 1 Source Y Modify Register */
  410. #define MDMA_S1_CURR_DESC_PTR 0xffc00fe0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
  411. #define MDMA_S1_CURR_ADDR 0xffc00fe4 /* Memory DMA Stream 1 Source Current Address Register */
  412. #define MDMA_S1_IRQ_STATUS 0xffc00fe8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
  413. #define MDMA_S1_PERIPHERAL_MAP 0xffc00fec /* Memory DMA Stream 1 Source Peripheral Map Register */
  414. #define MDMA_S1_CURR_X_COUNT 0xffc00ff0 /* Memory DMA Stream 1 Source Current X Count Register */
  415. #define MDMA_S1_CURR_Y_COUNT 0xffc00ff8 /* Memory DMA Stream 1 Source Current Y Count Register */
  416. /* UART3 Registers */
  417. #define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */
  418. #define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */
  419. #define UART3_GCTL 0xffc03108 /* Global Control Register */
  420. #define UART3_LCR 0xffc0310c /* Line Control Register */
  421. #define UART3_MCR 0xffc03110 /* Modem Control Register */
  422. #define UART3_LSR 0xffc03114 /* Line Status Register */
  423. #define UART3_MSR 0xffc03118 /* Modem Status Register */
  424. #define UART3_SCR 0xffc0311c /* Scratch Register */
  425. #define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */
  426. #define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */
  427. #define UART3_THR 0xffc03128 /* Transmit Hold Register */
  428. #define UART3_RBR 0xffc0312c /* Receive Buffer Register */
  429. /* EPPI1 Registers */
  430. #define EPPI1_STATUS 0xffc01300 /* EPPI1 Status Register */
  431. #define EPPI1_HCOUNT 0xffc01304 /* EPPI1 Horizontal Transfer Count Register */
  432. #define EPPI1_HDELAY 0xffc01308 /* EPPI1 Horizontal Delay Count Register */
  433. #define EPPI1_VCOUNT 0xffc0130c /* EPPI1 Vertical Transfer Count Register */
  434. #define EPPI1_VDELAY 0xffc01310 /* EPPI1 Vertical Delay Count Register */
  435. #define EPPI1_FRAME 0xffc01314 /* EPPI1 Lines per Frame Register */
  436. #define EPPI1_LINE 0xffc01318 /* EPPI1 Samples per Line Register */
  437. #define EPPI1_CLKDIV 0xffc0131c /* EPPI1 Clock Divide Register */
  438. #define EPPI1_CONTROL 0xffc01320 /* EPPI1 Control Register */
  439. #define EPPI1_FS1W_HBL 0xffc01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
  440. #define EPPI1_FS1P_AVPL 0xffc01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
  441. #define EPPI1_FS2W_LVB 0xffc0132c /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
  442. #define EPPI1_FS2P_LAVF 0xffc01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
  443. #define EPPI1_CLIP 0xffc01334 /* EPPI1 Clipping Register */
  444. /* Port Interrupt 0 Registers (32-bit) */
  445. #define PINT0_MASK_SET 0xffc01400 /* Pin Interrupt 0 Mask Set Register */
  446. #define PINT0_MASK_CLEAR 0xffc01404 /* Pin Interrupt 0 Mask Clear Register */
  447. #define PINT0_REQUEST 0xffc01408 /* Pin Interrupt 0 Interrupt Request Register */
  448. #define PINT0_ASSIGN 0xffc0140c /* Pin Interrupt 0 Port Assign Register */
  449. #define PINT0_EDGE_SET 0xffc01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
  450. #define PINT0_EDGE_CLEAR 0xffc01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
  451. #define PINT0_INVERT_SET 0xffc01418 /* Pin Interrupt 0 Inversion Set Register */
  452. #define PINT0_INVERT_CLEAR 0xffc0141c /* Pin Interrupt 0 Inversion Clear Register */
  453. #define PINT0_PINSTATE 0xffc01420 /* Pin Interrupt 0 Pin Status Register */
  454. #define PINT0_LATCH 0xffc01424 /* Pin Interrupt 0 Latch Register */
  455. /* Port Interrupt 1 Registers (32-bit) */
  456. #define PINT1_MASK_SET 0xffc01430 /* Pin Interrupt 1 Mask Set Register */
  457. #define PINT1_MASK_CLEAR 0xffc01434 /* Pin Interrupt 1 Mask Clear Register */
  458. #define PINT1_REQUEST 0xffc01438 /* Pin Interrupt 1 Interrupt Request Register */
  459. #define PINT1_ASSIGN 0xffc0143c /* Pin Interrupt 1 Port Assign Register */
  460. #define PINT1_EDGE_SET 0xffc01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
  461. #define PINT1_EDGE_CLEAR 0xffc01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
  462. #define PINT1_INVERT_SET 0xffc01448 /* Pin Interrupt 1 Inversion Set Register */
  463. #define PINT1_INVERT_CLEAR 0xffc0144c /* Pin Interrupt 1 Inversion Clear Register */
  464. #define PINT1_PINSTATE 0xffc01450 /* Pin Interrupt 1 Pin Status Register */
  465. #define PINT1_LATCH 0xffc01454 /* Pin Interrupt 1 Latch Register */
  466. /* Port Interrupt 2 Registers (32-bit) */
  467. #define PINT2_MASK_SET 0xffc01460 /* Pin Interrupt 2 Mask Set Register */
  468. #define PINT2_MASK_CLEAR 0xffc01464 /* Pin Interrupt 2 Mask Clear Register */
  469. #define PINT2_REQUEST 0xffc01468 /* Pin Interrupt 2 Interrupt Request Register */
  470. #define PINT2_ASSIGN 0xffc0146c /* Pin Interrupt 2 Port Assign Register */
  471. #define PINT2_EDGE_SET 0xffc01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
  472. #define PINT2_EDGE_CLEAR 0xffc01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
  473. #define PINT2_INVERT_SET 0xffc01478 /* Pin Interrupt 2 Inversion Set Register */
  474. #define PINT2_INVERT_CLEAR 0xffc0147c /* Pin Interrupt 2 Inversion Clear Register */
  475. #define PINT2_PINSTATE 0xffc01480 /* Pin Interrupt 2 Pin Status Register */
  476. #define PINT2_LATCH 0xffc01484 /* Pin Interrupt 2 Latch Register */
  477. /* Port Interrupt 3 Registers (32-bit) */
  478. #define PINT3_MASK_SET 0xffc01490 /* Pin Interrupt 3 Mask Set Register */
  479. #define PINT3_MASK_CLEAR 0xffc01494 /* Pin Interrupt 3 Mask Clear Register */
  480. #define PINT3_REQUEST 0xffc01498 /* Pin Interrupt 3 Interrupt Request Register */
  481. #define PINT3_ASSIGN 0xffc0149c /* Pin Interrupt 3 Port Assign Register */
  482. #define PINT3_EDGE_SET 0xffc014a0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
  483. #define PINT3_EDGE_CLEAR 0xffc014a4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
  484. #define PINT3_INVERT_SET 0xffc014a8 /* Pin Interrupt 3 Inversion Set Register */
  485. #define PINT3_INVERT_CLEAR 0xffc014ac /* Pin Interrupt 3 Inversion Clear Register */
  486. #define PINT3_PINSTATE 0xffc014b0 /* Pin Interrupt 3 Pin Status Register */
  487. #define PINT3_LATCH 0xffc014b4 /* Pin Interrupt 3 Latch Register */
  488. /* Port A Registers */
  489. #define PORTA_FER 0xffc014c0 /* Function Enable Register */
  490. #define PORTA 0xffc014c4 /* GPIO Data Register */
  491. #define PORTA_SET 0xffc014c8 /* GPIO Data Set Register */
  492. #define PORTA_CLEAR 0xffc014cc /* GPIO Data Clear Register */
  493. #define PORTA_DIR_SET 0xffc014d0 /* GPIO Direction Set Register */
  494. #define PORTA_DIR_CLEAR 0xffc014d4 /* GPIO Direction Clear Register */
  495. #define PORTA_INEN 0xffc014d8 /* GPIO Input Enable Register */
  496. #define PORTA_MUX 0xffc014dc /* Multiplexer Control Register */
  497. /* Port B Registers */
  498. #define PORTB_FER 0xffc014e0 /* Function Enable Register */
  499. #define PORTB 0xffc014e4 /* GPIO Data Register */
  500. #define PORTB_SET 0xffc014e8 /* GPIO Data Set Register */
  501. #define PORTB_CLEAR 0xffc014ec /* GPIO Data Clear Register */
  502. #define PORTB_DIR_SET 0xffc014f0 /* GPIO Direction Set Register */
  503. #define PORTB_DIR_CLEAR 0xffc014f4 /* GPIO Direction Clear Register */
  504. #define PORTB_INEN 0xffc014f8 /* GPIO Input Enable Register */
  505. #define PORTB_MUX 0xffc014fc /* Multiplexer Control Register */
  506. /* Port C Registers */
  507. #define PORTC_FER 0xffc01500 /* Function Enable Register */
  508. #define PORTC 0xffc01504 /* GPIO Data Register */
  509. #define PORTC_SET 0xffc01508 /* GPIO Data Set Register */
  510. #define PORTC_CLEAR 0xffc0150c /* GPIO Data Clear Register */
  511. #define PORTC_DIR_SET 0xffc01510 /* GPIO Direction Set Register */
  512. #define PORTC_DIR_CLEAR 0xffc01514 /* GPIO Direction Clear Register */
  513. #define PORTC_INEN 0xffc01518 /* GPIO Input Enable Register */
  514. #define PORTC_MUX 0xffc0151c /* Multiplexer Control Register */
  515. /* Port D Registers */
  516. #define PORTD_FER 0xffc01520 /* Function Enable Register */
  517. #define PORTD 0xffc01524 /* GPIO Data Register */
  518. #define PORTD_SET 0xffc01528 /* GPIO Data Set Register */
  519. #define PORTD_CLEAR 0xffc0152c /* GPIO Data Clear Register */
  520. #define PORTD_DIR_SET 0xffc01530 /* GPIO Direction Set Register */
  521. #define PORTD_DIR_CLEAR 0xffc01534 /* GPIO Direction Clear Register */
  522. #define PORTD_INEN 0xffc01538 /* GPIO Input Enable Register */
  523. #define PORTD_MUX 0xffc0153c /* Multiplexer Control Register */
  524. /* Port E Registers */
  525. #define PORTE_FER 0xffc01540 /* Function Enable Register */
  526. #define PORTE 0xffc01544 /* GPIO Data Register */
  527. #define PORTE_SET 0xffc01548 /* GPIO Data Set Register */
  528. #define PORTE_CLEAR 0xffc0154c /* GPIO Data Clear Register */
  529. #define PORTE_DIR_SET 0xffc01550 /* GPIO Direction Set Register */
  530. #define PORTE_DIR_CLEAR 0xffc01554 /* GPIO Direction Clear Register */
  531. #define PORTE_INEN 0xffc01558 /* GPIO Input Enable Register */
  532. #define PORTE_MUX 0xffc0155c /* Multiplexer Control Register */
  533. /* Port F Registers */
  534. #define PORTF_FER 0xffc01560 /* Function Enable Register */
  535. #define PORTF 0xffc01564 /* GPIO Data Register */
  536. #define PORTF_SET 0xffc01568 /* GPIO Data Set Register */
  537. #define PORTF_CLEAR 0xffc0156c /* GPIO Data Clear Register */
  538. #define PORTF_DIR_SET 0xffc01570 /* GPIO Direction Set Register */
  539. #define PORTF_DIR_CLEAR 0xffc01574 /* GPIO Direction Clear Register */
  540. #define PORTF_INEN 0xffc01578 /* GPIO Input Enable Register */
  541. #define PORTF_MUX 0xffc0157c /* Multiplexer Control Register */
  542. /* Port G Registers */
  543. #define PORTG_FER 0xffc01580 /* Function Enable Register */
  544. #define PORTG 0xffc01584 /* GPIO Data Register */
  545. #define PORTG_SET 0xffc01588 /* GPIO Data Set Register */
  546. #define PORTG_CLEAR 0xffc0158c /* GPIO Data Clear Register */
  547. #define PORTG_DIR_SET 0xffc01590 /* GPIO Direction Set Register */
  548. #define PORTG_DIR_CLEAR 0xffc01594 /* GPIO Direction Clear Register */
  549. #define PORTG_INEN 0xffc01598 /* GPIO Input Enable Register */
  550. #define PORTG_MUX 0xffc0159c /* Multiplexer Control Register */
  551. /* Port H Registers */
  552. #define PORTH_FER 0xffc015a0 /* Function Enable Register */
  553. #define PORTH 0xffc015a4 /* GPIO Data Register */
  554. #define PORTH_SET 0xffc015a8 /* GPIO Data Set Register */
  555. #define PORTH_CLEAR 0xffc015ac /* GPIO Data Clear Register */
  556. #define PORTH_DIR_SET 0xffc015b0 /* GPIO Direction Set Register */
  557. #define PORTH_DIR_CLEAR 0xffc015b4 /* GPIO Direction Clear Register */
  558. #define PORTH_INEN 0xffc015b8 /* GPIO Input Enable Register */
  559. #define PORTH_MUX 0xffc015bc /* Multiplexer Control Register */
  560. /* Port I Registers */
  561. #define PORTI_FER 0xffc015c0 /* Function Enable Register */
  562. #define PORTI 0xffc015c4 /* GPIO Data Register */
  563. #define PORTI_SET 0xffc015c8 /* GPIO Data Set Register */
  564. #define PORTI_CLEAR 0xffc015cc /* GPIO Data Clear Register */
  565. #define PORTI_DIR_SET 0xffc015d0 /* GPIO Direction Set Register */
  566. #define PORTI_DIR_CLEAR 0xffc015d4 /* GPIO Direction Clear Register */
  567. #define PORTI_INEN 0xffc015d8 /* GPIO Input Enable Register */
  568. #define PORTI_MUX 0xffc015dc /* Multiplexer Control Register */
  569. /* Port J Registers */
  570. #define PORTJ_FER 0xffc015e0 /* Function Enable Register */
  571. #define PORTJ 0xffc015e4 /* GPIO Data Register */
  572. #define PORTJ_SET 0xffc015e8 /* GPIO Data Set Register */
  573. #define PORTJ_CLEAR 0xffc015ec /* GPIO Data Clear Register */
  574. #define PORTJ_DIR_SET 0xffc015f0 /* GPIO Direction Set Register */
  575. #define PORTJ_DIR_CLEAR 0xffc015f4 /* GPIO Direction Clear Register */
  576. #define PORTJ_INEN 0xffc015f8 /* GPIO Input Enable Register */
  577. #define PORTJ_MUX 0xffc015fc /* Multiplexer Control Register */
  578. /* PWM Timer Registers */
  579. #define TIMER0_CONFIG 0xffc01600 /* Timer 0 Configuration Register */
  580. #define TIMER0_COUNTER 0xffc01604 /* Timer 0 Counter Register */
  581. #define TIMER0_PERIOD 0xffc01608 /* Timer 0 Period Register */
  582. #define TIMER0_WIDTH 0xffc0160c /* Timer 0 Width Register */
  583. #define TIMER1_CONFIG 0xffc01610 /* Timer 1 Configuration Register */
  584. #define TIMER1_COUNTER 0xffc01614 /* Timer 1 Counter Register */
  585. #define TIMER1_PERIOD 0xffc01618 /* Timer 1 Period Register */
  586. #define TIMER1_WIDTH 0xffc0161c /* Timer 1 Width Register */
  587. #define TIMER2_CONFIG 0xffc01620 /* Timer 2 Configuration Register */
  588. #define TIMER2_COUNTER 0xffc01624 /* Timer 2 Counter Register */
  589. #define TIMER2_PERIOD 0xffc01628 /* Timer 2 Period Register */
  590. #define TIMER2_WIDTH 0xffc0162c /* Timer 2 Width Register */
  591. #define TIMER3_CONFIG 0xffc01630 /* Timer 3 Configuration Register */
  592. #define TIMER3_COUNTER 0xffc01634 /* Timer 3 Counter Register */
  593. #define TIMER3_PERIOD 0xffc01638 /* Timer 3 Period Register */
  594. #define TIMER3_WIDTH 0xffc0163c /* Timer 3 Width Register */
  595. #define TIMER4_CONFIG 0xffc01640 /* Timer 4 Configuration Register */
  596. #define TIMER4_COUNTER 0xffc01644 /* Timer 4 Counter Register */
  597. #define TIMER4_PERIOD 0xffc01648 /* Timer 4 Period Register */
  598. #define TIMER4_WIDTH 0xffc0164c /* Timer 4 Width Register */
  599. #define TIMER5_CONFIG 0xffc01650 /* Timer 5 Configuration Register */
  600. #define TIMER5_COUNTER 0xffc01654 /* Timer 5 Counter Register */
  601. #define TIMER5_PERIOD 0xffc01658 /* Timer 5 Period Register */
  602. #define TIMER5_WIDTH 0xffc0165c /* Timer 5 Width Register */
  603. #define TIMER6_CONFIG 0xffc01660 /* Timer 6 Configuration Register */
  604. #define TIMER6_COUNTER 0xffc01664 /* Timer 6 Counter Register */
  605. #define TIMER6_PERIOD 0xffc01668 /* Timer 6 Period Register */
  606. #define TIMER6_WIDTH 0xffc0166c /* Timer 6 Width Register */
  607. #define TIMER7_CONFIG 0xffc01670 /* Timer 7 Configuration Register */
  608. #define TIMER7_COUNTER 0xffc01674 /* Timer 7 Counter Register */
  609. #define TIMER7_PERIOD 0xffc01678 /* Timer 7 Period Register */
  610. #define TIMER7_WIDTH 0xffc0167c /* Timer 7 Width Register */
  611. /* Timer Group of 8 */
  612. #define TIMER_ENABLE0 0xffc01680 /* Timer Group of 8 Enable Register */
  613. #define TIMER_DISABLE0 0xffc01684 /* Timer Group of 8 Disable Register */
  614. #define TIMER_STATUS0 0xffc01688 /* Timer Group of 8 Status Register */
  615. /* DMAC1 Registers */
  616. #define DMAC1_TCPER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */
  617. #define DMAC1_TCCNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */
  618. /* DMA Channel 12 Registers */
  619. #define DMA12_NEXT_DESC_PTR 0xffc01c00 /* DMA Channel 12 Next Descriptor Pointer Register */
  620. #define DMA12_START_ADDR 0xffc01c04 /* DMA Channel 12 Start Address Register */
  621. #define DMA12_CONFIG 0xffc01c08 /* DMA Channel 12 Configuration Register */
  622. #define DMA12_X_COUNT 0xffc01c10 /* DMA Channel 12 X Count Register */
  623. #define DMA12_X_MODIFY 0xffc01c14 /* DMA Channel 12 X Modify Register */
  624. #define DMA12_Y_COUNT 0xffc01c18 /* DMA Channel 12 Y Count Register */
  625. #define DMA12_Y_MODIFY 0xffc01c1c /* DMA Channel 12 Y Modify Register */
  626. #define DMA12_CURR_DESC_PTR 0xffc01c20 /* DMA Channel 12 Current Descriptor Pointer Register */
  627. #define DMA12_CURR_ADDR 0xffc01c24 /* DMA Channel 12 Current Address Register */
  628. #define DMA12_IRQ_STATUS 0xffc01c28 /* DMA Channel 12 Interrupt/Status Register */
  629. #define DMA12_PERIPHERAL_MAP 0xffc01c2c /* DMA Channel 12 Peripheral Map Register */
  630. #define DMA12_CURR_X_COUNT 0xffc01c30 /* DMA Channel 12 Current X Count Register */
  631. #define DMA12_CURR_Y_COUNT 0xffc01c38 /* DMA Channel 12 Current Y Count Register */
  632. /* DMA Channel 13 Registers */
  633. #define DMA13_NEXT_DESC_PTR 0xffc01c40 /* DMA Channel 13 Next Descriptor Pointer Register */
  634. #define DMA13_START_ADDR 0xffc01c44 /* DMA Channel 13 Start Address Register */
  635. #define DMA13_CONFIG 0xffc01c48 /* DMA Channel 13 Configuration Register */
  636. #define DMA13_X_COUNT 0xffc01c50 /* DMA Channel 13 X Count Register */
  637. #define DMA13_X_MODIFY 0xffc01c54 /* DMA Channel 13 X Modify Register */
  638. #define DMA13_Y_COUNT 0xffc01c58 /* DMA Channel 13 Y Count Register */
  639. #define DMA13_Y_MODIFY 0xffc01c5c /* DMA Channel 13 Y Modify Register */
  640. #define DMA13_CURR_DESC_PTR 0xffc01c60 /* DMA Channel 13 Current Descriptor Pointer Register */
  641. #define DMA13_CURR_ADDR 0xffc01c64 /* DMA Channel 13 Current Address Register */
  642. #define DMA13_IRQ_STATUS 0xffc01c68 /* DMA Channel 13 Interrupt/Status Register */
  643. #define DMA13_PERIPHERAL_MAP 0xffc01c6c /* DMA Channel 13 Peripheral Map Register */
  644. #define DMA13_CURR_X_COUNT 0xffc01c70 /* DMA Channel 13 Current X Count Register */
  645. #define DMA13_CURR_Y_COUNT 0xffc01c78 /* DMA Channel 13 Current Y Count Register */
  646. /* DMA Channel 14 Registers */
  647. #define DMA14_NEXT_DESC_PTR 0xffc01c80 /* DMA Channel 14 Next Descriptor Pointer Register */
  648. #define DMA14_START_ADDR 0xffc01c84 /* DMA Channel 14 Start Address Register */
  649. #define DMA14_CONFIG 0xffc01c88 /* DMA Channel 14 Configuration Register */
  650. #define DMA14_X_COUNT 0xffc01c90 /* DMA Channel 14 X Count Register */
  651. #define DMA14_X_MODIFY 0xffc01c94 /* DMA Channel 14 X Modify Register */
  652. #define DMA14_Y_COUNT 0xffc01c98 /* DMA Channel 14 Y Count Register */
  653. #define DMA14_Y_MODIFY 0xffc01c9c /* DMA Channel 14 Y Modify Register */
  654. #define DMA14_CURR_DESC_PTR 0xffc01ca0 /* DMA Channel 14 Current Descriptor Pointer Register */
  655. #define DMA14_CURR_ADDR 0xffc01ca4 /* DMA Channel 14 Current Address Register */
  656. #define DMA14_IRQ_STATUS 0xffc01ca8 /* DMA Channel 14 Interrupt/Status Register */
  657. #define DMA14_PERIPHERAL_MAP 0xffc01cac /* DMA Channel 14 Peripheral Map Register */
  658. #define DMA14_CURR_X_COUNT 0xffc01cb0 /* DMA Channel 14 Current X Count Register */
  659. #define DMA14_CURR_Y_COUNT 0xffc01cb8 /* DMA Channel 14 Current Y Count Register */
  660. /* DMA Channel 15 Registers */
  661. #define DMA15_NEXT_DESC_PTR 0xffc01cc0 /* DMA Channel 15 Next Descriptor Pointer Register */
  662. #define DMA15_START_ADDR 0xffc01cc4 /* DMA Channel 15 Start Address Register */
  663. #define DMA15_CONFIG 0xffc01cc8 /* DMA Channel 15 Configuration Register */
  664. #define DMA15_X_COUNT 0xffc01cd0 /* DMA Channel 15 X Count Register */
  665. #define DMA15_X_MODIFY 0xffc01cd4 /* DMA Channel 15 X Modify Register */
  666. #define DMA15_Y_COUNT 0xffc01cd8 /* DMA Channel 15 Y Count Register */
  667. #define DMA15_Y_MODIFY 0xffc01cdc /* DMA Channel 15 Y Modify Register */
  668. #define DMA15_CURR_DESC_PTR 0xffc01ce0 /* DMA Channel 15 Current Descriptor Pointer Register */
  669. #define DMA15_CURR_ADDR 0xffc01ce4 /* DMA Channel 15 Current Address Register */
  670. #define DMA15_IRQ_STATUS 0xffc01ce8 /* DMA Channel 15 Interrupt/Status Register */
  671. #define DMA15_PERIPHERAL_MAP 0xffc01cec /* DMA Channel 15 Peripheral Map Register */
  672. #define DMA15_CURR_X_COUNT 0xffc01cf0 /* DMA Channel 15 Current X Count Register */
  673. #define DMA15_CURR_Y_COUNT 0xffc01cf8 /* DMA Channel 15 Current Y Count Register */
  674. /* DMA Channel 16 Registers */
  675. #define DMA16_NEXT_DESC_PTR 0xffc01d00 /* DMA Channel 16 Next Descriptor Pointer Register */
  676. #define DMA16_START_ADDR 0xffc01d04 /* DMA Channel 16 Start Address Register */
  677. #define DMA16_CONFIG 0xffc01d08 /* DMA Channel 16 Configuration Register */
  678. #define DMA16_X_COUNT 0xffc01d10 /* DMA Channel 16 X Count Register */
  679. #define DMA16_X_MODIFY 0xffc01d14 /* DMA Channel 16 X Modify Register */
  680. #define DMA16_Y_COUNT 0xffc01d18 /* DMA Channel 16 Y Count Register */
  681. #define DMA16_Y_MODIFY 0xffc01d1c /* DMA Channel 16 Y Modify Register */
  682. #define DMA16_CURR_DESC_PTR 0xffc01d20 /* DMA Channel 16 Current Descriptor Pointer Register */
  683. #define DMA16_CURR_ADDR 0xffc01d24 /* DMA Channel 16 Current Address Register */
  684. #define DMA16_IRQ_STATUS 0xffc01d28 /* DMA Channel 16 Interrupt/Status Register */
  685. #define DMA16_PERIPHERAL_MAP 0xffc01d2c /* DMA Channel 16 Peripheral Map Register */
  686. #define DMA16_CURR_X_COUNT 0xffc01d30 /* DMA Channel 16 Current X Count Register */
  687. #define DMA16_CURR_Y_COUNT 0xffc01d38 /* DMA Channel 16 Current Y Count Register */
  688. /* DMA Channel 17 Registers */
  689. #define DMA17_NEXT_DESC_PTR 0xffc01d40 /* DMA Channel 17 Next Descriptor Pointer Register */
  690. #define DMA17_START_ADDR 0xffc01d44 /* DMA Channel 17 Start Address Register */
  691. #define DMA17_CONFIG 0xffc01d48 /* DMA Channel 17 Configuration Register */
  692. #define DMA17_X_COUNT 0xffc01d50 /* DMA Channel 17 X Count Register */
  693. #define DMA17_X_MODIFY 0xffc01d54 /* DMA Channel 17 X Modify Register */
  694. #define DMA17_Y_COUNT 0xffc01d58 /* DMA Channel 17 Y Count Register */
  695. #define DMA17_Y_MODIFY 0xffc01d5c /* DMA Channel 17 Y Modify Register */
  696. #define DMA17_CURR_DESC_PTR 0xffc01d60 /* DMA Channel 17 Current Descriptor Pointer Register */
  697. #define DMA17_CURR_ADDR 0xffc01d64 /* DMA Channel 17 Current Address Register */
  698. #define DMA17_IRQ_STATUS 0xffc01d68 /* DMA Channel 17 Interrupt/Status Register */
  699. #define DMA17_PERIPHERAL_MAP 0xffc01d6c /* DMA Channel 17 Peripheral Map Register */
  700. #define DMA17_CURR_X_COUNT 0xffc01d70 /* DMA Channel 17 Current X Count Register */
  701. #define DMA17_CURR_Y_COUNT 0xffc01d78 /* DMA Channel 17 Current Y Count Register */
  702. /* DMA Channel 18 Registers */
  703. #define DMA18_NEXT_DESC_PTR 0xffc01d80 /* DMA Channel 18 Next Descriptor Pointer Register */
  704. #define DMA18_START_ADDR 0xffc01d84 /* DMA Channel 18 Start Address Register */
  705. #define DMA18_CONFIG 0xffc01d88 /* DMA Channel 18 Configuration Register */
  706. #define DMA18_X_COUNT 0xffc01d90 /* DMA Channel 18 X Count Register */
  707. #define DMA18_X_MODIFY 0xffc01d94 /* DMA Channel 18 X Modify Register */
  708. #define DMA18_Y_COUNT 0xffc01d98 /* DMA Channel 18 Y Count Register */
  709. #define DMA18_Y_MODIFY 0xffc01d9c /* DMA Channel 18 Y Modify Register */
  710. #define DMA18_CURR_DESC_PTR 0xffc01da0 /* DMA Channel 18 Current Descriptor Pointer Register */
  711. #define DMA18_CURR_ADDR 0xffc01da4 /* DMA Channel 18 Current Address Register */
  712. #define DMA18_IRQ_STATUS 0xffc01da8 /* DMA Channel 18 Interrupt/Status Register */
  713. #define DMA18_PERIPHERAL_MAP 0xffc01dac /* DMA Channel 18 Peripheral Map Register */
  714. #define DMA18_CURR_X_COUNT 0xffc01db0 /* DMA Channel 18 Current X Count Register */
  715. #define DMA18_CURR_Y_COUNT 0xffc01db8 /* DMA Channel 18 Current Y Count Register */
  716. /* DMA Channel 19 Registers */
  717. #define DMA19_NEXT_DESC_PTR 0xffc01dc0 /* DMA Channel 19 Next Descriptor Pointer Register */
  718. #define DMA19_START_ADDR 0xffc01dc4 /* DMA Channel 19 Start Address Register */
  719. #define DMA19_CONFIG 0xffc01dc8 /* DMA Channel 19 Configuration Register */
  720. #define DMA19_X_COUNT 0xffc01dd0 /* DMA Channel 19 X Count Register */
  721. #define DMA19_X_MODIFY 0xffc01dd4 /* DMA Channel 19 X Modify Register */
  722. #define DMA19_Y_COUNT 0xffc01dd8 /* DMA Channel 19 Y Count Register */
  723. #define DMA19_Y_MODIFY 0xffc01ddc /* DMA Channel 19 Y Modify Register */
  724. #define DMA19_CURR_DESC_PTR 0xffc01de0 /* DMA Channel 19 Current Descriptor Pointer Register */
  725. #define DMA19_CURR_ADDR 0xffc01de4 /* DMA Channel 19 Current Address Register */
  726. #define DMA19_IRQ_STATUS 0xffc01de8 /* DMA Channel 19 Interrupt/Status Register */
  727. #define DMA19_PERIPHERAL_MAP 0xffc01dec /* DMA Channel 19 Peripheral Map Register */
  728. #define DMA19_CURR_X_COUNT 0xffc01df0 /* DMA Channel 19 Current X Count Register */
  729. #define DMA19_CURR_Y_COUNT 0xffc01df8 /* DMA Channel 19 Current Y Count Register */
  730. /* DMA Channel 20 Registers */
  731. #define DMA20_NEXT_DESC_PTR 0xffc01e00 /* DMA Channel 20 Next Descriptor Pointer Register */
  732. #define DMA20_START_ADDR 0xffc01e04 /* DMA Channel 20 Start Address Register */
  733. #define DMA20_CONFIG 0xffc01e08 /* DMA Channel 20 Configuration Register */
  734. #define DMA20_X_COUNT 0xffc01e10 /* DMA Channel 20 X Count Register */
  735. #define DMA20_X_MODIFY 0xffc01e14 /* DMA Channel 20 X Modify Register */
  736. #define DMA20_Y_COUNT 0xffc01e18 /* DMA Channel 20 Y Count Register */
  737. #define DMA20_Y_MODIFY 0xffc01e1c /* DMA Channel 20 Y Modify Register */
  738. #define DMA20_CURR_DESC_PTR 0xffc01e20 /* DMA Channel 20 Current Descriptor Pointer Register */
  739. #define DMA20_CURR_ADDR 0xffc01e24 /* DMA Channel 20 Current Address Register */
  740. #define DMA20_IRQ_STATUS 0xffc01e28 /* DMA Channel 20 Interrupt/Status Register */
  741. #define DMA20_PERIPHERAL_MAP 0xffc01e2c /* DMA Channel 20 Peripheral Map Register */
  742. #define DMA20_CURR_X_COUNT 0xffc01e30 /* DMA Channel 20 Current X Count Register */
  743. #define DMA20_CURR_Y_COUNT 0xffc01e38 /* DMA Channel 20 Current Y Count Register */
  744. /* DMA Channel 21 Registers */
  745. #define DMA21_NEXT_DESC_PTR 0xffc01e40 /* DMA Channel 21 Next Descriptor Pointer Register */
  746. #define DMA21_START_ADDR 0xffc01e44 /* DMA Channel 21 Start Address Register */
  747. #define DMA21_CONFIG 0xffc01e48 /* DMA Channel 21 Configuration Register */
  748. #define DMA21_X_COUNT 0xffc01e50 /* DMA Channel 21 X Count Register */
  749. #define DMA21_X_MODIFY 0xffc01e54 /* DMA Channel 21 X Modify Register */
  750. #define DMA21_Y_COUNT 0xffc01e58 /* DMA Channel 21 Y Count Register */
  751. #define DMA21_Y_MODIFY 0xffc01e5c /* DMA Channel 21 Y Modify Register */
  752. #define DMA21_CURR_DESC_PTR 0xffc01e60 /* DMA Channel 21 Current Descriptor Pointer Register */
  753. #define DMA21_CURR_ADDR 0xffc01e64 /* DMA Channel 21 Current Address Register */
  754. #define DMA21_IRQ_STATUS 0xffc01e68 /* DMA Channel 21 Interrupt/Status Register */
  755. #define DMA21_PERIPHERAL_MAP 0xffc01e6c /* DMA Channel 21 Peripheral Map Register */
  756. #define DMA21_CURR_X_COUNT 0xffc01e70 /* DMA Channel 21 Current X Count Register */
  757. #define DMA21_CURR_Y_COUNT 0xffc01e78 /* DMA Channel 21 Current Y Count Register */
  758. /* DMA Channel 22 Registers */
  759. #define DMA22_NEXT_DESC_PTR 0xffc01e80 /* DMA Channel 22 Next Descriptor Pointer Register */
  760. #define DMA22_START_ADDR 0xffc01e84 /* DMA Channel 22 Start Address Register */
  761. #define DMA22_CONFIG 0xffc01e88 /* DMA Channel 22 Configuration Register */
  762. #define DMA22_X_COUNT 0xffc01e90 /* DMA Channel 22 X Count Register */
  763. #define DMA22_X_MODIFY 0xffc01e94 /* DMA Channel 22 X Modify Register */
  764. #define DMA22_Y_COUNT 0xffc01e98 /* DMA Channel 22 Y Count Register */
  765. #define DMA22_Y_MODIFY 0xffc01e9c /* DMA Channel 22 Y Modify Register */
  766. #define DMA22_CURR_DESC_PTR 0xffc01ea0 /* DMA Channel 22 Current Descriptor Pointer Register */
  767. #define DMA22_CURR_ADDR 0xffc01ea4 /* DMA Channel 22 Current Address Register */
  768. #define DMA22_IRQ_STATUS 0xffc01ea8 /* DMA Channel 22 Interrupt/Status Register */
  769. #define DMA22_PERIPHERAL_MAP 0xffc01eac /* DMA Channel 22 Peripheral Map Register */
  770. #define DMA22_CURR_X_COUNT 0xffc01eb0 /* DMA Channel 22 Current X Count Register */
  771. #define DMA22_CURR_Y_COUNT 0xffc01eb8 /* DMA Channel 22 Current Y Count Register */
  772. /* DMA Channel 23 Registers */
  773. #define DMA23_NEXT_DESC_PTR 0xffc01ec0 /* DMA Channel 23 Next Descriptor Pointer Register */
  774. #define DMA23_START_ADDR 0xffc01ec4 /* DMA Channel 23 Start Address Register */
  775. #define DMA23_CONFIG 0xffc01ec8 /* DMA Channel 23 Configuration Register */
  776. #define DMA23_X_COUNT 0xffc01ed0 /* DMA Channel 23 X Count Register */
  777. #define DMA23_X_MODIFY 0xffc01ed4 /* DMA Channel 23 X Modify Register */
  778. #define DMA23_Y_COUNT 0xffc01ed8 /* DMA Channel 23 Y Count Register */
  779. #define DMA23_Y_MODIFY 0xffc01edc /* DMA Channel 23 Y Modify Register */
  780. #define DMA23_CURR_DESC_PTR 0xffc01ee0 /* DMA Channel 23 Current Descriptor Pointer Register */
  781. #define DMA23_CURR_ADDR 0xffc01ee4 /* DMA Channel 23 Current Address Register */
  782. #define DMA23_IRQ_STATUS 0xffc01ee8 /* DMA Channel 23 Interrupt/Status Register */
  783. #define DMA23_PERIPHERAL_MAP 0xffc01eec /* DMA Channel 23 Peripheral Map Register */
  784. #define DMA23_CURR_X_COUNT 0xffc01ef0 /* DMA Channel 23 Current X Count Register */
  785. #define DMA23_CURR_Y_COUNT 0xffc01ef8 /* DMA Channel 23 Current Y Count Register */
  786. /* MDMA Stream 2 Registers */
  787. #define MDMA_D2_NEXT_DESC_PTR 0xffc01f00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
  788. #define MDMA_D2_START_ADDR 0xffc01f04 /* Memory DMA Stream 2 Destination Start Address Register */
  789. #define MDMA_D2_CONFIG 0xffc01f08 /* Memory DMA Stream 2 Destination Configuration Register */
  790. #define MDMA_D2_X_COUNT 0xffc01f10 /* Memory DMA Stream 2 Destination X Count Register */
  791. #define MDMA_D2_X_MODIFY 0xffc01f14 /* Memory DMA Stream 2 Destination X Modify Register */
  792. #define MDMA_D2_Y_COUNT 0xffc01f18 /* Memory DMA Stream 2 Destination Y Count Register */
  793. #define MDMA_D2_Y_MODIFY 0xffc01f1c /* Memory DMA Stream 2 Destination Y Modify Register */
  794. #define MDMA_D2_CURR_DESC_PTR 0xffc01f20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
  795. #define MDMA_D2_CURR_ADDR 0xffc01f24 /* Memory DMA Stream 2 Destination Current Address Register */
  796. #define MDMA_D2_IRQ_STATUS 0xffc01f28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
  797. #define MDMA_D2_PERIPHERAL_MAP 0xffc01f2c /* Memory DMA Stream 2 Destination Peripheral Map Register */
  798. #define MDMA_D2_CURR_X_COUNT 0xffc01f30 /* Memory DMA Stream 2 Destination Current X Count Register */
  799. #define MDMA_D2_CURR_Y_COUNT 0xffc01f38 /* Memory DMA Stream 2 Destination Current Y Count Register */
  800. #define MDMA_S2_NEXT_DESC_PTR 0xffc01f40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
  801. #define MDMA_S2_START_ADDR 0xffc01f44 /* Memory DMA Stream 2 Source Start Address Register */
  802. #define MDMA_S2_CONFIG 0xffc01f48 /* Memory DMA Stream 2 Source Configuration Register */
  803. #define MDMA_S2_X_COUNT 0xffc01f50 /* Memory DMA Stream 2 Source X Count Register */
  804. #define MDMA_S2_X_MODIFY 0xffc01f54 /* Memory DMA Stream 2 Source X Modify Register */
  805. #define MDMA_S2_Y_COUNT 0xffc01f58 /* Memory DMA Stream 2 Source Y Count Register */
  806. #define MDMA_S2_Y_MODIFY 0xffc01f5c /* Memory DMA Stream 2 Source Y Modify Register */
  807. #define MDMA_S2_CURR_DESC_PTR 0xffc01f60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
  808. #define MDMA_S2_CURR_ADDR 0xffc01f64 /* Memory DMA Stream 2 Source Current Address Register */
  809. #define MDMA_S2_IRQ_STATUS 0xffc01f68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
  810. #define MDMA_S2_PERIPHERAL_MAP 0xffc01f6c /* Memory DMA Stream 2 Source Peripheral Map Register */
  811. #define MDMA_S2_CURR_X_COUNT 0xffc01f70 /* Memory DMA Stream 2 Source Current X Count Register */
  812. #define MDMA_S2_CURR_Y_COUNT 0xffc01f78 /* Memory DMA Stream 2 Source Current Y Count Register */
  813. /* MDMA Stream 3 Registers */
  814. #define MDMA_D3_NEXT_DESC_PTR 0xffc01f80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
  815. #define MDMA_D3_START_ADDR 0xffc01f84 /* Memory DMA Stream 3 Destination Start Address Register */
  816. #define MDMA_D3_CONFIG 0xffc01f88 /* Memory DMA Stream 3 Destination Configuration Register */
  817. #define MDMA_D3_X_COUNT 0xffc01f90 /* Memory DMA Stream 3 Destination X Count Register */
  818. #define MDMA_D3_X_MODIFY 0xffc01f94 /* Memory DMA Stream 3 Destination X Modify Register */
  819. #define MDMA_D3_Y_COUNT 0xffc01f98 /* Memory DMA Stream 3 Destination Y Count Register */
  820. #define MDMA_D3_Y_MODIFY 0xffc01f9c /* Memory DMA Stream 3 Destination Y Modify Register */
  821. #define MDMA_D3_CURR_DESC_PTR 0xffc01fa0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
  822. #define MDMA_D3_CURR_ADDR 0xffc01fa4 /* Memory DMA Stream 3 Destination Current Address Register */
  823. #define MDMA_D3_IRQ_STATUS 0xffc01fa8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
  824. #define MDMA_D3_PERIPHERAL_MAP 0xffc01fac /* Memory DMA Stream 3 Destination Peripheral Map Register */
  825. #define MDMA_D3_CURR_X_COUNT 0xffc01fb0 /* Memory DMA Stream 3 Destination Current X Count Register */
  826. #define MDMA_D3_CURR_Y_COUNT 0xffc01fb8 /* Memory DMA Stream 3 Destination Current Y Count Register */
  827. #define MDMA_S3_NEXT_DESC_PTR 0xffc01fc0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
  828. #define MDMA_S3_START_ADDR 0xffc01fc4 /* Memory DMA Stream 3 Source Start Address Register */
  829. #define MDMA_S3_CONFIG 0xffc01fc8 /* Memory DMA Stream 3 Source Configuration Register */
  830. #define MDMA_S3_X_COUNT 0xffc01fd0 /* Memory DMA Stream 3 Source X Count Register */
  831. #define MDMA_S3_X_MODIFY 0xffc01fd4 /* Memory DMA Stream 3 Source X Modify Register */
  832. #define MDMA_S3_Y_COUNT 0xffc01fd8 /* Memory DMA Stream 3 Source Y Count Register */
  833. #define MDMA_S3_Y_MODIFY 0xffc01fdc /* Memory DMA Stream 3 Source Y Modify Register */
  834. #define MDMA_S3_CURR_DESC_PTR 0xffc01fe0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
  835. #define MDMA_S3_CURR_ADDR 0xffc01fe4 /* Memory DMA Stream 3 Source Current Address Register */
  836. #define MDMA_S3_IRQ_STATUS 0xffc01fe8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
  837. #define MDMA_S3_PERIPHERAL_MAP 0xffc01fec /* Memory DMA Stream 3 Source Peripheral Map Register */
  838. #define MDMA_S3_CURR_X_COUNT 0xffc01ff0 /* Memory DMA Stream 3 Source Current X Count Register */
  839. #define MDMA_S3_CURR_Y_COUNT 0xffc01ff8 /* Memory DMA Stream 3 Source Current Y Count Register */
  840. /* UART1 Registers */
  841. #define UART1_DLL 0xffc02000 /* Divisor Latch Low Byte */
  842. #define UART1_DLH 0xffc02004 /* Divisor Latch High Byte */
  843. #define UART1_GCTL 0xffc02008 /* Global Control Register */
  844. #define UART1_LCR 0xffc0200c /* Line Control Register */
  845. #define UART1_MCR 0xffc02010 /* Modem Control Register */
  846. #define UART1_LSR 0xffc02014 /* Line Status Register */
  847. #define UART1_MSR 0xffc02018 /* Modem Status Register */
  848. #define UART1_SCR 0xffc0201c /* Scratch Register */
  849. #define UART1_IER_SET 0xffc02020 /* Interrupt Enable Register Set */
  850. #define UART1_IER_CLEAR 0xffc02024 /* Interrupt Enable Register Clear */
  851. #define UART1_THR 0xffc02028 /* Transmit Hold Register */
  852. #define UART1_RBR 0xffc0202c /* Receive Buffer Register */
  853. /* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
  854. /* SPI1 Registers */
  855. #define SPI1_REGBASE 0xffc02300
  856. #define SPI1_CTL 0xffc02300 /* SPI1 Control Register */
  857. #define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */
  858. #define SPI1_STAT 0xffc02308 /* SPI1 Status Register */
  859. #define SPI1_TDBR 0xffc0230c /* SPI1 Transmit Data Buffer Register */
  860. #define SPI1_RDBR 0xffc02310 /* SPI1 Receive Data Buffer Register */
  861. #define SPI1_BAUD 0xffc02314 /* SPI1 Baud Rate Register */
  862. #define SPI1_SHADOW 0xffc02318 /* SPI1 Receive Data Buffer Shadow Register */
  863. /* SPORT2 Registers */
  864. #define SPORT2_TCR1 0xffc02500 /* SPORT2 Transmit Configuration 1 Register */
  865. #define SPORT2_TCR2 0xffc02504 /* SPORT2 Transmit Configuration 2 Register */
  866. #define SPORT2_TCLKDIV 0xffc02508 /* SPORT2 Transmit Serial Clock Divider Register */
  867. #define SPORT2_TFSDIV 0xffc0250c /* SPORT2 Transmit Frame Sync Divider Register */
  868. #define SPORT2_TX 0xffc02510 /* SPORT2 Transmit Data Register */
  869. #define SPORT2_RX 0xffc02518 /* SPORT2 Receive Data Register */
  870. #define SPORT2_RCR1 0xffc02520 /* SPORT2 Receive Configuration 1 Register */
  871. #define SPORT2_RCR2 0xffc02524 /* SPORT2 Receive Configuration 2 Register */
  872. #define SPORT2_RCLKDIV 0xffc02528 /* SPORT2 Receive Serial Clock Divider Register */
  873. #define SPORT2_RFSDIV 0xffc0252c /* SPORT2 Receive Frame Sync Divider Register */
  874. #define SPORT2_STAT 0xffc02530 /* SPORT2 Status Register */
  875. #define SPORT2_CHNL 0xffc02534 /* SPORT2 Current Channel Register */
  876. #define SPORT2_MCMC1 0xffc02538 /* SPORT2 Multi channel Configuration Register 1 */
  877. #define SPORT2_MCMC2 0xffc0253c /* SPORT2 Multi channel Configuration Register 2 */
  878. #define SPORT2_MTCS0 0xffc02540 /* SPORT2 Multi channel Transmit Select Register 0 */
  879. #define SPORT2_MTCS1 0xffc02544 /* SPORT2 Multi channel Transmit Select Register 1 */
  880. #define SPORT2_MTCS2 0xffc02548 /* SPORT2 Multi channel Transmit Select Register 2 */
  881. #define SPORT2_MTCS3 0xffc0254c /* SPORT2 Multi channel Transmit Select Register 3 */
  882. #define SPORT2_MRCS0 0xffc02550 /* SPORT2 Multi channel Receive Select Register 0 */
  883. #define SPORT2_MRCS1 0xffc02554 /* SPORT2 Multi channel Receive Select Register 1 */
  884. #define SPORT2_MRCS2 0xffc02558 /* SPORT2 Multi channel Receive Select Register 2 */
  885. #define SPORT2_MRCS3 0xffc0255c /* SPORT2 Multi channel Receive Select Register 3 */
  886. /* SPORT3 Registers */
  887. #define SPORT3_TCR1 0xffc02600 /* SPORT3 Transmit Configuration 1 Register */
  888. #define SPORT3_TCR2 0xffc02604 /* SPORT3 Transmit Configuration 2 Register */
  889. #define SPORT3_TCLKDIV 0xffc02608 /* SPORT3 Transmit Serial Clock Divider Register */
  890. #define SPORT3_TFSDIV 0xffc0260c /* SPORT3 Transmit Frame Sync Divider Register */
  891. #define SPORT3_TX 0xffc02610 /* SPORT3 Transmit Data Register */
  892. #define SPORT3_RX 0xffc02618 /* SPORT3 Receive Data Register */
  893. #define SPORT3_RCR1 0xffc02620 /* SPORT3 Receive Configuration 1 Register */
  894. #define SPORT3_RCR2 0xffc02624 /* SPORT3 Receive Configuration 2 Register */
  895. #define SPORT3_RCLKDIV 0xffc02628 /* SPORT3 Receive Serial Clock Divider Register */
  896. #define SPORT3_RFSDIV 0xffc0262c /* SPORT3 Receive Frame Sync Divider Register */
  897. #define SPORT3_STAT 0xffc02630 /* SPORT3 Status Register */
  898. #define SPORT3_CHNL 0xffc02634 /* SPORT3 Current Channel Register */
  899. #define SPORT3_MCMC1 0xffc02638 /* SPORT3 Multi channel Configuration Register 1 */
  900. #define SPORT3_MCMC2 0xffc0263c /* SPORT3 Multi channel Configuration Register 2 */
  901. #define SPORT3_MTCS0 0xffc02640 /* SPORT3 Multi channel Transmit Select Register 0 */
  902. #define SPORT3_MTCS1 0xffc02644 /* SPORT3 Multi channel Transmit Select Register 1 */
  903. #define SPORT3_MTCS2 0xffc02648 /* SPORT3 Multi channel Transmit Select Register 2 */
  904. #define SPORT3_MTCS3 0xffc0264c /* SPORT3 Multi channel Transmit Select Register 3 */
  905. #define SPORT3_MRCS0 0xffc02650 /* SPORT3 Multi channel Receive Select Register 0 */
  906. #define SPORT3_MRCS1 0xffc02654 /* SPORT3 Multi channel Receive Select Register 1 */
  907. #define SPORT3_MRCS2 0xffc02658 /* SPORT3 Multi channel Receive Select Register 2 */
  908. #define SPORT3_MRCS3 0xffc0265c /* SPORT3 Multi channel Receive Select Register 3 */
  909. /* EPPI2 Registers */
  910. #define EPPI2_STATUS 0xffc02900 /* EPPI2 Status Register */
  911. #define EPPI2_HCOUNT 0xffc02904 /* EPPI2 Horizontal Transfer Count Register */
  912. #define EPPI2_HDELAY 0xffc02908 /* EPPI2 Horizontal Delay Count Register */
  913. #define EPPI2_VCOUNT 0xffc0290c /* EPPI2 Vertical Transfer Count Register */
  914. #define EPPI2_VDELAY 0xffc02910 /* EPPI2 Vertical Delay Count Register */
  915. #define EPPI2_FRAME 0xffc02914 /* EPPI2 Lines per Frame Register */
  916. #define EPPI2_LINE 0xffc02918 /* EPPI2 Samples per Line Register */
  917. #define EPPI2_CLKDIV 0xffc0291c /* EPPI2 Clock Divide Register */
  918. #define EPPI2_CONTROL 0xffc02920 /* EPPI2 Control Register */
  919. #define EPPI2_FS1W_HBL 0xffc02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
  920. #define EPPI2_FS1P_AVPL 0xffc02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
  921. #define EPPI2_FS2W_LVB 0xffc0292c /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
  922. #define EPPI2_FS2P_LAVF 0xffc02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
  923. #define EPPI2_CLIP 0xffc02934 /* EPPI2 Clipping Register */
  924. /* CAN Controller 0 Config 1 Registers */
  925. #define CAN0_MC1 0xffc02a00 /* CAN Controller 0 Mailbox Configuration Register 1 */
  926. #define CAN0_MD1 0xffc02a04 /* CAN Controller 0 Mailbox Direction Register 1 */
  927. #define CAN0_TRS1 0xffc02a08 /* CAN Controller 0 Transmit Request Set Register 1 */
  928. #define CAN0_TRR1 0xffc02a0c /* CAN Controller 0 Transmit Request Reset Register 1 */
  929. #define CAN0_TA1 0xffc02a10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
  930. #define CAN0_AA1 0xffc02a14 /* CAN Controller 0 Abort Acknowledge Register 1 */
  931. #define CAN0_RMP1 0xffc02a18 /* CAN Controller 0 Receive Message Pending Register 1 */
  932. #define CAN0_RML1 0xffc02a1c /* CAN Controller 0 Receive Message Lost Register 1 */
  933. #define CAN0_MBTIF1 0xffc02a20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
  934. #define CAN0_MBRIF1 0xffc02a24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
  935. #define CAN0_MBIM1 0xffc02a28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
  936. #define CAN0_RFH1 0xffc02a2c /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
  937. #define CAN0_OPSS1 0xffc02a30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
  938. /* CAN Controller 0 Config 2 Registers */
  939. #define CAN0_MC2 0xffc02a40 /* CAN Controller 0 Mailbox Configuration Register 2 */
  940. #define CAN0_MD2 0xffc02a44 /* CAN Controller 0 Mailbox Direction Register 2 */
  941. #define CAN0_TRS2 0xffc02a48 /* CAN Controller 0 Transmit Request Set Register 2 */
  942. #define CAN0_TRR2 0xffc02a4c /* CAN Controller 0 Transmit Request Reset Register 2 */
  943. #define CAN0_TA2 0xffc02a50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
  944. #define CAN0_AA2 0xffc02a54 /* CAN Controller 0 Abort Acknowledge Register 2 */
  945. #define CAN0_RMP2 0xffc02a58 /* CAN Controller 0 Receive Message Pending Register 2 */
  946. #define CAN0_RML2 0xffc02a5c /* CAN Controller 0 Receive Message Lost Register 2 */
  947. #define CAN0_MBTIF2 0xffc02a60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
  948. #define CAN0_MBRIF2 0xffc02a64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
  949. #define CAN0_MBIM2 0xffc02a68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
  950. #define CAN0_RFH2 0xffc02a6c /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
  951. #define CAN0_OPSS2 0xffc02a70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
  952. /* CAN Controller 0 Clock/Interrupt/Counter Registers */
  953. #define CAN0_CLOCK 0xffc02a80 /* CAN Controller 0 Clock Register */
  954. #define CAN0_TIMING 0xffc02a84 /* CAN Controller 0 Timing Register */
  955. #define CAN0_DEBUG 0xffc02a88 /* CAN Controller 0 Debug Register */
  956. #define CAN0_STATUS 0xffc02a8c /* CAN Controller 0 Global Status Register */
  957. #define CAN0_CEC 0xffc02a90 /* CAN Controller 0 Error Counter Register */
  958. #define CAN0_GIS 0xffc02a94 /* CAN Controller 0 Global Interrupt Status Register */
  959. #define CAN0_GIM 0xffc02a98 /* CAN Controller 0 Global Interrupt Mask Register */
  960. #define CAN0_GIF 0xffc02a9c /* CAN Controller 0 Global Interrupt Flag Register */
  961. #define CAN0_CONTROL 0xffc02aa0 /* CAN Controller 0 Master Control Register */
  962. #define CAN0_INTR 0xffc02aa4 /* CAN Controller 0 Interrupt Pending Register */
  963. #define CAN0_MBTD 0xffc02aac /* CAN Controller 0 Mailbox Temporary Disable Register */
  964. #define CAN0_EWR 0xffc02ab0 /* CAN Controller 0 Programmable Warning Level Register */
  965. #define CAN0_ESR 0xffc02ab4 /* CAN Controller 0 Error Status Register */
  966. #define CAN0_UCCNT 0xffc02ac4 /* CAN Controller 0 Universal Counter Register */
  967. #define CAN0_UCRC 0xffc02ac8 /* CAN Controller 0 Universal Counter Force Reload Register */
  968. #define CAN0_UCCNF 0xffc02acc /* CAN Controller 0 Universal Counter Configuration Register */
  969. /* CAN Controller 0 Acceptance Registers */
  970. #define CAN0_AM00L 0xffc02b00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
  971. #define CAN0_AM00H 0xffc02b04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
  972. #define CAN0_AM01L 0xffc02b08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
  973. #define CAN0_AM01H 0xffc02b0c /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
  974. #define CAN0_AM02L 0xffc02b10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
  975. #define CAN0_AM02H 0xffc02b14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
  976. #define CAN0_AM03L 0xffc02b18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
  977. #define CAN0_AM03H 0xffc02b1c /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
  978. #define CAN0_AM04L 0xffc02b20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
  979. #define CAN0_AM04H 0xffc02b24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
  980. #define CAN0_AM05L 0xffc02b28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
  981. #define CAN0_AM05H 0xffc02b2c /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
  982. #define CAN0_AM06L 0xffc02b30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
  983. #define CAN0_AM06H 0xffc02b34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
  984. #define CAN0_AM07L 0xffc02b38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
  985. #define CAN0_AM07H 0xffc02b3c /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
  986. #define CAN0_AM08L 0xffc02b40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
  987. #define CAN0_AM08H 0xffc02b44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
  988. #define CAN0_AM09L 0xffc02b48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
  989. #define CAN0_AM09H 0xffc02b4c /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
  990. #define CAN0_AM10L 0xffc02b50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
  991. #define CAN0_AM10H 0xffc02b54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
  992. #define CAN0_AM11L 0xffc02b58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
  993. #define CAN0_AM11H 0xffc02b5c /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
  994. #define CAN0_AM12L 0xffc02b60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
  995. #define CAN0_AM12H 0xffc02b64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
  996. #define CAN0_AM13L 0xffc02b68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
  997. #define CAN0_AM13H 0xffc02b6c /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
  998. #define CAN0_AM14L 0xffc02b70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
  999. #define CAN0_AM14H 0xffc02b74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
  1000. #define CAN0_AM15L 0xffc02b78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
  1001. #define CAN0_AM15H 0xffc02b7c /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
  1002. /* CAN Controller 0 Acceptance Registers */
  1003. #define CAN0_AM16L 0xffc02b80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
  1004. #define CAN0_AM16H 0xffc02b84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
  1005. #define CAN0_AM17L 0xffc02b88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
  1006. #define CAN0_AM17H 0xffc02b8c /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
  1007. #define CAN0_AM18L 0xffc02b90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
  1008. #define CAN0_AM18H 0xffc02b94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
  1009. #define CAN0_AM19L 0xffc02b98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
  1010. #define CAN0_AM19H 0xffc02b9c /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
  1011. #define CAN0_AM20L 0xffc02ba0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
  1012. #define CAN0_AM20H 0xffc02ba4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
  1013. #define CAN0_AM21L 0xffc02ba8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
  1014. #define CAN0_AM21H 0xffc02bac /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
  1015. #define CAN0_AM22L 0xffc02bb0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
  1016. #define CAN0_AM22H 0xffc02bb4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
  1017. #define CAN0_AM23L 0xffc02bb8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
  1018. #define CAN0_AM23H 0xffc02bbc /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
  1019. #define CAN0_AM24L 0xffc02bc0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
  1020. #define CAN0_AM24H 0xffc02bc4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
  1021. #define CAN0_AM25L 0xffc02bc8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
  1022. #define CAN0_AM25H 0xffc02bcc /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
  1023. #define CAN0_AM26L 0xffc02bd0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
  1024. #define CAN0_AM26H 0xffc02bd4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
  1025. #define CAN0_AM27L 0xffc02bd8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
  1026. #define CAN0_AM27H 0xffc02bdc /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
  1027. #define CAN0_AM28L 0xffc02be0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
  1028. #define CAN0_AM28H 0xffc02be4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
  1029. #define CAN0_AM29L 0xffc02be8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
  1030. #define CAN0_AM29H 0xffc02bec /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
  1031. #define CAN0_AM30L 0xffc02bf0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
  1032. #define CAN0_AM30H 0xffc02bf4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
  1033. #define CAN0_AM31L 0xffc02bf8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
  1034. #define CAN0_AM31H 0xffc02bfc /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
  1035. /* CAN Controller 0 Mailbox Data Registers */
  1036. #define CAN0_MB00_DATA0 0xffc02c00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
  1037. #define CAN0_MB00_DATA1 0xffc02c04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
  1038. #define CAN0_MB00_DATA2 0xffc02c08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
  1039. #define CAN0_MB00_DATA3 0xffc02c0c /* CAN Controller 0 Mailbox 0 Data 3 Register */
  1040. #define CAN0_MB00_LENGTH 0xffc02c10 /* CAN Controller 0 Mailbox 0 Length Register */
  1041. #define CAN0_MB00_TIMESTAMP 0xffc02c14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
  1042. #define CAN0_MB00_ID0 0xffc02c18 /* CAN Controller 0 Mailbox 0 ID0 Register */
  1043. #define CAN0_MB00_ID1 0xffc02c1c /* CAN Controller 0 Mailbox 0 ID1 Register */
  1044. #define CAN0_MB01_DATA0 0xffc02c20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
  1045. #define CAN0_MB01_DATA1 0xffc02c24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
  1046. #define CAN0_MB01_DATA2 0xffc02c28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
  1047. #define CAN0_MB01_DATA3 0xffc02c2c /* CAN Controller 0 Mailbox 1 Data 3 Register */
  1048. #define CAN0_MB01_LENGTH 0xffc02c30 /* CAN Controller 0 Mailbox 1 Length Register */
  1049. #define CAN0_MB01_TIMESTAMP 0xffc02c34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
  1050. #define CAN0_MB01_ID0 0xffc02c38 /* CAN Controller 0 Mailbox 1 ID0 Register */
  1051. #define CAN0_MB01_ID1 0xffc02c3c /* CAN Controller 0 Mailbox 1 ID1 Register */
  1052. #define CAN0_MB02_DATA0 0xffc02c40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
  1053. #define CAN0_MB02_DATA1 0xffc02c44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
  1054. #define CAN0_MB02_DATA2 0xffc02c48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
  1055. #define CAN0_MB02_DATA3 0xffc02c4c /* CAN Controller 0 Mailbox 2 Data 3 Register */
  1056. #define CAN0_MB02_LENGTH 0xffc02c50 /* CAN Controller 0 Mailbox 2 Length Register */
  1057. #define CAN0_MB02_TIMESTAMP 0xffc02c54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
  1058. #define CAN0_MB02_ID0 0xffc02c58 /* CAN Controller 0 Mailbox 2 ID0 Register */
  1059. #define CAN0_MB02_ID1 0xffc02c5c /* CAN Controller 0 Mailbox 2 ID1 Register */
  1060. #define CAN0_MB03_DATA0 0xffc02c60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
  1061. #define CAN0_MB03_DATA1 0xffc02c64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
  1062. #define CAN0_MB03_DATA2 0xffc02c68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
  1063. #define CAN0_MB03_DATA3 0xffc02c6c /* CAN Controller 0 Mailbox 3 Data 3 Register */
  1064. #define CAN0_MB03_LENGTH 0xffc02c70 /* CAN Controller 0 Mailbox 3 Length Register */
  1065. #define CAN0_MB03_TIMESTAMP 0xffc02c74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
  1066. #define CAN0_MB03_ID0 0xffc02c78 /* CAN Controller 0 Mailbox 3 ID0 Register */
  1067. #define CAN0_MB03_ID1 0xffc02c7c /* CAN Controller 0 Mailbox 3 ID1 Register */
  1068. #define CAN0_MB04_DATA0 0xffc02c80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
  1069. #define CAN0_MB04_DATA1 0xffc02c84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
  1070. #define CAN0_MB04_DATA2 0xffc02c88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
  1071. #define CAN0_MB04_DATA3 0xffc02c8c /* CAN Controller 0 Mailbox 4 Data 3 Register */
  1072. #define CAN0_MB04_LENGTH 0xffc02c90 /* CAN Controller 0 Mailbox 4 Length Register */
  1073. #define CAN0_MB04_TIMESTAMP 0xffc02c94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
  1074. #define CAN0_MB04_ID0 0xffc02c98 /* CAN Controller 0 Mailbox 4 ID0 Register */
  1075. #define CAN0_MB04_ID1 0xffc02c9c /* CAN Controller 0 Mailbox 4 ID1 Register */
  1076. #define CAN0_MB05_DATA0 0xffc02ca0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
  1077. #define CAN0_MB05_DATA1 0xffc02ca4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
  1078. #define CAN0_MB05_DATA2 0xffc02ca8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
  1079. #define CAN0_MB05_DATA3 0xffc02cac /* CAN Controller 0 Mailbox 5 Data 3 Register */
  1080. #define CAN0_MB05_LENGTH 0xffc02cb0 /* CAN Controller 0 Mailbox 5 Length Register */
  1081. #define CAN0_MB05_TIMESTAMP 0xffc02cb4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
  1082. #define CAN0_MB05_ID0 0xffc02cb8 /* CAN Controller 0 Mailbox 5 ID0 Register */
  1083. #define CAN0_MB05_ID1 0xffc02cbc /* CAN Controller 0 Mailbox 5 ID1 Register */
  1084. #define CAN0_MB06_DATA0 0xffc02cc0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
  1085. #define CAN0_MB06_DATA1 0xffc02cc4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
  1086. #define CAN0_MB06_DATA2 0xffc02cc8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
  1087. #define CAN0_MB06_DATA3 0xffc02ccc /* CAN Controller 0 Mailbox 6 Data 3 Register */
  1088. #define CAN0_MB06_LENGTH 0xffc02cd0 /* CAN Controller 0 Mailbox 6 Length Register */
  1089. #define CAN0_MB06_TIMESTAMP 0xffc02cd4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
  1090. #define CAN0_MB06_ID0 0xffc02cd8 /* CAN Controller 0 Mailbox 6 ID0 Register */
  1091. #define CAN0_MB06_ID1 0xffc02cdc /* CAN Controller 0 Mailbox 6 ID1 Register */
  1092. #define CAN0_MB07_DATA0 0xffc02ce0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
  1093. #define CAN0_MB07_DATA1 0xffc02ce4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
  1094. #define CAN0_MB07_DATA2 0xffc02ce8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
  1095. #define CAN0_MB07_DATA3 0xffc02cec /* CAN Controller 0 Mailbox 7 Data 3 Register */
  1096. #define CAN0_MB07_LENGTH 0xffc02cf0 /* CAN Controller 0 Mailbox 7 Length Register */
  1097. #define CAN0_MB07_TIMESTAMP 0xffc02cf4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
  1098. #define CAN0_MB07_ID0 0xffc02cf8 /* CAN Controller 0 Mailbox 7 ID0 Register */
  1099. #define CAN0_MB07_ID1 0xffc02cfc /* CAN Controller 0 Mailbox 7 ID1 Register */
  1100. #define CAN0_MB08_DATA0 0xffc02d00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
  1101. #define CAN0_MB08_DATA1 0xffc02d04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
  1102. #define CAN0_MB08_DATA2 0xffc02d08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
  1103. #define CAN0_MB08_DATA3 0xffc02d0c /* CAN Controller 0 Mailbox 8 Data 3 Register */
  1104. #define CAN0_MB08_LENGTH 0xffc02d10 /* CAN Controller 0 Mailbox 8 Length Register */
  1105. #define CAN0_MB08_TIMESTAMP 0xffc02d14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
  1106. #define CAN0_MB08_ID0 0xffc02d18 /* CAN Controller 0 Mailbox 8 ID0 Register */
  1107. #define CAN0_MB08_ID1 0xffc02d1c /* CAN Controller 0 Mailbox 8 ID1 Register */
  1108. #define CAN0_MB09_DATA0 0xffc02d20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
  1109. #define CAN0_MB09_DATA1 0xffc02d24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
  1110. #define CAN0_MB09_DATA2 0xffc02d28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
  1111. #define CAN0_MB09_DATA3 0xffc02d2c /* CAN Controller 0 Mailbox 9 Data 3 Register */
  1112. #define CAN0_MB09_LENGTH 0xffc02d30 /* CAN Controller 0 Mailbox 9 Length Register */
  1113. #define CAN0_MB09_TIMESTAMP 0xffc02d34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
  1114. #define CAN0_MB09_ID0 0xffc02d38 /* CAN Controller 0 Mailbox 9 ID0 Register */
  1115. #define CAN0_MB09_ID1 0xffc02d3c /* CAN Controller 0 Mailbox 9 ID1 Register */
  1116. #define CAN0_MB10_DATA0 0xffc02d40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
  1117. #define CAN0_MB10_DATA1 0xffc02d44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
  1118. #define CAN0_MB10_DATA2 0xffc02d48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
  1119. #define CAN0_MB10_DATA3 0xffc02d4c /* CAN Controller 0 Mailbox 10 Data 3 Register */
  1120. #define CAN0_MB10_LENGTH 0xffc02d50 /* CAN Controller 0 Mailbox 10 Length Register */
  1121. #define CAN0_MB10_TIMESTAMP 0xffc02d54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
  1122. #define CAN0_MB10_ID0 0xffc02d58 /* CAN Controller 0 Mailbox 10 ID0 Register */
  1123. #define CAN0_MB10_ID1 0xffc02d5c /* CAN Controller 0 Mailbox 10 ID1 Register */
  1124. #define CAN0_MB11_DATA0 0xffc02d60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
  1125. #define CAN0_MB11_DATA1 0xffc02d64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
  1126. #define CAN0_MB11_DATA2 0xffc02d68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
  1127. #define CAN0_MB11_DATA3 0xffc02d6c /* CAN Controller 0 Mailbox 11 Data 3 Register */
  1128. #define CAN0_MB11_LENGTH 0xffc02d70 /* CAN Controller 0 Mailbox 11 Length Register */
  1129. #define CAN0_MB11_TIMESTAMP 0xffc02d74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
  1130. #define CAN0_MB11_ID0 0xffc02d78 /* CAN Controller 0 Mailbox 11 ID0 Register */
  1131. #define CAN0_MB11_ID1 0xffc02d7c /* CAN Controller 0 Mailbox 11 ID1 Register */
  1132. #define CAN0_MB12_DATA0 0xffc02d80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
  1133. #define CAN0_MB12_DATA1 0xffc02d84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
  1134. #define CAN0_MB12_DATA2 0xffc02d88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
  1135. #define CAN0_MB12_DATA3 0xffc02d8c /* CAN Controller 0 Mailbox 12 Data 3 Register */
  1136. #define CAN0_MB12_LENGTH 0xffc02d90 /* CAN Controller 0 Mailbox 12 Length Register */
  1137. #define CAN0_MB12_TIMESTAMP 0xffc02d94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
  1138. #define CAN0_MB12_ID0 0xffc02d98 /* CAN Controller 0 Mailbox 12 ID0 Register */
  1139. #define CAN0_MB12_ID1 0xffc02d9c /* CAN Controller 0 Mailbox 12 ID1 Register */
  1140. #define CAN0_MB13_DATA0 0xffc02da0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
  1141. #define CAN0_MB13_DATA1 0xffc02da4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
  1142. #define CAN0_MB13_DATA2 0xffc02da8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
  1143. #define CAN0_MB13_DATA3 0xffc02dac /* CAN Controller 0 Mailbox 13 Data 3 Register */
  1144. #define CAN0_MB13_LENGTH 0xffc02db0 /* CAN Controller 0 Mailbox 13 Length Register */
  1145. #define CAN0_MB13_TIMESTAMP 0xffc02db4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
  1146. #define CAN0_MB13_ID0 0xffc02db8 /* CAN Controller 0 Mailbox 13 ID0 Register */
  1147. #define CAN0_MB13_ID1 0xffc02dbc /* CAN Controller 0 Mailbox 13 ID1 Register */
  1148. #define CAN0_MB14_DATA0 0xffc02dc0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
  1149. #define CAN0_MB14_DATA1 0xffc02dc4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
  1150. #define CAN0_MB14_DATA2 0xffc02dc8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
  1151. #define CAN0_MB14_DATA3 0xffc02dcc /* CAN Controller 0 Mailbox 14 Data 3 Register */
  1152. #define CAN0_MB14_LENGTH 0xffc02dd0 /* CAN Controller 0 Mailbox 14 Length Register */
  1153. #define CAN0_MB14_TIMESTAMP 0xffc02dd4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
  1154. #define CAN0_MB14_ID0 0xffc02dd8 /* CAN Controller 0 Mailbox 14 ID0 Register */
  1155. #define CAN0_MB14_ID1 0xffc02ddc /* CAN Controller 0 Mailbox 14 ID1 Register */
  1156. #define CAN0_MB15_DATA0 0xffc02de0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
  1157. #define CAN0_MB15_DATA1 0xffc02de4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
  1158. #define CAN0_MB15_DATA2 0xffc02de8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
  1159. #define CAN0_MB15_DATA3 0xffc02dec /* CAN Controller 0 Mailbox 15 Data 3 Register */
  1160. #define CAN0_MB15_LENGTH 0xffc02df0 /* CAN Controller 0 Mailbox 15 Length Register */
  1161. #define CAN0_MB15_TIMESTAMP 0xffc02df4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
  1162. #define CAN0_MB15_ID0 0xffc02df8 /* CAN Controller 0 Mailbox 15 ID0 Register */
  1163. #define CAN0_MB15_ID1 0xffc02dfc /* CAN Controller 0 Mailbox 15 ID1 Register */
  1164. /* CAN Controller 0 Mailbox Data Registers */
  1165. #define CAN0_MB16_DATA0 0xffc02e00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
  1166. #define CAN0_MB16_DATA1 0xffc02e04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
  1167. #define CAN0_MB16_DATA2 0xffc02e08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
  1168. #define CAN0_MB16_DATA3 0xffc02e0c /* CAN Controller 0 Mailbox 16 Data 3 Register */
  1169. #define CAN0_MB16_LENGTH 0xffc02e10 /* CAN Controller 0 Mailbox 16 Length Register */
  1170. #define CAN0_MB16_TIMESTAMP 0xffc02e14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
  1171. #define CAN0_MB16_ID0 0xffc02e18 /* CAN Controller 0 Mailbox 16 ID0 Register */
  1172. #define CAN0_MB16_ID1 0xffc02e1c /* CAN Controller 0 Mailbox 16 ID1 Register */
  1173. #define CAN0_MB17_DATA0 0xffc02e20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
  1174. #define CAN0_MB17_DATA1 0xffc02e24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
  1175. #define CAN0_MB17_DATA2 0xffc02e28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
  1176. #define CAN0_MB17_DATA3 0xffc02e2c /* CAN Controller 0 Mailbox 17 Data 3 Register */
  1177. #define CAN0_MB17_LENGTH 0xffc02e30 /* CAN Controller 0 Mailbox 17 Length Register */
  1178. #define CAN0_MB17_TIMESTAMP 0xffc02e34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
  1179. #define CAN0_MB17_ID0 0xffc02e38 /* CAN Controller 0 Mailbox 17 ID0 Register */
  1180. #define CAN0_MB17_ID1 0xffc02e3c /* CAN Controller 0 Mailbox 17 ID1 Register */
  1181. #define CAN0_MB18_DATA0 0xffc02e40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
  1182. #define CAN0_MB18_DATA1 0xffc02e44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
  1183. #define CAN0_MB18_DATA2 0xffc02e48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
  1184. #define CAN0_MB18_DATA3 0xffc02e4c /* CAN Controller 0 Mailbox 18 Data 3 Register */
  1185. #define CAN0_MB18_LENGTH 0xffc02e50 /* CAN Controller 0 Mailbox 18 Length Register */
  1186. #define CAN0_MB18_TIMESTAMP 0xffc02e54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
  1187. #define CAN0_MB18_ID0 0xffc02e58 /* CAN Controller 0 Mailbox 18 ID0 Register */
  1188. #define CAN0_MB18_ID1 0xffc02e5c /* CAN Controller 0 Mailbox 18 ID1 Register */
  1189. #define CAN0_MB19_DATA0 0xffc02e60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
  1190. #define CAN0_MB19_DATA1 0xffc02e64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
  1191. #define CAN0_MB19_DATA2 0xffc02e68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
  1192. #define CAN0_MB19_DATA3 0xffc02e6c /* CAN Controller 0 Mailbox 19 Data 3 Register */
  1193. #define CAN0_MB19_LENGTH 0xffc02e70 /* CAN Controller 0 Mailbox 19 Length Register */
  1194. #define CAN0_MB19_TIMESTAMP 0xffc02e74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
  1195. #define CAN0_MB19_ID0 0xffc02e78 /* CAN Controller 0 Mailbox 19 ID0 Register */
  1196. #define CAN0_MB19_ID1 0xffc02e7c /* CAN Controller 0 Mailbox 19 ID1 Register */
  1197. #define CAN0_MB20_DATA0 0xffc02e80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
  1198. #define CAN0_MB20_DATA1 0xffc02e84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
  1199. #define CAN0_MB20_DATA2 0xffc02e88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
  1200. #define CAN0_MB20_DATA3 0xffc02e8c /* CAN Controller 0 Mailbox 20 Data 3 Register */
  1201. #define CAN0_MB20_LENGTH 0xffc02e90 /* CAN Controller 0 Mailbox 20 Length Register */
  1202. #define CAN0_MB20_TIMESTAMP 0xffc02e94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
  1203. #define CAN0_MB20_ID0 0xffc02e98 /* CAN Controller 0 Mailbox 20 ID0 Register */
  1204. #define CAN0_MB20_ID1 0xffc02e9c /* CAN Controller 0 Mailbox 20 ID1 Register */
  1205. #define CAN0_MB21_DATA0 0xffc02ea0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
  1206. #define CAN0_MB21_DATA1 0xffc02ea4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
  1207. #define CAN0_MB21_DATA2 0xffc02ea8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
  1208. #define CAN0_MB21_DATA3 0xffc02eac /* CAN Controller 0 Mailbox 21 Data 3 Register */
  1209. #define CAN0_MB21_LENGTH 0xffc02eb0 /* CAN Controller 0 Mailbox 21 Length Register */
  1210. #define CAN0_MB21_TIMESTAMP 0xffc02eb4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
  1211. #define CAN0_MB21_ID0 0xffc02eb8 /* CAN Controller 0 Mailbox 21 ID0 Register */
  1212. #define CAN0_MB21_ID1 0xffc02ebc /* CAN Controller 0 Mailbox 21 ID1 Register */
  1213. #define CAN0_MB22_DATA0 0xffc02ec0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
  1214. #define CAN0_MB22_DATA1 0xffc02ec4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
  1215. #define CAN0_MB22_DATA2 0xffc02ec8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
  1216. #define CAN0_MB22_DATA3 0xffc02ecc /* CAN Controller 0 Mailbox 22 Data 3 Register */
  1217. #define CAN0_MB22_LENGTH 0xffc02ed0 /* CAN Controller 0 Mailbox 22 Length Register */
  1218. #define CAN0_MB22_TIMESTAMP 0xffc02ed4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
  1219. #define CAN0_MB22_ID0 0xffc02ed8 /* CAN Controller 0 Mailbox 22 ID0 Register */
  1220. #define CAN0_MB22_ID1 0xffc02edc /* CAN Controller 0 Mailbox 22 ID1 Register */
  1221. #define CAN0_MB23_DATA0 0xffc02ee0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
  1222. #define CAN0_MB23_DATA1 0xffc02ee4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
  1223. #define CAN0_MB23_DATA2 0xffc02ee8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
  1224. #define CAN0_MB23_DATA3 0xffc02eec /* CAN Controller 0 Mailbox 23 Data 3 Register */
  1225. #define CAN0_MB23_LENGTH 0xffc02ef0 /* CAN Controller 0 Mailbox 23 Length Register */
  1226. #define CAN0_MB23_TIMESTAMP 0xffc02ef4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
  1227. #define CAN0_MB23_ID0 0xffc02ef8 /* CAN Controller 0 Mailbox 23 ID0 Register */
  1228. #define CAN0_MB23_ID1 0xffc02efc /* CAN Controller 0 Mailbox 23 ID1 Register */
  1229. #define CAN0_MB24_DATA0 0xffc02f00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
  1230. #define CAN0_MB24_DATA1 0xffc02f04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
  1231. #define CAN0_MB24_DATA2 0xffc02f08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
  1232. #define CAN0_MB24_DATA3 0xffc02f0c /* CAN Controller 0 Mailbox 24 Data 3 Register */
  1233. #define CAN0_MB24_LENGTH 0xffc02f10 /* CAN Controller 0 Mailbox 24 Length Register */
  1234. #define CAN0_MB24_TIMESTAMP 0xffc02f14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
  1235. #define CAN0_MB24_ID0 0xffc02f18 /* CAN Controller 0 Mailbox 24 ID0 Register */
  1236. #define CAN0_MB24_ID1 0xffc02f1c /* CAN Controller 0 Mailbox 24 ID1 Register */
  1237. #define CAN0_MB25_DATA0 0xffc02f20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
  1238. #define CAN0_MB25_DATA1 0xffc02f24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
  1239. #define CAN0_MB25_DATA2 0xffc02f28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
  1240. #define CAN0_MB25_DATA3 0xffc02f2c /* CAN Controller 0 Mailbox 25 Data 3 Register */
  1241. #define CAN0_MB25_LENGTH 0xffc02f30 /* CAN Controller 0 Mailbox 25 Length Register */
  1242. #define CAN0_MB25_TIMESTAMP 0xffc02f34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
  1243. #define CAN0_MB25_ID0 0xffc02f38 /* CAN Controller 0 Mailbox 25 ID0 Register */
  1244. #define CAN0_MB25_ID1 0xffc02f3c /* CAN Controller 0 Mailbox 25 ID1 Register */
  1245. #define CAN0_MB26_DATA0 0xffc02f40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
  1246. #define CAN0_MB26_DATA1 0xffc02f44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
  1247. #define CAN0_MB26_DATA2 0xffc02f48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
  1248. #define CAN0_MB26_DATA3 0xffc02f4c /* CAN Controller 0 Mailbox 26 Data 3 Register */
  1249. #define CAN0_MB26_LENGTH 0xffc02f50 /* CAN Controller 0 Mailbox 26 Length Register */
  1250. #define CAN0_MB26_TIMESTAMP 0xffc02f54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
  1251. #define CAN0_MB26_ID0 0xffc02f58 /* CAN Controller 0 Mailbox 26 ID0 Register */
  1252. #define CAN0_MB26_ID1 0xffc02f5c /* CAN Controller 0 Mailbox 26 ID1 Register */
  1253. #define CAN0_MB27_DATA0 0xffc02f60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
  1254. #define CAN0_MB27_DATA1 0xffc02f64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
  1255. #define CAN0_MB27_DATA2 0xffc02f68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
  1256. #define CAN0_MB27_DATA3 0xffc02f6c /* CAN Controller 0 Mailbox 27 Data 3 Register */
  1257. #define CAN0_MB27_LENGTH 0xffc02f70 /* CAN Controller 0 Mailbox 27 Length Register */
  1258. #define CAN0_MB27_TIMESTAMP 0xffc02f74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
  1259. #define CAN0_MB27_ID0 0xffc02f78 /* CAN Controller 0 Mailbox 27 ID0 Register */
  1260. #define CAN0_MB27_ID1 0xffc02f7c /* CAN Controller 0 Mailbox 27 ID1 Register */
  1261. #define CAN0_MB28_DATA0 0xffc02f80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
  1262. #define CAN0_MB28_DATA1 0xffc02f84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
  1263. #define CAN0_MB28_DATA2 0xffc02f88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
  1264. #define CAN0_MB28_DATA3 0xffc02f8c /* CAN Controller 0 Mailbox 28 Data 3 Register */
  1265. #define CAN0_MB28_LENGTH 0xffc02f90 /* CAN Controller 0 Mailbox 28 Length Register */
  1266. #define CAN0_MB28_TIMESTAMP 0xffc02f94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
  1267. #define CAN0_MB28_ID0 0xffc02f98 /* CAN Controller 0 Mailbox 28 ID0 Register */
  1268. #define CAN0_MB28_ID1 0xffc02f9c /* CAN Controller 0 Mailbox 28 ID1 Register */
  1269. #define CAN0_MB29_DATA0 0xffc02fa0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
  1270. #define CAN0_MB29_DATA1 0xffc02fa4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
  1271. #define CAN0_MB29_DATA2 0xffc02fa8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
  1272. #define CAN0_MB29_DATA3 0xffc02fac /* CAN Controller 0 Mailbox 29 Data 3 Register */
  1273. #define CAN0_MB29_LENGTH 0xffc02fb0 /* CAN Controller 0 Mailbox 29 Length Register */
  1274. #define CAN0_MB29_TIMESTAMP 0xffc02fb4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
  1275. #define CAN0_MB29_ID0 0xffc02fb8 /* CAN Controller 0 Mailbox 29 ID0 Register */
  1276. #define CAN0_MB29_ID1 0xffc02fbc /* CAN Controller 0 Mailbox 29 ID1 Register */
  1277. #define CAN0_MB30_DATA0 0xffc02fc0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
  1278. #define CAN0_MB30_DATA1 0xffc02fc4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
  1279. #define CAN0_MB30_DATA2 0xffc02fc8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
  1280. #define CAN0_MB30_DATA3 0xffc02fcc /* CAN Controller 0 Mailbox 30 Data 3 Register */
  1281. #define CAN0_MB30_LENGTH 0xffc02fd0 /* CAN Controller 0 Mailbox 30 Length Register */
  1282. #define CAN0_MB30_TIMESTAMP 0xffc02fd4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
  1283. #define CAN0_MB30_ID0 0xffc02fd8 /* CAN Controller 0 Mailbox 30 ID0 Register */
  1284. #define CAN0_MB30_ID1 0xffc02fdc /* CAN Controller 0 Mailbox 30 ID1 Register */
  1285. #define CAN0_MB31_DATA0 0xffc02fe0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
  1286. #define CAN0_MB31_DATA1 0xffc02fe4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
  1287. #define CAN0_MB31_DATA2 0xffc02fe8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
  1288. #define CAN0_MB31_DATA3 0xffc02fec /* CAN Controller 0 Mailbox 31 Data 3 Register */
  1289. #define CAN0_MB31_LENGTH 0xffc02ff0 /* CAN Controller 0 Mailbox 31 Length Register */
  1290. #define CAN0_MB31_TIMESTAMP 0xffc02ff4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
  1291. #define CAN0_MB31_ID0 0xffc02ff8 /* CAN Controller 0 Mailbox 31 ID0 Register */
  1292. #define CAN0_MB31_ID1 0xffc02ffc /* CAN Controller 0 Mailbox 31 ID1 Register */
  1293. /* UART3 Registers */
  1294. #define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */
  1295. #define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */
  1296. #define UART3_GCTL 0xffc03108 /* Global Control Register */
  1297. #define UART3_LCR 0xffc0310c /* Line Control Register */
  1298. #define UART3_MCR 0xffc03110 /* Modem Control Register */
  1299. #define UART3_LSR 0xffc03114 /* Line Status Register */
  1300. #define UART3_MSR 0xffc03118 /* Modem Status Register */
  1301. #define UART3_SCR 0xffc0311c /* Scratch Register */
  1302. #define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */
  1303. #define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */
  1304. #define UART3_THR 0xffc03128 /* Transmit Hold Register */
  1305. #define UART3_RBR 0xffc0312c /* Receive Buffer Register */
  1306. /* NFC Registers */
  1307. #define NFC_CTL 0xffc03b00 /* NAND Control Register */
  1308. #define NFC_STAT 0xffc03b04 /* NAND Status Register */
  1309. #define NFC_IRQSTAT 0xffc03b08 /* NAND Interrupt Status Register */
  1310. #define NFC_IRQMASK 0xffc03b0c /* NAND Interrupt Mask Register */
  1311. #define NFC_ECC0 0xffc03b10 /* NAND ECC Register 0 */
  1312. #define NFC_ECC1 0xffc03b14 /* NAND ECC Register 1 */
  1313. #define NFC_ECC2 0xffc03b18 /* NAND ECC Register 2 */
  1314. #define NFC_ECC3 0xffc03b1c /* NAND ECC Register 3 */
  1315. #define NFC_COUNT 0xffc03b20 /* NAND ECC Count Register */
  1316. #define NFC_RST 0xffc03b24 /* NAND ECC Reset Register */
  1317. #define NFC_PGCTL 0xffc03b28 /* NAND Page Control Register */
  1318. #define NFC_READ 0xffc03b2c /* NAND Read Data Register */
  1319. #define NFC_ADDR 0xffc03b40 /* NAND Address Register */
  1320. #define NFC_CMD 0xffc03b44 /* NAND Command Register */
  1321. #define NFC_DATA_WR 0xffc03b48 /* NAND Data Write Register */
  1322. #define NFC_DATA_RD 0xffc03b4c /* NAND Data Read Register */
  1323. /* Counter Registers */
  1324. #define CNT_CONFIG 0xffc04200 /* Configuration Register */
  1325. #define CNT_IMASK 0xffc04204 /* Interrupt Mask Register */
  1326. #define CNT_STATUS 0xffc04208 /* Status Register */
  1327. #define CNT_COMMAND 0xffc0420c /* Command Register */
  1328. #define CNT_DEBOUNCE 0xffc04210 /* Debounce Register */
  1329. #define CNT_COUNTER 0xffc04214 /* Counter Register */
  1330. #define CNT_MAX 0xffc04218 /* Maximal Count Register */
  1331. #define CNT_MIN 0xffc0421c /* Minimal Count Register */
  1332. /* OTP/FUSE Registers */
  1333. #define OTP_CONTROL 0xffc04300 /* OTP/Fuse Control Register */
  1334. #define OTP_BEN 0xffc04304 /* OTP/Fuse Byte Enable */
  1335. #define OTP_STATUS 0xffc04308 /* OTP/Fuse Status */
  1336. #define OTP_TIMING 0xffc0430c /* OTP/Fuse Access Timing */
  1337. /* Security Registers */
  1338. #define SECURE_SYSSWT 0xffc04320 /* Secure System Switches */
  1339. #define SECURE_CONTROL 0xffc04324 /* Secure Control */
  1340. #define SECURE_STATUS 0xffc04328 /* Secure Status */
  1341. /* DMA Peripheral Mux Register */
  1342. #define DMAC1_PERIMUX 0xffc04340 /* DMA Controller 1 Peripheral Multiplexer Register */
  1343. /* OTP Read/Write Data Buffer Registers */
  1344. #define OTP_DATA0 0xffc04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
  1345. #define OTP_DATA1 0xffc04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
  1346. #define OTP_DATA2 0xffc04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
  1347. #define OTP_DATA3 0xffc0438c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
  1348. /* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 processor */
  1349. /* ********************************************************** */
  1350. /* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
  1351. /* and MULTI BIT READ MACROS */
  1352. /* ********************************************************** */
  1353. /* SIC_IMASK Masks */
  1354. #define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
  1355. #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
  1356. #define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
  1357. #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
  1358. /* SIC_IWR Masks */
  1359. #define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
  1360. #define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
  1361. #define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
  1362. #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
  1363. /* Bit masks for SIC_IAR0 */
  1364. #define PLL_WAKEUP 0x1 /* PLL Wakeup */
  1365. /* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */
  1366. #define DMA0_ERR 0x2 /* DMA Controller 0 Error */
  1367. #define EPPI0_ERR 0x4 /* EPPI0 Error */
  1368. #define SPORT0_ERR 0x8 /* SPORT0 Error */
  1369. #define SPORT1_ERR 0x10 /* SPORT1 Error */
  1370. #define SPI0_ERR 0x20 /* SPI0 Error */
  1371. #define UART0_ERR 0x40 /* UART0 Error */
  1372. #define RTC 0x80 /* Real-Time Clock */
  1373. #define DMA12 0x100 /* DMA Channel 12 */
  1374. #define DMA0 0x200 /* DMA Channel 0 */
  1375. #define DMA1 0x400 /* DMA Channel 1 */
  1376. #define DMA2 0x800 /* DMA Channel 2 */
  1377. #define DMA3 0x1000 /* DMA Channel 3 */
  1378. #define DMA4 0x2000 /* DMA Channel 4 */
  1379. #define DMA6 0x4000 /* DMA Channel 6 */
  1380. #define DMA7 0x8000 /* DMA Channel 7 */
  1381. #define PINT0 0x80000 /* Pin Interrupt 0 */
  1382. #define PINT1 0x100000 /* Pin Interrupt 1 */
  1383. #define MDMA0 0x200000 /* Memory DMA Stream 0 */
  1384. #define MDMA1 0x400000 /* Memory DMA Stream 1 */
  1385. #define WDOG 0x800000 /* Watchdog Timer */
  1386. #define DMA1_ERR 0x1000000 /* DMA Controller 1 Error */
  1387. #define SPORT2_ERR 0x2000000 /* SPORT2 Error */
  1388. #define SPORT3_ERR 0x4000000 /* SPORT3 Error */
  1389. #define MXVR_SD 0x8000000 /* MXVR Synchronous Data */
  1390. #define SPI1_ERR 0x10000000 /* SPI1 Error */
  1391. #define SPI2_ERR 0x20000000 /* SPI2 Error */
  1392. #define UART1_ERR 0x40000000 /* UART1 Error */
  1393. #define UART2_ERR 0x80000000 /* UART2 Error */
  1394. /* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */
  1395. #define CAN0_ERR 0x1 /* CAN0 Error */
  1396. #define DMA18 0x2 /* DMA Channel 18 */
  1397. #define DMA19 0x4 /* DMA Channel 19 */
  1398. #define DMA20 0x8 /* DMA Channel 20 */
  1399. #define DMA21 0x10 /* DMA Channel 21 */
  1400. #define DMA13 0x20 /* DMA Channel 13 */
  1401. #define DMA14 0x40 /* DMA Channel 14 */
  1402. #define DMA5 0x80 /* DMA Channel 5 */
  1403. #define DMA23 0x100 /* DMA Channel 23 */
  1404. #define DMA8 0x200 /* DMA Channel 8 */
  1405. #define DMA9 0x400 /* DMA Channel 9 */
  1406. #define DMA10 0x800 /* DMA Channel 10 */
  1407. #define DMA11 0x1000 /* DMA Channel 11 */
  1408. #define TWI0 0x2000 /* TWI0 */
  1409. #define TWI1 0x4000 /* TWI1 */
  1410. #define CAN0_RX 0x8000 /* CAN0 Receive */
  1411. #define CAN0_TX 0x10000 /* CAN0 Transmit */
  1412. #define MDMA2 0x20000 /* Memory DMA Stream 0 */
  1413. #define MDMA3 0x40000 /* Memory DMA Stream 1 */
  1414. #define MXVR_STAT 0x80000 /* MXVR Status */
  1415. #define MXVR_CM 0x100000 /* MXVR Control Message */
  1416. #define MXVR_AP 0x200000 /* MXVR Asynchronous Packet */
  1417. #define EPPI1_ERR 0x400000 /* EPPI1 Error */
  1418. #define EPPI2_ERR 0x800000 /* EPPI2 Error */
  1419. #define UART3_ERR 0x1000000 /* UART3 Error */
  1420. #define HOST_ERR 0x2000000 /* Host DMA Port Error */
  1421. #define USB_ERR 0x4000000 /* USB Error */
  1422. #define PIXC_ERR 0x8000000 /* Pixel Compositor Error */
  1423. #define NFC_ERR 0x10000000 /* Nand Flash Controller Error */
  1424. #define ATAPI_ERR 0x20000000 /* ATAPI Error */
  1425. #define CAN1_ERR 0x40000000 /* CAN1 Error */
  1426. #define DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */
  1427. #define DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */
  1428. #define DMAR0 0x80000000 /* DMAR0 Block */
  1429. #define DMAR1 0x80000000 /* DMAR1 Block */
  1430. /* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */
  1431. #define DMA15 0x1 /* DMA Channel 15 */
  1432. #define DMA16 0x2 /* DMA Channel 16 */
  1433. #define DMA17 0x4 /* DMA Channel 17 */
  1434. #define DMA22 0x8 /* DMA Channel 22 */
  1435. #define CNT 0x10 /* Counter */
  1436. #define KEY 0x20 /* Keypad */
  1437. #define CAN1_RX 0x40 /* CAN1 Receive */
  1438. #define CAN1_TX 0x80 /* CAN1 Transmit */
  1439. #define SDH_INT_MASK0 0x100 /* SDH Mask 0 */
  1440. #define SDH_INT_MASK1 0x200 /* SDH Mask 1 */
  1441. #define USB_EINT 0x400 /* USB Exception */
  1442. #define USB_INT0 0x800 /* USB Interrupt 0 */
  1443. #define USB_INT1 0x1000 /* USB Interrupt 1 */
  1444. #define USB_INT2 0x2000 /* USB Interrupt 2 */
  1445. #define USB_DMAINT 0x4000 /* USB DMA */
  1446. #define OTPSEC 0x8000 /* OTP Access Complete */
  1447. #define TIMER0 0x400000 /* Timer 0 */
  1448. #define TIMER1 0x800000 /* Timer 1 */
  1449. #define TIMER2 0x1000000 /* Timer 2 */
  1450. #define TIMER3 0x2000000 /* Timer 3 */
  1451. #define TIMER4 0x4000000 /* Timer 4 */
  1452. #define TIMER5 0x8000000 /* Timer 5 */
  1453. #define TIMER6 0x10000000 /* Timer 6 */
  1454. #define TIMER7 0x20000000 /* Timer 7 */
  1455. #define PINT2 0x40000000 /* Pin Interrupt 2 */
  1456. #define PINT3 0x80000000 /* Pin Interrupt 3 */
  1457. /* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */
  1458. #define DMAEN 0x1 /* DMA Channel Enable */
  1459. #define WNR 0x2 /* DMA Direction */
  1460. #define WDSIZE_8 0x0 /* Transfer Word Size = 8 */
  1461. #define WDSIZE_16 0x4 /* Transfer Word Size = 16 */
  1462. #define WDSIZE_32 0x8 /* Transfer Word Size = 32 */
  1463. #define DMA2D 0x10 /* DMA Mode */
  1464. #define RESTART 0x20 /* Work Unit Transitions */
  1465. #define DI_SEL 0x40 /* Data Interrupt Timing Select */
  1466. #define DI_EN 0x80 /* Data Interrupt Enable */
  1467. #define NDSIZE 0xf00 /* Flex Descriptor Size */
  1468. #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
  1469. #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
  1470. #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
  1471. #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
  1472. #define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
  1473. #define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
  1474. #define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
  1475. #define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
  1476. #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
  1477. #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
  1478. #define DMAFLOW 0xf000 /* Next Operation */
  1479. #define DMAFLOW_STOP 0x0000 /* Stop Mode */
  1480. #define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
  1481. #define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
  1482. #define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
  1483. #define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
  1484. /* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
  1485. #define DMA_DONE 0x1 /* DMA Completion Interrupt Status */
  1486. #define DMA_ERR 0x2 /* DMA Error Interrupt Status */
  1487. #define DFETCH 0x4 /* DMA Descriptor Fetch */
  1488. #define DMA_RUN 0x8 /* DMA Channel Running */
  1489. /* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
  1490. #define CTYPE 0x40 /* DMA Channel Type */
  1491. #define PMAP 0xf000 /* Peripheral Mapped To This Channel */
  1492. /* Bit masks for DMACx_TCPER */
  1493. #define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */
  1494. #define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */
  1495. #define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */
  1496. #define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */
  1497. /* Bit masks for DMACx_TCCNT */
  1498. #define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */
  1499. #define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */
  1500. #define DAB_TRAFFIC_COUNT 0x700 /* DAB Traffic Control Count */
  1501. #define MDMA_ROUND_ROBIN_COUNT 0xf800 /* MDMA Round Robin Count */
  1502. /* Bit masks for DMAC1_PERIMUX */
  1503. #define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */
  1504. /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
  1505. /* EBIU_AMGCTL Masks */
  1506. #define AMCKEN 0x0001 /* Enable CLKOUT */
  1507. #define AMBEN_NONE 0x0000 /* All Banks Disabled */
  1508. #define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
  1509. #define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
  1510. #define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
  1511. #define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
  1512. /* Bit masks for EBIU_AMBCTL0 */
  1513. #define B0RDYEN 0x1 /* Bank 0 ARDY Enable */
  1514. #define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */
  1515. #define B0TT 0xc /* Bank 0 transition time */
  1516. #define B0ST 0x30 /* Bank 0 Setup time */
  1517. #define B0HT 0xc0 /* Bank 0 Hold time */
  1518. #define B0RAT 0xf00 /* Bank 0 Read access time */
  1519. #define B0WAT 0xf000 /* Bank 0 write access time */
  1520. #define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */
  1521. #define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */
  1522. #define B1TT 0xc0000 /* Bank 1 transition time */
  1523. #define B1ST 0x300000 /* Bank 1 Setup time */
  1524. #define B1HT 0xc00000 /* Bank 1 Hold time */
  1525. #define B1RAT 0xf000000 /* Bank 1 Read access time */
  1526. #define B1WAT 0xf0000000 /* Bank 1 write access time */
  1527. /* Bit masks for EBIU_AMBCTL1 */
  1528. #define B2RDYEN 0x1 /* Bank 2 ARDY Enable */
  1529. #define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */
  1530. #define B2TT 0xc /* Bank 2 transition time */
  1531. #define B2ST 0x30 /* Bank 2 Setup time */
  1532. #define B2HT 0xc0 /* Bank 2 Hold time */
  1533. #define B2RAT 0xf00 /* Bank 2 Read access time */
  1534. #define B2WAT 0xf000 /* Bank 2 write access time */
  1535. #define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */
  1536. #define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */
  1537. #define B3TT 0xc0000 /* Bank 3 transition time */
  1538. #define B3ST 0x300000 /* Bank 3 Setup time */
  1539. #define B3HT 0xc00000 /* Bank 3 Hold time */
  1540. #define B3RAT 0xf000000 /* Bank 3 Read access time */
  1541. #define B3WAT 0xf0000000 /* Bank 3 write access time */
  1542. /* Bit masks for EBIU_MBSCTL */
  1543. #define AMSB0CTL 0x3 /* Async Memory Bank 0 select */
  1544. #define AMSB1CTL 0xc /* Async Memory Bank 1 select */
  1545. #define AMSB2CTL 0x30 /* Async Memory Bank 2 select */
  1546. #define AMSB3CTL 0xc0 /* Async Memory Bank 3 select */
  1547. /* Bit masks for EBIU_MODE */
  1548. #define B0MODE 0x3 /* Async Memory Bank 0 Access Mode */
  1549. #define B1MODE 0xc /* Async Memory Bank 1 Access Mode */
  1550. #define B2MODE 0x30 /* Async Memory Bank 2 Access Mode */
  1551. #define B3MODE 0xc0 /* Async Memory Bank 3 Access Mode */
  1552. /* Bit masks for EBIU_FCTL */
  1553. #define TESTSETLOCK 0x1 /* Test set lock */
  1554. #define BCLK 0x6 /* Burst clock frequency */
  1555. #define PGWS 0x38 /* Page wait states */
  1556. #define PGSZ 0x40 /* Page size */
  1557. #define RDDL 0x380 /* Read data delay */
  1558. /* Bit masks for EBIU_ARBSTAT */
  1559. #define ARBSTAT 0x1 /* Arbitration status */
  1560. #define BGSTAT 0x2 /* Bus grant status */
  1561. /* Bit masks for EBIU_DDRCTL0 */
  1562. #define TREFI 0x3fff /* Refresh Interval */
  1563. #define TRFC 0x3c000 /* Auto-refresh command period */
  1564. #define TRP 0x3c0000 /* Pre charge-to-active command period */
  1565. #define TRAS 0x3c00000 /* Min Active-to-pre charge time */
  1566. #define TRC 0x3c000000 /* Active-to-active time */
  1567. /* Bit masks for EBIU_DDRCTL1 */
  1568. #define TRCD 0xf /* Active-to-Read/write delay */
  1569. #define MRD 0xf0 /* Mode register set to active */
  1570. #define TWR 0x300 /* Write Recovery time */
  1571. #define DDRDATWIDTH 0x3000 /* DDR data width */
  1572. #define EXTBANKS 0xc000 /* External banks */
  1573. #define DDRDEVWIDTH 0x30000 /* DDR device width */
  1574. #define DDRDEVSIZE 0xc0000 /* DDR device size */
  1575. #define TWWTR 0xf0000000 /* Write-to-read delay */
  1576. /* Bit masks for EBIU_DDRCTL2 */
  1577. #define BURSTLENGTH 0x7 /* Burst length */
  1578. #define CASLATENCY 0x70 /* CAS latency */
  1579. #define DLLRESET 0x100 /* DLL Reset */
  1580. #define REGE 0x1000 /* Register mode enable */
  1581. /* Bit masks for EBIU_DDRCTL3 */
  1582. #define PASR 0x7 /* Partial array self-refresh */
  1583. /* Bit masks for EBIU_DDRQUE */
  1584. #define DEB1_PFLEN 0x3 /* Pre fetch length for DEB1 accesses */
  1585. #define DEB2_PFLEN 0xc /* Pre fetch length for DEB2 accesses */
  1586. #define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */
  1587. #define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */
  1588. #define DEB1_URGENT 0x1000 /* DEB1 Urgent */
  1589. #define DEB2_URGENT 0x2000 /* DEB2 Urgent */
  1590. #define DEB3_URGENT 0x4000 /* DEB3 Urgent */
  1591. /* Bit masks for EBIU_ERRMST */
  1592. #define DEB1_ERROR 0x1 /* DEB1 Error */
  1593. #define DEB2_ERROR 0x2 /* DEB2 Error */
  1594. #define DEB3_ERROR 0x4 /* DEB3 Error */
  1595. #define CORE_ERROR 0x8 /* Core error */
  1596. #define DEB_MERROR 0x10 /* DEB1 Error (2nd) */
  1597. #define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */
  1598. #define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */
  1599. #define CORE_MERROR 0x80 /* Core Error (2nd) */
  1600. /* Bit masks for EBIU_ERRADD */
  1601. #define ERROR_ADDRESS 0xffffffff /* Error Address */
  1602. /* Bit masks for EBIU_RSTCTL */
  1603. #define DDRSRESET 0x1 /* DDR soft reset */
  1604. #define PFTCHSRESET 0x4 /* DDR prefetch reset */
  1605. #define SRREQ 0x8 /* Self-refresh request */
  1606. #define SRACK 0x10 /* Self-refresh acknowledge */
  1607. #define MDDRENABLE 0x20 /* Mobile DDR enable */
  1608. /* Bit masks for EBIU_DDRBRC0 */
  1609. #define BRC0 0xffffffff /* Count */
  1610. /* Bit masks for EBIU_DDRBRC1 */
  1611. #define BRC1 0xffffffff /* Count */
  1612. /* Bit masks for EBIU_DDRBRC2 */
  1613. #define BRC2 0xffffffff /* Count */
  1614. /* Bit masks for EBIU_DDRBRC3 */
  1615. #define BRC3 0xffffffff /* Count */
  1616. /* Bit masks for EBIU_DDRBRC4 */
  1617. #define BRC4 0xffffffff /* Count */
  1618. /* Bit masks for EBIU_DDRBRC5 */
  1619. #define BRC5 0xffffffff /* Count */
  1620. /* Bit masks for EBIU_DDRBRC6 */
  1621. #define BRC6 0xffffffff /* Count */
  1622. /* Bit masks for EBIU_DDRBRC7 */
  1623. #define BRC7 0xffffffff /* Count */
  1624. /* Bit masks for EBIU_DDRBWC0 */
  1625. #define BWC0 0xffffffff /* Count */
  1626. /* Bit masks for EBIU_DDRBWC1 */
  1627. #define BWC1 0xffffffff /* Count */
  1628. /* Bit masks for EBIU_DDRBWC2 */
  1629. #define BWC2 0xffffffff /* Count */
  1630. /* Bit masks for EBIU_DDRBWC3 */
  1631. #define BWC3 0xffffffff /* Count */
  1632. /* Bit masks for EBIU_DDRBWC4 */
  1633. #define BWC4 0xffffffff /* Count */
  1634. /* Bit masks for EBIU_DDRBWC5 */
  1635. #define BWC5 0xffffffff /* Count */
  1636. /* Bit masks for EBIU_DDRBWC6 */
  1637. #define BWC6 0xffffffff /* Count */
  1638. /* Bit masks for EBIU_DDRBWC7 */
  1639. #define BWC7 0xffffffff /* Count */
  1640. /* Bit masks for EBIU_DDRACCT */
  1641. #define ACCT 0xffffffff /* Count */
  1642. /* Bit masks for EBIU_DDRTACT */
  1643. #define TECT 0xffffffff /* Count */
  1644. /* Bit masks for EBIU_DDRARCT */
  1645. #define ARCT 0xffffffff /* Count */
  1646. /* Bit masks for EBIU_DDRGC0 */
  1647. #define GC0 0xffffffff /* Count */
  1648. /* Bit masks for EBIU_DDRGC1 */
  1649. #define GC1 0xffffffff /* Count */
  1650. /* Bit masks for EBIU_DDRGC2 */
  1651. #define GC2 0xffffffff /* Count */
  1652. /* Bit masks for EBIU_DDRGC3 */
  1653. #define GC3 0xffffffff /* Count */
  1654. /* Bit masks for EBIU_DDRMCEN */
  1655. #define B0WCENABLE 0x1 /* Bank 0 write count enable */
  1656. #define B1WCENABLE 0x2 /* Bank 1 write count enable */
  1657. #define B2WCENABLE 0x4 /* Bank 2 write count enable */
  1658. #define B3WCENABLE 0x8 /* Bank 3 write count enable */
  1659. #define B4WCENABLE 0x10 /* Bank 4 write count enable */
  1660. #define B5WCENABLE 0x20 /* Bank 5 write count enable */
  1661. #define B6WCENABLE 0x40 /* Bank 6 write count enable */
  1662. #define B7WCENABLE 0x80 /* Bank 7 write count enable */
  1663. #define B0RCENABLE 0x100 /* Bank 0 read count enable */
  1664. #define B1RCENABLE 0x200 /* Bank 1 read count enable */
  1665. #define B2RCENABLE 0x400 /* Bank 2 read count enable */
  1666. #define B3RCENABLE 0x800 /* Bank 3 read count enable */
  1667. #define B4RCENABLE 0x1000 /* Bank 4 read count enable */
  1668. #define B5RCENABLE 0x2000 /* Bank 5 read count enable */
  1669. #define B6RCENABLE 0x4000 /* Bank 6 read count enable */
  1670. #define B7RCENABLE 0x8000 /* Bank 7 read count enable */
  1671. #define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */
  1672. #define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */
  1673. #define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */
  1674. #define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */
  1675. #define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */
  1676. #define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */
  1677. #define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */
  1678. #define GCCONTROL 0x3000000 /* DDR Grant Count Control */
  1679. /* Bit masks for EBIU_DDRMCCL */
  1680. #define CB0WCOUNT 0x1 /* Clear write count 0 */
  1681. #define CB1WCOUNT 0x2 /* Clear write count 1 */
  1682. #define CB2WCOUNT 0x4 /* Clear write count 2 */
  1683. #define CB3WCOUNT 0x8 /* Clear write count 3 */
  1684. #define CB4WCOUNT 0x10 /* Clear write count 4 */
  1685. #define CB5WCOUNT 0x20 /* Clear write count 5 */
  1686. #define CB6WCOUNT 0x40 /* Clear write count 6 */
  1687. #define CB7WCOUNT 0x80 /* Clear write count 7 */
  1688. #define CBRCOUNT 0x100 /* Clear read count 0 */
  1689. #define CB1RCOUNT 0x200 /* Clear read count 1 */
  1690. #define CB2RCOUNT 0x400 /* Clear read count 2 */
  1691. #define CB3RCOUNT 0x800 /* Clear read count 3 */
  1692. #define CB4RCOUNT 0x1000 /* Clear read count 4 */
  1693. #define CB5RCOUNT 0x2000 /* Clear read count 5 */
  1694. #define CB6RCOUNT 0x4000 /* Clear read count 6 */
  1695. #define CB7RCOUNT 0x8000 /* Clear read count 7 */
  1696. #define CRACOUNT 0x10000 /* Clear row activation count */
  1697. #define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */
  1698. #define CARCOUNT 0x40000 /* Clear auto-refresh count */
  1699. #define CG0COUNT 0x100000 /* Clear grant count 0 */
  1700. #define CG1COUNT 0x200000 /* Clear grant count 1 */
  1701. #define CG2COUNT 0x400000 /* Clear grant count 2 */
  1702. #define CG3COUNT 0x800000 /* Clear grant count 3 */
  1703. /* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */
  1704. #define Px0 0x1 /* GPIO 0 */
  1705. #define Px1 0x2 /* GPIO 1 */
  1706. #define Px2 0x4 /* GPIO 2 */
  1707. #define Px3 0x8 /* GPIO 3 */
  1708. #define Px4 0x10 /* GPIO 4 */
  1709. #define Px5 0x20 /* GPIO 5 */
  1710. #define Px6 0x40 /* GPIO 6 */
  1711. #define Px7 0x80 /* GPIO 7 */
  1712. #define Px8 0x100 /* GPIO 8 */
  1713. #define Px9 0x200 /* GPIO 9 */
  1714. #define Px10 0x400 /* GPIO 10 */
  1715. #define Px11 0x800 /* GPIO 11 */
  1716. #define Px12 0x1000 /* GPIO 12 */
  1717. #define Px13 0x2000 /* GPIO 13 */
  1718. #define Px14 0x4000 /* GPIO 14 */
  1719. #define Px15 0x8000 /* GPIO 15 */
  1720. /* Bit masks for PORTA_MUX - PORTJ_MUX */
  1721. #define PxM0 0x3 /* GPIO Mux 0 */
  1722. #define PxM1 0xc /* GPIO Mux 1 */
  1723. #define PxM2 0x30 /* GPIO Mux 2 */
  1724. #define PxM3 0xc0 /* GPIO Mux 3 */
  1725. #define PxM4 0x300 /* GPIO Mux 4 */
  1726. #define PxM5 0xc00 /* GPIO Mux 5 */
  1727. #define PxM6 0x3000 /* GPIO Mux 6 */
  1728. #define PxM7 0xc000 /* GPIO Mux 7 */
  1729. #define PxM8 0x30000 /* GPIO Mux 8 */
  1730. #define PxM9 0xc0000 /* GPIO Mux 9 */
  1731. #define PxM10 0x300000 /* GPIO Mux 10 */
  1732. #define PxM11 0xc00000 /* GPIO Mux 11 */
  1733. #define PxM12 0x3000000 /* GPIO Mux 12 */
  1734. #define PxM13 0xc000000 /* GPIO Mux 13 */
  1735. #define PxM14 0x30000000 /* GPIO Mux 14 */
  1736. #define PxM15 0xc0000000 /* GPIO Mux 15 */
  1737. /* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */
  1738. #define IB0 0x1 /* Interrupt Bit 0 */
  1739. #define IB1 0x2 /* Interrupt Bit 1 */
  1740. #define IB2 0x4 /* Interrupt Bit 2 */
  1741. #define IB3 0x8 /* Interrupt Bit 3 */
  1742. #define IB4 0x10 /* Interrupt Bit 4 */
  1743. #define IB5 0x20 /* Interrupt Bit 5 */
  1744. #define IB6 0x40 /* Interrupt Bit 6 */
  1745. #define IB7 0x80 /* Interrupt Bit 7 */
  1746. #define IB8 0x100 /* Interrupt Bit 8 */
  1747. #define IB9 0x200 /* Interrupt Bit 9 */
  1748. #define IB10 0x400 /* Interrupt Bit 10 */
  1749. #define IB11 0x800 /* Interrupt Bit 11 */
  1750. #define IB12 0x1000 /* Interrupt Bit 12 */
  1751. #define IB13 0x2000 /* Interrupt Bit 13 */
  1752. #define IB14 0x4000 /* Interrupt Bit 14 */
  1753. #define IB15 0x8000 /* Interrupt Bit 15 */
  1754. /* Bit masks for TIMERx_CONFIG */
  1755. #define TMODE 0x3 /* Timer Mode */
  1756. #define PULSE_HI 0x4 /* Pulse Polarity */
  1757. #define PERIOD_CNT 0x8 /* Period Count */
  1758. #define IRQ_ENA 0x10 /* Interrupt Request Enable */
  1759. #define TIN_SEL 0x20 /* Timer Input Select */
  1760. #define OUT_DIS 0x40 /* Output Pad Disable */
  1761. #define CLK_SEL 0x80 /* Timer Clock Select */
  1762. #define TOGGLE_HI 0x100 /* Toggle Mode */
  1763. #define EMU_RUN 0x200 /* Emulation Behavior Select */
  1764. #define ERR_TYP 0xc000 /* Error Type */
  1765. /* Bit masks for TIMER_ENABLE0 */
  1766. #define TIMEN0 0x1 /* Timer 0 Enable */
  1767. #define TIMEN1 0x2 /* Timer 1 Enable */
  1768. #define TIMEN2 0x4 /* Timer 2 Enable */
  1769. #define TIMEN3 0x8 /* Timer 3 Enable */
  1770. #define TIMEN4 0x10 /* Timer 4 Enable */
  1771. #define TIMEN5 0x20 /* Timer 5 Enable */
  1772. #define TIMEN6 0x40 /* Timer 6 Enable */
  1773. #define TIMEN7 0x80 /* Timer 7 Enable */
  1774. /* Bit masks for TIMER_DISABLE0 */
  1775. #define TIMDIS0 0x1 /* Timer 0 Disable */
  1776. #define TIMDIS1 0x2 /* Timer 1 Disable */
  1777. #define TIMDIS2 0x4 /* Timer 2 Disable */
  1778. #define TIMDIS3 0x8 /* Timer 3 Disable */
  1779. #define TIMDIS4 0x10 /* Timer 4 Disable */
  1780. #define TIMDIS5 0x20 /* Timer 5 Disable */
  1781. #define TIMDIS6 0x40 /* Timer 6 Disable */
  1782. #define TIMDIS7 0x80 /* Timer 7 Disable */
  1783. /* Bit masks for TIMER_STATUS0 */
  1784. #define TIMIL0 0x1 /* Timer 0 Interrupt */
  1785. #define TIMIL1 0x2 /* Timer 1 Interrupt */
  1786. #define TIMIL2 0x4 /* Timer 2 Interrupt */
  1787. #define TIMIL3 0x8 /* Timer 3 Interrupt */
  1788. #define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */
  1789. #define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */
  1790. #define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */
  1791. #define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */
  1792. #define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
  1793. #define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
  1794. #define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
  1795. #define TRUN3 0x8000 /* Timer 3 Slave Enable Status */
  1796. #define TIMIL4 0x10000 /* Timer 4 Interrupt */
  1797. #define TIMIL5 0x20000 /* Timer 5 Interrupt */
  1798. #define TIMIL6 0x40000 /* Timer 6 Interrupt */
  1799. #define TIMIL7 0x80000 /* Timer 7 Interrupt */
  1800. #define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */
  1801. #define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */
  1802. #define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */
  1803. #define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */
  1804. #define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
  1805. #define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
  1806. #define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
  1807. #define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
  1808. /* Bit masks for WDOG_CTL */
  1809. #define WDEV 0x6 /* Watchdog Event */
  1810. #define WDEN 0xff0 /* Watchdog Enable */
  1811. #define WDRO 0x8000 /* Watchdog Rolled Over */
  1812. /* Bit masks for CNT_CONFIG */
  1813. #define CNTE 0x1 /* Counter Enable */
  1814. #define DEBE 0x2 /* Debounce Enable */
  1815. #define CDGINV 0x10 /* CDG Pin Polarity Invert */
  1816. #define CUDINV 0x20 /* CUD Pin Polarity Invert */
  1817. #define CZMINV 0x40 /* CZM Pin Polarity Invert */
  1818. #define CNTMODE 0x700 /* Counter Operating Mode */
  1819. #define ZMZC 0x800 /* CZM Zeroes Counter Enable */
  1820. #define BNDMODE 0x3000 /* Boundary register Mode */
  1821. #define INPDIS 0x8000 /* CUG and CDG Input Disable */
  1822. /* Bit masks for CNT_IMASK */
  1823. #define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
  1824. #define UCIE 0x2 /* Up count Interrupt Enable */
  1825. #define DCIE 0x4 /* Down count Interrupt Enable */
  1826. #define MINCIE 0x8 /* Min Count Interrupt Enable */
  1827. #define MAXCIE 0x10 /* Max Count Interrupt Enable */
  1828. #define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
  1829. #define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
  1830. #define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
  1831. #define CZMIE 0x100 /* CZM Pin Interrupt Enable */
  1832. #define CZMEIE 0x200 /* CZM Error Interrupt Enable */
  1833. #define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
  1834. /* Bit masks for CNT_STATUS */
  1835. #define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
  1836. #define UCII 0x2 /* Up count Interrupt Identifier */
  1837. #define DCII 0x4 /* Down count Interrupt Identifier */
  1838. #define MINCII 0x8 /* Min Count Interrupt Identifier */
  1839. #define MAXCII 0x10 /* Max Count Interrupt Identifier */
  1840. #define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
  1841. #define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
  1842. #define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
  1843. #define CZMII 0x100 /* CZM Pin Interrupt Identifier */
  1844. #define CZMEII 0x200 /* CZM Error Interrupt Identifier */
  1845. #define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
  1846. /* Bit masks for CNT_COMMAND */
  1847. #define W1LCNT 0xf /* Load Counter Register */
  1848. #define W1LMIN 0xf0 /* Load Min Register */
  1849. #define W1LMAX 0xf00 /* Load Max Register */
  1850. #define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
  1851. /* Bit masks for CNT_DEBOUNCE */
  1852. #define DPRESCALE 0xf /* Load Counter Register */
  1853. /* Bit masks for RTC_STAT */
  1854. #define SECONDS 0x3f /* Seconds */
  1855. #define MINUTES 0xfc0 /* Minutes */
  1856. #define HOURS 0x1f000 /* Hours */
  1857. #define DAY_COUNTER 0xfffe0000 /* Day Counter */
  1858. /* Bit masks for RTC_ICTL */
  1859. #define STOPWATCH_INTERRUPT_ENABLE 0x1 /* Stopwatch Interrupt Enable */
  1860. #define ALARM_INTERRUPT_ENABLE 0x2 /* Alarm Interrupt Enable */
  1861. #define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */
  1862. #define MINUTES_INTERRUPT_ENABLE 0x8 /* Minutes Interrupt Enable */
  1863. #define HOURS_INTERRUPT_ENABLE 0x10 /* Hours Interrupt Enable */
  1864. #define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x20 /* 24 Hours Interrupt Enable */
  1865. #define DAY_ALARM_INTERRUPT_ENABLE 0x40 /* Day Alarm Interrupt Enable */
  1866. #define WRITE_COMPLETE_INTERRUPT_ENABLE 0x8000 /* Write Complete Interrupt Enable */
  1867. /* Bit masks for RTC_ISTAT */
  1868. #define STOPWATCH_EVENT_FLAG 0x1 /* Stopwatch Event Flag */
  1869. #define ALARM_EVENT_FLAG 0x2 /* Alarm Event Flag */
  1870. #define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */
  1871. #define MINUTES_EVENT_FLAG 0x8 /* Minutes Event Flag */
  1872. #define HOURS_EVENT_FLAG 0x10 /* Hours Event Flag */
  1873. #define TWENTY_FOUR_HOURS_EVENT_FLAG 0x20 /* 24 Hours Event Flag */
  1874. #define DAY_ALARM_EVENT_FLAG 0x40 /* Day Alarm Event Flag */
  1875. #define WRITE_PENDING__STATUS 0x4000 /* Write Pending Status */
  1876. #define WRITE_COMPLETE 0x8000 /* Write Complete */
  1877. /* Bit masks for RTC_SWCNT */
  1878. #define STOPWATCH_COUNT 0xffff /* Stopwatch Count */
  1879. /* Bit masks for RTC_ALARM */
  1880. #define SECONDS 0x3f /* Seconds */
  1881. #define MINUTES 0xfc0 /* Minutes */
  1882. #define HOURS 0x1f000 /* Hours */
  1883. #define DAY 0xfffe0000 /* Day */
  1884. /* Bit masks for RTC_PREN */
  1885. #define PREN 0x1 /* Prescaler Enable */
  1886. /* Bit masks for OTP_CONTROL */
  1887. #define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
  1888. #define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
  1889. #define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
  1890. #define FWRTEST 0x2000 /* OTP/Fuse Write Test */
  1891. #define FRDEN 0x4000 /* OTP/Fuse Read Enable */
  1892. #define FWREN 0x8000 /* OTP/Fuse Write Enable */
  1893. /* Bit masks for OTP_BEN */
  1894. #define FBEN 0xffff /* OTP/Fuse Byte Enable */
  1895. /* Bit masks for OTP_STATUS */
  1896. #define FCOMP 0x1 /* OTP/Fuse Access Complete */
  1897. #define FERROR 0x2 /* OTP/Fuse Access Error */
  1898. #define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
  1899. #define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
  1900. #define FPGMEN 0x40 /* OTP/Fuse Program Enable */
  1901. /* Bit masks for OTP_TIMING */
  1902. #define USECDIV 0xff /* Micro Second Divider */
  1903. #define READACC 0x7f00 /* Read Access Time */
  1904. #define CPUMPRL 0x38000 /* Charge Pump Release Time */
  1905. #define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
  1906. #define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
  1907. #define PGMTIME 0xff000000 /* Program Time */
  1908. /* Bit masks for SECURE_SYSSWT */
  1909. #define EMUDABL 0x1 /* Emulation Disable. */
  1910. #define RSTDABL 0x2 /* Reset Disable */
  1911. #define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
  1912. #define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
  1913. #define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
  1914. #define DMA0OVR 0x800 /* DMA0 Memory Access Override */
  1915. #define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
  1916. #define EMUOVR 0x4000 /* Emulation Override */
  1917. #define OTPSEN 0x8000 /* OTP Secrets Enable. */
  1918. #define L2DABL 0x70000 /* L2 Memory Disable. */
  1919. /* Bit masks for SECURE_CONTROL */
  1920. #define SECURE0 0x1 /* SECURE 0 */
  1921. #define SECURE1 0x2 /* SECURE 1 */
  1922. #define SECURE2 0x4 /* SECURE 2 */
  1923. #define SECURE3 0x8 /* SECURE 3 */
  1924. /* Bit masks for SECURE_STATUS */
  1925. #define SECMODE 0x3 /* Secured Mode Control State */
  1926. #define NMI 0x4 /* Non Maskable Interrupt */
  1927. #define AFVALID 0x8 /* Authentication Firmware Valid */
  1928. #define AFEXIT 0x10 /* Authentication Firmware Exit */
  1929. #define SECSTAT 0xe0 /* Secure Status */
  1930. /* Bit masks for PLL_DIV */
  1931. #define CSEL 0x30 /* Core Select */
  1932. #define SSEL 0xf /* System Select */
  1933. /* Bit masks for PLL_CTL */
  1934. #define MSEL 0x7e00 /* Multiplier Select */
  1935. #define BYPASS 0x100 /* PLL Bypass Enable */
  1936. #define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */
  1937. #define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */
  1938. #define PDWN 0x20 /* Power Down */
  1939. #define STOPCK 0x8 /* Stop Clock */
  1940. #define PLL_OFF 0x2 /* Disable PLL */
  1941. #define DF 0x1 /* Divide Frequency */
  1942. /* SWRST Masks */
  1943. #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
  1944. #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
  1945. #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
  1946. #define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
  1947. #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
  1948. /* Bit masks for PLL_STAT */
  1949. #define PLL_LOCKED 0x20 /* PLL Locked Status */
  1950. #define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */
  1951. #define FULL_ON 0x2 /* Full-On Mode */
  1952. #define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */
  1953. #define RTCWS 0x400 /* RTC/Reset Wake-Up Status */
  1954. #define CANWS 0x800 /* CAN Wake-Up Status */
  1955. #define USBWS 0x2000 /* USB Wake-Up Status */
  1956. #define KPADWS 0x4000 /* Keypad Wake-Up Status */
  1957. #define ROTWS 0x8000 /* Rotary Wake-Up Status */
  1958. #define GPWS 0x1000 /* General-Purpose Wake-Up Status */
  1959. /* Bit masks for VR_CTL */
  1960. #define FREQ 0x3 /* Regulator Switching Frequency */
  1961. #define GAIN 0xc /* Voltage Output Level Gain */
  1962. #define VLEV 0xf0 /* Internal Voltage Level */
  1963. #define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */
  1964. #define WAKE 0x100 /* RTC/Reset Wake-Up Enable */
  1965. #define CANWE 0x200 /* CAN0/1 Wake-Up Enable */
  1966. #define GPWE 0x400 /* General-Purpose Wake-Up Enable */
  1967. #define USBWE 0x800 /* USB Wake-Up Enable */
  1968. #define KPADWE 0x1000 /* Keypad Wake-Up Enable */
  1969. #define ROTWE 0x2000 /* Rotary Wake-Up Enable */
  1970. /* Bit masks for NFC_CTL */
  1971. #define WR_DLY 0xf /* Write Strobe Delay */
  1972. #define RD_DLY 0xf0 /* Read Strobe Delay */
  1973. #define NWIDTH 0x100 /* NAND Data Width */
  1974. #define PG_SIZE 0x200 /* Page Size */
  1975. /* Bit masks for NFC_STAT */
  1976. #define NBUSY 0x1 /* Not Busy */
  1977. #define WB_FULL 0x2 /* Write Buffer Full */
  1978. #define PG_WR_STAT 0x4 /* Page Write Pending */
  1979. #define PG_RD_STAT 0x8 /* Page Read Pending */
  1980. #define WB_EMPTY 0x10 /* Write Buffer Empty */
  1981. /* Bit masks for NFC_IRQSTAT */
  1982. #define NBUSYIRQ 0x1 /* Not Busy IRQ */
  1983. #define WB_OVF 0x2 /* Write Buffer Overflow */
  1984. #define WB_EDGE 0x4 /* Write Buffer Edge Detect */
  1985. #define RD_RDY 0x8 /* Read Data Ready */
  1986. #define WR_DONE 0x10 /* Page Write Done */
  1987. /* Bit masks for NFC_IRQMASK */
  1988. #define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
  1989. #define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
  1990. #define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */
  1991. #define MASK_RDRDY 0x8 /* Mask Read Data Ready */
  1992. #define MASK_WRDONE 0x10 /* Mask Write Done */
  1993. /* Bit masks for NFC_RST */
  1994. #define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
  1995. /* Bit masks for NFC_PGCTL */
  1996. #define PG_RD_START 0x1 /* Page Read Start */
  1997. #define PG_WR_START 0x2 /* Page Write Start */
  1998. /* Bit masks for NFC_ECC0 */
  1999. #define ECC0 0x7ff /* Parity Calculation Result0 */
  2000. /* Bit masks for NFC_ECC1 */
  2001. #define ECC1 0x7ff /* Parity Calculation Result1 */
  2002. /* Bit masks for NFC_ECC2 */
  2003. #define ECC2 0x7ff /* Parity Calculation Result2 */
  2004. /* Bit masks for NFC_ECC3 */
  2005. #define ECC3 0x7ff /* Parity Calculation Result3 */
  2006. /* Bit masks for NFC_COUNT */
  2007. #define ECCCNT 0x3ff /* Transfer Count */
  2008. /* Bit masks for CAN0_CONTROL */
  2009. #define SRS 0x1 /* Software Reset */
  2010. #define DNM 0x2 /* DeviceNet Mode */
  2011. #define ABO 0x4 /* Auto Bus On */
  2012. #define WBA 0x10 /* Wakeup On CAN Bus Activity */
  2013. #define SMR 0x20 /* Sleep Mode Request */
  2014. #define CSR 0x40 /* CAN Suspend Mode Request */
  2015. #define CCR 0x80 /* CAN Configuration Mode Request */
  2016. /* Bit masks for CAN0_STATUS */
  2017. #define WT 0x1 /* CAN Transmit Warning Flag */
  2018. #define WR 0x2 /* CAN Receive Warning Flag */
  2019. #define EP 0x4 /* CAN Error Passive Mode */
  2020. #define EBO 0x8 /* CAN Error Bus Off Mode */
  2021. #define CSA 0x40 /* CAN Suspend Mode Acknowledge */
  2022. #define CCA 0x80 /* CAN Configuration Mode Acknowledge */
  2023. #define MBPTR 0x1f00 /* Mailbox Pointer */
  2024. #define TRM 0x4000 /* Transmit Mode Status */
  2025. #define REC 0x8000 /* Receive Mode Status */
  2026. /* Bit masks for CAN0_DEBUG */
  2027. #define DEC 0x1 /* Disable Transmit/Receive Error Counters */
  2028. #define DRI 0x2 /* Disable CANRX Input Pin */
  2029. #define DTO 0x4 /* Disable CANTX Output Pin */
  2030. #define DIL 0x8 /* Disable Internal Loop */
  2031. #define MAA 0x10 /* Mode Auto-Acknowledge */
  2032. #define MRB 0x20 /* Mode Read Back */
  2033. #define CDE 0x8000 /* CAN Debug Mode Enable */
  2034. /* Bit masks for CAN0_CLOCK */
  2035. #define BRP 0x3ff /* CAN Bit Rate Prescaler */
  2036. /* Bit masks for CAN0_TIMING */
  2037. #define SJW 0x300 /* Synchronization Jump Width */
  2038. #define SAM 0x80 /* Sampling */
  2039. #define TSEG2 0x70 /* Time Segment 2 */
  2040. #define TSEG1 0xf /* Time Segment 1 */
  2041. /* Bit masks for CAN0_INTR */
  2042. #define CANRX 0x80 /* Serial Input From Transceiver */
  2043. #define CANTX 0x40 /* Serial Output To Transceiver */
  2044. #define SMACK 0x8 /* Sleep Mode Acknowledge */
  2045. #define GIRQ 0x4 /* Global Interrupt Request Status */
  2046. #define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */
  2047. #define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */
  2048. /* Bit masks for CAN0_GIM */
  2049. #define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */
  2050. #define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */
  2051. #define EPIM 0x4 /* Error Passive Interrupt Mask */
  2052. #define BOIM 0x8 /* Bus Off Interrupt Mask */
  2053. #define WUIM 0x10 /* Wakeup Interrupt Mask */
  2054. #define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */
  2055. #define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */
  2056. #define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */
  2057. #define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */
  2058. #define ADIM 0x400 /* Access Denied Interrupt Mask */
  2059. /* Bit masks for CAN0_GIS */
  2060. #define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */
  2061. #define EWRIS 0x2 /* Error Warning Receive Interrupt Status */
  2062. #define EPIS 0x4 /* Error Passive Interrupt Status */
  2063. #define BOIS 0x8 /* Bus Off Interrupt Status */
  2064. #define WUIS 0x10 /* Wakeup Interrupt Status */
  2065. #define UIAIS 0x20 /* Unimplemented Address Interrupt Status */
  2066. #define AAIS 0x40 /* Abort Acknowledge Interrupt Status */
  2067. #define RMLIS 0x80 /* Receive Message Lost Interrupt Status */
  2068. #define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */
  2069. #define ADIS 0x400 /* Access Denied Interrupt Status */
  2070. /* Bit masks for CAN0_GIF */
  2071. #define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */
  2072. #define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */
  2073. #define EPIF 0x4 /* Error Passive Interrupt Flag */
  2074. #define BOIF 0x8 /* Bus Off Interrupt Flag */
  2075. #define WUIF 0x10 /* Wakeup Interrupt Flag */
  2076. #define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */
  2077. #define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */
  2078. #define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */
  2079. #define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */
  2080. #define ADIF 0x400 /* Access Denied Interrupt Flag */
  2081. /* Bit masks for CAN0_MBTD */
  2082. #define TDR 0x80 /* Temporary Disable Request */
  2083. #define TDA 0x40 /* Temporary Disable Acknowledge */
  2084. #define TDPTR 0x1f /* Temporary Disable Pointer */
  2085. /* Bit masks for CAN0_UCCNF */
  2086. #define UCCNF 0xf /* Universal Counter Configuration */
  2087. #define UCRC 0x20 /* Universal Counter Reload/Clear */
  2088. #define UCCT 0x40 /* Universal Counter CAN Trigger */
  2089. #define UCE 0x80 /* Universal Counter Enable */
  2090. /* Bit masks for CAN0_UCCNT */
  2091. #define UCCNT 0xffff /* Universal Counter Count Value */
  2092. /* Bit masks for CAN0_UCRC */
  2093. #define UCVAL 0xffff /* Universal Counter Reload/Capture Value */
  2094. /* Bit masks for CAN0_CEC */
  2095. #define RXECNT 0xff /* Receive Error Counter */
  2096. #define TXECNT 0xff00 /* Transmit Error Counter */
  2097. /* Bit masks for CAN0_ESR */
  2098. #define FER 0x80 /* Form Error */
  2099. #define BEF 0x40 /* Bit Error Flag */
  2100. #define SA0 0x20 /* Stuck At Dominant */
  2101. #define CRCE 0x10 /* CRC Error */
  2102. #define SER 0x8 /* Stuff Bit Error */
  2103. #define ACKE 0x4 /* Acknowledge Error */
  2104. /* Bit masks for CAN0_EWR */
  2105. #define EWLTEC 0xff00 /* Transmit Error Warning Limit */
  2106. #define EWLREC 0xff /* Receive Error Warning Limit */
  2107. /* Bit masks for CAN0_AMxx_H */
  2108. #define FDF 0x8000 /* Filter On Data Field */
  2109. #define FMD 0x4000 /* Full Mask Data */
  2110. #define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */
  2111. #define BASEID 0x1ffc /* Base Identifier */
  2112. #define EXTID_HI 0x3 /* Extended Identifier High Bits */
  2113. /* Bit masks for CAN0_AMxx_L */
  2114. #define EXTID_LO 0xffff /* Extended Identifier Low Bits */
  2115. #define DFM 0xffff /* Data Field Mask */
  2116. /* Bit masks for CAN0_MBxx_ID1 */
  2117. #define AME 0x8000 /* Acceptance Mask Enable */
  2118. #define RTR 0x4000 /* Remote Transmission Request */
  2119. #define IDE 0x2000 /* Identifier Extension */
  2120. #define BASEID 0x1ffc /* Base Identifier */
  2121. #define EXTID_HI 0x3 /* Extended Identifier High Bits */
  2122. /* Bit masks for CAN0_MBxx_ID0 */
  2123. #define EXTID_LO 0xffff /* Extended Identifier Low Bits */
  2124. #define DFM 0xffff /* Data Field Mask */
  2125. /* Bit masks for CAN0_MBxx_TIMESTAMP */
  2126. #define TSV 0xffff /* Time Stamp Value */
  2127. /* Bit masks for CAN0_MBxx_LENGTH */
  2128. #define DLC 0xf /* Data Length Code */
  2129. /* Bit masks for CAN0_MBxx_DATA3 */
  2130. #define CAN_BYTE0 0xff00 /* Data Field Byte 0 */
  2131. #define CAN_BYTE1 0xff /* Data Field Byte 1 */
  2132. /* Bit masks for CAN0_MBxx_DATA2 */
  2133. #define CAN_BYTE2 0xff00 /* Data Field Byte 2 */
  2134. #define CAN_BYTE3 0xff /* Data Field Byte 3 */
  2135. /* Bit masks for CAN0_MBxx_DATA1 */
  2136. #define CAN_BYTE4 0xff00 /* Data Field Byte 4 */
  2137. #define CAN_BYTE5 0xff /* Data Field Byte 5 */
  2138. /* Bit masks for CAN0_MBxx_DATA0 */
  2139. #define CAN_BYTE6 0xff00 /* Data Field Byte 6 */
  2140. #define CAN_BYTE7 0xff /* Data Field Byte 7 */
  2141. /* Bit masks for CAN0_MC1 */
  2142. #define MC0 0x1 /* Mailbox 0 Enable */
  2143. #define MC1 0x2 /* Mailbox 1 Enable */
  2144. #define MC2 0x4 /* Mailbox 2 Enable */
  2145. #define MC3 0x8 /* Mailbox 3 Enable */
  2146. #define MC4 0x10 /* Mailbox 4 Enable */
  2147. #define MC5 0x20 /* Mailbox 5 Enable */
  2148. #define MC6 0x40 /* Mailbox 6 Enable */
  2149. #define MC7 0x80 /* Mailbox 7 Enable */
  2150. #define MC8 0x100 /* Mailbox 8 Enable */
  2151. #define MC9 0x200 /* Mailbox 9 Enable */
  2152. #define MC10 0x400 /* Mailbox 10 Enable */
  2153. #define MC11 0x800 /* Mailbox 11 Enable */
  2154. #define MC12 0x1000 /* Mailbox 12 Enable */
  2155. #define MC13 0x2000 /* Mailbox 13 Enable */
  2156. #define MC14 0x4000 /* Mailbox 14 Enable */
  2157. #define MC15 0x8000 /* Mailbox 15 Enable */
  2158. /* Bit masks for CAN0_MC2 */
  2159. #define MC16 0x1 /* Mailbox 16 Enable */
  2160. #define MC17 0x2 /* Mailbox 17 Enable */
  2161. #define MC18 0x4 /* Mailbox 18 Enable */
  2162. #define MC19 0x8 /* Mailbox 19 Enable */
  2163. #define MC20 0x10 /* Mailbox 20 Enable */
  2164. #define MC21 0x20 /* Mailbox 21 Enable */
  2165. #define MC22 0x40 /* Mailbox 22 Enable */
  2166. #define MC23 0x80 /* Mailbox 23 Enable */
  2167. #define MC24 0x100 /* Mailbox 24 Enable */
  2168. #define MC25 0x200 /* Mailbox 25 Enable */
  2169. #define MC26 0x400 /* Mailbox 26 Enable */
  2170. #define MC27 0x800 /* Mailbox 27 Enable */
  2171. #define MC28 0x1000 /* Mailbox 28 Enable */
  2172. #define MC29 0x2000 /* Mailbox 29 Enable */
  2173. #define MC30 0x4000 /* Mailbox 30 Enable */
  2174. #define MC31 0x8000 /* Mailbox 31 Enable */
  2175. /* Bit masks for CAN0_MD1 */
  2176. #define MD0 0x1 /* Mailbox 0 Receive Enable */
  2177. #define MD1 0x2 /* Mailbox 1 Receive Enable */
  2178. #define MD2 0x4 /* Mailbox 2 Receive Enable */
  2179. #define MD3 0x8 /* Mailbox 3 Receive Enable */
  2180. #define MD4 0x10 /* Mailbox 4 Receive Enable */
  2181. #define MD5 0x20 /* Mailbox 5 Receive Enable */
  2182. #define MD6 0x40 /* Mailbox 6 Receive Enable */
  2183. #define MD7 0x80 /* Mailbox 7 Receive Enable */
  2184. #define MD8 0x100 /* Mailbox 8 Receive Enable */
  2185. #define MD9 0x200 /* Mailbox 9 Receive Enable */
  2186. #define MD10 0x400 /* Mailbox 10 Receive Enable */
  2187. #define MD11 0x800 /* Mailbox 11 Receive Enable */
  2188. #define MD12 0x1000 /* Mailbox 12 Receive Enable */
  2189. #define MD13 0x2000 /* Mailbox 13 Receive Enable */
  2190. #define MD14 0x4000 /* Mailbox 14 Receive Enable */
  2191. #define MD15 0x8000 /* Mailbox 15 Receive Enable */
  2192. /* Bit masks for CAN0_MD2 */
  2193. #define MD16 0x1 /* Mailbox 16 Receive Enable */
  2194. #define MD17 0x2 /* Mailbox 17 Receive Enable */
  2195. #define MD18 0x4 /* Mailbox 18 Receive Enable */
  2196. #define MD19 0x8 /* Mailbox 19 Receive Enable */
  2197. #define MD20 0x10 /* Mailbox 20 Receive Enable */
  2198. #define MD21 0x20 /* Mailbox 21 Receive Enable */
  2199. #define MD22 0x40 /* Mailbox 22 Receive Enable */
  2200. #define MD23 0x80 /* Mailbox 23 Receive Enable */
  2201. #define MD24 0x100 /* Mailbox 24 Receive Enable */
  2202. #define MD25 0x200 /* Mailbox 25 Receive Enable */
  2203. #define MD26 0x400 /* Mailbox 26 Receive Enable */
  2204. #define MD27 0x800 /* Mailbox 27 Receive Enable */
  2205. #define MD28 0x1000 /* Mailbox 28 Receive Enable */
  2206. #define MD29 0x2000 /* Mailbox 29 Receive Enable */
  2207. #define MD30 0x4000 /* Mailbox 30 Receive Enable */
  2208. #define MD31 0x8000 /* Mailbox 31 Receive Enable */
  2209. /* Bit masks for CAN0_RMP1 */
  2210. #define RMP0 0x1 /* Mailbox 0 Receive Message Pending */
  2211. #define RMP1 0x2 /* Mailbox 1 Receive Message Pending */
  2212. #define RMP2 0x4 /* Mailbox 2 Receive Message Pending */
  2213. #define RMP3 0x8 /* Mailbox 3 Receive Message Pending */
  2214. #define RMP4 0x10 /* Mailbox 4 Receive Message Pending */
  2215. #define RMP5 0x20 /* Mailbox 5 Receive Message Pending */
  2216. #define RMP6 0x40 /* Mailbox 6 Receive Message Pending */
  2217. #define RMP7 0x80 /* Mailbox 7 Receive Message Pending */
  2218. #define RMP8 0x100 /* Mailbox 8 Receive Message Pending */
  2219. #define RMP9 0x200 /* Mailbox 9 Receive Message Pending */
  2220. #define RMP10 0x400 /* Mailbox 10 Receive Message Pending */
  2221. #define RMP11 0x800 /* Mailbox 11 Receive Message Pending */
  2222. #define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */
  2223. #define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */
  2224. #define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */
  2225. #define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */
  2226. /* Bit masks for CAN0_RMP2 */
  2227. #define RMP16 0x1 /* Mailbox 16 Receive Message Pending */
  2228. #define RMP17 0x2 /* Mailbox 17 Receive Message Pending */
  2229. #define RMP18 0x4 /* Mailbox 18 Receive Message Pending */
  2230. #define RMP19 0x8 /* Mailbox 19 Receive Message Pending */
  2231. #define RMP20 0x10 /* Mailbox 20 Receive Message Pending */
  2232. #define RMP21 0x20 /* Mailbox 21 Receive Message Pending */
  2233. #define RMP22 0x40 /* Mailbox 22 Receive Message Pending */
  2234. #define RMP23 0x80 /* Mailbox 23 Receive Message Pending */
  2235. #define RMP24 0x100 /* Mailbox 24 Receive Message Pending */
  2236. #define RMP25 0x200 /* Mailbox 25 Receive Message Pending */
  2237. #define RMP26 0x400 /* Mailbox 26 Receive Message Pending */
  2238. #define RMP27 0x800 /* Mailbox 27 Receive Message Pending */
  2239. #define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */
  2240. #define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */
  2241. #define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */
  2242. #define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */
  2243. /* Bit masks for CAN0_RML1 */
  2244. #define RML0 0x1 /* Mailbox 0 Receive Message Lost */
  2245. #define RML1 0x2 /* Mailbox 1 Receive Message Lost */
  2246. #define RML2 0x4 /* Mailbox 2 Receive Message Lost */
  2247. #define RML3 0x8 /* Mailbox 3 Receive Message Lost */
  2248. #define RML4 0x10 /* Mailbox 4 Receive Message Lost */
  2249. #define RML5 0x20 /* Mailbox 5 Receive Message Lost */
  2250. #define RML6 0x40 /* Mailbox 6 Receive Message Lost */
  2251. #define RML7 0x80 /* Mailbox 7 Receive Message Lost */
  2252. #define RML8 0x100 /* Mailbox 8 Receive Message Lost */
  2253. #define RML9 0x200 /* Mailbox 9 Receive Message Lost */
  2254. #define RML10 0x400 /* Mailbox 10 Receive Message Lost */
  2255. #define RML11 0x800 /* Mailbox 11 Receive Message Lost */
  2256. #define RML12 0x1000 /* Mailbox 12 Receive Message Lost */
  2257. #define RML13 0x2000 /* Mailbox 13 Receive Message Lost */
  2258. #define RML14 0x4000 /* Mailbox 14 Receive Message Lost */
  2259. #define RML15 0x8000 /* Mailbox 15 Receive Message Lost */
  2260. /* Bit masks for CAN0_RML2 */
  2261. #define RML16 0x1 /* Mailbox 16 Receive Message Lost */
  2262. #define RML17 0x2 /* Mailbox 17 Receive Message Lost */
  2263. #define RML18 0x4 /* Mailbox 18 Receive Message Lost */
  2264. #define RML19 0x8 /* Mailbox 19 Receive Message Lost */
  2265. #define RML20 0x10 /* Mailbox 20 Receive Message Lost */
  2266. #define RML21 0x20 /* Mailbox 21 Receive Message Lost */
  2267. #define RML22 0x40 /* Mailbox 22 Receive Message Lost */
  2268. #define RML23 0x80 /* Mailbox 23 Receive Message Lost */
  2269. #define RML24 0x100 /* Mailbox 24 Receive Message Lost */
  2270. #define RML25 0x200 /* Mailbox 25 Receive Message Lost */
  2271. #define RML26 0x400 /* Mailbox 26 Receive Message Lost */
  2272. #define RML27 0x800 /* Mailbox 27 Receive Message Lost */
  2273. #define RML28 0x1000 /* Mailbox 28 Receive Message Lost */
  2274. #define RML29 0x2000 /* Mailbox 29 Receive Message Lost */
  2275. #define RML30 0x4000 /* Mailbox 30 Receive Message Lost */
  2276. #define RML31 0x8000 /* Mailbox 31 Receive Message Lost */
  2277. /* Bit masks for CAN0_OPSS1 */
  2278. #define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */
  2279. #define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */
  2280. #define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */
  2281. #define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */
  2282. #define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */
  2283. #define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */
  2284. #define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */
  2285. #define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */
  2286. #define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */
  2287. #define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */
  2288. #define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */
  2289. #define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */
  2290. #define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */
  2291. #define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */
  2292. #define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */
  2293. #define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */
  2294. /* Bit masks for CAN0_OPSS2 */
  2295. #define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */
  2296. #define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */
  2297. #define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */
  2298. #define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */
  2299. #define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */
  2300. #define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */
  2301. #define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */
  2302. #define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */
  2303. #define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */
  2304. #define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */
  2305. #define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */
  2306. #define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */
  2307. #define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */
  2308. #define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */
  2309. #define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */
  2310. #define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */
  2311. /* Bit masks for CAN0_TRS1 */
  2312. #define TRS0 0x1 /* Mailbox 0 Transmit Request Set */
  2313. #define TRS1 0x2 /* Mailbox 1 Transmit Request Set */
  2314. #define TRS2 0x4 /* Mailbox 2 Transmit Request Set */
  2315. #define TRS3 0x8 /* Mailbox 3 Transmit Request Set */
  2316. #define TRS4 0x10 /* Mailbox 4 Transmit Request Set */
  2317. #define TRS5 0x20 /* Mailbox 5 Transmit Request Set */
  2318. #define TRS6 0x40 /* Mailbox 6 Transmit Request Set */
  2319. #define TRS7 0x80 /* Mailbox 7 Transmit Request Set */
  2320. #define TRS8 0x100 /* Mailbox 8 Transmit Request Set */
  2321. #define TRS9 0x200 /* Mailbox 9 Transmit Request Set */
  2322. #define TRS10 0x400 /* Mailbox 10 Transmit Request Set */
  2323. #define TRS11 0x800 /* Mailbox 11 Transmit Request Set */
  2324. #define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */
  2325. #define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */
  2326. #define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */
  2327. #define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */
  2328. /* Bit masks for CAN0_TRS2 */
  2329. #define TRS16 0x1 /* Mailbox 16 Transmit Request Set */
  2330. #define TRS17 0x2 /* Mailbox 17 Transmit Request Set */
  2331. #define TRS18 0x4 /* Mailbox 18 Transmit Request Set */
  2332. #define TRS19 0x8 /* Mailbox 19 Transmit Request Set */
  2333. #define TRS20 0x10 /* Mailbox 20 Transmit Request Set */
  2334. #define TRS21 0x20 /* Mailbox 21 Transmit Request Set */
  2335. #define TRS22 0x40 /* Mailbox 22 Transmit Request Set */
  2336. #define TRS23 0x80 /* Mailbox 23 Transmit Request Set */
  2337. #define TRS24 0x100 /* Mailbox 24 Transmit Request Set */
  2338. #define TRS25 0x200 /* Mailbox 25 Transmit Request Set */
  2339. #define TRS26 0x400 /* Mailbox 26 Transmit Request Set */
  2340. #define TRS27 0x800 /* Mailbox 27 Transmit Request Set */
  2341. #define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */
  2342. #define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */
  2343. #define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */
  2344. #define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */
  2345. /* Bit masks for CAN0_TRR1 */
  2346. #define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */
  2347. #define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */
  2348. #define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */
  2349. #define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */
  2350. #define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */
  2351. #define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */
  2352. #define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */
  2353. #define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */
  2354. #define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */
  2355. #define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */
  2356. #define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */
  2357. #define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */
  2358. #define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */
  2359. #define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */
  2360. #define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */
  2361. #define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */
  2362. /* Bit masks for CAN0_TRR2 */
  2363. #define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */
  2364. #define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */
  2365. #define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */
  2366. #define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */
  2367. #define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */
  2368. #define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */
  2369. #define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */
  2370. #define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */
  2371. #define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */
  2372. #define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */
  2373. #define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */
  2374. #define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */
  2375. #define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */
  2376. #define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */
  2377. #define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */
  2378. #define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */
  2379. /* Bit masks for CAN0_AA1 */
  2380. #define AA0 0x1 /* Mailbox 0 Abort Acknowledge */
  2381. #define AA1 0x2 /* Mailbox 1 Abort Acknowledge */
  2382. #define AA2 0x4 /* Mailbox 2 Abort Acknowledge */
  2383. #define AA3 0x8 /* Mailbox 3 Abort Acknowledge */
  2384. #define AA4 0x10 /* Mailbox 4 Abort Acknowledge */
  2385. #define AA5 0x20 /* Mailbox 5 Abort Acknowledge */
  2386. #define AA6 0x40 /* Mailbox 6 Abort Acknowledge */
  2387. #define AA7 0x80 /* Mailbox 7 Abort Acknowledge */
  2388. #define AA8 0x100 /* Mailbox 8 Abort Acknowledge */
  2389. #define AA9 0x200 /* Mailbox 9 Abort Acknowledge */
  2390. #define AA10 0x400 /* Mailbox 10 Abort Acknowledge */
  2391. #define AA11 0x800 /* Mailbox 11 Abort Acknowledge */
  2392. #define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */
  2393. #define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */
  2394. #define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */
  2395. #define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */
  2396. /* Bit masks for CAN0_AA2 */
  2397. #define AA16 0x1 /* Mailbox 16 Abort Acknowledge */
  2398. #define AA17 0x2 /* Mailbox 17 Abort Acknowledge */
  2399. #define AA18 0x4 /* Mailbox 18 Abort Acknowledge */
  2400. #define AA19 0x8 /* Mailbox 19 Abort Acknowledge */
  2401. #define AA20 0x10 /* Mailbox 20 Abort Acknowledge */
  2402. #define AA21 0x20 /* Mailbox 21 Abort Acknowledge */
  2403. #define AA22 0x40 /* Mailbox 22 Abort Acknowledge */
  2404. #define AA23 0x80 /* Mailbox 23 Abort Acknowledge */
  2405. #define AA24 0x100 /* Mailbox 24 Abort Acknowledge */
  2406. #define AA25 0x200 /* Mailbox 25 Abort Acknowledge */
  2407. #define AA26 0x400 /* Mailbox 26 Abort Acknowledge */
  2408. #define AA27 0x800 /* Mailbox 27 Abort Acknowledge */
  2409. #define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */
  2410. #define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */
  2411. #define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */
  2412. #define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */
  2413. /* Bit masks for CAN0_TA1 */
  2414. #define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */
  2415. #define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */
  2416. #define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */
  2417. #define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */
  2418. #define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */
  2419. #define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */
  2420. #define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */
  2421. #define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */
  2422. #define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */
  2423. #define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */
  2424. #define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */
  2425. #define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */
  2426. #define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */
  2427. #define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */
  2428. #define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */
  2429. #define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */
  2430. /* Bit masks for CAN0_TA2 */
  2431. #define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */
  2432. #define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */
  2433. #define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */
  2434. #define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */
  2435. #define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */
  2436. #define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */
  2437. #define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */
  2438. #define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */
  2439. #define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */
  2440. #define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */
  2441. #define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */
  2442. #define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */
  2443. #define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */
  2444. #define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */
  2445. #define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */
  2446. #define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */
  2447. /* Bit masks for CAN0_RFH1 */
  2448. #define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */
  2449. #define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */
  2450. #define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */
  2451. #define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */
  2452. #define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */
  2453. #define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */
  2454. #define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */
  2455. #define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */
  2456. #define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */
  2457. #define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */
  2458. #define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */
  2459. #define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */
  2460. #define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */
  2461. #define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */
  2462. #define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */
  2463. #define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */
  2464. /* Bit masks for CAN0_RFH2 */
  2465. #define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */
  2466. #define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */
  2467. #define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */
  2468. #define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */
  2469. #define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */
  2470. #define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */
  2471. #define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */
  2472. #define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */
  2473. #define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */
  2474. #define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */
  2475. #define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */
  2476. #define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */
  2477. #define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */
  2478. #define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */
  2479. #define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */
  2480. #define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */
  2481. /* Bit masks for CAN0_MBIM1 */
  2482. #define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */
  2483. #define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */
  2484. #define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */
  2485. #define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */
  2486. #define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */
  2487. #define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */
  2488. #define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */
  2489. #define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */
  2490. #define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */
  2491. #define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */
  2492. #define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */
  2493. #define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */
  2494. #define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */
  2495. #define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */
  2496. #define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */
  2497. #define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */
  2498. /* Bit masks for CAN0_MBIM2 */
  2499. #define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */
  2500. #define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */
  2501. #define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */
  2502. #define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */
  2503. #define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */
  2504. #define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */
  2505. #define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */
  2506. #define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */
  2507. #define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */
  2508. #define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */
  2509. #define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */
  2510. #define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */
  2511. #define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */
  2512. #define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */
  2513. #define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */
  2514. #define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */
  2515. /* Bit masks for CAN0_MBTIF1 */
  2516. #define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */
  2517. #define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */
  2518. #define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */
  2519. #define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */
  2520. #define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */
  2521. #define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */
  2522. #define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */
  2523. #define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */
  2524. #define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */
  2525. #define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */
  2526. #define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */
  2527. #define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */
  2528. #define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */
  2529. #define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */
  2530. #define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */
  2531. #define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */
  2532. /* Bit masks for CAN0_MBTIF2 */
  2533. #define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */
  2534. #define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */
  2535. #define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */
  2536. #define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */
  2537. #define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */
  2538. #define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */
  2539. #define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */
  2540. #define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */
  2541. #define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */
  2542. #define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */
  2543. #define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */
  2544. #define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */
  2545. #define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */
  2546. #define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */
  2547. #define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */
  2548. #define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */
  2549. /* Bit masks for CAN0_MBRIF1 */
  2550. #define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */
  2551. #define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */
  2552. #define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */
  2553. #define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */
  2554. #define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */
  2555. #define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */
  2556. #define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */
  2557. #define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */
  2558. #define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */
  2559. #define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */
  2560. #define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */
  2561. #define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */
  2562. #define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */
  2563. #define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */
  2564. #define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */
  2565. #define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */
  2566. /* Bit masks for CAN0_MBRIF2 */
  2567. #define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */
  2568. #define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */
  2569. #define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */
  2570. #define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */
  2571. #define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */
  2572. #define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */
  2573. #define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */
  2574. #define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */
  2575. #define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */
  2576. #define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */
  2577. #define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */
  2578. #define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */
  2579. #define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */
  2580. #define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */
  2581. #define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */
  2582. #define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */
  2583. /* Bit masks for EPPIx_STATUS */
  2584. #define CFIFO_ERR 0x1 /* Chroma FIFO Error */
  2585. #define YFIFO_ERR 0x2 /* Luma FIFO Error */
  2586. #define LTERR_OVR 0x4 /* Line Track Overflow */
  2587. #define LTERR_UNDR 0x8 /* Line Track Underflow */
  2588. #define FTERR_OVR 0x10 /* Frame Track Overflow */
  2589. #define FTERR_UNDR 0x20 /* Frame Track Underflow */
  2590. #define ERR_NCOR 0x40 /* Preamble Error Not Corrected */
  2591. #define DMA1URQ 0x80 /* DMA1 Urgent Request */
  2592. #define DMA0URQ 0x100 /* DMA0 Urgent Request */
  2593. #define ERR_DET 0x4000 /* Preamble Error Detected */
  2594. #define FLD 0x8000 /* Field */
  2595. /* Bit masks for EPPIx_CONTROL */
  2596. #define EPPI_EN 0x1 /* Enable */
  2597. #define EPPI_DIR 0x2 /* Direction */
  2598. #define XFR_TYPE 0xc /* Operating Mode */
  2599. #define FS_CFG 0x30 /* Frame Sync Configuration */
  2600. #define FLD_SEL 0x40 /* Field Select/Trigger */
  2601. #define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */
  2602. #define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */
  2603. #define ICLKGEN 0x200 /* Internal Clock Generation */
  2604. #define IFSGEN 0x400 /* Internal Frame Sync Generation */
  2605. #define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */
  2606. #define POLS 0x6000 /* Frame Sync Polarity */
  2607. #define DLENGTH 0x38000 /* Data Length */
  2608. #define SKIP_EN 0x40000 /* Skip Enable */
  2609. #define SKIP_EO 0x80000 /* Skip Even or Odd */
  2610. #define PACKEN 0x100000 /* Packing/Unpacking Enable */
  2611. #define SWAPEN 0x200000 /* Swap Enable */
  2612. #define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */
  2613. #define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */
  2614. #define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */
  2615. #define DMACFG 0x2000000 /* One or Two DMA Channels Mode */
  2616. #define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */
  2617. #define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */
  2618. #define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */
  2619. #define DLEN_8 (0 << 15) /* 000 - 8 bits */
  2620. #define DLEN_10 (1 << 15) /* 001 - 10 bits */
  2621. #define DLEN_12 (2 << 15) /* 010 - 12 bits */
  2622. #define DLEN_14 (3 << 15) /* 011 - 14 bits */
  2623. #define DLEN_16 (4 << 15) /* 100 - 16 bits */
  2624. #define DLEN_18 (5 << 15) /* 101 - 18 bits */
  2625. #define DLEN_24 (6 << 15) /* 110 - 24 bits */
  2626. /* Bit masks for EPPIx_FS2W_LVB */
  2627. #define F1VB_BD 0xff /* Vertical Blanking before Field 1 Active Data */
  2628. #define F1VB_AD 0xff00 /* Vertical Blanking after Field 1 Active Data */
  2629. #define F2VB_BD 0xff0000 /* Vertical Blanking before Field 2 Active Data */
  2630. #define F2VB_AD 0xff000000 /* Vertical Blanking after Field 2 Active Data */
  2631. /* Bit masks for EPPIx_FS2W_LAVF */
  2632. #define F1_ACT 0xffff /* Number of Lines of Active Data in Field 1 */
  2633. #define F2_ACT 0xffff0000 /* Number of Lines of Active Data in Field 2 */
  2634. /* Bit masks for EPPIx_CLIP */
  2635. #define LOW_ODD 0xff /* Lower Limit for Odd Bytes (Chroma) */
  2636. #define HIGH_ODD 0xff00 /* Upper Limit for Odd Bytes (Chroma) */
  2637. #define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */
  2638. #define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */
  2639. /* Bit masks for SPIx_BAUD */
  2640. #define SPI_BAUD 0xffff /* Baud Rate */
  2641. /* Bit masks for SPIx_CTL */
  2642. #define SPE 0x4000 /* SPI Enable */
  2643. #define WOM 0x2000 /* Write Open Drain Master */
  2644. #define MSTR 0x1000 /* Master Mode */
  2645. #define CPOL 0x800 /* Clock Polarity */
  2646. #define CPHA 0x400 /* Clock Phase */
  2647. #define LSBF 0x200 /* LSB First */
  2648. #define SIZE 0x100 /* Size of Words */
  2649. #define EMISO 0x20 /* Enable MISO Output */
  2650. #define PSSE 0x10 /* Slave-Select Enable */
  2651. #define GM 0x8 /* Get More Data */
  2652. #define SZ 0x4 /* Send Zero */
  2653. #define TIMOD 0x3 /* Transfer Initiation Mode */
  2654. /* Bit masks for SPIx_FLG */
  2655. #define FLS1 0x2 /* Slave Select Enable 1 */
  2656. #define FLS2 0x4 /* Slave Select Enable 2 */
  2657. #define FLS3 0x8 /* Slave Select Enable 3 */
  2658. #define FLG1 0x200 /* Slave Select Value 1 */
  2659. #define FLG2 0x400 /* Slave Select Value 2 */
  2660. #define FLG3 0x800 /* Slave Select Value 3 */
  2661. /* Bit masks for SPIx_STAT */
  2662. #define TXCOL 0x40 /* Transmit Collision Error */
  2663. #define RXS 0x20 /* RDBR Data Buffer Status */
  2664. #define RBSY 0x10 /* Receive Error */
  2665. #define TXS 0x8 /* TDBR Data Buffer Status */
  2666. #define TXE 0x4 /* Transmission Error */
  2667. #define MODF 0x2 /* Mode Fault Error */
  2668. #define SPIF 0x1 /* SPI Finished */
  2669. /* Bit masks for SPIx_TDBR */
  2670. #define TDBR 0xffff /* Transmit Data Buffer */
  2671. /* Bit masks for SPIx_RDBR */
  2672. #define RDBR 0xffff /* Receive Data Buffer */
  2673. /* Bit masks for SPIx_SHADOW */
  2674. #define SHADOW 0xffff /* RDBR Shadow */
  2675. /* ************************************************ */
  2676. /* The TWI bit masks fields are from the ADSP-BF538 */
  2677. /* and they have not been verified as the final */
  2678. /* ones for the Moab processors ... bz 1/19/2007 */
  2679. /* ************************************************ */
  2680. /* Bit masks for TWIx_CONTROL */
  2681. #define PRESCALE 0x7f /* Prescale Value */
  2682. #define TWI_ENA 0x80 /* TWI Enable */
  2683. #define SCCB 0x200 /* Serial Camera Control Bus */
  2684. /* Bit maskes for TWIx_CLKDIV */
  2685. #define CLKLOW 0xff /* Clock Low */
  2686. #define CLKHI 0xff00 /* Clock High */
  2687. /* Bit maskes for TWIx_SLAVE_CTL */
  2688. #define SEN 0x1 /* Slave Enable */
  2689. #define STDVAL 0x4 /* Slave Transmit Data Valid */
  2690. #define NAK 0x8 /* Not Acknowledge */
  2691. #define GEN 0x10 /* General Call Enable */
  2692. /* Bit maskes for TWIx_SLAVE_ADDR */
  2693. #define SADDR 0x7f /* Slave Mode Address */
  2694. /* Bit maskes for TWIx_SLAVE_STAT */
  2695. #define SDIR 0x1 /* Slave Transfer Direction */
  2696. #define GCALL 0x2 /* General Call */
  2697. /* Bit maskes for TWIx_MASTER_CTL */
  2698. #define MEN 0x1 /* Master Mode Enable */
  2699. #define MDIR 0x4 /* Master Transfer Direction */
  2700. #define FAST 0x8 /* Fast Mode */
  2701. #define STOP 0x10 /* Issue Stop Condition */
  2702. #define RSTART 0x20 /* Repeat Start */
  2703. #define DCNT 0x3fc0 /* Data Transfer Count */
  2704. #define SDAOVR 0x4000 /* Serial Data Override */
  2705. #define SCLOVR 0x8000 /* Serial Clock Override */
  2706. /* Bit maskes for TWIx_MASTER_ADDR */
  2707. #define MADDR 0x7f /* Master Mode Address */
  2708. /* Bit maskes for TWIx_MASTER_STAT */
  2709. #define MPROG 0x1 /* Master Transfer in Progress */
  2710. #define LOSTARB 0x2 /* Lost Arbitration */
  2711. #define ANAK 0x4 /* Address Not Acknowledged */
  2712. #define DNAK 0x8 /* Data Not Acknowledged */
  2713. #define BUFRDERR 0x10 /* Buffer Read Error */
  2714. #define BUFWRERR 0x20 /* Buffer Write Error */
  2715. #define SDASEN 0x40 /* Serial Data Sense */
  2716. #define SCLSEN 0x80 /* Serial Clock Sense */
  2717. #define BUSBUSY 0x100 /* Bus Busy */
  2718. /* Bit maskes for TWIx_FIFO_CTL */
  2719. #define XMTFLUSH 0x1 /* Transmit Buffer Flush */
  2720. #define RCVFLUSH 0x2 /* Receive Buffer Flush */
  2721. #define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */
  2722. #define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */
  2723. /* Bit maskes for TWIx_FIFO_STAT */
  2724. #define XMTSTAT 0x3 /* Transmit FIFO Status */
  2725. #define RCVSTAT 0xc /* Receive FIFO Status */
  2726. /* Bit maskes for TWIx_INT_MASK */
  2727. #define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */
  2728. #define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */
  2729. #define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */
  2730. #define SOVFM 0x8 /* Slave Overflow Interrupt Mask */
  2731. #define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */
  2732. #define MERRM 0x20 /* Master Transfer Error Interrupt Mask */
  2733. #define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */
  2734. #define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */
  2735. /* Bit maskes for TWIx_INT_STAT */
  2736. #define SINIT 0x1 /* Slave Transfer Initiated */
  2737. #define SCOMP 0x2 /* Slave Transfer Complete */
  2738. #define SERR 0x4 /* Slave Transfer Error */
  2739. #define SOVF 0x8 /* Slave Overflow */
  2740. #define MCOMP 0x10 /* Master Transfer Complete */
  2741. #define MERR 0x20 /* Master Transfer Error */
  2742. #define XMTSERV 0x40 /* Transmit FIFO Service */
  2743. #define RCVSERV 0x80 /* Receive FIFO Service */
  2744. /* Bit maskes for TWIx_XMT_DATA8 */
  2745. #define XMTDATA8 0xff /* Transmit FIFO 8-Bit Data */
  2746. /* Bit maskes for TWIx_XMT_DATA16 */
  2747. #define XMTDATA16 0xffff /* Transmit FIFO 16-Bit Data */
  2748. /* Bit maskes for TWIx_RCV_DATA8 */
  2749. #define RCVDATA8 0xff /* Receive FIFO 8-Bit Data */
  2750. /* Bit maskes for TWIx_RCV_DATA16 */
  2751. #define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */
  2752. /* Bit masks for SPORTx_TCR1 */
  2753. #define TCKFE 0x4000 /* Clock Falling Edge Select */
  2754. #define LATFS 0x2000 /* Late Transmit Frame Sync */
  2755. #define LTFS 0x1000 /* Low Transmit Frame Sync Select */
  2756. #define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */
  2757. #define TFSR 0x400 /* Transmit Frame Sync Required Select */
  2758. #define ITFS 0x200 /* Internal Transmit Frame Sync Select */
  2759. #define TLSBIT 0x10 /* Transmit Bit Order */
  2760. #define TDTYPE 0xc /* Data Formatting Type Select */
  2761. #define ITCLK 0x2 /* Internal Transmit Clock Select */
  2762. #define TSPEN 0x1 /* Transmit Enable */
  2763. /* Bit masks for SPORTx_TCR2 */
  2764. #define TRFST 0x400 /* Left/Right Order */
  2765. #define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */
  2766. #define TXSE 0x100 /* TxSEC Enable */
  2767. #define SLEN_T 0x1f /* SPORT Word Length */
  2768. /* Bit masks for SPORTx_RCR1 */
  2769. #define RCKFE 0x4000 /* Clock Falling Edge Select */
  2770. #define LARFS 0x2000 /* Late Receive Frame Sync */
  2771. #define LRFS 0x1000 /* Low Receive Frame Sync Select */
  2772. #define RFSR 0x400 /* Receive Frame Sync Required Select */
  2773. #define IRFS 0x200 /* Internal Receive Frame Sync Select */
  2774. #define RLSBIT 0x10 /* Receive Bit Order */
  2775. #define RDTYPE 0xc /* Data Formatting Type Select */
  2776. #define IRCLK 0x2 /* Internal Receive Clock Select */
  2777. #define RSPEN 0x1 /* Receive Enable */
  2778. /* Bit masks for SPORTx_RCR2 */
  2779. #define RRFST 0x400 /* Left/Right Order */
  2780. #define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */
  2781. #define RXSE 0x100 /* RxSEC Enable */
  2782. #define SLEN_R 0x1f /* SPORT Word Length */
  2783. /* Bit masks for SPORTx_STAT */
  2784. #define TXHRE 0x40 /* Transmit Hold Register Empty */
  2785. #define TOVF 0x20 /* Sticky Transmit Overflow Status */
  2786. #define TUVF 0x10 /* Sticky Transmit Underflow Status */
  2787. #define TXF 0x8 /* Transmit FIFO Full Status */
  2788. #define ROVF 0x4 /* Sticky Receive Overflow Status */
  2789. #define RUVF 0x2 /* Sticky Receive Underflow Status */
  2790. #define RXNE 0x1 /* Receive FIFO Not Empty Status */
  2791. /* Bit masks for SPORTx_MCMC1 */
  2792. #define SP_WSIZE 0xf000 /* Window Size */
  2793. #define SP_WOFF 0x3ff /* Windows Offset */
  2794. /* Bit masks for SPORTx_MCMC2 */
  2795. #define MFD 0xf000 /* Multi channel Frame Delay */
  2796. #define FSDR 0x80 /* Frame Sync to Data Relationship */
  2797. #define MCMEN 0x10 /* Multi channel Frame Mode Enable */
  2798. #define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */
  2799. #define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */
  2800. #define MCCRM 0x3 /* 2X Clock Recovery Mode */
  2801. /* Bit masks for SPORTx_CHNL */
  2802. #define CUR_CHNL 0x3ff /* Current Channel Indicator */
  2803. /* Bit masks for UARTx_LCR */
  2804. #if 0
  2805. /* conflicts with legacy one in last section */
  2806. #define WLS 0x3 /* Word Length Select */
  2807. #endif
  2808. #define STB 0x4 /* Stop Bits */
  2809. #define PEN 0x8 /* Parity Enable */
  2810. #define EPS 0x10 /* Even Parity Select */
  2811. #define STP 0x20 /* Sticky Parity */
  2812. #define SB 0x40 /* Set Break */
  2813. /* Bit masks for UARTx_MCR */
  2814. #define XOFF 0x1 /* Transmitter Off */
  2815. #define MRTS 0x2 /* Manual Request To Send */
  2816. #define RFIT 0x4 /* Receive FIFO IRQ Threshold */
  2817. #define RFRT 0x8 /* Receive FIFO RTS Threshold */
  2818. #define LOOP_ENA 0x10 /* Loopback Mode Enable */
  2819. #define FCPOL 0x20 /* Flow Control Pin Polarity */
  2820. #define ARTS 0x40 /* Automatic Request To Send */
  2821. #define ACTS 0x80 /* Automatic Clear To Send */
  2822. /* Bit masks for UARTx_LSR */
  2823. #define DR 0x1 /* Data Ready */
  2824. #define OE 0x2 /* Overrun Error */
  2825. #define PE 0x4 /* Parity Error */
  2826. #define FE 0x8 /* Framing Error */
  2827. #define BI 0x10 /* Break Interrupt */
  2828. #define THRE 0x20 /* THR Empty */
  2829. #define TEMT 0x40 /* Transmitter Empty */
  2830. #define TFI 0x80 /* Transmission Finished Indicator */
  2831. /* Bit masks for UARTx_MSR */
  2832. #define SCTS 0x1 /* Sticky CTS */
  2833. #define CTS 0x10 /* Clear To Send */
  2834. #define RFCS 0x20 /* Receive FIFO Count Status */
  2835. /* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */
  2836. #define ERBFI 0x1 /* Enable Receive Buffer Full Interrupt */
  2837. #define ETBEI 0x2 /* Enable Transmit Buffer Empty Interrupt */
  2838. #define ELSI 0x4 /* Enable Receive Status Interrupt */
  2839. #define EDSSI 0x8 /* Enable Modem Status Interrupt */
  2840. #define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
  2841. #define ETFI 0x20 /* Enable Transmission Finished Interrupt */
  2842. #define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
  2843. /* Bit masks for UARTx_GCTL */
  2844. #define UCEN 0x1 /* UART Enable */
  2845. #define IREN 0x2 /* IrDA Mode Enable */
  2846. #define TPOLC 0x4 /* IrDA TX Polarity Change */
  2847. #define RPOLC 0x8 /* IrDA RX Polarity Change */
  2848. #define FPE 0x10 /* Force Parity Error */
  2849. #define FFE 0x20 /* Force Framing Error */
  2850. #define EDBO 0x40 /* Enable Divide-by-One */
  2851. #define EGLSI 0x80 /* Enable Global LS Interrupt */
  2852. /* ******************************************* */
  2853. /* MULTI BIT MACRO ENUMERATIONS */
  2854. /* ******************************************* */
  2855. /* BCODE bit field options (SYSCFG register) */
  2856. #define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */
  2857. #define BCODE_FULLBOOT 0x0010 /* always perform full boot */
  2858. #define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */
  2859. #define BCODE_NOBOOT 0x0030 /* always perform full boot */
  2860. /* CNT_COMMAND bit field options */
  2861. #define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */
  2862. #define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */
  2863. #define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */
  2864. #define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */
  2865. #define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */
  2866. #define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */
  2867. #define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */
  2868. #define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */
  2869. #define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */
  2870. /* CNT_CONFIG bit field options */
  2871. #define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */
  2872. #define CNTMODE_BINENC 0x0100 /* binary encoder mode */
  2873. #define CNTMODE_UDCNT 0x0200 /* up/down counter mode */
  2874. #define CNTMODE_DIRCNT 0x0400 /* direction counter mode */
  2875. #define CNTMODE_DIRTMR 0x0500 /* direction timer mode */
  2876. #define BNDMODE_COMP 0x0000 /* boundary compare mode */
  2877. #define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */
  2878. #define BNDMODE_CAPT 0x2000 /* boundary capture mode */
  2879. #define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
  2880. /* TMODE in TIMERx_CONFIG bit field options */
  2881. #define PWM_OUT 0x0001
  2882. #define WDTH_CAP 0x0002
  2883. #define EXT_CLK 0x0003
  2884. /* UARTx_LCR bit field options */
  2885. #define WLS_5 0x0000 /* 5 data bits */
  2886. #define WLS_6 0x0001 /* 6 data bits */
  2887. #define WLS_7 0x0002 /* 7 data bits */
  2888. #define WLS_8 0x0003 /* 8 data bits */
  2889. /* PINTx Register Bit Definitions */
  2890. #define PIQ0 0x00000001
  2891. #define PIQ1 0x00000002
  2892. #define PIQ2 0x00000004
  2893. #define PIQ3 0x00000008
  2894. #define PIQ4 0x00000010
  2895. #define PIQ5 0x00000020
  2896. #define PIQ6 0x00000040
  2897. #define PIQ7 0x00000080
  2898. #define PIQ8 0x00000100
  2899. #define PIQ9 0x00000200
  2900. #define PIQ10 0x00000400
  2901. #define PIQ11 0x00000800
  2902. #define PIQ12 0x00001000
  2903. #define PIQ13 0x00002000
  2904. #define PIQ14 0x00004000
  2905. #define PIQ15 0x00008000
  2906. #define PIQ16 0x00010000
  2907. #define PIQ17 0x00020000
  2908. #define PIQ18 0x00040000
  2909. #define PIQ19 0x00080000
  2910. #define PIQ20 0x00100000
  2911. #define PIQ21 0x00200000
  2912. #define PIQ22 0x00400000
  2913. #define PIQ23 0x00800000
  2914. #define PIQ24 0x01000000
  2915. #define PIQ25 0x02000000
  2916. #define PIQ26 0x04000000
  2917. #define PIQ27 0x08000000
  2918. #define PIQ28 0x10000000
  2919. #define PIQ29 0x20000000
  2920. #define PIQ30 0x40000000
  2921. #define PIQ31 0x80000000
  2922. /* PORT A Bit Definitions for the registers
  2923. PORTA, PORTA_SET, PORTA_CLEAR,
  2924. PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN,
  2925. PORTA_FER registers
  2926. */
  2927. #define PA0 0x0001
  2928. #define PA1 0x0002
  2929. #define PA2 0x0004
  2930. #define PA3 0x0008
  2931. #define PA4 0x0010
  2932. #define PA5 0x0020
  2933. #define PA6 0x0040
  2934. #define PA7 0x0080
  2935. #define PA8 0x0100
  2936. #define PA9 0x0200
  2937. #define PA10 0x0400
  2938. #define PA11 0x0800
  2939. #define PA12 0x1000
  2940. #define PA13 0x2000
  2941. #define PA14 0x4000
  2942. #define PA15 0x8000
  2943. /* PORT B Bit Definitions for the registers
  2944. PORTB, PORTB_SET, PORTB_CLEAR,
  2945. PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN,
  2946. PORTB_FER registers
  2947. */
  2948. #define PB0 0x0001
  2949. #define PB1 0x0002
  2950. #define PB2 0x0004
  2951. #define PB3 0x0008
  2952. #define PB4 0x0010
  2953. #define PB5 0x0020
  2954. #define PB6 0x0040
  2955. #define PB7 0x0080
  2956. #define PB8 0x0100
  2957. #define PB9 0x0200
  2958. #define PB10 0x0400
  2959. #define PB11 0x0800
  2960. #define PB12 0x1000
  2961. #define PB13 0x2000
  2962. #define PB14 0x4000
  2963. /* PORT C Bit Definitions for the registers
  2964. PORTC, PORTC_SET, PORTC_CLEAR,
  2965. PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN,
  2966. PORTC_FER registers
  2967. */
  2968. #define PC0 0x0001
  2969. #define PC1 0x0002
  2970. #define PC2 0x0004
  2971. #define PC3 0x0008
  2972. #define PC4 0x0010
  2973. #define PC5 0x0020
  2974. #define PC6 0x0040
  2975. #define PC7 0x0080
  2976. #define PC8 0x0100
  2977. #define PC9 0x0200
  2978. #define PC10 0x0400
  2979. #define PC11 0x0800
  2980. #define PC12 0x1000
  2981. #define PC13 0x2000
  2982. /* PORT D Bit Definitions for the registers
  2983. PORTD, PORTD_SET, PORTD_CLEAR,
  2984. PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN,
  2985. PORTD_FER registers
  2986. */
  2987. #define PD0 0x0001
  2988. #define PD1 0x0002
  2989. #define PD2 0x0004
  2990. #define PD3 0x0008
  2991. #define PD4 0x0010
  2992. #define PD5 0x0020
  2993. #define PD6 0x0040
  2994. #define PD7 0x0080
  2995. #define PD8 0x0100
  2996. #define PD9 0x0200
  2997. #define PD10 0x0400
  2998. #define PD11 0x0800
  2999. #define PD12 0x1000
  3000. #define PD13 0x2000
  3001. #define PD14 0x4000
  3002. #define PD15 0x8000
  3003. /* PORT E Bit Definitions for the registers
  3004. PORTE, PORTE_SET, PORTE_CLEAR,
  3005. PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN,
  3006. PORTE_FER registers
  3007. */
  3008. #define PE0 0x0001
  3009. #define PE1 0x0002
  3010. #define PE2 0x0004
  3011. #define PE3 0x0008
  3012. #define PE4 0x0010
  3013. #define PE5 0x0020
  3014. #define PE6 0x0040
  3015. #define PE7 0x0080
  3016. #define PE8 0x0100
  3017. #define PE9 0x0200
  3018. #define PE10 0x0400
  3019. #define PE11 0x0800
  3020. #define PE12 0x1000
  3021. #define PE13 0x2000
  3022. #define PE14 0x4000
  3023. #define PE15 0x8000
  3024. /* PORT F Bit Definitions for the registers
  3025. PORTF, PORTF_SET, PORTF_CLEAR,
  3026. PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN,
  3027. PORTF_FER registers
  3028. */
  3029. #define PF0 0x0001
  3030. #define PF1 0x0002
  3031. #define PF2 0x0004
  3032. #define PF3 0x0008
  3033. #define PF4 0x0010
  3034. #define PF5 0x0020
  3035. #define PF6 0x0040
  3036. #define PF7 0x0080
  3037. #define PF8 0x0100
  3038. #define PF9 0x0200
  3039. #define PF10 0x0400
  3040. #define PF11 0x0800
  3041. #define PF12 0x1000
  3042. #define PF13 0x2000
  3043. #define PF14 0x4000
  3044. #define PF15 0x8000
  3045. /* PORT G Bit Definitions for the registers
  3046. PORTG, PORTG_SET, PORTG_CLEAR,
  3047. PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN,
  3048. PORTG_FER registers
  3049. */
  3050. #define PG0 0x0001
  3051. #define PG1 0x0002
  3052. #define PG2 0x0004
  3053. #define PG3 0x0008
  3054. #define PG4 0x0010
  3055. #define PG5 0x0020
  3056. #define PG6 0x0040
  3057. #define PG7 0x0080
  3058. #define PG8 0x0100
  3059. #define PG9 0x0200
  3060. #define PG10 0x0400
  3061. #define PG11 0x0800
  3062. #define PG12 0x1000
  3063. #define PG13 0x2000
  3064. #define PG14 0x4000
  3065. #define PG15 0x8000
  3066. /* PORT H Bit Definitions for the registers
  3067. PORTH, PORTH_SET, PORTH_CLEAR,
  3068. PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN,
  3069. PORTH_FER registers
  3070. */
  3071. #define PH0 0x0001
  3072. #define PH1 0x0002
  3073. #define PH2 0x0004
  3074. #define PH3 0x0008
  3075. #define PH4 0x0010
  3076. #define PH5 0x0020
  3077. #define PH6 0x0040
  3078. #define PH7 0x0080
  3079. #define PH8 0x0100
  3080. #define PH9 0x0200
  3081. #define PH10 0x0400
  3082. #define PH11 0x0800
  3083. #define PH12 0x1000
  3084. #define PH13 0x2000
  3085. /* PORT I Bit Definitions for the registers
  3086. PORTI, PORTI_SET, PORTI_CLEAR,
  3087. PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN,
  3088. PORTI_FER registers
  3089. */
  3090. #define PI0 0x0001
  3091. #define PI1 0x0002
  3092. #define PI2 0x0004
  3093. #define PI3 0x0008
  3094. #define PI4 0x0010
  3095. #define PI5 0x0020
  3096. #define PI6 0x0040
  3097. #define PI7 0x0080
  3098. #define PI8 0x0100
  3099. #define PI9 0x0200
  3100. #define PI10 0x0400
  3101. #define PI11 0x0800
  3102. #define PI12 0x1000
  3103. #define PI13 0x2000
  3104. #define PI14 0x4000
  3105. #define PI15 0x8000
  3106. /* PORT J Bit Definitions for the registers
  3107. PORTJ, PORTJ_SET, PORTJ_CLEAR,
  3108. PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN,
  3109. PORTJ_FER registers
  3110. */
  3111. #define PJ0 0x0001
  3112. #define PJ1 0x0002
  3113. #define PJ2 0x0004
  3114. #define PJ3 0x0008
  3115. #define PJ4 0x0010
  3116. #define PJ5 0x0020
  3117. #define PJ6 0x0040
  3118. #define PJ7 0x0080
  3119. #define PJ8 0x0100
  3120. #define PJ9 0x0200
  3121. #define PJ10 0x0400
  3122. #define PJ11 0x0800
  3123. #define PJ12 0x1000
  3124. #define PJ13 0x2000
  3125. /* Port Muxing Bit Fields for PORTx_MUX Registers */
  3126. #define MUX0 0x00000003
  3127. #define MUX0_0 0x00000000
  3128. #define MUX0_1 0x00000001
  3129. #define MUX0_2 0x00000002
  3130. #define MUX0_3 0x00000003
  3131. #define MUX1 0x0000000C
  3132. #define MUX1_0 0x00000000
  3133. #define MUX1_1 0x00000004
  3134. #define MUX1_2 0x00000008
  3135. #define MUX1_3 0x0000000C
  3136. #define MUX2 0x00000030
  3137. #define MUX2_0 0x00000000
  3138. #define MUX2_1 0x00000010
  3139. #define MUX2_2 0x00000020
  3140. #define MUX2_3 0x00000030
  3141. #define MUX3 0x000000C0
  3142. #define MUX3_0 0x00000000
  3143. #define MUX3_1 0x00000040
  3144. #define MUX3_2 0x00000080
  3145. #define MUX3_3 0x000000C0
  3146. #define MUX4 0x00000300
  3147. #define MUX4_0 0x00000000
  3148. #define MUX4_1 0x00000100
  3149. #define MUX4_2 0x00000200
  3150. #define MUX4_3 0x00000300
  3151. #define MUX5 0x00000C00
  3152. #define MUX5_0 0x00000000
  3153. #define MUX5_1 0x00000400
  3154. #define MUX5_2 0x00000800
  3155. #define MUX5_3 0x00000C00
  3156. #define MUX6 0x00003000
  3157. #define MUX6_0 0x00000000
  3158. #define MUX6_1 0x00001000
  3159. #define MUX6_2 0x00002000
  3160. #define MUX6_3 0x00003000
  3161. #define MUX7 0x0000C000
  3162. #define MUX7_0 0x00000000
  3163. #define MUX7_1 0x00004000
  3164. #define MUX7_2 0x00008000
  3165. #define MUX7_3 0x0000C000
  3166. #define MUX8 0x00030000
  3167. #define MUX8_0 0x00000000
  3168. #define MUX8_1 0x00010000
  3169. #define MUX8_2 0x00020000
  3170. #define MUX8_3 0x00030000
  3171. #define MUX9 0x000C0000
  3172. #define MUX9_0 0x00000000
  3173. #define MUX9_1 0x00040000
  3174. #define MUX9_2 0x00080000
  3175. #define MUX9_3 0x000C0000
  3176. #define MUX10 0x00300000
  3177. #define MUX10_0 0x00000000
  3178. #define MUX10_1 0x00100000
  3179. #define MUX10_2 0x00200000
  3180. #define MUX10_3 0x00300000
  3181. #define MUX11 0x00C00000
  3182. #define MUX11_0 0x00000000
  3183. #define MUX11_1 0x00400000
  3184. #define MUX11_2 0x00800000
  3185. #define MUX11_3 0x00C00000
  3186. #define MUX12 0x03000000
  3187. #define MUX12_0 0x00000000
  3188. #define MUX12_1 0x01000000
  3189. #define MUX12_2 0x02000000
  3190. #define MUX12_3 0x03000000
  3191. #define MUX13 0x0C000000
  3192. #define MUX13_0 0x00000000
  3193. #define MUX13_1 0x04000000
  3194. #define MUX13_2 0x08000000
  3195. #define MUX13_3 0x0C000000
  3196. #define MUX14 0x30000000
  3197. #define MUX14_0 0x00000000
  3198. #define MUX14_1 0x10000000
  3199. #define MUX14_2 0x20000000
  3200. #define MUX14_3 0x30000000
  3201. #define MUX15 0xC0000000
  3202. #define MUX15_0 0x00000000
  3203. #define MUX15_1 0x40000000
  3204. #define MUX15_2 0x80000000
  3205. #define MUX15_3 0xC0000000
  3206. #define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \
  3207. ((((b15)&3) << 30) | \
  3208. (((b14)&3) << 28) | \
  3209. (((b13)&3) << 26) | \
  3210. (((b12)&3) << 24) | \
  3211. (((b11)&3) << 22) | \
  3212. (((b10)&3) << 20) | \
  3213. (((b9) &3) << 18) | \
  3214. (((b8) &3) << 16) | \
  3215. (((b7) &3) << 14) | \
  3216. (((b6) &3) << 12) | \
  3217. (((b5) &3) << 10) | \
  3218. (((b4) &3) << 8) | \
  3219. (((b3) &3) << 6) | \
  3220. (((b2) &3) << 4) | \
  3221. (((b1) &3) << 2) | \
  3222. (((b0) &3)))
  3223. /* Bit fields for PINT0_ASSIGN and PINT1_ASSIGN registers */
  3224. #define B0MAP 0x000000FF /* Byte 0 Lower Half Port Mapping */
  3225. #define B0MAP_PAL 0x00000000 /* Map Port A Low to Byte 0 */
  3226. #define B0MAP_PBL 0x00000001 /* Map Port B Low to Byte 0 */
  3227. #define B1MAP 0x0000FF00 /* Byte 1 Upper Half Port Mapping */
  3228. #define B1MAP_PAH 0x00000000 /* Map Port A High to Byte 1 */
  3229. #define B1MAP_PBH 0x00000100 /* Map Port B High to Byte 1 */
  3230. #define B2MAP 0x00FF0000 /* Byte 2 Lower Half Port Mapping */
  3231. #define B2MAP_PAL 0x00000000 /* Map Port A Low to Byte 2 */
  3232. #define B2MAP_PBL 0x00010000 /* Map Port B Low to Byte 2 */
  3233. #define B3MAP 0xFF000000 /* Byte 3 Upper Half Port Mapping */
  3234. #define B3MAP_PAH 0x00000000 /* Map Port A High to Byte 3 */
  3235. #define B3MAP_PBH 0x01000000 /* Map Port B High to Byte 3 */
  3236. /* Bit fields for PINT2_ASSIGN and PINT3_ASSIGN registers */
  3237. #define B0MAP_PCL 0x00000000 /* Map Port C Low to Byte 0 */
  3238. #define B0MAP_PDL 0x00000001 /* Map Port D Low to Byte 0 */
  3239. #define B0MAP_PEL 0x00000002 /* Map Port E Low to Byte 0 */
  3240. #define B0MAP_PFL 0x00000003 /* Map Port F Low to Byte 0 */
  3241. #define B0MAP_PGL 0x00000004 /* Map Port G Low to Byte 0 */
  3242. #define B0MAP_PHL 0x00000005 /* Map Port H Low to Byte 0 */
  3243. #define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */
  3244. #define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */
  3245. #define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */
  3246. #define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */
  3247. #define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */
  3248. #define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */
  3249. #define B1MAP_PGH 0x00000400 /* Map Port G High to Byte 1 */
  3250. #define B1MAP_PHH 0x00000500 /* Map Port H High to Byte 1 */
  3251. #define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */
  3252. #define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */
  3253. #define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */
  3254. #define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */
  3255. #define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */
  3256. #define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */
  3257. #define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */
  3258. #define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */
  3259. #define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */
  3260. #define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */
  3261. #define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */
  3262. #define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */
  3263. #define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */
  3264. #define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */
  3265. #define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */
  3266. #define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */
  3267. #define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */
  3268. #define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */
  3269. /* for legacy compatibility */
  3270. #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
  3271. #define W1LMAX_MAX W1LMAX_MIN
  3272. #define EBIU_AMCBCTL0 EBIU_AMBCTL0
  3273. #define EBIU_AMCBCTL1 EBIU_AMBCTL1
  3274. #define PINT0_IRQ PINT0_REQUEST
  3275. #define PINT1_IRQ PINT1_REQUEST
  3276. #define PINT2_IRQ PINT2_REQUEST
  3277. #define PINT3_IRQ PINT3_REQUEST
  3278. #endif /* _DEF_BF54X_H */