s3c2410_udc.c 48 KB

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  1. /*
  2. * linux/drivers/usb/gadget/s3c2410_udc.c
  3. *
  4. * Samsung S3C24xx series on-chip full speed USB device controllers
  5. *
  6. * Copyright (C) 2004-2007 Herbert Pötzl - Arnaud Patard
  7. * Additional cleanups by Ben Dooks <ben-linux@fluff.org>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. *
  23. */
  24. #include <linux/module.h>
  25. #include <linux/kernel.h>
  26. #include <linux/delay.h>
  27. #include <linux/ioport.h>
  28. #include <linux/sched.h>
  29. #include <linux/slab.h>
  30. #include <linux/smp_lock.h>
  31. #include <linux/errno.h>
  32. #include <linux/init.h>
  33. #include <linux/timer.h>
  34. #include <linux/list.h>
  35. #include <linux/interrupt.h>
  36. #include <linux/platform_device.h>
  37. #include <linux/version.h>
  38. #include <linux/clk.h>
  39. #include <linux/debugfs.h>
  40. #include <linux/seq_file.h>
  41. #include <linux/usb.h>
  42. #include <linux/usb/gadget.h>
  43. #include <asm/byteorder.h>
  44. #include <asm/io.h>
  45. #include <asm/irq.h>
  46. #include <asm/system.h>
  47. #include <asm/unaligned.h>
  48. #include <asm/arch/irqs.h>
  49. #include <asm/arch/hardware.h>
  50. #include <asm/arch/regs-gpio.h>
  51. #include <asm/plat-s3c24xx/regs-udc.h>
  52. #include <asm/plat-s3c24xx/udc.h>
  53. #include <asm/mach-types.h>
  54. #include "s3c2410_udc.h"
  55. #define DRIVER_DESC "S3C2410 USB Device Controller Gadget"
  56. #define DRIVER_VERSION "29 Apr 2007"
  57. #define DRIVER_AUTHOR "Herbert Pötzl <herbert@13thfloor.at>, " \
  58. "Arnaud Patard <arnaud.patard@rtp-net.org>"
  59. static const char gadget_name[] = "s3c2410_udc";
  60. static const char driver_desc[] = DRIVER_DESC;
  61. static struct s3c2410_udc *the_controller;
  62. static struct clk *udc_clock;
  63. static struct clk *usb_bus_clock;
  64. static void __iomem *base_addr;
  65. static u64 rsrc_start;
  66. static u64 rsrc_len;
  67. static struct dentry *s3c2410_udc_debugfs_root;
  68. static inline u32 udc_read(u32 reg)
  69. {
  70. return readb(base_addr + reg);
  71. }
  72. static inline void udc_write(u32 value, u32 reg)
  73. {
  74. writeb(value, base_addr + reg);
  75. }
  76. static inline void udc_writeb(void __iomem *base, u32 value, u32 reg)
  77. {
  78. writeb(value, base + reg);
  79. }
  80. static struct s3c2410_udc_mach_info *udc_info;
  81. /*************************** DEBUG FUNCTION ***************************/
  82. #define DEBUG_NORMAL 1
  83. #define DEBUG_VERBOSE 2
  84. #ifdef CONFIG_USB_S3C2410_DEBUG
  85. #define USB_S3C2410_DEBUG_LEVEL 0
  86. static uint32_t s3c2410_ticks = 0;
  87. static int dprintk(int level, const char *fmt, ...)
  88. {
  89. static char printk_buf[1024];
  90. static long prevticks;
  91. static int invocation;
  92. va_list args;
  93. int len;
  94. if (level > USB_S3C2410_DEBUG_LEVEL)
  95. return 0;
  96. if (s3c2410_ticks != prevticks) {
  97. prevticks = s3c2410_ticks;
  98. invocation = 0;
  99. }
  100. len = scnprintf(printk_buf,
  101. sizeof(printk_buf), "%1lu.%02d USB: ",
  102. prevticks, invocation++);
  103. va_start(args, fmt);
  104. len = vscnprintf(printk_buf+len,
  105. sizeof(printk_buf)-len, fmt, args);
  106. va_end(args);
  107. return printk(KERN_DEBUG "%s", printk_buf);
  108. }
  109. #else
  110. static int dprintk(int level, const char *fmt, ...)
  111. {
  112. return 0;
  113. }
  114. #endif
  115. static int s3c2410_udc_debugfs_seq_show(struct seq_file *m, void *p)
  116. {
  117. u32 addr_reg,pwr_reg,ep_int_reg,usb_int_reg;
  118. u32 ep_int_en_reg, usb_int_en_reg, ep0_csr;
  119. u32 ep1_i_csr1,ep1_i_csr2,ep1_o_csr1,ep1_o_csr2;
  120. u32 ep2_i_csr1,ep2_i_csr2,ep2_o_csr1,ep2_o_csr2;
  121. addr_reg = udc_read(S3C2410_UDC_FUNC_ADDR_REG);
  122. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  123. ep_int_reg = udc_read(S3C2410_UDC_EP_INT_REG);
  124. usb_int_reg = udc_read(S3C2410_UDC_USB_INT_REG);
  125. ep_int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  126. usb_int_en_reg = udc_read(S3C2410_UDC_USB_INT_EN_REG);
  127. udc_write(0, S3C2410_UDC_INDEX_REG);
  128. ep0_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  129. udc_write(1, S3C2410_UDC_INDEX_REG);
  130. ep1_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  131. ep1_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  132. ep1_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  133. ep1_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  134. udc_write(2, S3C2410_UDC_INDEX_REG);
  135. ep2_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  136. ep2_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  137. ep2_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  138. ep2_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  139. seq_printf(m, "FUNC_ADDR_REG : 0x%04X\n"
  140. "PWR_REG : 0x%04X\n"
  141. "EP_INT_REG : 0x%04X\n"
  142. "USB_INT_REG : 0x%04X\n"
  143. "EP_INT_EN_REG : 0x%04X\n"
  144. "USB_INT_EN_REG : 0x%04X\n"
  145. "EP0_CSR : 0x%04X\n"
  146. "EP1_I_CSR1 : 0x%04X\n"
  147. "EP1_I_CSR2 : 0x%04X\n"
  148. "EP1_O_CSR1 : 0x%04X\n"
  149. "EP1_O_CSR2 : 0x%04X\n"
  150. "EP2_I_CSR1 : 0x%04X\n"
  151. "EP2_I_CSR2 : 0x%04X\n"
  152. "EP2_O_CSR1 : 0x%04X\n"
  153. "EP2_O_CSR2 : 0x%04X\n",
  154. addr_reg,pwr_reg,ep_int_reg,usb_int_reg,
  155. ep_int_en_reg, usb_int_en_reg, ep0_csr,
  156. ep1_i_csr1,ep1_i_csr2,ep1_o_csr1,ep1_o_csr2,
  157. ep2_i_csr1,ep2_i_csr2,ep2_o_csr1,ep2_o_csr2
  158. );
  159. return 0;
  160. }
  161. static int s3c2410_udc_debugfs_fops_open(struct inode *inode,
  162. struct file *file)
  163. {
  164. return single_open(file, s3c2410_udc_debugfs_seq_show, NULL);
  165. }
  166. static const struct file_operations s3c2410_udc_debugfs_fops = {
  167. .open = s3c2410_udc_debugfs_fops_open,
  168. .read = seq_read,
  169. .llseek = seq_lseek,
  170. .release = single_release,
  171. .owner = THIS_MODULE,
  172. };
  173. /* io macros */
  174. static inline void s3c2410_udc_clear_ep0_opr(void __iomem *base)
  175. {
  176. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  177. udc_writeb(base, S3C2410_UDC_EP0_CSR_SOPKTRDY,
  178. S3C2410_UDC_EP0_CSR_REG);
  179. }
  180. static inline void s3c2410_udc_clear_ep0_sst(void __iomem *base)
  181. {
  182. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  183. writeb(0x00, base + S3C2410_UDC_EP0_CSR_REG);
  184. }
  185. static inline void s3c2410_udc_clear_ep0_se(void __iomem *base)
  186. {
  187. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  188. udc_writeb(base, S3C2410_UDC_EP0_CSR_SSE, S3C2410_UDC_EP0_CSR_REG);
  189. }
  190. static inline void s3c2410_udc_set_ep0_ipr(void __iomem *base)
  191. {
  192. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  193. udc_writeb(base, S3C2410_UDC_EP0_CSR_IPKRDY, S3C2410_UDC_EP0_CSR_REG);
  194. }
  195. static inline void s3c2410_udc_set_ep0_de(void __iomem *base)
  196. {
  197. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  198. udc_writeb(base, S3C2410_UDC_EP0_CSR_DE, S3C2410_UDC_EP0_CSR_REG);
  199. }
  200. inline void s3c2410_udc_set_ep0_ss(void __iomem *b)
  201. {
  202. udc_writeb(b, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  203. udc_writeb(b, S3C2410_UDC_EP0_CSR_SENDSTL, S3C2410_UDC_EP0_CSR_REG);
  204. }
  205. static inline void s3c2410_udc_set_ep0_de_out(void __iomem *base)
  206. {
  207. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  208. udc_writeb(base,(S3C2410_UDC_EP0_CSR_SOPKTRDY
  209. | S3C2410_UDC_EP0_CSR_DE),
  210. S3C2410_UDC_EP0_CSR_REG);
  211. }
  212. static inline void s3c2410_udc_set_ep0_sse_out(void __iomem *base)
  213. {
  214. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  215. udc_writeb(base, (S3C2410_UDC_EP0_CSR_SOPKTRDY
  216. | S3C2410_UDC_EP0_CSR_SSE),
  217. S3C2410_UDC_EP0_CSR_REG);
  218. }
  219. static inline void s3c2410_udc_set_ep0_de_in(void __iomem *base)
  220. {
  221. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  222. udc_writeb(base, (S3C2410_UDC_EP0_CSR_IPKRDY
  223. | S3C2410_UDC_EP0_CSR_DE),
  224. S3C2410_UDC_EP0_CSR_REG);
  225. }
  226. /*------------------------- I/O ----------------------------------*/
  227. /*
  228. * s3c2410_udc_done
  229. */
  230. static void s3c2410_udc_done(struct s3c2410_ep *ep,
  231. struct s3c2410_request *req, int status)
  232. {
  233. unsigned halted = ep->halted;
  234. list_del_init(&req->queue);
  235. if (likely (req->req.status == -EINPROGRESS))
  236. req->req.status = status;
  237. else
  238. status = req->req.status;
  239. ep->halted = 1;
  240. req->req.complete(&ep->ep, &req->req);
  241. ep->halted = halted;
  242. }
  243. static void s3c2410_udc_nuke(struct s3c2410_udc *udc,
  244. struct s3c2410_ep *ep, int status)
  245. {
  246. /* Sanity check */
  247. if (&ep->queue == NULL)
  248. return;
  249. while (!list_empty (&ep->queue)) {
  250. struct s3c2410_request *req;
  251. req = list_entry (ep->queue.next, struct s3c2410_request,
  252. queue);
  253. s3c2410_udc_done(ep, req, status);
  254. }
  255. }
  256. static inline void s3c2410_udc_clear_ep_state(struct s3c2410_udc *dev)
  257. {
  258. unsigned i;
  259. /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
  260. * fifos, and pending transactions mustn't be continued in any case.
  261. */
  262. for (i = 1; i < S3C2410_ENDPOINTS; i++)
  263. s3c2410_udc_nuke(dev, &dev->ep[i], -ECONNABORTED);
  264. }
  265. static inline int s3c2410_udc_fifo_count_out(void)
  266. {
  267. int tmp;
  268. tmp = udc_read(S3C2410_UDC_OUT_FIFO_CNT2_REG) << 8;
  269. tmp |= udc_read(S3C2410_UDC_OUT_FIFO_CNT1_REG);
  270. return tmp;
  271. }
  272. /*
  273. * s3c2410_udc_write_packet
  274. */
  275. static inline int s3c2410_udc_write_packet(int fifo,
  276. struct s3c2410_request *req,
  277. unsigned max)
  278. {
  279. unsigned len = min(req->req.length - req->req.actual, max);
  280. u8 *buf = req->req.buf + req->req.actual;
  281. prefetch(buf);
  282. dprintk(DEBUG_VERBOSE, "%s %d %d %d %d\n", __func__,
  283. req->req.actual, req->req.length, len, req->req.actual + len);
  284. req->req.actual += len;
  285. udelay(5);
  286. writesb(base_addr + fifo, buf, len);
  287. return len;
  288. }
  289. /*
  290. * s3c2410_udc_write_fifo
  291. *
  292. * return: 0 = still running, 1 = completed, negative = errno
  293. */
  294. static int s3c2410_udc_write_fifo(struct s3c2410_ep *ep,
  295. struct s3c2410_request *req)
  296. {
  297. unsigned count;
  298. int is_last;
  299. u32 idx;
  300. int fifo_reg;
  301. u32 ep_csr;
  302. idx = ep->bEndpointAddress & 0x7F;
  303. switch (idx) {
  304. default:
  305. idx = 0;
  306. case 0:
  307. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  308. break;
  309. case 1:
  310. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  311. break;
  312. case 2:
  313. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  314. break;
  315. case 3:
  316. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  317. break;
  318. case 4:
  319. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  320. break;
  321. }
  322. count = s3c2410_udc_write_packet(fifo_reg, req, ep->ep.maxpacket);
  323. /* last packet is often short (sometimes a zlp) */
  324. if (count != ep->ep.maxpacket)
  325. is_last = 1;
  326. else if (req->req.length != req->req.actual || req->req.zero)
  327. is_last = 0;
  328. else
  329. is_last = 2;
  330. /* Only ep0 debug messages are interesting */
  331. if (idx == 0)
  332. dprintk(DEBUG_NORMAL,
  333. "Written ep%d %d.%d of %d b [last %d,z %d]\n",
  334. idx, count, req->req.actual, req->req.length,
  335. is_last, req->req.zero);
  336. if (is_last) {
  337. /* The order is important. It prevents sending 2 packets
  338. * at the same time */
  339. if (idx == 0) {
  340. /* Reset signal => no need to say 'data sent' */
  341. if (! (udc_read(S3C2410_UDC_USB_INT_REG)
  342. & S3C2410_UDC_USBINT_RESET))
  343. s3c2410_udc_set_ep0_de_in(base_addr);
  344. ep->dev->ep0state=EP0_IDLE;
  345. } else {
  346. udc_write(idx, S3C2410_UDC_INDEX_REG);
  347. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  348. udc_write(idx, S3C2410_UDC_INDEX_REG);
  349. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  350. S3C2410_UDC_IN_CSR1_REG);
  351. }
  352. s3c2410_udc_done(ep, req, 0);
  353. is_last = 1;
  354. } else {
  355. if (idx == 0) {
  356. /* Reset signal => no need to say 'data sent' */
  357. if (! (udc_read(S3C2410_UDC_USB_INT_REG)
  358. & S3C2410_UDC_USBINT_RESET))
  359. s3c2410_udc_set_ep0_ipr(base_addr);
  360. } else {
  361. udc_write(idx, S3C2410_UDC_INDEX_REG);
  362. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  363. udc_write(idx, S3C2410_UDC_INDEX_REG);
  364. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  365. S3C2410_UDC_IN_CSR1_REG);
  366. }
  367. }
  368. return is_last;
  369. }
  370. static inline int s3c2410_udc_read_packet(int fifo, u8 *buf,
  371. struct s3c2410_request *req, unsigned avail)
  372. {
  373. unsigned len;
  374. len = min(req->req.length - req->req.actual, avail);
  375. req->req.actual += len;
  376. readsb(fifo + base_addr, buf, len);
  377. return len;
  378. }
  379. /*
  380. * return: 0 = still running, 1 = queue empty, negative = errno
  381. */
  382. static int s3c2410_udc_read_fifo(struct s3c2410_ep *ep,
  383. struct s3c2410_request *req)
  384. {
  385. u8 *buf;
  386. u32 ep_csr;
  387. unsigned bufferspace;
  388. int is_last=1;
  389. unsigned avail;
  390. int fifo_count = 0;
  391. u32 idx;
  392. int fifo_reg;
  393. idx = ep->bEndpointAddress & 0x7F;
  394. switch (idx) {
  395. default:
  396. idx = 0;
  397. case 0:
  398. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  399. break;
  400. case 1:
  401. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  402. break;
  403. case 2:
  404. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  405. break;
  406. case 3:
  407. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  408. break;
  409. case 4:
  410. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  411. break;
  412. }
  413. if (!req->req.length)
  414. return 1;
  415. buf = req->req.buf + req->req.actual;
  416. bufferspace = req->req.length - req->req.actual;
  417. if (!bufferspace) {
  418. dprintk(DEBUG_NORMAL, "%s: buffer full!\n", __func__);
  419. return -1;
  420. }
  421. udc_write(idx, S3C2410_UDC_INDEX_REG);
  422. fifo_count = s3c2410_udc_fifo_count_out();
  423. dprintk(DEBUG_NORMAL, "%s fifo count : %d\n", __func__, fifo_count);
  424. if (fifo_count > ep->ep.maxpacket)
  425. avail = ep->ep.maxpacket;
  426. else
  427. avail = fifo_count;
  428. fifo_count = s3c2410_udc_read_packet(fifo_reg, buf, req, avail);
  429. /* checking this with ep0 is not accurate as we already
  430. * read a control request
  431. **/
  432. if (idx != 0 && fifo_count < ep->ep.maxpacket) {
  433. is_last = 1;
  434. /* overflowed this request? flush extra data */
  435. if (fifo_count != avail)
  436. req->req.status = -EOVERFLOW;
  437. } else {
  438. is_last = (req->req.length <= req->req.actual) ? 1 : 0;
  439. }
  440. udc_write(idx, S3C2410_UDC_INDEX_REG);
  441. fifo_count = s3c2410_udc_fifo_count_out();
  442. /* Only ep0 debug messages are interesting */
  443. if (idx == 0)
  444. dprintk(DEBUG_VERBOSE, "%s fifo count : %d [last %d]\n",
  445. __func__, fifo_count,is_last);
  446. if (is_last) {
  447. if (idx == 0) {
  448. s3c2410_udc_set_ep0_de_out(base_addr);
  449. ep->dev->ep0state = EP0_IDLE;
  450. } else {
  451. udc_write(idx, S3C2410_UDC_INDEX_REG);
  452. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  453. udc_write(idx, S3C2410_UDC_INDEX_REG);
  454. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  455. S3C2410_UDC_OUT_CSR1_REG);
  456. }
  457. s3c2410_udc_done(ep, req, 0);
  458. } else {
  459. if (idx == 0) {
  460. s3c2410_udc_clear_ep0_opr(base_addr);
  461. } else {
  462. udc_write(idx, S3C2410_UDC_INDEX_REG);
  463. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  464. udc_write(idx, S3C2410_UDC_INDEX_REG);
  465. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  466. S3C2410_UDC_OUT_CSR1_REG);
  467. }
  468. }
  469. return is_last;
  470. }
  471. static int s3c2410_udc_read_fifo_crq(struct usb_ctrlrequest *crq)
  472. {
  473. unsigned char *outbuf = (unsigned char*)crq;
  474. int bytes_read = 0;
  475. udc_write(0, S3C2410_UDC_INDEX_REG);
  476. bytes_read = s3c2410_udc_fifo_count_out();
  477. dprintk(DEBUG_NORMAL, "%s: fifo_count=%d\n", __func__, bytes_read);
  478. if (bytes_read > sizeof(struct usb_ctrlrequest))
  479. bytes_read = sizeof(struct usb_ctrlrequest);
  480. readsb(S3C2410_UDC_EP0_FIFO_REG + base_addr, outbuf, bytes_read);
  481. dprintk(DEBUG_VERBOSE, "%s: len=%d %02x:%02x {%x,%x,%x}\n", __func__,
  482. bytes_read, crq->bRequest, crq->bRequestType,
  483. crq->wValue, crq->wIndex, crq->wLength);
  484. return bytes_read;
  485. }
  486. static int s3c2410_udc_get_status(struct s3c2410_udc *dev,
  487. struct usb_ctrlrequest *crq)
  488. {
  489. u16 status = 0;
  490. u8 ep_num = crq->wIndex & 0x7F;
  491. u8 is_in = crq->wIndex & USB_DIR_IN;
  492. switch (crq->bRequestType & USB_RECIP_MASK) {
  493. case USB_RECIP_INTERFACE:
  494. break;
  495. case USB_RECIP_DEVICE:
  496. status = dev->devstatus;
  497. break;
  498. case USB_RECIP_ENDPOINT:
  499. if (ep_num > 4 || crq->wLength > 2)
  500. return 1;
  501. if (ep_num == 0) {
  502. udc_write(0, S3C2410_UDC_INDEX_REG);
  503. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  504. status = status & S3C2410_UDC_EP0_CSR_SENDSTL;
  505. } else {
  506. udc_write(ep_num, S3C2410_UDC_INDEX_REG);
  507. if (is_in) {
  508. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  509. status = status & S3C2410_UDC_ICSR1_SENDSTL;
  510. } else {
  511. status = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  512. status = status & S3C2410_UDC_OCSR1_SENDSTL;
  513. }
  514. }
  515. status = status ? 1 : 0;
  516. break;
  517. default:
  518. return 1;
  519. }
  520. /* Seems to be needed to get it working. ouch :( */
  521. udelay(5);
  522. udc_write(status & 0xFF, S3C2410_UDC_EP0_FIFO_REG);
  523. udc_write(status >> 8, S3C2410_UDC_EP0_FIFO_REG);
  524. s3c2410_udc_set_ep0_de_in(base_addr);
  525. return 0;
  526. }
  527. /*------------------------- usb state machine -------------------------------*/
  528. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value);
  529. static void s3c2410_udc_handle_ep0_idle(struct s3c2410_udc *dev,
  530. struct s3c2410_ep *ep,
  531. struct usb_ctrlrequest *crq,
  532. u32 ep0csr)
  533. {
  534. int len, ret, tmp;
  535. /* start control request? */
  536. if (!(ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY))
  537. return;
  538. s3c2410_udc_nuke(dev, ep, -EPROTO);
  539. len = s3c2410_udc_read_fifo_crq(crq);
  540. if (len != sizeof(*crq)) {
  541. dprintk(DEBUG_NORMAL, "setup begin: fifo READ ERROR"
  542. " wanted %d bytes got %d. Stalling out...\n",
  543. sizeof(*crq), len);
  544. s3c2410_udc_set_ep0_ss(base_addr);
  545. return;
  546. }
  547. dprintk(DEBUG_NORMAL, "bRequest = %d bRequestType %d wLength = %d\n",
  548. crq->bRequest, crq->bRequestType, crq->wLength);
  549. /* cope with automagic for some standard requests. */
  550. dev->req_std = (crq->bRequestType & USB_TYPE_MASK)
  551. == USB_TYPE_STANDARD;
  552. dev->req_config = 0;
  553. dev->req_pending = 1;
  554. switch (crq->bRequest) {
  555. case USB_REQ_SET_CONFIGURATION:
  556. dprintk(DEBUG_NORMAL, "USB_REQ_SET_CONFIGURATION ... \n");
  557. if (crq->bRequestType == USB_RECIP_DEVICE) {
  558. dev->req_config = 1;
  559. s3c2410_udc_set_ep0_de_out(base_addr);
  560. }
  561. break;
  562. case USB_REQ_SET_INTERFACE:
  563. dprintk(DEBUG_NORMAL, "USB_REQ_SET_INTERFACE ... \n");
  564. if (crq->bRequestType == USB_RECIP_INTERFACE) {
  565. dev->req_config = 1;
  566. s3c2410_udc_set_ep0_de_out(base_addr);
  567. }
  568. break;
  569. case USB_REQ_SET_ADDRESS:
  570. dprintk(DEBUG_NORMAL, "USB_REQ_SET_ADDRESS ... \n");
  571. if (crq->bRequestType == USB_RECIP_DEVICE) {
  572. tmp = crq->wValue & 0x7F;
  573. dev->address = tmp;
  574. udc_write((tmp | S3C2410_UDC_FUNCADDR_UPDATE),
  575. S3C2410_UDC_FUNC_ADDR_REG);
  576. s3c2410_udc_set_ep0_de_out(base_addr);
  577. return;
  578. }
  579. break;
  580. case USB_REQ_GET_STATUS:
  581. dprintk(DEBUG_NORMAL, "USB_REQ_GET_STATUS ... \n");
  582. s3c2410_udc_clear_ep0_opr(base_addr);
  583. if (dev->req_std) {
  584. if (!s3c2410_udc_get_status(dev, crq)) {
  585. return;
  586. }
  587. }
  588. break;
  589. case USB_REQ_CLEAR_FEATURE:
  590. s3c2410_udc_clear_ep0_opr(base_addr);
  591. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  592. break;
  593. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  594. break;
  595. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 0);
  596. s3c2410_udc_set_ep0_de_out(base_addr);
  597. return;
  598. case USB_REQ_SET_FEATURE:
  599. s3c2410_udc_clear_ep0_opr(base_addr);
  600. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  601. break;
  602. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  603. break;
  604. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 1);
  605. s3c2410_udc_set_ep0_de_out(base_addr);
  606. return;
  607. default:
  608. s3c2410_udc_clear_ep0_opr(base_addr);
  609. break;
  610. }
  611. if (crq->bRequestType & USB_DIR_IN)
  612. dev->ep0state = EP0_IN_DATA_PHASE;
  613. else
  614. dev->ep0state = EP0_OUT_DATA_PHASE;
  615. ret = dev->driver->setup(&dev->gadget, crq);
  616. if (ret < 0) {
  617. if (dev->req_config) {
  618. dprintk(DEBUG_NORMAL, "config change %02x fail %d?\n",
  619. crq->bRequest, ret);
  620. return;
  621. }
  622. if (ret == -EOPNOTSUPP)
  623. dprintk(DEBUG_NORMAL, "Operation not supported\n");
  624. else
  625. dprintk(DEBUG_NORMAL,
  626. "dev->driver->setup failed. (%d)\n", ret);
  627. udelay(5);
  628. s3c2410_udc_set_ep0_ss(base_addr);
  629. s3c2410_udc_set_ep0_de_out(base_addr);
  630. dev->ep0state = EP0_IDLE;
  631. /* deferred i/o == no response yet */
  632. } else if (dev->req_pending) {
  633. dprintk(DEBUG_VERBOSE, "dev->req_pending... what now?\n");
  634. dev->req_pending=0;
  635. }
  636. dprintk(DEBUG_VERBOSE, "ep0state %s\n", ep0states[dev->ep0state]);
  637. }
  638. static void s3c2410_udc_handle_ep0(struct s3c2410_udc *dev)
  639. {
  640. u32 ep0csr;
  641. struct s3c2410_ep *ep = &dev->ep[0];
  642. struct s3c2410_request *req;
  643. struct usb_ctrlrequest crq;
  644. if (list_empty(&ep->queue))
  645. req = NULL;
  646. else
  647. req = list_entry(ep->queue.next, struct s3c2410_request, queue);
  648. /* We make the assumption that S3C2410_UDC_IN_CSR1_REG equal to
  649. * S3C2410_UDC_EP0_CSR_REG when index is zero */
  650. udc_write(0, S3C2410_UDC_INDEX_REG);
  651. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  652. dprintk(DEBUG_NORMAL, "ep0csr %x ep0state %s\n",
  653. ep0csr, ep0states[dev->ep0state]);
  654. /* clear stall status */
  655. if (ep0csr & S3C2410_UDC_EP0_CSR_SENTSTL) {
  656. s3c2410_udc_nuke(dev, ep, -EPIPE);
  657. dprintk(DEBUG_NORMAL, "... clear SENT_STALL ...\n");
  658. s3c2410_udc_clear_ep0_sst(base_addr);
  659. dev->ep0state = EP0_IDLE;
  660. return;
  661. }
  662. /* clear setup end */
  663. if (ep0csr & S3C2410_UDC_EP0_CSR_SE) {
  664. dprintk(DEBUG_NORMAL, "... serviced SETUP_END ...\n");
  665. s3c2410_udc_nuke(dev, ep, 0);
  666. s3c2410_udc_clear_ep0_se(base_addr);
  667. dev->ep0state = EP0_IDLE;
  668. }
  669. switch (dev->ep0state) {
  670. case EP0_IDLE:
  671. s3c2410_udc_handle_ep0_idle(dev, ep, &crq, ep0csr);
  672. break;
  673. case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
  674. dprintk(DEBUG_NORMAL, "EP0_IN_DATA_PHASE ... what now?\n");
  675. if (!(ep0csr & S3C2410_UDC_EP0_CSR_IPKRDY) && req) {
  676. s3c2410_udc_write_fifo(ep, req);
  677. }
  678. break;
  679. case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
  680. dprintk(DEBUG_NORMAL, "EP0_OUT_DATA_PHASE ... what now?\n");
  681. if ((ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY) && req ) {
  682. s3c2410_udc_read_fifo(ep,req);
  683. }
  684. break;
  685. case EP0_END_XFER:
  686. dprintk(DEBUG_NORMAL, "EP0_END_XFER ... what now?\n");
  687. dev->ep0state = EP0_IDLE;
  688. break;
  689. case EP0_STALL:
  690. dprintk(DEBUG_NORMAL, "EP0_STALL ... what now?\n");
  691. dev->ep0state = EP0_IDLE;
  692. break;
  693. }
  694. }
  695. /*
  696. * handle_ep - Manage I/O endpoints
  697. */
  698. static void s3c2410_udc_handle_ep(struct s3c2410_ep *ep)
  699. {
  700. struct s3c2410_request *req;
  701. int is_in = ep->bEndpointAddress & USB_DIR_IN;
  702. u32 ep_csr1;
  703. u32 idx;
  704. if (likely (!list_empty(&ep->queue)))
  705. req = list_entry(ep->queue.next,
  706. struct s3c2410_request, queue);
  707. else
  708. req = NULL;
  709. idx = ep->bEndpointAddress & 0x7F;
  710. if (is_in) {
  711. udc_write(idx, S3C2410_UDC_INDEX_REG);
  712. ep_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  713. dprintk(DEBUG_VERBOSE, "ep%01d write csr:%02x %d\n",
  714. idx, ep_csr1, req ? 1 : 0);
  715. if (ep_csr1 & S3C2410_UDC_ICSR1_SENTSTL) {
  716. dprintk(DEBUG_VERBOSE, "st\n");
  717. udc_write(idx, S3C2410_UDC_INDEX_REG);
  718. udc_write(ep_csr1 & ~S3C2410_UDC_ICSR1_SENTSTL,
  719. S3C2410_UDC_IN_CSR1_REG);
  720. return;
  721. }
  722. if (!(ep_csr1 & S3C2410_UDC_ICSR1_PKTRDY) && req) {
  723. s3c2410_udc_write_fifo(ep,req);
  724. }
  725. } else {
  726. udc_write(idx, S3C2410_UDC_INDEX_REG);
  727. ep_csr1 = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  728. dprintk(DEBUG_VERBOSE, "ep%01d rd csr:%02x\n", idx, ep_csr1);
  729. if (ep_csr1 & S3C2410_UDC_OCSR1_SENTSTL) {
  730. udc_write(idx, S3C2410_UDC_INDEX_REG);
  731. udc_write(ep_csr1 & ~S3C2410_UDC_OCSR1_SENTSTL,
  732. S3C2410_UDC_OUT_CSR1_REG);
  733. return;
  734. }
  735. if ((ep_csr1 & S3C2410_UDC_OCSR1_PKTRDY) && req) {
  736. s3c2410_udc_read_fifo(ep,req);
  737. }
  738. }
  739. }
  740. #include <asm/arch/regs-irq.h>
  741. /*
  742. * s3c2410_udc_irq - interrupt handler
  743. */
  744. static irqreturn_t s3c2410_udc_irq(int irq, void *_dev)
  745. {
  746. struct s3c2410_udc *dev = _dev;
  747. int usb_status;
  748. int usbd_status;
  749. int pwr_reg;
  750. int ep0csr;
  751. int i;
  752. u32 idx;
  753. unsigned long flags;
  754. spin_lock_irqsave(&dev->lock, flags);
  755. /* Driver connected ? */
  756. if (!dev->driver) {
  757. /* Clear interrupts */
  758. udc_write(udc_read(S3C2410_UDC_USB_INT_REG),
  759. S3C2410_UDC_USB_INT_REG);
  760. udc_write(udc_read(S3C2410_UDC_EP_INT_REG),
  761. S3C2410_UDC_EP_INT_REG);
  762. }
  763. /* Save index */
  764. idx = udc_read(S3C2410_UDC_INDEX_REG);
  765. /* Read status registers */
  766. usb_status = udc_read(S3C2410_UDC_USB_INT_REG);
  767. usbd_status = udc_read(S3C2410_UDC_EP_INT_REG);
  768. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  769. udc_writeb(base_addr, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  770. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  771. dprintk(DEBUG_NORMAL, "usbs=%02x, usbds=%02x, pwr=%02x ep0csr=%02x\n",
  772. usb_status, usbd_status, pwr_reg, ep0csr);
  773. /*
  774. * Now, handle interrupts. There's two types :
  775. * - Reset, Resume, Suspend coming -> usb_int_reg
  776. * - EP -> ep_int_reg
  777. */
  778. /* RESET */
  779. if (usb_status & S3C2410_UDC_USBINT_RESET) {
  780. /* two kind of reset :
  781. * - reset start -> pwr reg = 8
  782. * - reset end -> pwr reg = 0
  783. **/
  784. dprintk(DEBUG_NORMAL, "USB reset csr %x pwr %x\n",
  785. ep0csr, pwr_reg);
  786. dev->gadget.speed = USB_SPEED_UNKNOWN;
  787. udc_write(0x00, S3C2410_UDC_INDEX_REG);
  788. udc_write((dev->ep[0].ep.maxpacket & 0x7ff) >> 3,
  789. S3C2410_UDC_MAXP_REG);
  790. dev->address = 0;
  791. dev->ep0state = EP0_IDLE;
  792. dev->gadget.speed = USB_SPEED_FULL;
  793. /* clear interrupt */
  794. udc_write(S3C2410_UDC_USBINT_RESET,
  795. S3C2410_UDC_USB_INT_REG);
  796. udc_write(idx, S3C2410_UDC_INDEX_REG);
  797. spin_unlock_irqrestore(&dev->lock, flags);
  798. return IRQ_HANDLED;
  799. }
  800. /* RESUME */
  801. if (usb_status & S3C2410_UDC_USBINT_RESUME) {
  802. dprintk(DEBUG_NORMAL, "USB resume\n");
  803. /* clear interrupt */
  804. udc_write(S3C2410_UDC_USBINT_RESUME,
  805. S3C2410_UDC_USB_INT_REG);
  806. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  807. && dev->driver
  808. && dev->driver->resume)
  809. dev->driver->resume(&dev->gadget);
  810. }
  811. /* SUSPEND */
  812. if (usb_status & S3C2410_UDC_USBINT_SUSPEND) {
  813. dprintk(DEBUG_NORMAL, "USB suspend\n");
  814. /* clear interrupt */
  815. udc_write(S3C2410_UDC_USBINT_SUSPEND,
  816. S3C2410_UDC_USB_INT_REG);
  817. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  818. && dev->driver
  819. && dev->driver->suspend)
  820. dev->driver->suspend(&dev->gadget);
  821. dev->ep0state = EP0_IDLE;
  822. }
  823. /* EP */
  824. /* control traffic */
  825. /* check on ep0csr != 0 is not a good idea as clearing in_pkt_ready
  826. * generate an interrupt
  827. */
  828. if (usbd_status & S3C2410_UDC_INT_EP0) {
  829. dprintk(DEBUG_VERBOSE, "USB ep0 irq\n");
  830. /* Clear the interrupt bit by setting it to 1 */
  831. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_REG);
  832. s3c2410_udc_handle_ep0(dev);
  833. }
  834. /* endpoint data transfers */
  835. for (i = 1; i < S3C2410_ENDPOINTS; i++) {
  836. u32 tmp = 1 << i;
  837. if (usbd_status & tmp) {
  838. dprintk(DEBUG_VERBOSE, "USB ep%d irq\n", i);
  839. /* Clear the interrupt bit by setting it to 1 */
  840. udc_write(tmp, S3C2410_UDC_EP_INT_REG);
  841. s3c2410_udc_handle_ep(&dev->ep[i]);
  842. }
  843. }
  844. dprintk(DEBUG_VERBOSE, "irq: %d s3c2410_udc_done.\n", irq);
  845. /* Restore old index */
  846. udc_write(idx, S3C2410_UDC_INDEX_REG);
  847. spin_unlock_irqrestore(&dev->lock, flags);
  848. return IRQ_HANDLED;
  849. }
  850. /*------------------------- s3c2410_ep_ops ----------------------------------*/
  851. static inline struct s3c2410_ep *to_s3c2410_ep(struct usb_ep *ep)
  852. {
  853. return container_of(ep, struct s3c2410_ep, ep);
  854. }
  855. static inline struct s3c2410_udc *to_s3c2410_udc(struct usb_gadget *gadget)
  856. {
  857. return container_of(gadget, struct s3c2410_udc, gadget);
  858. }
  859. static inline struct s3c2410_request *to_s3c2410_req(struct usb_request *req)
  860. {
  861. return container_of(req, struct s3c2410_request, req);
  862. }
  863. /*
  864. * s3c2410_udc_ep_enable
  865. */
  866. static int s3c2410_udc_ep_enable(struct usb_ep *_ep,
  867. const struct usb_endpoint_descriptor *desc)
  868. {
  869. struct s3c2410_udc *dev;
  870. struct s3c2410_ep *ep;
  871. u32 max, tmp;
  872. unsigned long flags;
  873. u32 csr1,csr2;
  874. u32 int_en_reg;
  875. ep = to_s3c2410_ep(_ep);
  876. if (!_ep || !desc || ep->desc
  877. || _ep->name == ep0name
  878. || desc->bDescriptorType != USB_DT_ENDPOINT)
  879. return -EINVAL;
  880. dev = ep->dev;
  881. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  882. return -ESHUTDOWN;
  883. max = le16_to_cpu(desc->wMaxPacketSize) & 0x1fff;
  884. local_irq_save (flags);
  885. _ep->maxpacket = max & 0x7ff;
  886. ep->desc = desc;
  887. ep->halted = 0;
  888. ep->bEndpointAddress = desc->bEndpointAddress;
  889. /* set max packet */
  890. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  891. udc_write(max >> 3, S3C2410_UDC_MAXP_REG);
  892. /* set type, direction, address; reset fifo counters */
  893. if (desc->bEndpointAddress & USB_DIR_IN) {
  894. csr1 = S3C2410_UDC_ICSR1_FFLUSH|S3C2410_UDC_ICSR1_CLRDT;
  895. csr2 = S3C2410_UDC_ICSR2_MODEIN|S3C2410_UDC_ICSR2_DMAIEN;
  896. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  897. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  898. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  899. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  900. } else {
  901. /* don't flush in fifo or it will cause endpoint interrupt */
  902. csr1 = S3C2410_UDC_ICSR1_CLRDT;
  903. csr2 = S3C2410_UDC_ICSR2_DMAIEN;
  904. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  905. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  906. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  907. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  908. csr1 = S3C2410_UDC_OCSR1_FFLUSH | S3C2410_UDC_OCSR1_CLRDT;
  909. csr2 = S3C2410_UDC_OCSR2_DMAIEN;
  910. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  911. udc_write(csr1, S3C2410_UDC_OUT_CSR1_REG);
  912. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  913. udc_write(csr2, S3C2410_UDC_OUT_CSR2_REG);
  914. }
  915. /* enable irqs */
  916. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  917. udc_write(int_en_reg | (1 << ep->num), S3C2410_UDC_EP_INT_EN_REG);
  918. /* print some debug message */
  919. tmp = desc->bEndpointAddress;
  920. dprintk (DEBUG_NORMAL, "enable %s(%d) ep%x%s-blk max %02x\n",
  921. _ep->name,ep->num, tmp,
  922. desc->bEndpointAddress & USB_DIR_IN ? "in" : "out", max);
  923. local_irq_restore (flags);
  924. s3c2410_udc_set_halt(_ep, 0);
  925. return 0;
  926. }
  927. /*
  928. * s3c2410_udc_ep_disable
  929. */
  930. static int s3c2410_udc_ep_disable(struct usb_ep *_ep)
  931. {
  932. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  933. unsigned long flags;
  934. u32 int_en_reg;
  935. if (!_ep || !ep->desc) {
  936. dprintk(DEBUG_NORMAL, "%s not enabled\n",
  937. _ep ? ep->ep.name : NULL);
  938. return -EINVAL;
  939. }
  940. local_irq_save(flags);
  941. dprintk(DEBUG_NORMAL, "ep_disable: %s\n", _ep->name);
  942. ep->desc = NULL;
  943. ep->halted = 1;
  944. s3c2410_udc_nuke (ep->dev, ep, -ESHUTDOWN);
  945. /* disable irqs */
  946. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  947. udc_write(int_en_reg & ~(1<<ep->num), S3C2410_UDC_EP_INT_EN_REG);
  948. local_irq_restore(flags);
  949. dprintk(DEBUG_NORMAL, "%s disabled\n", _ep->name);
  950. return 0;
  951. }
  952. /*
  953. * s3c2410_udc_alloc_request
  954. */
  955. static struct usb_request *
  956. s3c2410_udc_alloc_request(struct usb_ep *_ep, gfp_t mem_flags)
  957. {
  958. struct s3c2410_request *req;
  959. dprintk(DEBUG_VERBOSE,"%s(%p,%d)\n", __func__, _ep, mem_flags);
  960. if (!_ep)
  961. return NULL;
  962. req = kzalloc (sizeof(struct s3c2410_request), mem_flags);
  963. if (!req)
  964. return NULL;
  965. INIT_LIST_HEAD (&req->queue);
  966. return &req->req;
  967. }
  968. /*
  969. * s3c2410_udc_free_request
  970. */
  971. static void
  972. s3c2410_udc_free_request(struct usb_ep *_ep, struct usb_request *_req)
  973. {
  974. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  975. struct s3c2410_request *req = to_s3c2410_req(_req);
  976. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  977. if (!ep || !_req || (!ep->desc && _ep->name != ep0name))
  978. return;
  979. WARN_ON (!list_empty (&req->queue));
  980. kfree(req);
  981. }
  982. /*
  983. * s3c2410_udc_queue
  984. */
  985. static int s3c2410_udc_queue(struct usb_ep *_ep, struct usb_request *_req,
  986. gfp_t gfp_flags)
  987. {
  988. struct s3c2410_request *req = to_s3c2410_req(_req);
  989. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  990. struct s3c2410_udc *dev;
  991. u32 ep_csr = 0;
  992. int fifo_count = 0;
  993. unsigned long flags;
  994. if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  995. dprintk(DEBUG_NORMAL, "%s: invalid args\n", __func__);
  996. return -EINVAL;
  997. }
  998. dev = ep->dev;
  999. if (unlikely (!dev->driver
  1000. || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
  1001. return -ESHUTDOWN;
  1002. }
  1003. local_irq_save (flags);
  1004. if (unlikely(!_req || !_req->complete
  1005. || !_req->buf || !list_empty(&req->queue))) {
  1006. if (!_req)
  1007. dprintk(DEBUG_NORMAL, "%s: 1 X X X\n", __func__);
  1008. else {
  1009. dprintk(DEBUG_NORMAL, "%s: 0 %01d %01d %01d\n",
  1010. __func__, !_req->complete,!_req->buf,
  1011. !list_empty(&req->queue));
  1012. }
  1013. local_irq_restore(flags);
  1014. return -EINVAL;
  1015. }
  1016. _req->status = -EINPROGRESS;
  1017. _req->actual = 0;
  1018. dprintk(DEBUG_VERBOSE, "%s: ep%x len %d\n",
  1019. __func__, ep->bEndpointAddress, _req->length);
  1020. if (ep->bEndpointAddress) {
  1021. udc_write(ep->bEndpointAddress & 0x7F, S3C2410_UDC_INDEX_REG);
  1022. ep_csr = udc_read((ep->bEndpointAddress & USB_DIR_IN)
  1023. ? S3C2410_UDC_IN_CSR1_REG
  1024. : S3C2410_UDC_OUT_CSR1_REG);
  1025. fifo_count = s3c2410_udc_fifo_count_out();
  1026. } else {
  1027. udc_write(0, S3C2410_UDC_INDEX_REG);
  1028. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  1029. fifo_count = s3c2410_udc_fifo_count_out();
  1030. }
  1031. /* kickstart this i/o queue? */
  1032. if (list_empty(&ep->queue) && !ep->halted) {
  1033. if (ep->bEndpointAddress == 0 /* ep0 */) {
  1034. switch (dev->ep0state) {
  1035. case EP0_IN_DATA_PHASE:
  1036. if (!(ep_csr&S3C2410_UDC_EP0_CSR_IPKRDY)
  1037. && s3c2410_udc_write_fifo(ep,
  1038. req)) {
  1039. dev->ep0state = EP0_IDLE;
  1040. req = NULL;
  1041. }
  1042. break;
  1043. case EP0_OUT_DATA_PHASE:
  1044. if ((!_req->length)
  1045. || ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1046. && s3c2410_udc_read_fifo(ep,
  1047. req))) {
  1048. dev->ep0state = EP0_IDLE;
  1049. req = NULL;
  1050. }
  1051. break;
  1052. default:
  1053. local_irq_restore(flags);
  1054. return -EL2HLT;
  1055. }
  1056. } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0
  1057. && (!(ep_csr&S3C2410_UDC_OCSR1_PKTRDY))
  1058. && s3c2410_udc_write_fifo(ep, req)) {
  1059. req = NULL;
  1060. } else if ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1061. && fifo_count
  1062. && s3c2410_udc_read_fifo(ep, req)) {
  1063. req = NULL;
  1064. }
  1065. }
  1066. /* pio or dma irq handler advances the queue. */
  1067. if (likely (req != 0))
  1068. list_add_tail(&req->queue, &ep->queue);
  1069. local_irq_restore(flags);
  1070. dprintk(DEBUG_VERBOSE, "%s ok\n", __func__);
  1071. return 0;
  1072. }
  1073. /*
  1074. * s3c2410_udc_dequeue
  1075. */
  1076. static int s3c2410_udc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1077. {
  1078. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1079. struct s3c2410_udc *udc;
  1080. int retval = -EINVAL;
  1081. unsigned long flags;
  1082. struct s3c2410_request *req = NULL;
  1083. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  1084. if (!the_controller->driver)
  1085. return -ESHUTDOWN;
  1086. if (!_ep || !_req)
  1087. return retval;
  1088. udc = to_s3c2410_udc(ep->gadget);
  1089. local_irq_save (flags);
  1090. list_for_each_entry (req, &ep->queue, queue) {
  1091. if (&req->req == _req) {
  1092. list_del_init (&req->queue);
  1093. _req->status = -ECONNRESET;
  1094. retval = 0;
  1095. break;
  1096. }
  1097. }
  1098. if (retval == 0) {
  1099. dprintk(DEBUG_VERBOSE,
  1100. "dequeued req %p from %s, len %d buf %p\n",
  1101. req, _ep->name, _req->length, _req->buf);
  1102. s3c2410_udc_done(ep, req, -ECONNRESET);
  1103. }
  1104. local_irq_restore (flags);
  1105. return retval;
  1106. }
  1107. /*
  1108. * s3c2410_udc_set_halt
  1109. */
  1110. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value)
  1111. {
  1112. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1113. u32 ep_csr = 0;
  1114. unsigned long flags;
  1115. u32 idx;
  1116. if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  1117. dprintk(DEBUG_NORMAL, "%s: inval 2\n", __func__);
  1118. return -EINVAL;
  1119. }
  1120. local_irq_save (flags);
  1121. idx = ep->bEndpointAddress & 0x7F;
  1122. if (idx == 0) {
  1123. s3c2410_udc_set_ep0_ss(base_addr);
  1124. s3c2410_udc_set_ep0_de_out(base_addr);
  1125. } else {
  1126. udc_write(idx, S3C2410_UDC_INDEX_REG);
  1127. ep_csr = udc_read((ep->bEndpointAddress &USB_DIR_IN)
  1128. ? S3C2410_UDC_IN_CSR1_REG
  1129. : S3C2410_UDC_OUT_CSR1_REG);
  1130. if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
  1131. if (value)
  1132. udc_write(ep_csr | S3C2410_UDC_ICSR1_SENDSTL,
  1133. S3C2410_UDC_IN_CSR1_REG);
  1134. else {
  1135. ep_csr &= ~S3C2410_UDC_ICSR1_SENDSTL;
  1136. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1137. ep_csr |= S3C2410_UDC_ICSR1_CLRDT;
  1138. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1139. }
  1140. } else {
  1141. if (value)
  1142. udc_write(ep_csr | S3C2410_UDC_OCSR1_SENDSTL,
  1143. S3C2410_UDC_OUT_CSR1_REG);
  1144. else {
  1145. ep_csr &= ~S3C2410_UDC_OCSR1_SENDSTL;
  1146. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1147. ep_csr |= S3C2410_UDC_OCSR1_CLRDT;
  1148. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1149. }
  1150. }
  1151. }
  1152. ep->halted = value ? 1 : 0;
  1153. local_irq_restore (flags);
  1154. return 0;
  1155. }
  1156. static const struct usb_ep_ops s3c2410_ep_ops = {
  1157. .enable = s3c2410_udc_ep_enable,
  1158. .disable = s3c2410_udc_ep_disable,
  1159. .alloc_request = s3c2410_udc_alloc_request,
  1160. .free_request = s3c2410_udc_free_request,
  1161. .queue = s3c2410_udc_queue,
  1162. .dequeue = s3c2410_udc_dequeue,
  1163. .set_halt = s3c2410_udc_set_halt,
  1164. };
  1165. /*------------------------- usb_gadget_ops ----------------------------------*/
  1166. /*
  1167. * s3c2410_udc_get_frame
  1168. */
  1169. static int s3c2410_udc_get_frame(struct usb_gadget *_gadget)
  1170. {
  1171. int tmp;
  1172. dprintk(DEBUG_VERBOSE, "%s()\n", __func__);
  1173. tmp = udc_read(S3C2410_UDC_FRAME_NUM2_REG) << 8;
  1174. tmp |= udc_read(S3C2410_UDC_FRAME_NUM1_REG);
  1175. return tmp;
  1176. }
  1177. /*
  1178. * s3c2410_udc_wakeup
  1179. */
  1180. static int s3c2410_udc_wakeup(struct usb_gadget *_gadget)
  1181. {
  1182. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1183. return 0;
  1184. }
  1185. /*
  1186. * s3c2410_udc_set_selfpowered
  1187. */
  1188. static int s3c2410_udc_set_selfpowered(struct usb_gadget *gadget, int value)
  1189. {
  1190. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1191. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1192. if (value)
  1193. udc->devstatus |= (1 << USB_DEVICE_SELF_POWERED);
  1194. else
  1195. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  1196. return 0;
  1197. }
  1198. static void s3c2410_udc_disable(struct s3c2410_udc *dev);
  1199. static void s3c2410_udc_enable(struct s3c2410_udc *dev);
  1200. static int s3c2410_udc_set_pullup(struct s3c2410_udc *udc, int is_on)
  1201. {
  1202. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1203. if (udc_info && udc_info->udc_command) {
  1204. if (is_on)
  1205. s3c2410_udc_enable(udc);
  1206. else {
  1207. if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
  1208. if (udc->driver && udc->driver->disconnect)
  1209. udc->driver->disconnect(&udc->gadget);
  1210. }
  1211. s3c2410_udc_disable(udc);
  1212. }
  1213. }
  1214. else
  1215. return -EOPNOTSUPP;
  1216. return 0;
  1217. }
  1218. static int s3c2410_udc_vbus_session(struct usb_gadget *gadget, int is_active)
  1219. {
  1220. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1221. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1222. udc->vbus = (is_active != 0);
  1223. s3c2410_udc_set_pullup(udc, is_active);
  1224. return 0;
  1225. }
  1226. static int s3c2410_udc_pullup(struct usb_gadget *gadget, int is_on)
  1227. {
  1228. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1229. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1230. s3c2410_udc_set_pullup(udc, is_on ? 0 : 1);
  1231. return 0;
  1232. }
  1233. static irqreturn_t s3c2410_udc_vbus_irq(int irq, void *_dev)
  1234. {
  1235. struct s3c2410_udc *dev = _dev;
  1236. unsigned int value;
  1237. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1238. /* some cpus cannot read from an line configured to IRQ! */
  1239. s3c2410_gpio_cfgpin(udc_info->vbus_pin, S3C2410_GPIO_INPUT);
  1240. value = s3c2410_gpio_getpin(udc_info->vbus_pin);
  1241. s3c2410_gpio_cfgpin(udc_info->vbus_pin, S3C2410_GPIO_SFN2);
  1242. if (udc_info->vbus_pin_inverted)
  1243. value = !value;
  1244. if (value != dev->vbus)
  1245. s3c2410_udc_vbus_session(&dev->gadget, value);
  1246. return IRQ_HANDLED;
  1247. }
  1248. static int s3c2410_vbus_draw(struct usb_gadget *_gadget, unsigned ma)
  1249. {
  1250. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1251. if (udc_info && udc_info->vbus_draw) {
  1252. udc_info->vbus_draw(ma);
  1253. return 0;
  1254. }
  1255. return -ENOTSUPP;
  1256. }
  1257. static const struct usb_gadget_ops s3c2410_ops = {
  1258. .get_frame = s3c2410_udc_get_frame,
  1259. .wakeup = s3c2410_udc_wakeup,
  1260. .set_selfpowered = s3c2410_udc_set_selfpowered,
  1261. .pullup = s3c2410_udc_pullup,
  1262. .vbus_session = s3c2410_udc_vbus_session,
  1263. .vbus_draw = s3c2410_vbus_draw,
  1264. };
  1265. /*------------------------- gadget driver handling---------------------------*/
  1266. /*
  1267. * s3c2410_udc_disable
  1268. */
  1269. static void s3c2410_udc_disable(struct s3c2410_udc *dev)
  1270. {
  1271. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1272. /* Disable all interrupts */
  1273. udc_write(0x00, S3C2410_UDC_USB_INT_EN_REG);
  1274. udc_write(0x00, S3C2410_UDC_EP_INT_EN_REG);
  1275. /* Clear the interrupt registers */
  1276. udc_write(S3C2410_UDC_USBINT_RESET
  1277. | S3C2410_UDC_USBINT_RESUME
  1278. | S3C2410_UDC_USBINT_SUSPEND,
  1279. S3C2410_UDC_USB_INT_REG);
  1280. udc_write(0x1F, S3C2410_UDC_EP_INT_REG);
  1281. /* Good bye, cruel world */
  1282. if (udc_info && udc_info->udc_command)
  1283. udc_info->udc_command(S3C2410_UDC_P_DISABLE);
  1284. /* Set speed to unknown */
  1285. dev->gadget.speed = USB_SPEED_UNKNOWN;
  1286. }
  1287. /*
  1288. * s3c2410_udc_reinit
  1289. */
  1290. static void s3c2410_udc_reinit(struct s3c2410_udc *dev)
  1291. {
  1292. u32 i;
  1293. /* device/ep0 records init */
  1294. INIT_LIST_HEAD (&dev->gadget.ep_list);
  1295. INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
  1296. dev->ep0state = EP0_IDLE;
  1297. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1298. struct s3c2410_ep *ep = &dev->ep[i];
  1299. if (i != 0)
  1300. list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list);
  1301. ep->dev = dev;
  1302. ep->desc = NULL;
  1303. ep->halted = 0;
  1304. INIT_LIST_HEAD (&ep->queue);
  1305. }
  1306. }
  1307. /*
  1308. * s3c2410_udc_enable
  1309. */
  1310. static void s3c2410_udc_enable(struct s3c2410_udc *dev)
  1311. {
  1312. int i;
  1313. dprintk(DEBUG_NORMAL, "s3c2410_udc_enable called\n");
  1314. /* dev->gadget.speed = USB_SPEED_UNKNOWN; */
  1315. dev->gadget.speed = USB_SPEED_FULL;
  1316. /* Set MAXP for all endpoints */
  1317. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1318. udc_write(i, S3C2410_UDC_INDEX_REG);
  1319. udc_write((dev->ep[i].ep.maxpacket & 0x7ff) >> 3,
  1320. S3C2410_UDC_MAXP_REG);
  1321. }
  1322. /* Set default power state */
  1323. udc_write(DEFAULT_POWER_STATE, S3C2410_UDC_PWR_REG);
  1324. /* Enable reset and suspend interrupt interrupts */
  1325. udc_write(S3C2410_UDC_USBINT_RESET | S3C2410_UDC_USBINT_SUSPEND,
  1326. S3C2410_UDC_USB_INT_EN_REG);
  1327. /* Enable ep0 interrupt */
  1328. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_EN_REG);
  1329. /* time to say "hello, world" */
  1330. if (udc_info && udc_info->udc_command)
  1331. udc_info->udc_command(S3C2410_UDC_P_ENABLE);
  1332. }
  1333. /*
  1334. * usb_gadget_register_driver
  1335. */
  1336. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1337. {
  1338. struct s3c2410_udc *udc = the_controller;
  1339. int retval;
  1340. dprintk(DEBUG_NORMAL, "usb_gadget_register_driver() '%s'\n",
  1341. driver->driver.name);
  1342. /* Sanity checks */
  1343. if (!udc)
  1344. return -ENODEV;
  1345. if (udc->driver)
  1346. return -EBUSY;
  1347. if (!driver->bind || !driver->setup
  1348. || driver->speed != USB_SPEED_FULL) {
  1349. printk(KERN_ERR "Invalid driver: bind %p setup %p speed %d\n",
  1350. driver->bind, driver->setup, driver->speed);
  1351. return -EINVAL;
  1352. }
  1353. #if defined(MODULE)
  1354. if (!driver->unbind) {
  1355. printk(KERN_ERR "Invalid driver: no unbind method\n");
  1356. return -EINVAL;
  1357. }
  1358. #endif
  1359. /* Hook the driver */
  1360. udc->driver = driver;
  1361. udc->gadget.dev.driver = &driver->driver;
  1362. /* Bind the driver */
  1363. if ((retval = device_add(&udc->gadget.dev)) != 0) {
  1364. printk(KERN_ERR "Error in device_add() : %d\n",retval);
  1365. goto register_error;
  1366. }
  1367. dprintk(DEBUG_NORMAL, "binding gadget driver '%s'\n",
  1368. driver->driver.name);
  1369. if ((retval = driver->bind (&udc->gadget)) != 0) {
  1370. device_del(&udc->gadget.dev);
  1371. goto register_error;
  1372. }
  1373. /* Enable udc */
  1374. s3c2410_udc_enable(udc);
  1375. return 0;
  1376. register_error:
  1377. udc->driver = NULL;
  1378. udc->gadget.dev.driver = NULL;
  1379. return retval;
  1380. }
  1381. /*
  1382. * usb_gadget_unregister_driver
  1383. */
  1384. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1385. {
  1386. struct s3c2410_udc *udc = the_controller;
  1387. if (!udc)
  1388. return -ENODEV;
  1389. if (!driver || driver != udc->driver || !driver->unbind)
  1390. return -EINVAL;
  1391. dprintk(DEBUG_NORMAL,"usb_gadget_register_driver() '%s'\n",
  1392. driver->driver.name);
  1393. if (driver->disconnect)
  1394. driver->disconnect(&udc->gadget);
  1395. device_del(&udc->gadget.dev);
  1396. udc->driver = NULL;
  1397. /* Disable udc */
  1398. s3c2410_udc_disable(udc);
  1399. return 0;
  1400. }
  1401. /*---------------------------------------------------------------------------*/
  1402. static struct s3c2410_udc memory = {
  1403. .gadget = {
  1404. .ops = &s3c2410_ops,
  1405. .ep0 = &memory.ep[0].ep,
  1406. .name = gadget_name,
  1407. .dev = {
  1408. .bus_id = "gadget",
  1409. },
  1410. },
  1411. /* control endpoint */
  1412. .ep[0] = {
  1413. .num = 0,
  1414. .ep = {
  1415. .name = ep0name,
  1416. .ops = &s3c2410_ep_ops,
  1417. .maxpacket = EP0_FIFO_SIZE,
  1418. },
  1419. .dev = &memory,
  1420. },
  1421. /* first group of endpoints */
  1422. .ep[1] = {
  1423. .num = 1,
  1424. .ep = {
  1425. .name = "ep1-bulk",
  1426. .ops = &s3c2410_ep_ops,
  1427. .maxpacket = EP_FIFO_SIZE,
  1428. },
  1429. .dev = &memory,
  1430. .fifo_size = EP_FIFO_SIZE,
  1431. .bEndpointAddress = 1,
  1432. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1433. },
  1434. .ep[2] = {
  1435. .num = 2,
  1436. .ep = {
  1437. .name = "ep2-bulk",
  1438. .ops = &s3c2410_ep_ops,
  1439. .maxpacket = EP_FIFO_SIZE,
  1440. },
  1441. .dev = &memory,
  1442. .fifo_size = EP_FIFO_SIZE,
  1443. .bEndpointAddress = 2,
  1444. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1445. },
  1446. .ep[3] = {
  1447. .num = 3,
  1448. .ep = {
  1449. .name = "ep3-bulk",
  1450. .ops = &s3c2410_ep_ops,
  1451. .maxpacket = EP_FIFO_SIZE,
  1452. },
  1453. .dev = &memory,
  1454. .fifo_size = EP_FIFO_SIZE,
  1455. .bEndpointAddress = 3,
  1456. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1457. },
  1458. .ep[4] = {
  1459. .num = 4,
  1460. .ep = {
  1461. .name = "ep4-bulk",
  1462. .ops = &s3c2410_ep_ops,
  1463. .maxpacket = EP_FIFO_SIZE,
  1464. },
  1465. .dev = &memory,
  1466. .fifo_size = EP_FIFO_SIZE,
  1467. .bEndpointAddress = 4,
  1468. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1469. }
  1470. };
  1471. /*
  1472. * probe - binds to the platform device
  1473. */
  1474. static int s3c2410_udc_probe(struct platform_device *pdev)
  1475. {
  1476. struct s3c2410_udc *udc = &memory;
  1477. struct device *dev = &pdev->dev;
  1478. int retval;
  1479. unsigned int irq;
  1480. dev_dbg(dev, "%s()\n", __func__);
  1481. usb_bus_clock = clk_get(NULL, "usb-bus-gadget");
  1482. if (IS_ERR(usb_bus_clock)) {
  1483. dev_err(dev, "failed to get usb bus clock source\n");
  1484. return PTR_ERR(usb_bus_clock);
  1485. }
  1486. clk_enable(usb_bus_clock);
  1487. udc_clock = clk_get(NULL, "usb-device");
  1488. if (IS_ERR(udc_clock)) {
  1489. dev_err(dev, "failed to get udc clock source\n");
  1490. return PTR_ERR(udc_clock);
  1491. }
  1492. clk_enable(udc_clock);
  1493. mdelay(10);
  1494. dev_dbg(dev, "got and enabled clocks\n");
  1495. if (strncmp(pdev->name, "s3c2440", 7) == 0) {
  1496. dev_info(dev, "S3C2440: increasing FIFO to 128 bytes\n");
  1497. memory.ep[1].fifo_size = S3C2440_EP_FIFO_SIZE;
  1498. memory.ep[2].fifo_size = S3C2440_EP_FIFO_SIZE;
  1499. memory.ep[3].fifo_size = S3C2440_EP_FIFO_SIZE;
  1500. memory.ep[4].fifo_size = S3C2440_EP_FIFO_SIZE;
  1501. }
  1502. spin_lock_init (&udc->lock);
  1503. udc_info = pdev->dev.platform_data;
  1504. rsrc_start = S3C2410_PA_USBDEV;
  1505. rsrc_len = S3C24XX_SZ_USBDEV;
  1506. if (!request_mem_region(rsrc_start, rsrc_len, gadget_name))
  1507. return -EBUSY;
  1508. base_addr = ioremap(rsrc_start, rsrc_len);
  1509. if (!base_addr) {
  1510. retval = -ENOMEM;
  1511. goto err_mem;
  1512. }
  1513. device_initialize(&udc->gadget.dev);
  1514. udc->gadget.dev.parent = &pdev->dev;
  1515. udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1516. the_controller = udc;
  1517. platform_set_drvdata(pdev, udc);
  1518. s3c2410_udc_disable(udc);
  1519. s3c2410_udc_reinit(udc);
  1520. /* irq setup after old hardware state is cleaned up */
  1521. retval = request_irq(IRQ_USBD, s3c2410_udc_irq,
  1522. IRQF_DISABLED, gadget_name, udc);
  1523. if (retval != 0) {
  1524. dev_err(dev, "cannot get irq %i, err %d\n", IRQ_USBD, retval);
  1525. retval = -EBUSY;
  1526. goto err_map;
  1527. }
  1528. dev_dbg(dev, "got irq %i\n", IRQ_USBD);
  1529. if (udc_info && udc_info->vbus_pin > 0) {
  1530. irq = s3c2410_gpio_getirq(udc_info->vbus_pin);
  1531. retval = request_irq(irq, s3c2410_udc_vbus_irq,
  1532. IRQF_DISABLED | IRQF_TRIGGER_RISING
  1533. | IRQF_TRIGGER_FALLING | IRQF_SHARED,
  1534. gadget_name, udc);
  1535. if (retval != 0) {
  1536. dev_err(dev, "can't get vbus irq %i, err %d\n",
  1537. irq, retval);
  1538. retval = -EBUSY;
  1539. goto err_int;
  1540. }
  1541. dev_dbg(dev, "got irq %i\n", irq);
  1542. } else {
  1543. udc->vbus = 1;
  1544. }
  1545. if (s3c2410_udc_debugfs_root) {
  1546. udc->regs_info = debugfs_create_file("registers", S_IRUGO,
  1547. s3c2410_udc_debugfs_root,
  1548. udc, &s3c2410_udc_debugfs_fops);
  1549. if (IS_ERR(udc->regs_info)) {
  1550. dev_warn(dev, "debugfs file creation failed %ld\n",
  1551. PTR_ERR(udc->regs_info));
  1552. udc->regs_info = NULL;
  1553. }
  1554. }
  1555. dev_dbg(dev, "probe ok\n");
  1556. return 0;
  1557. err_int:
  1558. free_irq(IRQ_USBD, udc);
  1559. err_map:
  1560. iounmap(base_addr);
  1561. err_mem:
  1562. release_mem_region(rsrc_start, rsrc_len);
  1563. return retval;
  1564. }
  1565. /*
  1566. * s3c2410_udc_remove
  1567. */
  1568. static int s3c2410_udc_remove(struct platform_device *pdev)
  1569. {
  1570. struct s3c2410_udc *udc = platform_get_drvdata(pdev);
  1571. unsigned int irq;
  1572. dev_dbg(&pdev->dev, "%s()\n", __func__);
  1573. if (udc->driver)
  1574. return -EBUSY;
  1575. debugfs_remove(udc->regs_info);
  1576. if (udc_info && udc_info->vbus_pin > 0) {
  1577. irq = s3c2410_gpio_getirq(udc_info->vbus_pin);
  1578. free_irq(irq, udc);
  1579. }
  1580. free_irq(IRQ_USBD, udc);
  1581. iounmap(base_addr);
  1582. release_mem_region(rsrc_start, rsrc_len);
  1583. platform_set_drvdata(pdev, NULL);
  1584. if (!IS_ERR(udc_clock) && udc_clock != NULL) {
  1585. clk_disable(udc_clock);
  1586. clk_put(udc_clock);
  1587. udc_clock = NULL;
  1588. }
  1589. if (!IS_ERR(usb_bus_clock) && usb_bus_clock != NULL) {
  1590. clk_disable(usb_bus_clock);
  1591. clk_put(usb_bus_clock);
  1592. usb_bus_clock = NULL;
  1593. }
  1594. dev_dbg(&pdev->dev, "%s: remove ok\n", __func__);
  1595. return 0;
  1596. }
  1597. #ifdef CONFIG_PM
  1598. static int s3c2410_udc_suspend(struct platform_device *pdev, pm_message_t message)
  1599. {
  1600. if (udc_info && udc_info->udc_command)
  1601. udc_info->udc_command(S3C2410_UDC_P_DISABLE);
  1602. return 0;
  1603. }
  1604. static int s3c2410_udc_resume(struct platform_device *pdev)
  1605. {
  1606. if (udc_info && udc_info->udc_command)
  1607. udc_info->udc_command(S3C2410_UDC_P_ENABLE);
  1608. return 0;
  1609. }
  1610. #else
  1611. #define s3c2410_udc_suspend NULL
  1612. #define s3c2410_udc_resume NULL
  1613. #endif
  1614. static struct platform_driver udc_driver_2410 = {
  1615. .driver = {
  1616. .name = "s3c2410-usbgadget",
  1617. .owner = THIS_MODULE,
  1618. },
  1619. .probe = s3c2410_udc_probe,
  1620. .remove = s3c2410_udc_remove,
  1621. .suspend = s3c2410_udc_suspend,
  1622. .resume = s3c2410_udc_resume,
  1623. };
  1624. static struct platform_driver udc_driver_2440 = {
  1625. .driver = {
  1626. .name = "s3c2440-usbgadget",
  1627. .owner = THIS_MODULE,
  1628. },
  1629. .probe = s3c2410_udc_probe,
  1630. .remove = s3c2410_udc_remove,
  1631. .suspend = s3c2410_udc_suspend,
  1632. .resume = s3c2410_udc_resume,
  1633. };
  1634. static int __init udc_init(void)
  1635. {
  1636. int retval;
  1637. dprintk(DEBUG_NORMAL, "%s: version %s\n", gadget_name, DRIVER_VERSION);
  1638. s3c2410_udc_debugfs_root = debugfs_create_dir(gadget_name, NULL);
  1639. if (IS_ERR(s3c2410_udc_debugfs_root)) {
  1640. printk(KERN_ERR "%s: debugfs dir creation failed %ld\n",
  1641. gadget_name, PTR_ERR(s3c2410_udc_debugfs_root));
  1642. s3c2410_udc_debugfs_root = NULL;
  1643. }
  1644. retval = platform_driver_register(&udc_driver_2410);
  1645. if (retval)
  1646. goto err;
  1647. retval = platform_driver_register(&udc_driver_2440);
  1648. if (retval)
  1649. goto err;
  1650. return 0;
  1651. err:
  1652. debugfs_remove(s3c2410_udc_debugfs_root);
  1653. return retval;
  1654. }
  1655. static void __exit udc_exit(void)
  1656. {
  1657. platform_driver_unregister(&udc_driver_2410);
  1658. platform_driver_unregister(&udc_driver_2440);
  1659. debugfs_remove(s3c2410_udc_debugfs_root);
  1660. }
  1661. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1662. EXPORT_SYMBOL(usb_gadget_register_driver);
  1663. module_init(udc_init);
  1664. module_exit(udc_exit);
  1665. MODULE_AUTHOR(DRIVER_AUTHOR);
  1666. MODULE_DESCRIPTION(DRIVER_DESC);
  1667. MODULE_VERSION(DRIVER_VERSION);
  1668. MODULE_LICENSE("GPL");