gdth.c 178 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-06 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.6.x supported *
  31. * *
  32. ************************************************************************/
  33. /* All GDT Disk Array Controllers are fully supported by this driver.
  34. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  35. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  36. * list of all controller types.
  37. *
  38. * If you have one or more GDT3000/3020 EISA controllers with
  39. * controller BIOS disabled, you have to set the IRQ values with the
  40. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  41. * the IRQ values for the EISA controllers.
  42. *
  43. * After the optional list of IRQ values, other possible
  44. * command line options are:
  45. * disable:Y disable driver
  46. * disable:N enable driver
  47. * reserve_mode:0 reserve no drives for the raw service
  48. * reserve_mode:1 reserve all not init., removable drives
  49. * reserve_mode:2 reserve all not init. drives
  50. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  51. * h- controller no., b- channel no.,
  52. * t- target ID, l- LUN
  53. * reverse_scan:Y reverse scan order for PCI controllers
  54. * reverse_scan:N scan PCI controllers like BIOS
  55. * max_ids:x x - target ID count per channel (1..MAXID)
  56. * rescan:Y rescan all channels/IDs
  57. * rescan:N use all devices found until now
  58. * hdr_channel:x x - number of virtual bus for host drives
  59. * shared_access:Y disable driver reserve/release protocol to
  60. * access a shared resource from several nodes,
  61. * appropriate controller firmware required
  62. * shared_access:N enable driver reserve/release protocol
  63. * probe_eisa_isa:Y scan for EISA/ISA controllers
  64. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  65. * force_dma32:Y use only 32 bit DMA mode
  66. * force_dma32:N use 64 bit DMA mode, if supported
  67. *
  68. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  69. * max_ids:127,rescan:N,hdr_channel:0,
  70. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  71. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  72. *
  73. * When loading the gdth driver as a module, the same options are available.
  74. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  75. * options changes slightly. You must replace all ',' between options
  76. * with ' ' and all ':' with '=' and you must use
  77. * '1' in place of 'Y' and '0' in place of 'N'.
  78. *
  79. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  80. * max_ids=127 rescan=0 hdr_channel=0 shared_access=0
  81. * probe_eisa_isa=0 force_dma32=0"
  82. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  83. */
  84. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  85. * ptr: Chaining
  86. * this_residual: gdth_bufflen
  87. * buffer: gdth_sglist
  88. * dma_handle: unused
  89. * buffers_residual: gdth_sg_count
  90. * Status: unused
  91. * Message: unused
  92. * have_data_in: unused
  93. * sent_command: unused
  94. * phase: unused
  95. */
  96. /* interrupt coalescing */
  97. /* #define INT_COAL */
  98. /* statistics */
  99. #define GDTH_STATISTICS
  100. #include <linux/module.h>
  101. #include <linux/version.h>
  102. #include <linux/kernel.h>
  103. #include <linux/types.h>
  104. #include <linux/pci.h>
  105. #include <linux/string.h>
  106. #include <linux/ctype.h>
  107. #include <linux/ioport.h>
  108. #include <linux/delay.h>
  109. #include <linux/interrupt.h>
  110. #include <linux/in.h>
  111. #include <linux/proc_fs.h>
  112. #include <linux/time.h>
  113. #include <linux/timer.h>
  114. #include <linux/dma-mapping.h>
  115. #include <linux/list.h>
  116. #ifdef GDTH_RTC
  117. #include <linux/mc146818rtc.h>
  118. #endif
  119. #include <linux/reboot.h>
  120. #include <asm/dma.h>
  121. #include <asm/system.h>
  122. #include <asm/io.h>
  123. #include <asm/uaccess.h>
  124. #include <linux/spinlock.h>
  125. #include <linux/blkdev.h>
  126. #include <linux/scatterlist.h>
  127. #include "scsi.h"
  128. #include <scsi/scsi_host.h>
  129. #include "gdth.h"
  130. static void gdth_delay(int milliseconds);
  131. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
  132. static irqreturn_t gdth_interrupt(int irq, void *dev_id);
  133. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
  134. int gdth_from_wait, int* pIndex);
  135. static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
  136. Scsi_Cmnd *scp);
  137. static int gdth_async_event(gdth_ha_str *ha);
  138. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  139. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority);
  140. static void gdth_next(gdth_ha_str *ha);
  141. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b);
  142. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  143. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  144. ushort idx, gdth_evt_data *evt);
  145. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  146. static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
  147. gdth_evt_str *estr);
  148. static void gdth_clear_events(void);
  149. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  150. char *buffer, ushort count, int to_buffer);
  151. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  152. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive);
  153. static void gdth_enable_int(gdth_ha_str *ha);
  154. static int gdth_test_busy(gdth_ha_str *ha);
  155. static int gdth_get_cmd_index(gdth_ha_str *ha);
  156. static void gdth_release_event(gdth_ha_str *ha);
  157. static int gdth_wait(gdth_ha_str *ha, int index,ulong32 time);
  158. static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
  159. ulong32 p1, ulong64 p2,ulong64 p3);
  160. static int gdth_search_drives(gdth_ha_str *ha);
  161. static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive);
  162. static const char *gdth_ctr_name(gdth_ha_str *ha);
  163. static int gdth_open(struct inode *inode, struct file *filep);
  164. static int gdth_close(struct inode *inode, struct file *filep);
  165. static int gdth_ioctl(struct inode *inode, struct file *filep,
  166. unsigned int cmd, unsigned long arg);
  167. static void gdth_flush(gdth_ha_str *ha);
  168. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
  169. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
  170. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  171. struct gdth_cmndinfo *cmndinfo);
  172. static void gdth_scsi_done(struct scsi_cmnd *scp);
  173. #ifdef DEBUG_GDTH
  174. static unchar DebugState = DEBUG_GDTH;
  175. #ifdef __SERIAL__
  176. #define MAX_SERBUF 160
  177. static void ser_init(void);
  178. static void ser_puts(char *str);
  179. static void ser_putc(char c);
  180. static int ser_printk(const char *fmt, ...);
  181. static char strbuf[MAX_SERBUF+1];
  182. #ifdef __COM2__
  183. #define COM_BASE 0x2f8
  184. #else
  185. #define COM_BASE 0x3f8
  186. #endif
  187. static void ser_init()
  188. {
  189. unsigned port=COM_BASE;
  190. outb(0x80,port+3);
  191. outb(0,port+1);
  192. /* 19200 Baud, if 9600: outb(12,port) */
  193. outb(6, port);
  194. outb(3,port+3);
  195. outb(0,port+1);
  196. /*
  197. ser_putc('I');
  198. ser_putc(' ');
  199. */
  200. }
  201. static void ser_puts(char *str)
  202. {
  203. char *ptr;
  204. ser_init();
  205. for (ptr=str;*ptr;++ptr)
  206. ser_putc(*ptr);
  207. }
  208. static void ser_putc(char c)
  209. {
  210. unsigned port=COM_BASE;
  211. while ((inb(port+5) & 0x20)==0);
  212. outb(c,port);
  213. if (c==0x0a)
  214. {
  215. while ((inb(port+5) & 0x20)==0);
  216. outb(0x0d,port);
  217. }
  218. }
  219. static int ser_printk(const char *fmt, ...)
  220. {
  221. va_list args;
  222. int i;
  223. va_start(args,fmt);
  224. i = vsprintf(strbuf,fmt,args);
  225. ser_puts(strbuf);
  226. va_end(args);
  227. return i;
  228. }
  229. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  230. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  231. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  232. #else /* !__SERIAL__ */
  233. #define TRACE(a) {if (DebugState==1) {printk a;}}
  234. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  235. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  236. #endif
  237. #else /* !DEBUG */
  238. #define TRACE(a)
  239. #define TRACE2(a)
  240. #define TRACE3(a)
  241. #endif
  242. #ifdef GDTH_STATISTICS
  243. static ulong32 max_rq=0, max_index=0, max_sg=0;
  244. #ifdef INT_COAL
  245. static ulong32 max_int_coal=0;
  246. #endif
  247. static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  248. static struct timer_list gdth_timer;
  249. #endif
  250. #define PTR2USHORT(a) (ushort)(ulong)(a)
  251. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  252. #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
  253. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  254. #ifdef CONFIG_ISA
  255. static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  256. #endif
  257. #if defined(CONFIG_EISA) || defined(CONFIG_ISA)
  258. static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  259. #endif
  260. static unchar gdth_polling; /* polling if TRUE */
  261. static int gdth_ctr_count = 0; /* controller count */
  262. static LIST_HEAD(gdth_instances); /* controller list */
  263. static unchar gdth_write_through = FALSE; /* write through */
  264. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  265. static int elastidx;
  266. static int eoldidx;
  267. static int major;
  268. #define DIN 1 /* IN data direction */
  269. #define DOU 2 /* OUT data direction */
  270. #define DNO DIN /* no data transfer */
  271. #define DUN DIN /* unknown data direction */
  272. static unchar gdth_direction_tab[0x100] = {
  273. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  274. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  275. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  276. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  277. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  278. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  279. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  280. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  281. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  282. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  283. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  284. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  285. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  286. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  287. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  288. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  289. };
  290. /* LILO and modprobe/insmod parameters */
  291. /* IRQ list for GDT3000/3020 EISA controllers */
  292. static int irq[MAXHA] __initdata =
  293. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  294. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  295. /* disable driver flag */
  296. static int disable __initdata = 0;
  297. /* reserve flag */
  298. static int reserve_mode = 1;
  299. /* reserve list */
  300. static int reserve_list[MAX_RES_ARGS] =
  301. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  302. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  303. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  304. /* scan order for PCI controllers */
  305. static int reverse_scan = 0;
  306. /* virtual channel for the host drives */
  307. static int hdr_channel = 0;
  308. /* max. IDs per channel */
  309. static int max_ids = MAXID;
  310. /* rescan all IDs */
  311. static int rescan = 0;
  312. /* shared access */
  313. static int shared_access = 1;
  314. /* enable support for EISA and ISA controllers */
  315. static int probe_eisa_isa = 0;
  316. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  317. static int force_dma32 = 0;
  318. /* parameters for modprobe/insmod */
  319. module_param_array(irq, int, NULL, 0);
  320. module_param(disable, int, 0);
  321. module_param(reserve_mode, int, 0);
  322. module_param_array(reserve_list, int, NULL, 0);
  323. module_param(reverse_scan, int, 0);
  324. module_param(hdr_channel, int, 0);
  325. module_param(max_ids, int, 0);
  326. module_param(rescan, int, 0);
  327. module_param(shared_access, int, 0);
  328. module_param(probe_eisa_isa, int, 0);
  329. module_param(force_dma32, int, 0);
  330. MODULE_AUTHOR("Achim Leubner");
  331. MODULE_LICENSE("GPL");
  332. /* ioctl interface */
  333. static const struct file_operations gdth_fops = {
  334. .ioctl = gdth_ioctl,
  335. .open = gdth_open,
  336. .release = gdth_close,
  337. };
  338. /*
  339. * gdth scsi_command access wrappers.
  340. * below 6 functions are used throughout the driver to access scsi_command's
  341. * io parameters. The reason we do not use the regular accessors from
  342. * scsi_cmnd.h is because of gdth_execute(). Since it is unrecommended for
  343. * llds to directly set scsi_cmnd's IO members. This driver will use SCp
  344. * members for IO parameters, and will copy scsi_cmnd's members to Scp
  345. * members in queuecommand. For internal commands through gdth_execute()
  346. * SCp's members will be set directly.
  347. */
  348. static inline unsigned gdth_bufflen(struct scsi_cmnd *cmd)
  349. {
  350. return (unsigned)cmd->SCp.this_residual;
  351. }
  352. static inline void gdth_set_bufflen(struct scsi_cmnd *cmd, unsigned bufflen)
  353. {
  354. cmd->SCp.this_residual = bufflen;
  355. }
  356. static inline unsigned gdth_sg_count(struct scsi_cmnd *cmd)
  357. {
  358. return (unsigned)cmd->SCp.buffers_residual;
  359. }
  360. static inline void gdth_set_sg_count(struct scsi_cmnd *cmd, unsigned sg_count)
  361. {
  362. cmd->SCp.buffers_residual = sg_count;
  363. }
  364. static inline struct scatterlist *gdth_sglist(struct scsi_cmnd *cmd)
  365. {
  366. return cmd->SCp.buffer;
  367. }
  368. static inline void gdth_set_sglist(struct scsi_cmnd *cmd,
  369. struct scatterlist *sglist)
  370. {
  371. cmd->SCp.buffer = sglist;
  372. }
  373. #include "gdth_proc.h"
  374. #include "gdth_proc.c"
  375. /* notifier block to get a notify on system shutdown/halt/reboot */
  376. static struct notifier_block gdth_notifier = {
  377. gdth_halt, NULL, 0
  378. };
  379. static int notifier_disabled = 0;
  380. static gdth_ha_str *gdth_find_ha(int hanum)
  381. {
  382. gdth_ha_str *ha;
  383. list_for_each_entry(ha, &gdth_instances, list)
  384. if (hanum == ha->hanum)
  385. return ha;
  386. return NULL;
  387. }
  388. static struct gdth_cmndinfo *gdth_get_cmndinfo(gdth_ha_str *ha)
  389. {
  390. struct gdth_cmndinfo *priv = NULL;
  391. ulong flags;
  392. int i;
  393. spin_lock_irqsave(&ha->smp_lock, flags);
  394. for (i=0; i<GDTH_MAXCMDS; ++i) {
  395. if (ha->cmndinfo[i].index == 0) {
  396. priv = &ha->cmndinfo[i];
  397. priv->index = i+1;
  398. memset(priv, 0, sizeof(*priv));
  399. break;
  400. }
  401. }
  402. spin_unlock_irqrestore(&ha->smp_lock, flags);
  403. return priv;
  404. }
  405. static void gdth_put_cmndinfo(struct gdth_cmndinfo *priv)
  406. {
  407. BUG_ON(!priv);
  408. priv->index = 0;
  409. }
  410. static void gdth_delay(int milliseconds)
  411. {
  412. if (milliseconds == 0) {
  413. udelay(1);
  414. } else {
  415. mdelay(milliseconds);
  416. }
  417. }
  418. static void gdth_scsi_done(struct scsi_cmnd *scp)
  419. {
  420. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  421. int internal_command = cmndinfo->internal_command;
  422. TRACE2(("gdth_scsi_done()\n"));
  423. gdth_put_cmndinfo(cmndinfo);
  424. scp->host_scribble = NULL;
  425. if (internal_command)
  426. complete((struct completion *)scp->request);
  427. else
  428. scp->scsi_done(scp);
  429. }
  430. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  431. int timeout, u32 *info)
  432. {
  433. gdth_ha_str *ha = shost_priv(sdev->host);
  434. Scsi_Cmnd *scp;
  435. struct gdth_cmndinfo cmndinfo;
  436. struct scatterlist one_sg;
  437. DECLARE_COMPLETION_ONSTACK(wait);
  438. int rval;
  439. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  440. if (!scp)
  441. return -ENOMEM;
  442. scp->device = sdev;
  443. memset(&cmndinfo, 0, sizeof(cmndinfo));
  444. /* use request field to save the ptr. to completion struct. */
  445. scp->request = (struct request *)&wait;
  446. scp->timeout_per_command = timeout*HZ;
  447. sg_init_one(&one_sg, gdtcmd, sizeof(*gdtcmd));
  448. gdth_set_sglist(scp, &one_sg);
  449. gdth_set_sg_count(scp, 1);
  450. gdth_set_bufflen(scp, sizeof(*gdtcmd));
  451. scp->cmd_len = 12;
  452. memcpy(scp->cmnd, cmnd, 12);
  453. cmndinfo.priority = IOCTL_PRI;
  454. cmndinfo.internal_command = 1;
  455. TRACE(("__gdth_execute() cmd 0x%x\n", scp->cmnd[0]));
  456. __gdth_queuecommand(ha, scp, &cmndinfo);
  457. wait_for_completion(&wait);
  458. rval = cmndinfo.status;
  459. if (info)
  460. *info = cmndinfo.info;
  461. kfree(scp);
  462. return rval;
  463. }
  464. int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
  465. int timeout, u32 *info)
  466. {
  467. struct scsi_device *sdev = scsi_get_host_dev(shost);
  468. int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
  469. scsi_free_host_dev(sdev);
  470. return rval;
  471. }
  472. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
  473. {
  474. *cyls = size /HEADS/SECS;
  475. if (*cyls <= MAXCYLS) {
  476. *heads = HEADS;
  477. *secs = SECS;
  478. } else { /* too high for 64*32 */
  479. *cyls = size /MEDHEADS/MEDSECS;
  480. if (*cyls <= MAXCYLS) {
  481. *heads = MEDHEADS;
  482. *secs = MEDSECS;
  483. } else { /* too high for 127*63 */
  484. *cyls = size /BIGHEADS/BIGSECS;
  485. *heads = BIGHEADS;
  486. *secs = BIGSECS;
  487. }
  488. }
  489. }
  490. /* controller search and initialization functions */
  491. #ifdef CONFIG_EISA
  492. static int __init gdth_search_eisa(ushort eisa_adr)
  493. {
  494. ulong32 id;
  495. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  496. id = inl(eisa_adr+ID0REG);
  497. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  498. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  499. return 0; /* not EISA configured */
  500. return 1;
  501. }
  502. if (id == GDT3_ID) /* GDT3000 */
  503. return 1;
  504. return 0;
  505. }
  506. #endif /* CONFIG_EISA */
  507. #ifdef CONFIG_ISA
  508. static int __init gdth_search_isa(ulong32 bios_adr)
  509. {
  510. void __iomem *addr;
  511. ulong32 id;
  512. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  513. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
  514. id = readl(addr);
  515. iounmap(addr);
  516. if (id == GDT2_ID) /* GDT2000 */
  517. return 1;
  518. }
  519. return 0;
  520. }
  521. #endif /* CONFIG_ISA */
  522. #ifdef CONFIG_PCI
  523. static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  524. ushort vendor, ushort dev);
  525. static int __init gdth_search_pci(gdth_pci_str *pcistr)
  526. {
  527. ushort device, cnt;
  528. TRACE(("gdth_search_pci()\n"));
  529. cnt = 0;
  530. for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
  531. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  532. for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
  533. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
  534. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  535. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  536. PCI_DEVICE_ID_VORTEX_GDTNEWRX);
  537. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  538. PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
  539. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  540. PCI_DEVICE_ID_INTEL_SRC);
  541. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  542. PCI_DEVICE_ID_INTEL_SRC_XSCALE);
  543. return cnt;
  544. }
  545. /* Vortex only makes RAID controllers.
  546. * We do not really want to specify all 550 ids here, so wildcard match.
  547. */
  548. static struct pci_device_id gdthtable[] __maybe_unused = {
  549. {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
  550. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
  551. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
  552. {0}
  553. };
  554. MODULE_DEVICE_TABLE(pci,gdthtable);
  555. static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  556. ushort vendor, ushort device)
  557. {
  558. ulong base0, base1, base2;
  559. struct pci_dev *pdev;
  560. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  561. *cnt, vendor, device));
  562. pdev = NULL;
  563. while ((pdev = pci_find_device(vendor, device, pdev))
  564. != NULL) {
  565. if (pci_enable_device(pdev))
  566. continue;
  567. if (*cnt >= MAXHA)
  568. return;
  569. /* GDT PCI controller found, resources are already in pdev */
  570. pcistr[*cnt].pdev = pdev;
  571. pcistr[*cnt].irq = pdev->irq;
  572. base0 = pci_resource_flags(pdev, 0);
  573. base1 = pci_resource_flags(pdev, 1);
  574. base2 = pci_resource_flags(pdev, 2);
  575. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  576. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  577. if (!(base0 & IORESOURCE_MEM))
  578. continue;
  579. pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
  580. } else { /* GDT6110, GDT6120, .. */
  581. if (!(base0 & IORESOURCE_MEM) ||
  582. !(base2 & IORESOURCE_MEM) ||
  583. !(base1 & IORESOURCE_IO))
  584. continue;
  585. pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
  586. pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
  587. pcistr[*cnt].io = pci_resource_start(pdev, 1);
  588. }
  589. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  590. pcistr[*cnt].pdev->bus->number,
  591. PCI_SLOT(pcistr[*cnt].pdev->devfn),
  592. pcistr[*cnt].irq, pcistr[*cnt].dpmem));
  593. (*cnt)++;
  594. }
  595. }
  596. static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
  597. {
  598. gdth_pci_str temp;
  599. int i, changed;
  600. TRACE(("gdth_sort_pci() cnt %d\n",cnt));
  601. if (cnt == 0)
  602. return;
  603. do {
  604. changed = FALSE;
  605. for (i = 0; i < cnt-1; ++i) {
  606. if (!reverse_scan) {
  607. if ((pcistr[i].pdev->bus->number > pcistr[i+1].pdev->bus->number) ||
  608. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  609. PCI_SLOT(pcistr[i].pdev->devfn) >
  610. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  611. temp = pcistr[i];
  612. pcistr[i] = pcistr[i+1];
  613. pcistr[i+1] = temp;
  614. changed = TRUE;
  615. }
  616. } else {
  617. if ((pcistr[i].pdev->bus->number < pcistr[i+1].pdev->bus->number) ||
  618. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  619. PCI_SLOT(pcistr[i].pdev->devfn) <
  620. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  621. temp = pcistr[i];
  622. pcistr[i] = pcistr[i+1];
  623. pcistr[i+1] = temp;
  624. changed = TRUE;
  625. }
  626. }
  627. }
  628. } while (changed);
  629. }
  630. #endif /* CONFIG_PCI */
  631. #ifdef CONFIG_EISA
  632. static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
  633. {
  634. ulong32 retries,id;
  635. unchar prot_ver,eisacf,i,irq_found;
  636. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  637. /* disable board interrupts, deinitialize services */
  638. outb(0xff,eisa_adr+EDOORREG);
  639. outb(0x00,eisa_adr+EDENABREG);
  640. outb(0x00,eisa_adr+EINTENABREG);
  641. outb(0xff,eisa_adr+LDOORREG);
  642. retries = INIT_RETRIES;
  643. gdth_delay(20);
  644. while (inb(eisa_adr+EDOORREG) != 0xff) {
  645. if (--retries == 0) {
  646. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  647. return 0;
  648. }
  649. gdth_delay(1);
  650. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  651. }
  652. prot_ver = inb(eisa_adr+MAILBOXREG);
  653. outb(0xff,eisa_adr+EDOORREG);
  654. if (prot_ver != PROTOCOL_VERSION) {
  655. printk("GDT-EISA: Illegal protocol version\n");
  656. return 0;
  657. }
  658. ha->bmic = eisa_adr;
  659. ha->brd_phys = (ulong32)eisa_adr >> 12;
  660. outl(0,eisa_adr+MAILBOXREG);
  661. outl(0,eisa_adr+MAILBOXREG+4);
  662. outl(0,eisa_adr+MAILBOXREG+8);
  663. outl(0,eisa_adr+MAILBOXREG+12);
  664. /* detect IRQ */
  665. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  666. ha->oem_id = OEM_ID_ICP;
  667. ha->type = GDT_EISA;
  668. ha->stype = id;
  669. outl(1,eisa_adr+MAILBOXREG+8);
  670. outb(0xfe,eisa_adr+LDOORREG);
  671. retries = INIT_RETRIES;
  672. gdth_delay(20);
  673. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  674. if (--retries == 0) {
  675. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  676. return 0;
  677. }
  678. gdth_delay(1);
  679. }
  680. ha->irq = inb(eisa_adr+MAILBOXREG);
  681. outb(0xff,eisa_adr+EDOORREG);
  682. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  683. /* check the result */
  684. if (ha->irq == 0) {
  685. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  686. for (i = 0, irq_found = FALSE;
  687. i < MAXHA && irq[i] != 0xff; ++i) {
  688. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  689. irq_found = TRUE;
  690. break;
  691. }
  692. }
  693. if (irq_found) {
  694. ha->irq = irq[i];
  695. irq[i] = 0;
  696. printk("GDT-EISA: Can not detect controller IRQ,\n");
  697. printk("Use IRQ setting from command line (IRQ = %d)\n",
  698. ha->irq);
  699. } else {
  700. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  701. printk("the controller BIOS or use command line parameters\n");
  702. return 0;
  703. }
  704. }
  705. } else {
  706. eisacf = inb(eisa_adr+EISAREG) & 7;
  707. if (eisacf > 4) /* level triggered */
  708. eisacf -= 4;
  709. ha->irq = gdth_irq_tab[eisacf];
  710. ha->oem_id = OEM_ID_ICP;
  711. ha->type = GDT_EISA;
  712. ha->stype = id;
  713. }
  714. ha->dma64_support = 0;
  715. return 1;
  716. }
  717. #endif /* CONFIG_EISA */
  718. #ifdef CONFIG_ISA
  719. static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
  720. {
  721. register gdt2_dpram_str __iomem *dp2_ptr;
  722. int i;
  723. unchar irq_drq,prot_ver;
  724. ulong32 retries;
  725. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  726. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  727. if (ha->brd == NULL) {
  728. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  729. return 0;
  730. }
  731. dp2_ptr = ha->brd;
  732. writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  733. /* reset interface area */
  734. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  735. if (readl(&dp2_ptr->u) != 0) {
  736. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  737. iounmap(ha->brd);
  738. return 0;
  739. }
  740. /* disable board interrupts, read DRQ and IRQ */
  741. writeb(0xff, &dp2_ptr->io.irqdel);
  742. writeb(0x00, &dp2_ptr->io.irqen);
  743. writeb(0x00, &dp2_ptr->u.ic.S_Status);
  744. writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  745. irq_drq = readb(&dp2_ptr->io.rq);
  746. for (i=0; i<3; ++i) {
  747. if ((irq_drq & 1)==0)
  748. break;
  749. irq_drq >>= 1;
  750. }
  751. ha->drq = gdth_drq_tab[i];
  752. irq_drq = readb(&dp2_ptr->io.rq) >> 3;
  753. for (i=1; i<5; ++i) {
  754. if ((irq_drq & 1)==0)
  755. break;
  756. irq_drq >>= 1;
  757. }
  758. ha->irq = gdth_irq_tab[i];
  759. /* deinitialize services */
  760. writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  761. writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  762. writeb(0, &dp2_ptr->io.event);
  763. retries = INIT_RETRIES;
  764. gdth_delay(20);
  765. while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  766. if (--retries == 0) {
  767. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  768. iounmap(ha->brd);
  769. return 0;
  770. }
  771. gdth_delay(1);
  772. }
  773. prot_ver = (unchar)readl(&dp2_ptr->u.ic.S_Info[0]);
  774. writeb(0, &dp2_ptr->u.ic.Status);
  775. writeb(0xff, &dp2_ptr->io.irqdel);
  776. if (prot_ver != PROTOCOL_VERSION) {
  777. printk("GDT-ISA: Illegal protocol version\n");
  778. iounmap(ha->brd);
  779. return 0;
  780. }
  781. ha->oem_id = OEM_ID_ICP;
  782. ha->type = GDT_ISA;
  783. ha->ic_all_size = sizeof(dp2_ptr->u);
  784. ha->stype= GDT2_ID;
  785. ha->brd_phys = bios_adr >> 4;
  786. /* special request to controller BIOS */
  787. writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  788. writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  789. writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  790. writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  791. writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  792. writeb(0, &dp2_ptr->io.event);
  793. retries = INIT_RETRIES;
  794. gdth_delay(20);
  795. while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  796. if (--retries == 0) {
  797. printk("GDT-ISA: Initialization error\n");
  798. iounmap(ha->brd);
  799. return 0;
  800. }
  801. gdth_delay(1);
  802. }
  803. writeb(0, &dp2_ptr->u.ic.Status);
  804. writeb(0xff, &dp2_ptr->io.irqdel);
  805. ha->dma64_support = 0;
  806. return 1;
  807. }
  808. #endif /* CONFIG_ISA */
  809. #ifdef CONFIG_PCI
  810. static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
  811. {
  812. register gdt6_dpram_str __iomem *dp6_ptr;
  813. register gdt6c_dpram_str __iomem *dp6c_ptr;
  814. register gdt6m_dpram_str __iomem *dp6m_ptr;
  815. ulong32 retries;
  816. unchar prot_ver;
  817. ushort command;
  818. int i, found = FALSE;
  819. TRACE(("gdth_init_pci()\n"));
  820. if (pcistr->pdev->vendor == PCI_VENDOR_ID_INTEL)
  821. ha->oem_id = OEM_ID_INTEL;
  822. else
  823. ha->oem_id = OEM_ID_ICP;
  824. ha->brd_phys = (pcistr->pdev->bus->number << 8) | (pcistr->pdev->devfn & 0xf8);
  825. ha->stype = (ulong32)pcistr->pdev->device;
  826. ha->irq = pcistr->irq;
  827. ha->pdev = pcistr->pdev;
  828. if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  829. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  830. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  831. if (ha->brd == NULL) {
  832. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  833. return 0;
  834. }
  835. /* check and reset interface area */
  836. dp6_ptr = ha->brd;
  837. writel(DPMEM_MAGIC, &dp6_ptr->u);
  838. if (readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  839. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  840. pcistr->dpmem);
  841. found = FALSE;
  842. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  843. iounmap(ha->brd);
  844. ha->brd = ioremap(i, sizeof(ushort));
  845. if (ha->brd == NULL) {
  846. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  847. return 0;
  848. }
  849. if (readw(ha->brd) != 0xffff) {
  850. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  851. continue;
  852. }
  853. iounmap(ha->brd);
  854. pci_write_config_dword(pcistr->pdev,
  855. PCI_BASE_ADDRESS_0, i);
  856. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  857. if (ha->brd == NULL) {
  858. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  859. return 0;
  860. }
  861. dp6_ptr = ha->brd;
  862. writel(DPMEM_MAGIC, &dp6_ptr->u);
  863. if (readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  864. printk("GDT-PCI: Use free address at 0x%x\n", i);
  865. found = TRUE;
  866. break;
  867. }
  868. }
  869. if (!found) {
  870. printk("GDT-PCI: No free address found!\n");
  871. iounmap(ha->brd);
  872. return 0;
  873. }
  874. }
  875. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  876. if (readl(&dp6_ptr->u) != 0) {
  877. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  878. iounmap(ha->brd);
  879. return 0;
  880. }
  881. /* disable board interrupts, deinit services */
  882. writeb(0xff, &dp6_ptr->io.irqdel);
  883. writeb(0x00, &dp6_ptr->io.irqen);
  884. writeb(0x00, &dp6_ptr->u.ic.S_Status);
  885. writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  886. writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  887. writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  888. writeb(0, &dp6_ptr->io.event);
  889. retries = INIT_RETRIES;
  890. gdth_delay(20);
  891. while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  892. if (--retries == 0) {
  893. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  894. iounmap(ha->brd);
  895. return 0;
  896. }
  897. gdth_delay(1);
  898. }
  899. prot_ver = (unchar)readl(&dp6_ptr->u.ic.S_Info[0]);
  900. writeb(0, &dp6_ptr->u.ic.S_Status);
  901. writeb(0xff, &dp6_ptr->io.irqdel);
  902. if (prot_ver != PROTOCOL_VERSION) {
  903. printk("GDT-PCI: Illegal protocol version\n");
  904. iounmap(ha->brd);
  905. return 0;
  906. }
  907. ha->type = GDT_PCI;
  908. ha->ic_all_size = sizeof(dp6_ptr->u);
  909. /* special command to controller BIOS */
  910. writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  911. writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  912. writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  913. writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  914. writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  915. writeb(0, &dp6_ptr->io.event);
  916. retries = INIT_RETRIES;
  917. gdth_delay(20);
  918. while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  919. if (--retries == 0) {
  920. printk("GDT-PCI: Initialization error\n");
  921. iounmap(ha->brd);
  922. return 0;
  923. }
  924. gdth_delay(1);
  925. }
  926. writeb(0, &dp6_ptr->u.ic.S_Status);
  927. writeb(0xff, &dp6_ptr->io.irqdel);
  928. ha->dma64_support = 0;
  929. } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  930. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  931. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  932. pcistr->dpmem,ha->irq));
  933. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  934. if (ha->brd == NULL) {
  935. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  936. iounmap(ha->brd);
  937. return 0;
  938. }
  939. /* check and reset interface area */
  940. dp6c_ptr = ha->brd;
  941. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  942. if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  943. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  944. pcistr->dpmem);
  945. found = FALSE;
  946. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  947. iounmap(ha->brd);
  948. ha->brd = ioremap(i, sizeof(ushort));
  949. if (ha->brd == NULL) {
  950. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  951. return 0;
  952. }
  953. if (readw(ha->brd) != 0xffff) {
  954. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  955. continue;
  956. }
  957. iounmap(ha->brd);
  958. pci_write_config_dword(pcistr->pdev,
  959. PCI_BASE_ADDRESS_2, i);
  960. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  961. if (ha->brd == NULL) {
  962. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  963. return 0;
  964. }
  965. dp6c_ptr = ha->brd;
  966. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  967. if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  968. printk("GDT-PCI: Use free address at 0x%x\n", i);
  969. found = TRUE;
  970. break;
  971. }
  972. }
  973. if (!found) {
  974. printk("GDT-PCI: No free address found!\n");
  975. iounmap(ha->brd);
  976. return 0;
  977. }
  978. }
  979. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  980. if (readl(&dp6c_ptr->u) != 0) {
  981. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  982. iounmap(ha->brd);
  983. return 0;
  984. }
  985. /* disable board interrupts, deinit services */
  986. outb(0x00,PTR2USHORT(&ha->plx->control1));
  987. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  988. writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  989. writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  990. writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  991. writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  992. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  993. retries = INIT_RETRIES;
  994. gdth_delay(20);
  995. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  996. if (--retries == 0) {
  997. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  998. iounmap(ha->brd);
  999. return 0;
  1000. }
  1001. gdth_delay(1);
  1002. }
  1003. prot_ver = (unchar)readl(&dp6c_ptr->u.ic.S_Info[0]);
  1004. writeb(0, &dp6c_ptr->u.ic.Status);
  1005. if (prot_ver != PROTOCOL_VERSION) {
  1006. printk("GDT-PCI: Illegal protocol version\n");
  1007. iounmap(ha->brd);
  1008. return 0;
  1009. }
  1010. ha->type = GDT_PCINEW;
  1011. ha->ic_all_size = sizeof(dp6c_ptr->u);
  1012. /* special command to controller BIOS */
  1013. writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  1014. writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  1015. writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  1016. writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  1017. writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  1018. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  1019. retries = INIT_RETRIES;
  1020. gdth_delay(20);
  1021. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  1022. if (--retries == 0) {
  1023. printk("GDT-PCI: Initialization error\n");
  1024. iounmap(ha->brd);
  1025. return 0;
  1026. }
  1027. gdth_delay(1);
  1028. }
  1029. writeb(0, &dp6c_ptr->u.ic.S_Status);
  1030. ha->dma64_support = 0;
  1031. } else { /* MPR */
  1032. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  1033. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  1034. if (ha->brd == NULL) {
  1035. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1036. return 0;
  1037. }
  1038. /* manipulate config. space to enable DPMEM, start RP controller */
  1039. pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
  1040. command |= 6;
  1041. pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
  1042. if (pci_resource_start(pcistr->pdev, 8) == 1UL)
  1043. pci_resource_start(pcistr->pdev, 8) = 0UL;
  1044. i = 0xFEFF0001UL;
  1045. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
  1046. gdth_delay(1);
  1047. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
  1048. pci_resource_start(pcistr->pdev, 8));
  1049. dp6m_ptr = ha->brd;
  1050. /* Ensure that it is safe to access the non HW portions of DPMEM.
  1051. * Aditional check needed for Xscale based RAID controllers */
  1052. while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  1053. gdth_delay(1);
  1054. /* check and reset interface area */
  1055. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1056. if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  1057. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1058. pcistr->dpmem);
  1059. found = FALSE;
  1060. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1061. iounmap(ha->brd);
  1062. ha->brd = ioremap(i, sizeof(ushort));
  1063. if (ha->brd == NULL) {
  1064. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1065. return 0;
  1066. }
  1067. if (readw(ha->brd) != 0xffff) {
  1068. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1069. continue;
  1070. }
  1071. iounmap(ha->brd);
  1072. pci_write_config_dword(pcistr->pdev,
  1073. PCI_BASE_ADDRESS_0, i);
  1074. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1075. if (ha->brd == NULL) {
  1076. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1077. return 0;
  1078. }
  1079. dp6m_ptr = ha->brd;
  1080. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1081. if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1082. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1083. found = TRUE;
  1084. break;
  1085. }
  1086. }
  1087. if (!found) {
  1088. printk("GDT-PCI: No free address found!\n");
  1089. iounmap(ha->brd);
  1090. return 0;
  1091. }
  1092. }
  1093. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1094. /* disable board interrupts, deinit services */
  1095. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1096. &dp6m_ptr->i960r.edoor_en_reg);
  1097. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1098. writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1099. writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1100. writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1101. writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1102. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1103. retries = INIT_RETRIES;
  1104. gdth_delay(20);
  1105. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1106. if (--retries == 0) {
  1107. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1108. iounmap(ha->brd);
  1109. return 0;
  1110. }
  1111. gdth_delay(1);
  1112. }
  1113. prot_ver = (unchar)readl(&dp6m_ptr->u.ic.S_Info[0]);
  1114. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1115. if (prot_ver != PROTOCOL_VERSION) {
  1116. printk("GDT-PCI: Illegal protocol version\n");
  1117. iounmap(ha->brd);
  1118. return 0;
  1119. }
  1120. ha->type = GDT_PCIMPR;
  1121. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1122. /* special command to controller BIOS */
  1123. writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1124. writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1125. writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1126. writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1127. writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1128. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1129. retries = INIT_RETRIES;
  1130. gdth_delay(20);
  1131. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1132. if (--retries == 0) {
  1133. printk("GDT-PCI: Initialization error\n");
  1134. iounmap(ha->brd);
  1135. return 0;
  1136. }
  1137. gdth_delay(1);
  1138. }
  1139. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1140. /* read FW version to detect 64-bit DMA support */
  1141. writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1142. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1143. retries = INIT_RETRIES;
  1144. gdth_delay(20);
  1145. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1146. if (--retries == 0) {
  1147. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1148. iounmap(ha->brd);
  1149. return 0;
  1150. }
  1151. gdth_delay(1);
  1152. }
  1153. prot_ver = (unchar)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1154. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1155. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1156. ha->dma64_support = 0;
  1157. else
  1158. ha->dma64_support = 1;
  1159. }
  1160. return 1;
  1161. }
  1162. #endif /* CONFIG_PCI */
  1163. /* controller protocol functions */
  1164. static void __init gdth_enable_int(gdth_ha_str *ha)
  1165. {
  1166. ulong flags;
  1167. gdt2_dpram_str __iomem *dp2_ptr;
  1168. gdt6_dpram_str __iomem *dp6_ptr;
  1169. gdt6m_dpram_str __iomem *dp6m_ptr;
  1170. TRACE(("gdth_enable_int() hanum %d\n",ha->hanum));
  1171. spin_lock_irqsave(&ha->smp_lock, flags);
  1172. if (ha->type == GDT_EISA) {
  1173. outb(0xff, ha->bmic + EDOORREG);
  1174. outb(0xff, ha->bmic + EDENABREG);
  1175. outb(0x01, ha->bmic + EINTENABREG);
  1176. } else if (ha->type == GDT_ISA) {
  1177. dp2_ptr = ha->brd;
  1178. writeb(1, &dp2_ptr->io.irqdel);
  1179. writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1180. writeb(1, &dp2_ptr->io.irqen);
  1181. } else if (ha->type == GDT_PCI) {
  1182. dp6_ptr = ha->brd;
  1183. writeb(1, &dp6_ptr->io.irqdel);
  1184. writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1185. writeb(1, &dp6_ptr->io.irqen);
  1186. } else if (ha->type == GDT_PCINEW) {
  1187. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1188. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1189. } else if (ha->type == GDT_PCIMPR) {
  1190. dp6m_ptr = ha->brd;
  1191. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1192. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1193. &dp6m_ptr->i960r.edoor_en_reg);
  1194. }
  1195. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1196. }
  1197. /* return IStatus if interrupt was from this card else 0 */
  1198. static unchar gdth_get_status(gdth_ha_str *ha)
  1199. {
  1200. unchar IStatus = 0;
  1201. TRACE(("gdth_get_status() irq %d ctr_count %d\n", ha->irq, gdth_ctr_count));
  1202. if (ha->type == GDT_EISA)
  1203. IStatus = inb((ushort)ha->bmic + EDOORREG);
  1204. else if (ha->type == GDT_ISA)
  1205. IStatus =
  1206. readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1207. else if (ha->type == GDT_PCI)
  1208. IStatus =
  1209. readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1210. else if (ha->type == GDT_PCINEW)
  1211. IStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1212. else if (ha->type == GDT_PCIMPR)
  1213. IStatus =
  1214. readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1215. return IStatus;
  1216. }
  1217. static int gdth_test_busy(gdth_ha_str *ha)
  1218. {
  1219. register int gdtsema0 = 0;
  1220. TRACE(("gdth_test_busy() hanum %d\n", ha->hanum));
  1221. if (ha->type == GDT_EISA)
  1222. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1223. else if (ha->type == GDT_ISA)
  1224. gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1225. else if (ha->type == GDT_PCI)
  1226. gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1227. else if (ha->type == GDT_PCINEW)
  1228. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1229. else if (ha->type == GDT_PCIMPR)
  1230. gdtsema0 =
  1231. (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1232. return (gdtsema0 & 1);
  1233. }
  1234. static int gdth_get_cmd_index(gdth_ha_str *ha)
  1235. {
  1236. int i;
  1237. TRACE(("gdth_get_cmd_index() hanum %d\n", ha->hanum));
  1238. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1239. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1240. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1241. ha->cmd_tab[i].service = ha->pccb->Service;
  1242. ha->pccb->CommandIndex = (ulong32)i+2;
  1243. return (i+2);
  1244. }
  1245. }
  1246. return 0;
  1247. }
  1248. static void gdth_set_sema0(gdth_ha_str *ha)
  1249. {
  1250. TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum));
  1251. if (ha->type == GDT_EISA) {
  1252. outb(1, ha->bmic + SEMA0REG);
  1253. } else if (ha->type == GDT_ISA) {
  1254. writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1255. } else if (ha->type == GDT_PCI) {
  1256. writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1257. } else if (ha->type == GDT_PCINEW) {
  1258. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1259. } else if (ha->type == GDT_PCIMPR) {
  1260. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1261. }
  1262. }
  1263. static void gdth_copy_command(gdth_ha_str *ha)
  1264. {
  1265. register gdth_cmd_str *cmd_ptr;
  1266. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1267. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1268. gdt6_dpram_str __iomem *dp6_ptr;
  1269. gdt2_dpram_str __iomem *dp2_ptr;
  1270. ushort cp_count,dp_offset,cmd_no;
  1271. TRACE(("gdth_copy_command() hanum %d\n", ha->hanum));
  1272. cp_count = ha->cmd_len;
  1273. dp_offset= ha->cmd_offs_dpmem;
  1274. cmd_no = ha->cmd_cnt;
  1275. cmd_ptr = ha->pccb;
  1276. ++ha->cmd_cnt;
  1277. if (ha->type == GDT_EISA)
  1278. return; /* no DPMEM, no copy */
  1279. /* set cpcount dword aligned */
  1280. if (cp_count & 3)
  1281. cp_count += (4 - (cp_count & 3));
  1282. ha->cmd_offs_dpmem += cp_count;
  1283. /* set offset and service, copy command to DPMEM */
  1284. if (ha->type == GDT_ISA) {
  1285. dp2_ptr = ha->brd;
  1286. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1287. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1288. writew((ushort)cmd_ptr->Service,
  1289. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1290. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1291. } else if (ha->type == GDT_PCI) {
  1292. dp6_ptr = ha->brd;
  1293. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1294. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1295. writew((ushort)cmd_ptr->Service,
  1296. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1297. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1298. } else if (ha->type == GDT_PCINEW) {
  1299. dp6c_ptr = ha->brd;
  1300. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1301. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1302. writew((ushort)cmd_ptr->Service,
  1303. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1304. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1305. } else if (ha->type == GDT_PCIMPR) {
  1306. dp6m_ptr = ha->brd;
  1307. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1308. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1309. writew((ushort)cmd_ptr->Service,
  1310. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1311. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1312. }
  1313. }
  1314. static void gdth_release_event(gdth_ha_str *ha)
  1315. {
  1316. TRACE(("gdth_release_event() hanum %d\n", ha->hanum));
  1317. #ifdef GDTH_STATISTICS
  1318. {
  1319. ulong32 i,j;
  1320. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1321. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1322. ++i;
  1323. }
  1324. if (max_index < i) {
  1325. max_index = i;
  1326. TRACE3(("GDT: max_index = %d\n",(ushort)i));
  1327. }
  1328. }
  1329. #endif
  1330. if (ha->pccb->OpCode == GDT_INIT)
  1331. ha->pccb->Service |= 0x80;
  1332. if (ha->type == GDT_EISA) {
  1333. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1334. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1335. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1336. } else if (ha->type == GDT_ISA) {
  1337. writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1338. } else if (ha->type == GDT_PCI) {
  1339. writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1340. } else if (ha->type == GDT_PCINEW) {
  1341. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1342. } else if (ha->type == GDT_PCIMPR) {
  1343. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1344. }
  1345. }
  1346. static int gdth_wait(gdth_ha_str *ha, int index, ulong32 time)
  1347. {
  1348. int answer_found = FALSE;
  1349. int wait_index = 0;
  1350. TRACE(("gdth_wait() hanum %d index %d time %d\n", ha->hanum, index, time));
  1351. if (index == 0)
  1352. return 1; /* no wait required */
  1353. do {
  1354. __gdth_interrupt(ha, true, &wait_index);
  1355. if (wait_index == index) {
  1356. answer_found = TRUE;
  1357. break;
  1358. }
  1359. gdth_delay(1);
  1360. } while (--time);
  1361. while (gdth_test_busy(ha))
  1362. gdth_delay(0);
  1363. return (answer_found);
  1364. }
  1365. static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
  1366. ulong32 p1, ulong64 p2, ulong64 p3)
  1367. {
  1368. register gdth_cmd_str *cmd_ptr;
  1369. int retries,index;
  1370. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1371. cmd_ptr = ha->pccb;
  1372. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1373. /* make command */
  1374. for (retries = INIT_RETRIES;;) {
  1375. cmd_ptr->Service = service;
  1376. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1377. if (!(index=gdth_get_cmd_index(ha))) {
  1378. TRACE(("GDT: No free command index found\n"));
  1379. return 0;
  1380. }
  1381. gdth_set_sema0(ha);
  1382. cmd_ptr->OpCode = opcode;
  1383. cmd_ptr->BoardNode = LOCALBOARD;
  1384. if (service == CACHESERVICE) {
  1385. if (opcode == GDT_IOCTL) {
  1386. cmd_ptr->u.ioctl.subfunc = p1;
  1387. cmd_ptr->u.ioctl.channel = (ulong32)p2;
  1388. cmd_ptr->u.ioctl.param_size = (ushort)p3;
  1389. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1390. } else {
  1391. if (ha->cache_feat & GDT_64BIT) {
  1392. cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
  1393. cmd_ptr->u.cache64.BlockNo = p2;
  1394. } else {
  1395. cmd_ptr->u.cache.DeviceNo = (ushort)p1;
  1396. cmd_ptr->u.cache.BlockNo = (ulong32)p2;
  1397. }
  1398. }
  1399. } else if (service == SCSIRAWSERVICE) {
  1400. if (ha->raw_feat & GDT_64BIT) {
  1401. cmd_ptr->u.raw64.direction = p1;
  1402. cmd_ptr->u.raw64.bus = (unchar)p2;
  1403. cmd_ptr->u.raw64.target = (unchar)p3;
  1404. cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
  1405. } else {
  1406. cmd_ptr->u.raw.direction = p1;
  1407. cmd_ptr->u.raw.bus = (unchar)p2;
  1408. cmd_ptr->u.raw.target = (unchar)p3;
  1409. cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
  1410. }
  1411. } else if (service == SCREENSERVICE) {
  1412. if (opcode == GDT_REALTIME) {
  1413. *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1414. *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
  1415. *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
  1416. }
  1417. }
  1418. ha->cmd_len = sizeof(gdth_cmd_str);
  1419. ha->cmd_offs_dpmem = 0;
  1420. ha->cmd_cnt = 0;
  1421. gdth_copy_command(ha);
  1422. gdth_release_event(ha);
  1423. gdth_delay(20);
  1424. if (!gdth_wait(ha, index, INIT_TIMEOUT)) {
  1425. printk("GDT: Initialization error (timeout service %d)\n",service);
  1426. return 0;
  1427. }
  1428. if (ha->status != S_BSY || --retries == 0)
  1429. break;
  1430. gdth_delay(1);
  1431. }
  1432. return (ha->status != S_OK ? 0:1);
  1433. }
  1434. /* search for devices */
  1435. static int __init gdth_search_drives(gdth_ha_str *ha)
  1436. {
  1437. ushort cdev_cnt, i;
  1438. int ok;
  1439. ulong32 bus_no, drv_cnt, drv_no, j;
  1440. gdth_getch_str *chn;
  1441. gdth_drlist_str *drl;
  1442. gdth_iochan_str *ioc;
  1443. gdth_raw_iochan_str *iocr;
  1444. gdth_arcdl_str *alst;
  1445. gdth_alist_str *alst2;
  1446. gdth_oem_str_ioctl *oemstr;
  1447. #ifdef INT_COAL
  1448. gdth_perf_modes *pmod;
  1449. #endif
  1450. #ifdef GDTH_RTC
  1451. unchar rtc[12];
  1452. ulong flags;
  1453. #endif
  1454. TRACE(("gdth_search_drives() hanum %d\n", ha->hanum));
  1455. ok = 0;
  1456. /* initialize controller services, at first: screen service */
  1457. ha->screen_feat = 0;
  1458. if (!force_dma32) {
  1459. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_X_INIT_SCR, 0, 0, 0);
  1460. if (ok)
  1461. ha->screen_feat = GDT_64BIT;
  1462. }
  1463. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1464. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_INIT, 0, 0, 0);
  1465. if (!ok) {
  1466. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1467. ha->hanum, ha->status);
  1468. return 0;
  1469. }
  1470. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1471. #ifdef GDTH_RTC
  1472. /* read realtime clock info, send to controller */
  1473. /* 1. wait for the falling edge of update flag */
  1474. spin_lock_irqsave(&rtc_lock, flags);
  1475. for (j = 0; j < 1000000; ++j)
  1476. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1477. break;
  1478. for (j = 0; j < 1000000; ++j)
  1479. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1480. break;
  1481. /* 2. read info */
  1482. do {
  1483. for (j = 0; j < 12; ++j)
  1484. rtc[j] = CMOS_READ(j);
  1485. } while (rtc[0] != CMOS_READ(0));
  1486. spin_unlock_irqrestore(&rtc_lock, flags);
  1487. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
  1488. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
  1489. /* 3. send to controller firmware */
  1490. gdth_internal_cmd(ha, SCREENSERVICE, GDT_REALTIME, *(ulong32 *)&rtc[0],
  1491. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
  1492. #endif
  1493. /* unfreeze all IOs */
  1494. gdth_internal_cmd(ha, CACHESERVICE, GDT_UNFREEZE_IO, 0, 0, 0);
  1495. /* initialize cache service */
  1496. ha->cache_feat = 0;
  1497. if (!force_dma32) {
  1498. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INIT_HOST, LINUX_OS,
  1499. 0, 0);
  1500. if (ok)
  1501. ha->cache_feat = GDT_64BIT;
  1502. }
  1503. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1504. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_INIT, LINUX_OS, 0, 0);
  1505. if (!ok) {
  1506. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1507. ha->hanum, ha->status);
  1508. return 0;
  1509. }
  1510. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1511. cdev_cnt = (ushort)ha->info;
  1512. ha->fw_vers = ha->service;
  1513. #ifdef INT_COAL
  1514. if (ha->type == GDT_PCIMPR) {
  1515. /* set perf. modes */
  1516. pmod = (gdth_perf_modes *)ha->pscratch;
  1517. pmod->version = 1;
  1518. pmod->st_mode = 1; /* enable one status buffer */
  1519. *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1520. pmod->st_buff_indx1 = COALINDEX;
  1521. pmod->st_buff_addr2 = 0;
  1522. pmod->st_buff_u_addr2 = 0;
  1523. pmod->st_buff_indx2 = 0;
  1524. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1525. pmod->cmd_mode = 0; // disable all cmd buffers
  1526. pmod->cmd_buff_addr1 = 0;
  1527. pmod->cmd_buff_u_addr1 = 0;
  1528. pmod->cmd_buff_indx1 = 0;
  1529. pmod->cmd_buff_addr2 = 0;
  1530. pmod->cmd_buff_u_addr2 = 0;
  1531. pmod->cmd_buff_indx2 = 0;
  1532. pmod->cmd_buff_size = 0;
  1533. pmod->reserved1 = 0;
  1534. pmod->reserved2 = 0;
  1535. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SET_PERF_MODES,
  1536. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1537. printk("GDT-HA %d: Interrupt coalescing activated\n", ha->hanum);
  1538. }
  1539. }
  1540. #endif
  1541. /* detect number of buses - try new IOCTL */
  1542. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1543. iocr->hdr.version = 0xffffffff;
  1544. iocr->hdr.list_entries = MAXBUS;
  1545. iocr->hdr.first_chan = 0;
  1546. iocr->hdr.last_chan = MAXBUS-1;
  1547. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1548. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_RAW_DESC,
  1549. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1550. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1551. ha->bus_cnt = iocr->hdr.chan_count;
  1552. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1553. if (iocr->list[bus_no].proc_id < MAXID)
  1554. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1555. else
  1556. ha->bus_id[bus_no] = 0xff;
  1557. }
  1558. } else {
  1559. /* old method */
  1560. chn = (gdth_getch_str *)ha->pscratch;
  1561. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1562. chn->channel_no = bus_no;
  1563. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1564. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1565. IO_CHANNEL | INVALID_CHANNEL,
  1566. sizeof(gdth_getch_str))) {
  1567. if (bus_no == 0) {
  1568. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1569. ha->hanum, ha->status);
  1570. return 0;
  1571. }
  1572. break;
  1573. }
  1574. if (chn->siop_id < MAXID)
  1575. ha->bus_id[bus_no] = chn->siop_id;
  1576. else
  1577. ha->bus_id[bus_no] = 0xff;
  1578. }
  1579. ha->bus_cnt = (unchar)bus_no;
  1580. }
  1581. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1582. /* read cache configuration */
  1583. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_INFO,
  1584. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1585. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1586. ha->hanum, ha->status);
  1587. return 0;
  1588. }
  1589. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1590. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1591. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1592. ha->cpar.write_back,ha->cpar.block_size));
  1593. /* read board info and features */
  1594. ha->more_proc = FALSE;
  1595. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_INFO,
  1596. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1597. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1598. sizeof(gdth_binfo_str));
  1599. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_FEATURES,
  1600. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1601. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1602. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1603. ha->more_proc = TRUE;
  1604. }
  1605. } else {
  1606. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1607. strcpy(ha->binfo.type_string, gdth_ctr_name(ha));
  1608. }
  1609. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1610. /* read more informations */
  1611. if (ha->more_proc) {
  1612. /* physical drives, channel addresses */
  1613. ioc = (gdth_iochan_str *)ha->pscratch;
  1614. ioc->hdr.version = 0xffffffff;
  1615. ioc->hdr.list_entries = MAXBUS;
  1616. ioc->hdr.first_chan = 0;
  1617. ioc->hdr.last_chan = MAXBUS-1;
  1618. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1619. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_DESC,
  1620. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1621. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1622. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1623. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1624. }
  1625. } else {
  1626. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1627. ha->raw[bus_no].address = IO_CHANNEL;
  1628. ha->raw[bus_no].local_no = bus_no;
  1629. }
  1630. }
  1631. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1632. chn = (gdth_getch_str *)ha->pscratch;
  1633. chn->channel_no = ha->raw[bus_no].local_no;
  1634. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1635. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1636. ha->raw[bus_no].address | INVALID_CHANNEL,
  1637. sizeof(gdth_getch_str))) {
  1638. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1639. TRACE2(("Channel %d: %d phys. drives\n",
  1640. bus_no,chn->drive_cnt));
  1641. }
  1642. if (ha->raw[bus_no].pdev_cnt > 0) {
  1643. drl = (gdth_drlist_str *)ha->pscratch;
  1644. drl->sc_no = ha->raw[bus_no].local_no;
  1645. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1646. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1647. SCSI_DR_LIST | L_CTRL_PATTERN,
  1648. ha->raw[bus_no].address | INVALID_CHANNEL,
  1649. sizeof(gdth_drlist_str))) {
  1650. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1651. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1652. } else {
  1653. ha->raw[bus_no].pdev_cnt = 0;
  1654. }
  1655. }
  1656. }
  1657. /* logical drives */
  1658. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_CNT,
  1659. INVALID_CHANNEL,sizeof(ulong32))) {
  1660. drv_cnt = *(ulong32 *)ha->pscratch;
  1661. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_LIST,
  1662. INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
  1663. for (j = 0; j < drv_cnt; ++j) {
  1664. drv_no = ((ulong32 *)ha->pscratch)[j];
  1665. if (drv_no < MAX_LDRIVES) {
  1666. ha->hdr[drv_no].is_logdrv = TRUE;
  1667. TRACE2(("Drive %d is log. drive\n",drv_no));
  1668. }
  1669. }
  1670. }
  1671. alst = (gdth_arcdl_str *)ha->pscratch;
  1672. alst->entries_avail = MAX_LDRIVES;
  1673. alst->first_entry = 0;
  1674. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1675. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1676. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1677. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1678. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1679. for (j = 0; j < alst->entries_init; ++j) {
  1680. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1681. ha->hdr[j].is_master = alst->list[j].is_master;
  1682. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1683. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1684. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1685. }
  1686. } else if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1687. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1688. 0, 35 * sizeof(gdth_alist_str))) {
  1689. for (j = 0; j < 35; ++j) {
  1690. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1691. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1692. ha->hdr[j].is_master = alst2->is_master;
  1693. ha->hdr[j].is_parity = alst2->is_parity;
  1694. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1695. ha->hdr[j].master_no = alst2->cd_handle;
  1696. }
  1697. }
  1698. }
  1699. }
  1700. /* initialize raw service */
  1701. ha->raw_feat = 0;
  1702. if (!force_dma32) {
  1703. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_X_INIT_RAW, 0, 0, 0);
  1704. if (ok)
  1705. ha->raw_feat = GDT_64BIT;
  1706. }
  1707. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1708. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_INIT, 0, 0, 0);
  1709. if (!ok) {
  1710. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  1711. ha->hanum, ha->status);
  1712. return 0;
  1713. }
  1714. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  1715. /* set/get features raw service (scatter/gather) */
  1716. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_SET_FEAT, SCATTER_GATHER,
  1717. 0, 0)) {
  1718. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  1719. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1720. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  1721. ha->info));
  1722. ha->raw_feat |= (ushort)ha->info;
  1723. }
  1724. }
  1725. /* set/get features cache service (equal to raw service) */
  1726. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_SET_FEAT, 0,
  1727. SCATTER_GATHER,0)) {
  1728. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  1729. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1730. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  1731. ha->info));
  1732. ha->cache_feat |= (ushort)ha->info;
  1733. }
  1734. }
  1735. /* reserve drives for raw service */
  1736. if (reserve_mode != 0) {
  1737. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE_ALL,
  1738. reserve_mode == 1 ? 1 : 3, 0, 0);
  1739. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  1740. ha->status));
  1741. }
  1742. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  1743. if (reserve_list[i] == ha->hanum && reserve_list[i+1] < ha->bus_cnt &&
  1744. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  1745. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  1746. reserve_list[i], reserve_list[i+1],
  1747. reserve_list[i+2], reserve_list[i+3]));
  1748. if (!gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE, 0,
  1749. reserve_list[i+1], reserve_list[i+2] |
  1750. (reserve_list[i+3] << 8))) {
  1751. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  1752. ha->hanum, ha->status);
  1753. }
  1754. }
  1755. }
  1756. /* Determine OEM string using IOCTL */
  1757. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  1758. oemstr->params.ctl_version = 0x01;
  1759. oemstr->params.buffer_size = sizeof(oemstr->text);
  1760. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1761. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  1762. sizeof(gdth_oem_str_ioctl))) {
  1763. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  1764. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  1765. ha->hanum, oemstr->text.oem_company_name, ha->binfo.type_string);
  1766. /* Save the Host Drive inquiry data */
  1767. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  1768. sizeof(ha->oem_name));
  1769. } else {
  1770. /* Old method, based on PCI ID */
  1771. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  1772. printk("GDT-HA %d: Name: %s\n",
  1773. ha->hanum, ha->binfo.type_string);
  1774. if (ha->oem_id == OEM_ID_INTEL)
  1775. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  1776. else
  1777. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  1778. }
  1779. /* scanning for host drives */
  1780. for (i = 0; i < cdev_cnt; ++i)
  1781. gdth_analyse_hdrive(ha, i);
  1782. TRACE(("gdth_search_drives() OK\n"));
  1783. return 1;
  1784. }
  1785. static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive)
  1786. {
  1787. ulong32 drv_cyls;
  1788. int drv_hds, drv_secs;
  1789. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n", ha->hanum, hdrive));
  1790. if (hdrive >= MAX_HDRIVES)
  1791. return 0;
  1792. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_INFO, hdrive, 0, 0))
  1793. return 0;
  1794. ha->hdr[hdrive].present = TRUE;
  1795. ha->hdr[hdrive].size = ha->info;
  1796. /* evaluate mapping (sectors per head, heads per cylinder) */
  1797. ha->hdr[hdrive].size &= ~SECS32;
  1798. if (ha->info2 == 0) {
  1799. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  1800. } else {
  1801. drv_hds = ha->info2 & 0xff;
  1802. drv_secs = (ha->info2 >> 8) & 0xff;
  1803. drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  1804. }
  1805. ha->hdr[hdrive].heads = (unchar)drv_hds;
  1806. ha->hdr[hdrive].secs = (unchar)drv_secs;
  1807. /* round size */
  1808. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  1809. if (ha->cache_feat & GDT_64BIT) {
  1810. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INFO, hdrive, 0, 0)
  1811. && ha->info2 != 0) {
  1812. ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
  1813. }
  1814. }
  1815. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  1816. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  1817. /* get informations about device */
  1818. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_DEVTYPE, hdrive, 0, 0)) {
  1819. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  1820. hdrive,ha->info));
  1821. ha->hdr[hdrive].devtype = (ushort)ha->info;
  1822. }
  1823. /* cluster info */
  1824. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_CLUST_INFO, hdrive, 0, 0)) {
  1825. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  1826. hdrive,ha->info));
  1827. if (!shared_access)
  1828. ha->hdr[hdrive].cluster_type = (unchar)ha->info;
  1829. }
  1830. /* R/W attributes */
  1831. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_RW_ATTRIBS, hdrive, 0, 0)) {
  1832. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  1833. hdrive,ha->info));
  1834. ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
  1835. }
  1836. return 1;
  1837. }
  1838. /* command queueing/sending functions */
  1839. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority)
  1840. {
  1841. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  1842. register Scsi_Cmnd *pscp;
  1843. register Scsi_Cmnd *nscp;
  1844. ulong flags;
  1845. unchar b, t;
  1846. TRACE(("gdth_putq() priority %d\n",priority));
  1847. spin_lock_irqsave(&ha->smp_lock, flags);
  1848. if (!cmndinfo->internal_command) {
  1849. cmndinfo->priority = priority;
  1850. b = scp->device->channel;
  1851. t = scp->device->id;
  1852. if (priority >= DEFAULT_PRI) {
  1853. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1854. (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
  1855. TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
  1856. cmndinfo->timeout = gdth_update_timeout(scp, 0);
  1857. }
  1858. }
  1859. }
  1860. if (ha->req_first==NULL) {
  1861. ha->req_first = scp; /* queue was empty */
  1862. scp->SCp.ptr = NULL;
  1863. } else { /* queue not empty */
  1864. pscp = ha->req_first;
  1865. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1866. /* priority: 0-highest,..,0xff-lowest */
  1867. while (nscp && gdth_cmnd_priv(nscp)->priority <= priority) {
  1868. pscp = nscp;
  1869. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1870. }
  1871. pscp->SCp.ptr = (char *)scp;
  1872. scp->SCp.ptr = (char *)nscp;
  1873. }
  1874. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1875. #ifdef GDTH_STATISTICS
  1876. flags = 0;
  1877. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  1878. ++flags;
  1879. if (max_rq < flags) {
  1880. max_rq = flags;
  1881. TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
  1882. }
  1883. #endif
  1884. }
  1885. static void gdth_next(gdth_ha_str *ha)
  1886. {
  1887. register Scsi_Cmnd *pscp;
  1888. register Scsi_Cmnd *nscp;
  1889. unchar b, t, l, firsttime;
  1890. unchar this_cmd, next_cmd;
  1891. ulong flags = 0;
  1892. int cmd_index;
  1893. TRACE(("gdth_next() hanum %d\n", ha->hanum));
  1894. if (!gdth_polling)
  1895. spin_lock_irqsave(&ha->smp_lock, flags);
  1896. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  1897. this_cmd = firsttime = TRUE;
  1898. next_cmd = gdth_polling ? FALSE:TRUE;
  1899. cmd_index = 0;
  1900. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  1901. struct gdth_cmndinfo *nscp_cmndinfo = gdth_cmnd_priv(nscp);
  1902. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  1903. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1904. if (!nscp_cmndinfo->internal_command) {
  1905. b = nscp->device->channel;
  1906. t = nscp->device->id;
  1907. l = nscp->device->lun;
  1908. if (nscp_cmndinfo->priority >= DEFAULT_PRI) {
  1909. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1910. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  1911. continue;
  1912. }
  1913. } else
  1914. b = t = l = 0;
  1915. if (firsttime) {
  1916. if (gdth_test_busy(ha)) { /* controller busy ? */
  1917. TRACE(("gdth_next() controller %d busy !\n", ha->hanum));
  1918. if (!gdth_polling) {
  1919. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1920. return;
  1921. }
  1922. while (gdth_test_busy(ha))
  1923. gdth_delay(1);
  1924. }
  1925. firsttime = FALSE;
  1926. }
  1927. if (!nscp_cmndinfo->internal_command) {
  1928. if (nscp_cmndinfo->phase == -1) {
  1929. nscp_cmndinfo->phase = CACHESERVICE; /* default: cache svc. */
  1930. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  1931. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  1932. b, t, l));
  1933. /* TEST_UNIT_READY -> set scan mode */
  1934. if ((ha->scan_mode & 0x0f) == 0) {
  1935. if (b == 0 && t == 0 && l == 0) {
  1936. ha->scan_mode |= 1;
  1937. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1938. }
  1939. } else if ((ha->scan_mode & 0x0f) == 1) {
  1940. if (b == 0 && ((t == 0 && l == 1) ||
  1941. (t == 1 && l == 0))) {
  1942. nscp_cmndinfo->OpCode = GDT_SCAN_START;
  1943. nscp_cmndinfo->phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  1944. | SCSIRAWSERVICE;
  1945. ha->scan_mode = 0x12;
  1946. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  1947. ha->scan_mode));
  1948. } else {
  1949. ha->scan_mode &= 0x10;
  1950. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1951. }
  1952. } else if (ha->scan_mode == 0x12) {
  1953. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  1954. nscp_cmndinfo->phase = SCSIRAWSERVICE;
  1955. nscp_cmndinfo->OpCode = GDT_SCAN_END;
  1956. ha->scan_mode &= 0x10;
  1957. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  1958. ha->scan_mode));
  1959. }
  1960. }
  1961. }
  1962. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  1963. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  1964. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  1965. /* always GDT_CLUST_INFO! */
  1966. nscp_cmndinfo->OpCode = GDT_CLUST_INFO;
  1967. }
  1968. }
  1969. }
  1970. if (nscp_cmndinfo->OpCode != -1) {
  1971. if ((nscp_cmndinfo->phase & 0xff) == CACHESERVICE) {
  1972. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1973. this_cmd = FALSE;
  1974. next_cmd = FALSE;
  1975. } else if ((nscp_cmndinfo->phase & 0xff) == SCSIRAWSERVICE) {
  1976. if (!(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1977. this_cmd = FALSE;
  1978. next_cmd = FALSE;
  1979. } else {
  1980. memset((char*)nscp->sense_buffer,0,16);
  1981. nscp->sense_buffer[0] = 0x70;
  1982. nscp->sense_buffer[2] = NOT_READY;
  1983. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1984. if (!nscp_cmndinfo->wait_for_completion)
  1985. nscp_cmndinfo->wait_for_completion++;
  1986. else
  1987. gdth_scsi_done(nscp);
  1988. }
  1989. } else if (gdth_cmnd_priv(nscp)->internal_command) {
  1990. if (!(cmd_index=gdth_special_cmd(ha, nscp)))
  1991. this_cmd = FALSE;
  1992. next_cmd = FALSE;
  1993. } else if (b != ha->virt_bus) {
  1994. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  1995. !(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1996. this_cmd = FALSE;
  1997. else
  1998. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  1999. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  2000. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  2001. nscp->cmnd[0], b, t, l));
  2002. nscp->result = DID_BAD_TARGET << 16;
  2003. if (!nscp_cmndinfo->wait_for_completion)
  2004. nscp_cmndinfo->wait_for_completion++;
  2005. else
  2006. gdth_scsi_done(nscp);
  2007. } else {
  2008. switch (nscp->cmnd[0]) {
  2009. case TEST_UNIT_READY:
  2010. case INQUIRY:
  2011. case REQUEST_SENSE:
  2012. case READ_CAPACITY:
  2013. case VERIFY:
  2014. case START_STOP:
  2015. case MODE_SENSE:
  2016. case SERVICE_ACTION_IN:
  2017. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2018. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2019. nscp->cmnd[4],nscp->cmnd[5]));
  2020. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  2021. /* return UNIT_ATTENTION */
  2022. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2023. nscp->cmnd[0], t));
  2024. ha->hdr[t].media_changed = FALSE;
  2025. memset((char*)nscp->sense_buffer,0,16);
  2026. nscp->sense_buffer[0] = 0x70;
  2027. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2028. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2029. if (!nscp_cmndinfo->wait_for_completion)
  2030. nscp_cmndinfo->wait_for_completion++;
  2031. else
  2032. gdth_scsi_done(nscp);
  2033. } else if (gdth_internal_cache_cmd(ha, nscp))
  2034. gdth_scsi_done(nscp);
  2035. break;
  2036. case ALLOW_MEDIUM_REMOVAL:
  2037. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2038. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2039. nscp->cmnd[4],nscp->cmnd[5]));
  2040. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  2041. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  2042. nscp->result = DID_OK << 16;
  2043. nscp->sense_buffer[0] = 0;
  2044. if (!nscp_cmndinfo->wait_for_completion)
  2045. nscp_cmndinfo->wait_for_completion++;
  2046. else
  2047. gdth_scsi_done(nscp);
  2048. } else {
  2049. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  2050. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  2051. nscp->cmnd[4],nscp->cmnd[3]));
  2052. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2053. this_cmd = FALSE;
  2054. }
  2055. break;
  2056. case RESERVE:
  2057. case RELEASE:
  2058. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  2059. "RESERVE" : "RELEASE"));
  2060. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2061. this_cmd = FALSE;
  2062. break;
  2063. case READ_6:
  2064. case WRITE_6:
  2065. case READ_10:
  2066. case WRITE_10:
  2067. case READ_16:
  2068. case WRITE_16:
  2069. if (ha->hdr[t].media_changed) {
  2070. /* return UNIT_ATTENTION */
  2071. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2072. nscp->cmnd[0], t));
  2073. ha->hdr[t].media_changed = FALSE;
  2074. memset((char*)nscp->sense_buffer,0,16);
  2075. nscp->sense_buffer[0] = 0x70;
  2076. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2077. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2078. if (!nscp_cmndinfo->wait_for_completion)
  2079. nscp_cmndinfo->wait_for_completion++;
  2080. else
  2081. gdth_scsi_done(nscp);
  2082. } else if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2083. this_cmd = FALSE;
  2084. break;
  2085. default:
  2086. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2087. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2088. nscp->cmnd[4],nscp->cmnd[5]));
  2089. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2090. ha->hanum, nscp->cmnd[0]);
  2091. nscp->result = DID_ABORT << 16;
  2092. if (!nscp_cmndinfo->wait_for_completion)
  2093. nscp_cmndinfo->wait_for_completion++;
  2094. else
  2095. gdth_scsi_done(nscp);
  2096. break;
  2097. }
  2098. }
  2099. if (!this_cmd)
  2100. break;
  2101. if (nscp == ha->req_first)
  2102. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2103. else
  2104. pscp->SCp.ptr = nscp->SCp.ptr;
  2105. if (!next_cmd)
  2106. break;
  2107. }
  2108. if (ha->cmd_cnt > 0) {
  2109. gdth_release_event(ha);
  2110. }
  2111. if (!gdth_polling)
  2112. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2113. if (gdth_polling && ha->cmd_cnt > 0) {
  2114. if (!gdth_wait(ha, cmd_index, POLL_TIMEOUT))
  2115. printk("GDT-HA %d: Command %d timed out !\n",
  2116. ha->hanum, cmd_index);
  2117. }
  2118. }
  2119. /*
  2120. * gdth_copy_internal_data() - copy to/from a buffer onto a scsi_cmnd's
  2121. * buffers, kmap_atomic() as needed.
  2122. */
  2123. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  2124. char *buffer, ushort count, int to_buffer)
  2125. {
  2126. ushort cpcount,i, max_sg = gdth_sg_count(scp);
  2127. ushort cpsum,cpnow;
  2128. struct scatterlist *sl;
  2129. char *address;
  2130. cpcount = min_t(ushort, count, gdth_bufflen(scp));
  2131. if (cpcount) {
  2132. cpsum=0;
  2133. scsi_for_each_sg(scp, sl, max_sg, i) {
  2134. unsigned long flags;
  2135. cpnow = (ushort)sl->length;
  2136. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2137. cpnow, cpsum, cpcount, gdth_bufflen(scp)));
  2138. if (cpsum+cpnow > cpcount)
  2139. cpnow = cpcount - cpsum;
  2140. cpsum += cpnow;
  2141. if (!sg_page(sl)) {
  2142. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2143. ha->hanum);
  2144. return;
  2145. }
  2146. local_irq_save(flags);
  2147. address = kmap_atomic(sg_page(sl), KM_BIO_SRC_IRQ) + sl->offset;
  2148. if (to_buffer)
  2149. memcpy(buffer, address, cpnow);
  2150. else
  2151. memcpy(address, buffer, cpnow);
  2152. flush_dcache_page(sg_page(sl));
  2153. kunmap_atomic(address, KM_BIO_SRC_IRQ);
  2154. local_irq_restore(flags);
  2155. if (cpsum == cpcount)
  2156. break;
  2157. buffer += cpnow;
  2158. }
  2159. } else if (count) {
  2160. printk("GDT-HA %d: SCSI command with no buffers but data transfer expected!\n",
  2161. ha->hanum);
  2162. WARN_ON(1);
  2163. }
  2164. }
  2165. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2166. {
  2167. unchar t;
  2168. gdth_inq_data inq;
  2169. gdth_rdcap_data rdc;
  2170. gdth_sense_data sd;
  2171. gdth_modep_data mpd;
  2172. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2173. t = scp->device->id;
  2174. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2175. scp->cmnd[0],t));
  2176. scp->result = DID_OK << 16;
  2177. scp->sense_buffer[0] = 0;
  2178. switch (scp->cmnd[0]) {
  2179. case TEST_UNIT_READY:
  2180. case VERIFY:
  2181. case START_STOP:
  2182. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2183. break;
  2184. case INQUIRY:
  2185. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2186. t,ha->hdr[t].devtype));
  2187. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2188. /* you can here set all disks to removable, if you want to do
  2189. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2190. inq.modif_rmb = 0x00;
  2191. if ((ha->hdr[t].devtype & 1) ||
  2192. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2193. inq.modif_rmb = 0x80;
  2194. inq.version = 2;
  2195. inq.resp_aenc = 2;
  2196. inq.add_length= 32;
  2197. strcpy(inq.vendor,ha->oem_name);
  2198. sprintf(inq.product,"Host Drive #%02d",t);
  2199. strcpy(inq.revision," ");
  2200. gdth_copy_internal_data(ha, scp, (char*)&inq, sizeof(gdth_inq_data), 0);
  2201. break;
  2202. case REQUEST_SENSE:
  2203. TRACE2(("Request sense hdrive %d\n",t));
  2204. sd.errorcode = 0x70;
  2205. sd.segno = 0x00;
  2206. sd.key = NO_SENSE;
  2207. sd.info = 0;
  2208. sd.add_length= 0;
  2209. gdth_copy_internal_data(ha, scp, (char*)&sd, sizeof(gdth_sense_data), 0);
  2210. break;
  2211. case MODE_SENSE:
  2212. TRACE2(("Mode sense hdrive %d\n",t));
  2213. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2214. mpd.hd.data_length = sizeof(gdth_modep_data);
  2215. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2216. mpd.hd.bd_length = sizeof(mpd.bd);
  2217. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2218. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2219. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2220. gdth_copy_internal_data(ha, scp, (char*)&mpd, sizeof(gdth_modep_data), 0);
  2221. break;
  2222. case READ_CAPACITY:
  2223. TRACE2(("Read capacity hdrive %d\n",t));
  2224. if (ha->hdr[t].size > (ulong64)0xffffffff)
  2225. rdc.last_block_no = 0xffffffff;
  2226. else
  2227. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2228. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2229. gdth_copy_internal_data(ha, scp, (char*)&rdc, sizeof(gdth_rdcap_data), 0);
  2230. break;
  2231. case SERVICE_ACTION_IN:
  2232. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2233. (ha->cache_feat & GDT_64BIT)) {
  2234. gdth_rdcap16_data rdc16;
  2235. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2236. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2237. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2238. gdth_copy_internal_data(ha, scp, (char*)&rdc16,
  2239. sizeof(gdth_rdcap16_data), 0);
  2240. } else {
  2241. scp->result = DID_ABORT << 16;
  2242. }
  2243. break;
  2244. default:
  2245. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2246. break;
  2247. }
  2248. if (!cmndinfo->wait_for_completion)
  2249. cmndinfo->wait_for_completion++;
  2250. else
  2251. return 1;
  2252. return 0;
  2253. }
  2254. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive)
  2255. {
  2256. register gdth_cmd_str *cmdp;
  2257. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2258. ulong32 cnt, blockcnt;
  2259. ulong64 no, blockno;
  2260. int i, cmd_index, read_write, sgcnt, mode64;
  2261. cmdp = ha->pccb;
  2262. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2263. scp->cmnd[0],scp->cmd_len,hdrive));
  2264. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2265. return 0;
  2266. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2267. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2268. not required, should not occur due to error return on
  2269. READ_CAPACITY_16 */
  2270. cmdp->Service = CACHESERVICE;
  2271. cmdp->RequestBuffer = scp;
  2272. /* search free command index */
  2273. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2274. TRACE(("GDT: No free command index found\n"));
  2275. return 0;
  2276. }
  2277. /* if it's the first command, set command semaphore */
  2278. if (ha->cmd_cnt == 0)
  2279. gdth_set_sema0(ha);
  2280. /* fill command */
  2281. read_write = 0;
  2282. if (cmndinfo->OpCode != -1)
  2283. cmdp->OpCode = cmndinfo->OpCode; /* special cache cmd. */
  2284. else if (scp->cmnd[0] == RESERVE)
  2285. cmdp->OpCode = GDT_RESERVE_DRV;
  2286. else if (scp->cmnd[0] == RELEASE)
  2287. cmdp->OpCode = GDT_RELEASE_DRV;
  2288. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2289. if (scp->cmnd[4] & 1) /* prevent ? */
  2290. cmdp->OpCode = GDT_MOUNT;
  2291. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2292. cmdp->OpCode = GDT_UNMOUNT;
  2293. else
  2294. cmdp->OpCode = GDT_FLUSH;
  2295. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2296. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2297. ) {
  2298. read_write = 1;
  2299. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2300. (ha->cache_feat & GDT_WR_THROUGH)))
  2301. cmdp->OpCode = GDT_WRITE_THR;
  2302. else
  2303. cmdp->OpCode = GDT_WRITE;
  2304. } else {
  2305. read_write = 2;
  2306. cmdp->OpCode = GDT_READ;
  2307. }
  2308. cmdp->BoardNode = LOCALBOARD;
  2309. if (mode64) {
  2310. cmdp->u.cache64.DeviceNo = hdrive;
  2311. cmdp->u.cache64.BlockNo = 1;
  2312. cmdp->u.cache64.sg_canz = 0;
  2313. } else {
  2314. cmdp->u.cache.DeviceNo = hdrive;
  2315. cmdp->u.cache.BlockNo = 1;
  2316. cmdp->u.cache.sg_canz = 0;
  2317. }
  2318. if (read_write) {
  2319. if (scp->cmd_len == 16) {
  2320. memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
  2321. blockno = be64_to_cpu(no);
  2322. memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
  2323. blockcnt = be32_to_cpu(cnt);
  2324. } else if (scp->cmd_len == 10) {
  2325. memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
  2326. blockno = be32_to_cpu(no);
  2327. memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
  2328. blockcnt = be16_to_cpu(cnt);
  2329. } else {
  2330. memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
  2331. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2332. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2333. }
  2334. if (mode64) {
  2335. cmdp->u.cache64.BlockNo = blockno;
  2336. cmdp->u.cache64.BlockCnt = blockcnt;
  2337. } else {
  2338. cmdp->u.cache.BlockNo = (ulong32)blockno;
  2339. cmdp->u.cache.BlockCnt = blockcnt;
  2340. }
  2341. if (gdth_bufflen(scp)) {
  2342. cmndinfo->dma_dir = (read_write == 1 ?
  2343. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2344. sgcnt = pci_map_sg(ha->pdev, gdth_sglist(scp), gdth_sg_count(scp),
  2345. cmndinfo->dma_dir);
  2346. if (mode64) {
  2347. struct scatterlist *sl;
  2348. cmdp->u.cache64.DestAddr= (ulong64)-1;
  2349. cmdp->u.cache64.sg_canz = sgcnt;
  2350. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2351. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2352. #ifdef GDTH_DMA_STATISTICS
  2353. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2354. ha->dma64_cnt++;
  2355. else
  2356. ha->dma32_cnt++;
  2357. #endif
  2358. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2359. }
  2360. } else {
  2361. struct scatterlist *sl;
  2362. cmdp->u.cache.DestAddr= 0xffffffff;
  2363. cmdp->u.cache.sg_canz = sgcnt;
  2364. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2365. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2366. #ifdef GDTH_DMA_STATISTICS
  2367. ha->dma32_cnt++;
  2368. #endif
  2369. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2370. }
  2371. }
  2372. #ifdef GDTH_STATISTICS
  2373. if (max_sg < (ulong32)sgcnt) {
  2374. max_sg = (ulong32)sgcnt;
  2375. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2376. }
  2377. #endif
  2378. }
  2379. }
  2380. /* evaluate command size, check space */
  2381. if (mode64) {
  2382. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2383. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2384. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2385. cmdp->u.cache64.sg_lst[0].sg_len));
  2386. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2387. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2388. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2389. (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2390. } else {
  2391. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2392. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2393. cmdp->u.cache.sg_lst[0].sg_ptr,
  2394. cmdp->u.cache.sg_lst[0].sg_len));
  2395. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2396. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2397. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2398. (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2399. }
  2400. if (ha->cmd_len & 3)
  2401. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2402. if (ha->cmd_cnt > 0) {
  2403. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2404. ha->ic_all_size) {
  2405. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2406. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2407. return 0;
  2408. }
  2409. }
  2410. /* copy command */
  2411. gdth_copy_command(ha);
  2412. return cmd_index;
  2413. }
  2414. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b)
  2415. {
  2416. register gdth_cmd_str *cmdp;
  2417. ushort i;
  2418. dma_addr_t sense_paddr;
  2419. int cmd_index, sgcnt, mode64;
  2420. unchar t,l;
  2421. struct page *page;
  2422. ulong offset;
  2423. struct gdth_cmndinfo *cmndinfo;
  2424. t = scp->device->id;
  2425. l = scp->device->lun;
  2426. cmdp = ha->pccb;
  2427. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2428. scp->cmnd[0],b,t,l));
  2429. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2430. return 0;
  2431. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2432. cmdp->Service = SCSIRAWSERVICE;
  2433. cmdp->RequestBuffer = scp;
  2434. /* search free command index */
  2435. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2436. TRACE(("GDT: No free command index found\n"));
  2437. return 0;
  2438. }
  2439. /* if it's the first command, set command semaphore */
  2440. if (ha->cmd_cnt == 0)
  2441. gdth_set_sema0(ha);
  2442. cmndinfo = gdth_cmnd_priv(scp);
  2443. /* fill command */
  2444. if (cmndinfo->OpCode != -1) {
  2445. cmdp->OpCode = cmndinfo->OpCode; /* special raw cmd. */
  2446. cmdp->BoardNode = LOCALBOARD;
  2447. if (mode64) {
  2448. cmdp->u.raw64.direction = (cmndinfo->phase >> 8);
  2449. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2450. cmdp->OpCode, cmdp->u.raw64.direction));
  2451. /* evaluate command size */
  2452. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2453. } else {
  2454. cmdp->u.raw.direction = (cmndinfo->phase >> 8);
  2455. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2456. cmdp->OpCode, cmdp->u.raw.direction));
  2457. /* evaluate command size */
  2458. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2459. }
  2460. } else {
  2461. page = virt_to_page(scp->sense_buffer);
  2462. offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
  2463. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2464. 16,PCI_DMA_FROMDEVICE);
  2465. cmndinfo->sense_paddr = sense_paddr;
  2466. cmdp->OpCode = GDT_WRITE; /* always */
  2467. cmdp->BoardNode = LOCALBOARD;
  2468. if (mode64) {
  2469. cmdp->u.raw64.reserved = 0;
  2470. cmdp->u.raw64.mdisc_time = 0;
  2471. cmdp->u.raw64.mcon_time = 0;
  2472. cmdp->u.raw64.clen = scp->cmd_len;
  2473. cmdp->u.raw64.target = t;
  2474. cmdp->u.raw64.lun = l;
  2475. cmdp->u.raw64.bus = b;
  2476. cmdp->u.raw64.priority = 0;
  2477. cmdp->u.raw64.sdlen = gdth_bufflen(scp);
  2478. cmdp->u.raw64.sense_len = 16;
  2479. cmdp->u.raw64.sense_data = sense_paddr;
  2480. cmdp->u.raw64.direction =
  2481. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2482. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2483. cmdp->u.raw64.sg_ranz = 0;
  2484. } else {
  2485. cmdp->u.raw.reserved = 0;
  2486. cmdp->u.raw.mdisc_time = 0;
  2487. cmdp->u.raw.mcon_time = 0;
  2488. cmdp->u.raw.clen = scp->cmd_len;
  2489. cmdp->u.raw.target = t;
  2490. cmdp->u.raw.lun = l;
  2491. cmdp->u.raw.bus = b;
  2492. cmdp->u.raw.priority = 0;
  2493. cmdp->u.raw.link_p = 0;
  2494. cmdp->u.raw.sdlen = gdth_bufflen(scp);
  2495. cmdp->u.raw.sense_len = 16;
  2496. cmdp->u.raw.sense_data = sense_paddr;
  2497. cmdp->u.raw.direction =
  2498. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2499. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2500. cmdp->u.raw.sg_ranz = 0;
  2501. }
  2502. if (gdth_bufflen(scp)) {
  2503. cmndinfo->dma_dir = PCI_DMA_BIDIRECTIONAL;
  2504. sgcnt = pci_map_sg(ha->pdev, gdth_sglist(scp), gdth_sg_count(scp),
  2505. cmndinfo->dma_dir);
  2506. if (mode64) {
  2507. struct scatterlist *sl;
  2508. cmdp->u.raw64.sdata = (ulong64)-1;
  2509. cmdp->u.raw64.sg_ranz = sgcnt;
  2510. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2511. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2512. #ifdef GDTH_DMA_STATISTICS
  2513. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2514. ha->dma64_cnt++;
  2515. else
  2516. ha->dma32_cnt++;
  2517. #endif
  2518. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2519. }
  2520. } else {
  2521. struct scatterlist *sl;
  2522. cmdp->u.raw.sdata = 0xffffffff;
  2523. cmdp->u.raw.sg_ranz = sgcnt;
  2524. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2525. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2526. #ifdef GDTH_DMA_STATISTICS
  2527. ha->dma32_cnt++;
  2528. #endif
  2529. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2530. }
  2531. }
  2532. #ifdef GDTH_STATISTICS
  2533. if (max_sg < sgcnt) {
  2534. max_sg = sgcnt;
  2535. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2536. }
  2537. #endif
  2538. }
  2539. if (mode64) {
  2540. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2541. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2542. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2543. cmdp->u.raw64.sg_lst[0].sg_len));
  2544. /* evaluate command size */
  2545. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2546. (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2547. } else {
  2548. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2549. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2550. cmdp->u.raw.sg_lst[0].sg_ptr,
  2551. cmdp->u.raw.sg_lst[0].sg_len));
  2552. /* evaluate command size */
  2553. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2554. (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2555. }
  2556. }
  2557. /* check space */
  2558. if (ha->cmd_len & 3)
  2559. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2560. if (ha->cmd_cnt > 0) {
  2561. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2562. ha->ic_all_size) {
  2563. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2564. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2565. return 0;
  2566. }
  2567. }
  2568. /* copy command */
  2569. gdth_copy_command(ha);
  2570. return cmd_index;
  2571. }
  2572. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2573. {
  2574. register gdth_cmd_str *cmdp;
  2575. int cmd_index;
  2576. cmdp= ha->pccb;
  2577. TRACE2(("gdth_special_cmd(): "));
  2578. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2579. return 0;
  2580. gdth_copy_internal_data(ha, scp, (char *)cmdp, sizeof(gdth_cmd_str), 1);
  2581. cmdp->RequestBuffer = scp;
  2582. /* search free command index */
  2583. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2584. TRACE(("GDT: No free command index found\n"));
  2585. return 0;
  2586. }
  2587. /* if it's the first command, set command semaphore */
  2588. if (ha->cmd_cnt == 0)
  2589. gdth_set_sema0(ha);
  2590. /* evaluate command size, check space */
  2591. if (cmdp->OpCode == GDT_IOCTL) {
  2592. TRACE2(("IOCTL\n"));
  2593. ha->cmd_len =
  2594. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
  2595. } else if (cmdp->Service == CACHESERVICE) {
  2596. TRACE2(("cache command %d\n",cmdp->OpCode));
  2597. if (ha->cache_feat & GDT_64BIT)
  2598. ha->cmd_len =
  2599. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2600. else
  2601. ha->cmd_len =
  2602. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2603. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2604. TRACE2(("raw command %d\n",cmdp->OpCode));
  2605. if (ha->raw_feat & GDT_64BIT)
  2606. ha->cmd_len =
  2607. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2608. else
  2609. ha->cmd_len =
  2610. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  2611. }
  2612. if (ha->cmd_len & 3)
  2613. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2614. if (ha->cmd_cnt > 0) {
  2615. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2616. ha->ic_all_size) {
  2617. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  2618. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2619. return 0;
  2620. }
  2621. }
  2622. /* copy command */
  2623. gdth_copy_command(ha);
  2624. return cmd_index;
  2625. }
  2626. /* Controller event handling functions */
  2627. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  2628. ushort idx, gdth_evt_data *evt)
  2629. {
  2630. gdth_evt_str *e;
  2631. struct timeval tv;
  2632. /* no GDTH_LOCK_HA() ! */
  2633. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  2634. if (source == 0) /* no source -> no event */
  2635. return NULL;
  2636. if (ebuffer[elastidx].event_source == source &&
  2637. ebuffer[elastidx].event_idx == idx &&
  2638. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  2639. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  2640. (char *)&evt->eu, evt->size)) ||
  2641. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  2642. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  2643. (char *)&evt->event_string)))) {
  2644. e = &ebuffer[elastidx];
  2645. do_gettimeofday(&tv);
  2646. e->last_stamp = tv.tv_sec;
  2647. ++e->same_count;
  2648. } else {
  2649. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  2650. ++elastidx;
  2651. if (elastidx == MAX_EVENTS)
  2652. elastidx = 0;
  2653. if (elastidx == eoldidx) { /* reached mark ? */
  2654. ++eoldidx;
  2655. if (eoldidx == MAX_EVENTS)
  2656. eoldidx = 0;
  2657. }
  2658. }
  2659. e = &ebuffer[elastidx];
  2660. e->event_source = source;
  2661. e->event_idx = idx;
  2662. do_gettimeofday(&tv);
  2663. e->first_stamp = e->last_stamp = tv.tv_sec;
  2664. e->same_count = 1;
  2665. e->event_data = *evt;
  2666. e->application = 0;
  2667. }
  2668. return e;
  2669. }
  2670. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  2671. {
  2672. gdth_evt_str *e;
  2673. int eindex;
  2674. ulong flags;
  2675. TRACE2(("gdth_read_event() handle %d\n", handle));
  2676. spin_lock_irqsave(&ha->smp_lock, flags);
  2677. if (handle == -1)
  2678. eindex = eoldidx;
  2679. else
  2680. eindex = handle;
  2681. estr->event_source = 0;
  2682. if (eindex >= MAX_EVENTS) {
  2683. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2684. return eindex;
  2685. }
  2686. e = &ebuffer[eindex];
  2687. if (e->event_source != 0) {
  2688. if (eindex != elastidx) {
  2689. if (++eindex == MAX_EVENTS)
  2690. eindex = 0;
  2691. } else {
  2692. eindex = -1;
  2693. }
  2694. memcpy(estr, e, sizeof(gdth_evt_str));
  2695. }
  2696. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2697. return eindex;
  2698. }
  2699. static void gdth_readapp_event(gdth_ha_str *ha,
  2700. unchar application, gdth_evt_str *estr)
  2701. {
  2702. gdth_evt_str *e;
  2703. int eindex;
  2704. ulong flags;
  2705. unchar found = FALSE;
  2706. TRACE2(("gdth_readapp_event() app. %d\n", application));
  2707. spin_lock_irqsave(&ha->smp_lock, flags);
  2708. eindex = eoldidx;
  2709. for (;;) {
  2710. e = &ebuffer[eindex];
  2711. if (e->event_source == 0)
  2712. break;
  2713. if ((e->application & application) == 0) {
  2714. e->application |= application;
  2715. found = TRUE;
  2716. break;
  2717. }
  2718. if (eindex == elastidx)
  2719. break;
  2720. if (++eindex == MAX_EVENTS)
  2721. eindex = 0;
  2722. }
  2723. if (found)
  2724. memcpy(estr, e, sizeof(gdth_evt_str));
  2725. else
  2726. estr->event_source = 0;
  2727. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2728. }
  2729. static void gdth_clear_events(void)
  2730. {
  2731. TRACE(("gdth_clear_events()"));
  2732. eoldidx = elastidx = 0;
  2733. ebuffer[0].event_source = 0;
  2734. }
  2735. /* SCSI interface functions */
  2736. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
  2737. int gdth_from_wait, int* pIndex)
  2738. {
  2739. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  2740. gdt6_dpram_str __iomem *dp6_ptr;
  2741. gdt2_dpram_str __iomem *dp2_ptr;
  2742. Scsi_Cmnd *scp;
  2743. int rval, i;
  2744. unchar IStatus;
  2745. ushort Service;
  2746. ulong flags = 0;
  2747. #ifdef INT_COAL
  2748. int coalesced = FALSE;
  2749. int next = FALSE;
  2750. gdth_coal_status *pcs = NULL;
  2751. int act_int_coal = 0;
  2752. #endif
  2753. TRACE(("gdth_interrupt() IRQ %d\n", ha->irq));
  2754. /* if polling and not from gdth_wait() -> return */
  2755. if (gdth_polling) {
  2756. if (!gdth_from_wait) {
  2757. return IRQ_HANDLED;
  2758. }
  2759. }
  2760. if (!gdth_polling)
  2761. spin_lock_irqsave(&ha->smp_lock, flags);
  2762. /* search controller */
  2763. IStatus = gdth_get_status(ha);
  2764. if (IStatus == 0) {
  2765. /* spurious interrupt */
  2766. if (!gdth_polling)
  2767. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2768. return IRQ_HANDLED;
  2769. }
  2770. #ifdef GDTH_STATISTICS
  2771. ++act_ints;
  2772. #endif
  2773. #ifdef INT_COAL
  2774. /* See if the fw is returning coalesced status */
  2775. if (IStatus == COALINDEX) {
  2776. /* Coalesced status. Setup the initial status
  2777. buffer pointer and flags */
  2778. pcs = ha->coal_stat;
  2779. coalesced = TRUE;
  2780. next = TRUE;
  2781. }
  2782. do {
  2783. if (coalesced) {
  2784. /* For coalesced requests all status
  2785. information is found in the status buffer */
  2786. IStatus = (unchar)(pcs->status & 0xff);
  2787. }
  2788. #endif
  2789. if (ha->type == GDT_EISA) {
  2790. if (IStatus & 0x80) { /* error flag */
  2791. IStatus &= ~0x80;
  2792. ha->status = inw(ha->bmic + MAILBOXREG+8);
  2793. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2794. } else /* no error */
  2795. ha->status = S_OK;
  2796. ha->info = inl(ha->bmic + MAILBOXREG+12);
  2797. ha->service = inw(ha->bmic + MAILBOXREG+10);
  2798. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  2799. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  2800. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  2801. } else if (ha->type == GDT_ISA) {
  2802. dp2_ptr = ha->brd;
  2803. if (IStatus & 0x80) { /* error flag */
  2804. IStatus &= ~0x80;
  2805. ha->status = readw(&dp2_ptr->u.ic.Status);
  2806. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2807. } else /* no error */
  2808. ha->status = S_OK;
  2809. ha->info = readl(&dp2_ptr->u.ic.Info[0]);
  2810. ha->service = readw(&dp2_ptr->u.ic.Service);
  2811. ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
  2812. writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  2813. writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  2814. writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  2815. } else if (ha->type == GDT_PCI) {
  2816. dp6_ptr = ha->brd;
  2817. if (IStatus & 0x80) { /* error flag */
  2818. IStatus &= ~0x80;
  2819. ha->status = readw(&dp6_ptr->u.ic.Status);
  2820. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2821. } else /* no error */
  2822. ha->status = S_OK;
  2823. ha->info = readl(&dp6_ptr->u.ic.Info[0]);
  2824. ha->service = readw(&dp6_ptr->u.ic.Service);
  2825. ha->info2 = readl(&dp6_ptr->u.ic.Info[1]);
  2826. writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  2827. writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  2828. writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  2829. } else if (ha->type == GDT_PCINEW) {
  2830. if (IStatus & 0x80) { /* error flag */
  2831. IStatus &= ~0x80;
  2832. ha->status = inw(PTR2USHORT(&ha->plx->status));
  2833. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2834. } else
  2835. ha->status = S_OK;
  2836. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  2837. ha->service = inw(PTR2USHORT(&ha->plx->service));
  2838. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  2839. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  2840. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  2841. } else if (ha->type == GDT_PCIMPR) {
  2842. dp6m_ptr = ha->brd;
  2843. if (IStatus & 0x80) { /* error flag */
  2844. IStatus &= ~0x80;
  2845. #ifdef INT_COAL
  2846. if (coalesced)
  2847. ha->status = pcs->ext_status & 0xffff;
  2848. else
  2849. #endif
  2850. ha->status = readw(&dp6m_ptr->i960r.status);
  2851. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2852. } else /* no error */
  2853. ha->status = S_OK;
  2854. #ifdef INT_COAL
  2855. /* get information */
  2856. if (coalesced) {
  2857. ha->info = pcs->info0;
  2858. ha->info2 = pcs->info1;
  2859. ha->service = (pcs->ext_status >> 16) & 0xffff;
  2860. } else
  2861. #endif
  2862. {
  2863. ha->info = readl(&dp6m_ptr->i960r.info[0]);
  2864. ha->service = readw(&dp6m_ptr->i960r.service);
  2865. ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
  2866. }
  2867. /* event string */
  2868. if (IStatus == ASYNCINDEX) {
  2869. if (ha->service != SCREENSERVICE &&
  2870. (ha->fw_vers & 0xff) >= 0x1a) {
  2871. ha->dvr.severity = readb
  2872. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  2873. for (i = 0; i < 256; ++i) {
  2874. ha->dvr.event_string[i] = readb
  2875. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  2876. if (ha->dvr.event_string[i] == 0)
  2877. break;
  2878. }
  2879. }
  2880. }
  2881. #ifdef INT_COAL
  2882. /* Make sure that non coalesced interrupts get cleared
  2883. before being handled by gdth_async_event/gdth_sync_event */
  2884. if (!coalesced)
  2885. #endif
  2886. {
  2887. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2888. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2889. }
  2890. } else {
  2891. TRACE2(("gdth_interrupt() unknown controller type\n"));
  2892. if (!gdth_polling)
  2893. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2894. return IRQ_HANDLED;
  2895. }
  2896. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  2897. IStatus,ha->status,ha->info));
  2898. if (gdth_from_wait) {
  2899. *pIndex = (int)IStatus;
  2900. }
  2901. if (IStatus == ASYNCINDEX) {
  2902. TRACE2(("gdth_interrupt() async. event\n"));
  2903. gdth_async_event(ha);
  2904. if (!gdth_polling)
  2905. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2906. gdth_next(ha);
  2907. return IRQ_HANDLED;
  2908. }
  2909. if (IStatus == SPEZINDEX) {
  2910. TRACE2(("Service unknown or not initialized !\n"));
  2911. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2912. ha->dvr.eu.driver.ionode = ha->hanum;
  2913. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  2914. if (!gdth_polling)
  2915. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2916. return IRQ_HANDLED;
  2917. }
  2918. scp = ha->cmd_tab[IStatus-2].cmnd;
  2919. Service = ha->cmd_tab[IStatus-2].service;
  2920. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  2921. if (scp == UNUSED_CMND) {
  2922. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  2923. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2924. ha->dvr.eu.driver.ionode = ha->hanum;
  2925. ha->dvr.eu.driver.index = IStatus;
  2926. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  2927. if (!gdth_polling)
  2928. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2929. return IRQ_HANDLED;
  2930. }
  2931. if (scp == INTERNAL_CMND) {
  2932. TRACE(("gdth_interrupt() answer to internal command\n"));
  2933. if (!gdth_polling)
  2934. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2935. return IRQ_HANDLED;
  2936. }
  2937. TRACE(("gdth_interrupt() sync. status\n"));
  2938. rval = gdth_sync_event(ha,Service,IStatus,scp);
  2939. if (!gdth_polling)
  2940. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2941. if (rval == 2) {
  2942. gdth_putq(ha, scp, gdth_cmnd_priv(scp)->priority);
  2943. } else if (rval == 1) {
  2944. gdth_scsi_done(scp);
  2945. }
  2946. #ifdef INT_COAL
  2947. if (coalesced) {
  2948. /* go to the next status in the status buffer */
  2949. ++pcs;
  2950. #ifdef GDTH_STATISTICS
  2951. ++act_int_coal;
  2952. if (act_int_coal > max_int_coal) {
  2953. max_int_coal = act_int_coal;
  2954. printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
  2955. }
  2956. #endif
  2957. /* see if there is another status */
  2958. if (pcs->status == 0)
  2959. /* Stop the coalesce loop */
  2960. next = FALSE;
  2961. }
  2962. } while (next);
  2963. /* coalescing only for new GDT_PCIMPR controllers available */
  2964. if (ha->type == GDT_PCIMPR && coalesced) {
  2965. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2966. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2967. }
  2968. #endif
  2969. gdth_next(ha);
  2970. return IRQ_HANDLED;
  2971. }
  2972. static irqreturn_t gdth_interrupt(int irq, void *dev_id)
  2973. {
  2974. gdth_ha_str *ha = dev_id;
  2975. return __gdth_interrupt(ha, false, NULL);
  2976. }
  2977. static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
  2978. Scsi_Cmnd *scp)
  2979. {
  2980. gdth_msg_str *msg;
  2981. gdth_cmd_str *cmdp;
  2982. unchar b, t;
  2983. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2984. cmdp = ha->pccb;
  2985. TRACE(("gdth_sync_event() serv %d status %d\n",
  2986. service,ha->status));
  2987. if (service == SCREENSERVICE) {
  2988. msg = ha->pmsg;
  2989. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  2990. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  2991. if (msg->msg_len > MSGLEN+1)
  2992. msg->msg_len = MSGLEN+1;
  2993. if (msg->msg_len)
  2994. if (!(msg->msg_answer && msg->msg_ext)) {
  2995. msg->msg_text[msg->msg_len] = '\0';
  2996. printk("%s",msg->msg_text);
  2997. }
  2998. if (msg->msg_ext && !msg->msg_answer) {
  2999. while (gdth_test_busy(ha))
  3000. gdth_delay(0);
  3001. cmdp->Service = SCREENSERVICE;
  3002. cmdp->RequestBuffer = SCREEN_CMND;
  3003. gdth_get_cmd_index(ha);
  3004. gdth_set_sema0(ha);
  3005. cmdp->OpCode = GDT_READ;
  3006. cmdp->BoardNode = LOCALBOARD;
  3007. cmdp->u.screen.reserved = 0;
  3008. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3009. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3010. ha->cmd_offs_dpmem = 0;
  3011. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3012. + sizeof(ulong64);
  3013. ha->cmd_cnt = 0;
  3014. gdth_copy_command(ha);
  3015. gdth_release_event(ha);
  3016. return 0;
  3017. }
  3018. if (msg->msg_answer && msg->msg_alen) {
  3019. /* default answers (getchar() not possible) */
  3020. if (msg->msg_alen == 1) {
  3021. msg->msg_alen = 0;
  3022. msg->msg_len = 1;
  3023. msg->msg_text[0] = 0;
  3024. } else {
  3025. msg->msg_alen -= 2;
  3026. msg->msg_len = 2;
  3027. msg->msg_text[0] = 1;
  3028. msg->msg_text[1] = 0;
  3029. }
  3030. msg->msg_ext = 0;
  3031. msg->msg_answer = 0;
  3032. while (gdth_test_busy(ha))
  3033. gdth_delay(0);
  3034. cmdp->Service = SCREENSERVICE;
  3035. cmdp->RequestBuffer = SCREEN_CMND;
  3036. gdth_get_cmd_index(ha);
  3037. gdth_set_sema0(ha);
  3038. cmdp->OpCode = GDT_WRITE;
  3039. cmdp->BoardNode = LOCALBOARD;
  3040. cmdp->u.screen.reserved = 0;
  3041. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3042. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3043. ha->cmd_offs_dpmem = 0;
  3044. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3045. + sizeof(ulong64);
  3046. ha->cmd_cnt = 0;
  3047. gdth_copy_command(ha);
  3048. gdth_release_event(ha);
  3049. return 0;
  3050. }
  3051. printk("\n");
  3052. } else {
  3053. b = scp->device->channel;
  3054. t = scp->device->id;
  3055. if (cmndinfo->OpCode == -1 && b != ha->virt_bus) {
  3056. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  3057. }
  3058. /* cache or raw service */
  3059. if (ha->status == S_BSY) {
  3060. TRACE2(("Controller busy -> retry !\n"));
  3061. if (cmndinfo->OpCode == GDT_MOUNT)
  3062. cmndinfo->OpCode = GDT_CLUST_INFO;
  3063. /* retry */
  3064. return 2;
  3065. }
  3066. if (gdth_bufflen(scp))
  3067. pci_unmap_sg(ha->pdev, gdth_sglist(scp), gdth_sg_count(scp),
  3068. cmndinfo->dma_dir);
  3069. if (cmndinfo->sense_paddr)
  3070. pci_unmap_page(ha->pdev, cmndinfo->sense_paddr, 16,
  3071. PCI_DMA_FROMDEVICE);
  3072. if (ha->status == S_OK) {
  3073. cmndinfo->status = S_OK;
  3074. cmndinfo->info = ha->info;
  3075. if (cmndinfo->OpCode != -1) {
  3076. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  3077. cmndinfo->OpCode));
  3078. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3079. if (cmndinfo->OpCode == GDT_CLUST_INFO) {
  3080. ha->hdr[t].cluster_type = (unchar)ha->info;
  3081. if (!(ha->hdr[t].cluster_type &
  3082. CLUSTER_MOUNTED)) {
  3083. /* NOT MOUNTED -> MOUNT */
  3084. cmndinfo->OpCode = GDT_MOUNT;
  3085. if (ha->hdr[t].cluster_type &
  3086. CLUSTER_RESERVED) {
  3087. /* cluster drive RESERVED (on the other node) */
  3088. cmndinfo->phase = -2; /* reservation conflict */
  3089. }
  3090. } else {
  3091. cmndinfo->OpCode = -1;
  3092. }
  3093. } else {
  3094. if (cmndinfo->OpCode == GDT_MOUNT) {
  3095. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3096. ha->hdr[t].media_changed = TRUE;
  3097. } else if (cmndinfo->OpCode == GDT_UNMOUNT) {
  3098. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3099. ha->hdr[t].media_changed = TRUE;
  3100. }
  3101. cmndinfo->OpCode = -1;
  3102. }
  3103. /* retry */
  3104. cmndinfo->priority = HIGH_PRI;
  3105. return 2;
  3106. } else {
  3107. /* RESERVE/RELEASE ? */
  3108. if (scp->cmnd[0] == RESERVE) {
  3109. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3110. } else if (scp->cmnd[0] == RELEASE) {
  3111. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3112. }
  3113. scp->result = DID_OK << 16;
  3114. scp->sense_buffer[0] = 0;
  3115. }
  3116. } else {
  3117. cmndinfo->status = ha->status;
  3118. cmndinfo->info = ha->info;
  3119. if (cmndinfo->OpCode != -1) {
  3120. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3121. cmndinfo->OpCode, ha->status));
  3122. if (cmndinfo->OpCode == GDT_SCAN_START ||
  3123. cmndinfo->OpCode == GDT_SCAN_END) {
  3124. cmndinfo->OpCode = -1;
  3125. /* retry */
  3126. cmndinfo->priority = HIGH_PRI;
  3127. return 2;
  3128. }
  3129. memset((char*)scp->sense_buffer,0,16);
  3130. scp->sense_buffer[0] = 0x70;
  3131. scp->sense_buffer[2] = NOT_READY;
  3132. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3133. } else if (service == CACHESERVICE) {
  3134. if (ha->status == S_CACHE_UNKNOWN &&
  3135. (ha->hdr[t].cluster_type &
  3136. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3137. /* bus reset -> force GDT_CLUST_INFO */
  3138. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3139. }
  3140. memset((char*)scp->sense_buffer,0,16);
  3141. if (ha->status == (ushort)S_CACHE_RESERV) {
  3142. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3143. } else {
  3144. scp->sense_buffer[0] = 0x70;
  3145. scp->sense_buffer[2] = NOT_READY;
  3146. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3147. }
  3148. if (!cmndinfo->internal_command) {
  3149. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3150. ha->dvr.eu.sync.ionode = ha->hanum;
  3151. ha->dvr.eu.sync.service = service;
  3152. ha->dvr.eu.sync.status = ha->status;
  3153. ha->dvr.eu.sync.info = ha->info;
  3154. ha->dvr.eu.sync.hostdrive = t;
  3155. if (ha->status >= 0x8000)
  3156. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3157. else
  3158. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3159. }
  3160. } else {
  3161. /* sense buffer filled from controller firmware (DMA) */
  3162. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3163. scp->result = DID_BAD_TARGET << 16;
  3164. } else {
  3165. scp->result = (DID_OK << 16) | ha->info;
  3166. }
  3167. }
  3168. }
  3169. if (!cmndinfo->wait_for_completion)
  3170. cmndinfo->wait_for_completion++;
  3171. else
  3172. return 1;
  3173. }
  3174. return 0;
  3175. }
  3176. static char *async_cache_tab[] = {
  3177. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3178. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3179. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3180. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3181. /* 2*/ "\005\000\002\006\004"
  3182. "GDT HA %u, Host Drive %lu not ready",
  3183. /* 3*/ "\005\000\002\006\004"
  3184. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3185. /* 4*/ "\005\000\002\006\004"
  3186. "GDT HA %u, mirror update on Host Drive %lu failed",
  3187. /* 5*/ "\005\000\002\006\004"
  3188. "GDT HA %u, Mirror Drive %lu failed",
  3189. /* 6*/ "\005\000\002\006\004"
  3190. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3191. /* 7*/ "\005\000\002\006\004"
  3192. "GDT HA %u, Host Drive %lu write protected",
  3193. /* 8*/ "\005\000\002\006\004"
  3194. "GDT HA %u, media changed in Host Drive %lu",
  3195. /* 9*/ "\005\000\002\006\004"
  3196. "GDT HA %u, Host Drive %lu is offline",
  3197. /*10*/ "\005\000\002\006\004"
  3198. "GDT HA %u, media change of Mirror Drive %lu",
  3199. /*11*/ "\005\000\002\006\004"
  3200. "GDT HA %u, Mirror Drive %lu is write protected",
  3201. /*12*/ "\005\000\002\006\004"
  3202. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3203. /*13*/ "\007\000\002\006\002\010\002"
  3204. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3205. /*14*/ "\005\000\002\006\002"
  3206. "GDT HA %u, Array Drive %u: FAIL state entered",
  3207. /*15*/ "\005\000\002\006\002"
  3208. "GDT HA %u, Array Drive %u: error",
  3209. /*16*/ "\007\000\002\006\002\010\002"
  3210. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3211. /*17*/ "\005\000\002\006\002"
  3212. "GDT HA %u, Array Drive %u: parity build failed",
  3213. /*18*/ "\005\000\002\006\002"
  3214. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3215. /*19*/ "\005\000\002\010\002"
  3216. "GDT HA %u, Test of Hot Fix %u failed",
  3217. /*20*/ "\005\000\002\006\002"
  3218. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3219. /*21*/ "\005\000\002\006\002"
  3220. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3221. /*22*/ "\007\000\002\006\002\010\002"
  3222. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3223. /*23*/ "\005\000\002\006\002"
  3224. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3225. /*24*/ "\005\000\002\010\002"
  3226. "GDT HA %u, mirror update on Cache Drive %u completed",
  3227. /*25*/ "\005\000\002\010\002"
  3228. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3229. /*26*/ "\005\000\002\006\002"
  3230. "GDT HA %u, Array Drive %u: drive rebuild started",
  3231. /*27*/ "\005\000\002\012\001"
  3232. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3233. /*28*/ "\005\000\002\012\001"
  3234. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3235. /*29*/ "\007\000\002\012\001\013\001"
  3236. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3237. /*30*/ "\007\000\002\012\001\013\001"
  3238. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3239. /*31*/ "\007\000\002\012\001\013\001"
  3240. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3241. /*32*/ "\007\000\002\012\001\013\001"
  3242. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3243. /*33*/ "\007\000\002\012\001\013\001"
  3244. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3245. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3246. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3247. /*35*/ "\007\000\002\012\001\013\001"
  3248. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3249. /*36*/ "\007\000\002\012\001\013\001"
  3250. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3251. /*37*/ "\007\000\002\012\001\006\004"
  3252. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3253. /*38*/ "\007\000\002\012\001\013\001"
  3254. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3255. /*39*/ "\007\000\002\012\001\013\001"
  3256. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3257. /*40*/ "\007\000\002\012\001\013\001"
  3258. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3259. /*41*/ "\007\000\002\012\001\013\001"
  3260. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3261. /*42*/ "\005\000\002\006\002"
  3262. "GDT HA %u, Array Drive %u: drive build started",
  3263. /*43*/ "\003\000\002"
  3264. "GDT HA %u, DRAM parity error detected",
  3265. /*44*/ "\005\000\002\006\002"
  3266. "GDT HA %u, Mirror Drive %u: update started",
  3267. /*45*/ "\007\000\002\006\002\010\002"
  3268. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3269. /*46*/ "\005\000\002\006\002"
  3270. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3271. /*47*/ "\005\000\002\006\002"
  3272. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3273. /*48*/ "\005\000\002\006\002"
  3274. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3275. /*49*/ "\005\000\002\006\002"
  3276. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3277. /*50*/ "\007\000\002\012\001\013\001"
  3278. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3279. /*51*/ "\005\000\002\006\002"
  3280. "GDT HA %u, Array Drive %u: expand started",
  3281. /*52*/ "\005\000\002\006\002"
  3282. "GDT HA %u, Array Drive %u: expand finished successfully",
  3283. /*53*/ "\005\000\002\006\002"
  3284. "GDT HA %u, Array Drive %u: expand failed",
  3285. /*54*/ "\003\000\002"
  3286. "GDT HA %u, CPU temperature critical",
  3287. /*55*/ "\003\000\002"
  3288. "GDT HA %u, CPU temperature OK",
  3289. /*56*/ "\005\000\002\006\004"
  3290. "GDT HA %u, Host drive %lu created",
  3291. /*57*/ "\005\000\002\006\002"
  3292. "GDT HA %u, Array Drive %u: expand restarted",
  3293. /*58*/ "\005\000\002\006\002"
  3294. "GDT HA %u, Array Drive %u: expand stopped",
  3295. /*59*/ "\005\000\002\010\002"
  3296. "GDT HA %u, Mirror Drive %u: drive build quited",
  3297. /*60*/ "\005\000\002\006\002"
  3298. "GDT HA %u, Array Drive %u: parity build quited",
  3299. /*61*/ "\005\000\002\006\002"
  3300. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3301. /*62*/ "\005\000\002\006\002"
  3302. "GDT HA %u, Array Drive %u: parity verify started",
  3303. /*63*/ "\005\000\002\006\002"
  3304. "GDT HA %u, Array Drive %u: parity verify done",
  3305. /*64*/ "\005\000\002\006\002"
  3306. "GDT HA %u, Array Drive %u: parity verify failed",
  3307. /*65*/ "\005\000\002\006\002"
  3308. "GDT HA %u, Array Drive %u: parity error detected",
  3309. /*66*/ "\005\000\002\006\002"
  3310. "GDT HA %u, Array Drive %u: parity verify quited",
  3311. /*67*/ "\005\000\002\006\002"
  3312. "GDT HA %u, Host Drive %u reserved",
  3313. /*68*/ "\005\000\002\006\002"
  3314. "GDT HA %u, Host Drive %u mounted and released",
  3315. /*69*/ "\005\000\002\006\002"
  3316. "GDT HA %u, Host Drive %u released",
  3317. /*70*/ "\003\000\002"
  3318. "GDT HA %u, DRAM error detected and corrected with ECC",
  3319. /*71*/ "\003\000\002"
  3320. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3321. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3322. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3323. /*73*/ "\005\000\002\006\002"
  3324. "GDT HA %u, Host drive %u resetted locally",
  3325. /*74*/ "\005\000\002\006\002"
  3326. "GDT HA %u, Host drive %u resetted remotely",
  3327. /*75*/ "\003\000\002"
  3328. "GDT HA %u, async. status 75 unknown",
  3329. };
  3330. static int gdth_async_event(gdth_ha_str *ha)
  3331. {
  3332. gdth_cmd_str *cmdp;
  3333. int cmd_index;
  3334. cmdp= ha->pccb;
  3335. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3336. ha->hanum, ha->service));
  3337. if (ha->service == SCREENSERVICE) {
  3338. if (ha->status == MSG_REQUEST) {
  3339. while (gdth_test_busy(ha))
  3340. gdth_delay(0);
  3341. cmdp->Service = SCREENSERVICE;
  3342. cmdp->RequestBuffer = SCREEN_CMND;
  3343. cmd_index = gdth_get_cmd_index(ha);
  3344. gdth_set_sema0(ha);
  3345. cmdp->OpCode = GDT_READ;
  3346. cmdp->BoardNode = LOCALBOARD;
  3347. cmdp->u.screen.reserved = 0;
  3348. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3349. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3350. ha->cmd_offs_dpmem = 0;
  3351. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3352. + sizeof(ulong64);
  3353. ha->cmd_cnt = 0;
  3354. gdth_copy_command(ha);
  3355. if (ha->type == GDT_EISA)
  3356. printk("[EISA slot %d] ",(ushort)ha->brd_phys);
  3357. else if (ha->type == GDT_ISA)
  3358. printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
  3359. else
  3360. printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
  3361. (ushort)((ha->brd_phys>>3)&0x1f));
  3362. gdth_release_event(ha);
  3363. }
  3364. } else {
  3365. if (ha->type == GDT_PCIMPR &&
  3366. (ha->fw_vers & 0xff) >= 0x1a) {
  3367. ha->dvr.size = 0;
  3368. ha->dvr.eu.async.ionode = ha->hanum;
  3369. ha->dvr.eu.async.status = ha->status;
  3370. /* severity and event_string already set! */
  3371. } else {
  3372. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3373. ha->dvr.eu.async.ionode = ha->hanum;
  3374. ha->dvr.eu.async.service = ha->service;
  3375. ha->dvr.eu.async.status = ha->status;
  3376. ha->dvr.eu.async.info = ha->info;
  3377. *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3378. }
  3379. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3380. gdth_log_event( &ha->dvr, NULL );
  3381. /* new host drive from expand? */
  3382. if (ha->service == CACHESERVICE && ha->status == 56) {
  3383. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3384. (ushort)ha->info));
  3385. /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
  3386. }
  3387. }
  3388. return 1;
  3389. }
  3390. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3391. {
  3392. gdth_stackframe stack;
  3393. char *f = NULL;
  3394. int i,j;
  3395. TRACE2(("gdth_log_event()\n"));
  3396. if (dvr->size == 0) {
  3397. if (buffer == NULL) {
  3398. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3399. } else {
  3400. sprintf(buffer,"Adapter %d: %s\n",
  3401. dvr->eu.async.ionode,dvr->event_string);
  3402. }
  3403. } else if (dvr->eu.async.service == CACHESERVICE &&
  3404. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3405. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3406. dvr->eu.async.status));
  3407. f = async_cache_tab[dvr->eu.async.status];
  3408. /* i: parameter to push, j: stack element to fill */
  3409. for (j=0,i=1; i < f[0]; i+=2) {
  3410. switch (f[i+1]) {
  3411. case 4:
  3412. stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
  3413. break;
  3414. case 2:
  3415. stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
  3416. break;
  3417. case 1:
  3418. stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
  3419. break;
  3420. default:
  3421. break;
  3422. }
  3423. }
  3424. if (buffer == NULL) {
  3425. printk(&f[(int)f[0]],stack);
  3426. printk("\n");
  3427. } else {
  3428. sprintf(buffer,&f[(int)f[0]],stack);
  3429. }
  3430. } else {
  3431. if (buffer == NULL) {
  3432. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3433. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3434. } else {
  3435. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3436. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3437. }
  3438. }
  3439. }
  3440. #ifdef GDTH_STATISTICS
  3441. static void gdth_timeout(ulong data)
  3442. {
  3443. ulong32 i;
  3444. Scsi_Cmnd *nscp;
  3445. gdth_ha_str *ha;
  3446. ulong flags;
  3447. ha = list_first_entry(&gdth_instances, gdth_ha_str, list);
  3448. spin_lock_irqsave(&ha->smp_lock, flags);
  3449. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3450. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3451. ++act_stats;
  3452. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3453. ++act_rq;
  3454. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3455. act_ints, act_ios, act_stats, act_rq));
  3456. act_ints = act_ios = 0;
  3457. gdth_timer.expires = jiffies + 30 * HZ;
  3458. add_timer(&gdth_timer);
  3459. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3460. }
  3461. #endif
  3462. static void __init internal_setup(char *str,int *ints)
  3463. {
  3464. int i, argc;
  3465. char *cur_str, *argv;
  3466. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3467. str ? str:"NULL", ints ? ints[0]:0));
  3468. /* read irq[] from ints[] */
  3469. if (ints) {
  3470. argc = ints[0];
  3471. if (argc > 0) {
  3472. if (argc > MAXHA)
  3473. argc = MAXHA;
  3474. for (i = 0; i < argc; ++i)
  3475. irq[i] = ints[i+1];
  3476. }
  3477. }
  3478. /* analyse string */
  3479. argv = str;
  3480. while (argv && (cur_str = strchr(argv, ':'))) {
  3481. int val = 0, c = *++cur_str;
  3482. if (c == 'n' || c == 'N')
  3483. val = 0;
  3484. else if (c == 'y' || c == 'Y')
  3485. val = 1;
  3486. else
  3487. val = (int)simple_strtoul(cur_str, NULL, 0);
  3488. if (!strncmp(argv, "disable:", 8))
  3489. disable = val;
  3490. else if (!strncmp(argv, "reserve_mode:", 13))
  3491. reserve_mode = val;
  3492. else if (!strncmp(argv, "reverse_scan:", 13))
  3493. reverse_scan = val;
  3494. else if (!strncmp(argv, "hdr_channel:", 12))
  3495. hdr_channel = val;
  3496. else if (!strncmp(argv, "max_ids:", 8))
  3497. max_ids = val;
  3498. else if (!strncmp(argv, "rescan:", 7))
  3499. rescan = val;
  3500. else if (!strncmp(argv, "shared_access:", 14))
  3501. shared_access = val;
  3502. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3503. probe_eisa_isa = val;
  3504. else if (!strncmp(argv, "reserve_list:", 13)) {
  3505. reserve_list[0] = val;
  3506. for (i = 1; i < MAX_RES_ARGS; i++) {
  3507. cur_str = strchr(cur_str, ',');
  3508. if (!cur_str)
  3509. break;
  3510. if (!isdigit((int)*++cur_str)) {
  3511. --cur_str;
  3512. break;
  3513. }
  3514. reserve_list[i] =
  3515. (int)simple_strtoul(cur_str, NULL, 0);
  3516. }
  3517. if (!cur_str)
  3518. break;
  3519. argv = ++cur_str;
  3520. continue;
  3521. }
  3522. if ((argv = strchr(argv, ',')))
  3523. ++argv;
  3524. }
  3525. }
  3526. int __init option_setup(char *str)
  3527. {
  3528. int ints[MAXHA];
  3529. char *cur = str;
  3530. int i = 1;
  3531. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3532. while (cur && isdigit(*cur) && i <= MAXHA) {
  3533. ints[i++] = simple_strtoul(cur, NULL, 0);
  3534. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3535. }
  3536. ints[0] = i - 1;
  3537. internal_setup(cur, ints);
  3538. return 1;
  3539. }
  3540. static const char *gdth_ctr_name(gdth_ha_str *ha)
  3541. {
  3542. TRACE2(("gdth_ctr_name()\n"));
  3543. if (ha->type == GDT_EISA) {
  3544. switch (ha->stype) {
  3545. case GDT3_ID:
  3546. return("GDT3000/3020");
  3547. case GDT3A_ID:
  3548. return("GDT3000A/3020A/3050A");
  3549. case GDT3B_ID:
  3550. return("GDT3000B/3010A");
  3551. }
  3552. } else if (ha->type == GDT_ISA) {
  3553. return("GDT2000/2020");
  3554. } else if (ha->type == GDT_PCI) {
  3555. switch (ha->pdev->device) {
  3556. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  3557. return("GDT6000/6020/6050");
  3558. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  3559. return("GDT6000B/6010");
  3560. }
  3561. }
  3562. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  3563. return("");
  3564. }
  3565. static const char *gdth_info(struct Scsi_Host *shp)
  3566. {
  3567. gdth_ha_str *ha = shost_priv(shp);
  3568. TRACE2(("gdth_info()\n"));
  3569. return ((const char *)ha->binfo.type_string);
  3570. }
  3571. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  3572. {
  3573. gdth_ha_str *ha = shost_priv(scp->device->host);
  3574. int i;
  3575. ulong flags;
  3576. Scsi_Cmnd *cmnd;
  3577. unchar b;
  3578. TRACE2(("gdth_eh_bus_reset()\n"));
  3579. b = scp->device->channel;
  3580. /* clear command tab */
  3581. spin_lock_irqsave(&ha->smp_lock, flags);
  3582. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  3583. cmnd = ha->cmd_tab[i].cmnd;
  3584. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  3585. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  3586. }
  3587. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3588. if (b == ha->virt_bus) {
  3589. /* host drives */
  3590. for (i = 0; i < MAX_HDRIVES; ++i) {
  3591. if (ha->hdr[i].present) {
  3592. spin_lock_irqsave(&ha->smp_lock, flags);
  3593. gdth_polling = TRUE;
  3594. while (gdth_test_busy(ha))
  3595. gdth_delay(0);
  3596. if (gdth_internal_cmd(ha, CACHESERVICE,
  3597. GDT_CLUST_RESET, i, 0, 0))
  3598. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  3599. gdth_polling = FALSE;
  3600. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3601. }
  3602. }
  3603. } else {
  3604. /* raw devices */
  3605. spin_lock_irqsave(&ha->smp_lock, flags);
  3606. for (i = 0; i < MAXID; ++i)
  3607. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  3608. gdth_polling = TRUE;
  3609. while (gdth_test_busy(ha))
  3610. gdth_delay(0);
  3611. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESET_BUS,
  3612. BUS_L2P(ha,b), 0, 0);
  3613. gdth_polling = FALSE;
  3614. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3615. }
  3616. return SUCCESS;
  3617. }
  3618. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  3619. {
  3620. unchar b, t;
  3621. gdth_ha_str *ha = shost_priv(sdev->host);
  3622. struct scsi_device *sd;
  3623. unsigned capacity;
  3624. sd = sdev;
  3625. capacity = cap;
  3626. b = sd->channel;
  3627. t = sd->id;
  3628. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", ha->hanum, b, t));
  3629. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  3630. /* raw device or host drive without mapping information */
  3631. TRACE2(("Evaluate mapping\n"));
  3632. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  3633. } else {
  3634. ip[0] = ha->hdr[t].heads;
  3635. ip[1] = ha->hdr[t].secs;
  3636. ip[2] = capacity / ip[0] / ip[1];
  3637. }
  3638. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  3639. ip[0],ip[1],ip[2]));
  3640. return 0;
  3641. }
  3642. static int gdth_queuecommand(struct scsi_cmnd *scp,
  3643. void (*done)(struct scsi_cmnd *))
  3644. {
  3645. gdth_ha_str *ha = shost_priv(scp->device->host);
  3646. struct gdth_cmndinfo *cmndinfo;
  3647. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  3648. cmndinfo = gdth_get_cmndinfo(ha);
  3649. BUG_ON(!cmndinfo);
  3650. scp->scsi_done = done;
  3651. gdth_update_timeout(scp, scp->timeout_per_command * 6);
  3652. cmndinfo->priority = DEFAULT_PRI;
  3653. gdth_set_bufflen(scp, scsi_bufflen(scp));
  3654. gdth_set_sg_count(scp, scsi_sg_count(scp));
  3655. gdth_set_sglist(scp, scsi_sglist(scp));
  3656. return __gdth_queuecommand(ha, scp, cmndinfo);
  3657. }
  3658. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  3659. struct gdth_cmndinfo *cmndinfo)
  3660. {
  3661. scp->host_scribble = (unsigned char *)cmndinfo;
  3662. cmndinfo->wait_for_completion = 1;
  3663. cmndinfo->phase = -1;
  3664. cmndinfo->OpCode = -1;
  3665. #ifdef GDTH_STATISTICS
  3666. ++act_ios;
  3667. #endif
  3668. gdth_putq(ha, scp, cmndinfo->priority);
  3669. gdth_next(ha);
  3670. return 0;
  3671. }
  3672. static int gdth_open(struct inode *inode, struct file *filep)
  3673. {
  3674. gdth_ha_str *ha;
  3675. list_for_each_entry(ha, &gdth_instances, list) {
  3676. if (!ha->sdev)
  3677. ha->sdev = scsi_get_host_dev(ha->shost);
  3678. }
  3679. TRACE(("gdth_open()\n"));
  3680. return 0;
  3681. }
  3682. static int gdth_close(struct inode *inode, struct file *filep)
  3683. {
  3684. TRACE(("gdth_close()\n"));
  3685. return 0;
  3686. }
  3687. static int ioc_event(void __user *arg)
  3688. {
  3689. gdth_ioctl_event evt;
  3690. gdth_ha_str *ha;
  3691. ulong flags;
  3692. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)))
  3693. return -EFAULT;
  3694. ha = gdth_find_ha(evt.ionode);
  3695. if (!ha)
  3696. return -EFAULT;
  3697. if (evt.erase == 0xff) {
  3698. if (evt.event.event_source == ES_TEST)
  3699. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  3700. else if (evt.event.event_source == ES_DRIVER)
  3701. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  3702. else if (evt.event.event_source == ES_SYNC)
  3703. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  3704. else
  3705. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  3706. spin_lock_irqsave(&ha->smp_lock, flags);
  3707. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  3708. &evt.event.event_data);
  3709. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3710. } else if (evt.erase == 0xfe) {
  3711. gdth_clear_events();
  3712. } else if (evt.erase == 0) {
  3713. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  3714. } else {
  3715. gdth_readapp_event(ha, evt.erase, &evt.event);
  3716. }
  3717. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  3718. return -EFAULT;
  3719. return 0;
  3720. }
  3721. static int ioc_lockdrv(void __user *arg)
  3722. {
  3723. gdth_ioctl_lockdrv ldrv;
  3724. unchar i, j;
  3725. ulong flags;
  3726. gdth_ha_str *ha;
  3727. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)))
  3728. return -EFAULT;
  3729. ha = gdth_find_ha(ldrv.ionode);
  3730. if (!ha)
  3731. return -EFAULT;
  3732. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  3733. j = ldrv.drives[i];
  3734. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  3735. continue;
  3736. if (ldrv.lock) {
  3737. spin_lock_irqsave(&ha->smp_lock, flags);
  3738. ha->hdr[j].lock = 1;
  3739. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3740. gdth_wait_completion(ha, ha->bus_cnt, j);
  3741. gdth_stop_timeout(ha, ha->bus_cnt, j);
  3742. } else {
  3743. spin_lock_irqsave(&ha->smp_lock, flags);
  3744. ha->hdr[j].lock = 0;
  3745. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3746. gdth_start_timeout(ha, ha->bus_cnt, j);
  3747. gdth_next(ha);
  3748. }
  3749. }
  3750. return 0;
  3751. }
  3752. static int ioc_resetdrv(void __user *arg, char *cmnd)
  3753. {
  3754. gdth_ioctl_reset res;
  3755. gdth_cmd_str cmd;
  3756. gdth_ha_str *ha;
  3757. int rval;
  3758. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  3759. res.number >= MAX_HDRIVES)
  3760. return -EFAULT;
  3761. ha = gdth_find_ha(res.ionode);
  3762. if (!ha)
  3763. return -EFAULT;
  3764. if (!ha->hdr[res.number].present)
  3765. return 0;
  3766. memset(&cmd, 0, sizeof(gdth_cmd_str));
  3767. cmd.Service = CACHESERVICE;
  3768. cmd.OpCode = GDT_CLUST_RESET;
  3769. if (ha->cache_feat & GDT_64BIT)
  3770. cmd.u.cache64.DeviceNo = res.number;
  3771. else
  3772. cmd.u.cache.DeviceNo = res.number;
  3773. rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
  3774. if (rval < 0)
  3775. return rval;
  3776. res.status = rval;
  3777. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  3778. return -EFAULT;
  3779. return 0;
  3780. }
  3781. static int ioc_general(void __user *arg, char *cmnd)
  3782. {
  3783. gdth_ioctl_general gen;
  3784. char *buf = NULL;
  3785. ulong64 paddr;
  3786. gdth_ha_str *ha;
  3787. int rval;
  3788. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)))
  3789. return -EFAULT;
  3790. ha = gdth_find_ha(gen.ionode);
  3791. if (!ha)
  3792. return -EFAULT;
  3793. if (gen.data_len + gen.sense_len != 0) {
  3794. if (!(buf = gdth_ioctl_alloc(ha, gen.data_len + gen.sense_len,
  3795. FALSE, &paddr)))
  3796. return -EFAULT;
  3797. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  3798. gen.data_len + gen.sense_len)) {
  3799. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3800. return -EFAULT;
  3801. }
  3802. if (gen.command.OpCode == GDT_IOCTL) {
  3803. gen.command.u.ioctl.p_param = paddr;
  3804. } else if (gen.command.Service == CACHESERVICE) {
  3805. if (ha->cache_feat & GDT_64BIT) {
  3806. /* copy elements from 32-bit IOCTL structure */
  3807. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  3808. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  3809. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  3810. /* addresses */
  3811. if (ha->cache_feat & SCATTER_GATHER) {
  3812. gen.command.u.cache64.DestAddr = (ulong64)-1;
  3813. gen.command.u.cache64.sg_canz = 1;
  3814. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  3815. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  3816. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  3817. } else {
  3818. gen.command.u.cache64.DestAddr = paddr;
  3819. gen.command.u.cache64.sg_canz = 0;
  3820. }
  3821. } else {
  3822. if (ha->cache_feat & SCATTER_GATHER) {
  3823. gen.command.u.cache.DestAddr = 0xffffffff;
  3824. gen.command.u.cache.sg_canz = 1;
  3825. gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
  3826. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  3827. gen.command.u.cache.sg_lst[1].sg_len = 0;
  3828. } else {
  3829. gen.command.u.cache.DestAddr = paddr;
  3830. gen.command.u.cache.sg_canz = 0;
  3831. }
  3832. }
  3833. } else if (gen.command.Service == SCSIRAWSERVICE) {
  3834. if (ha->raw_feat & GDT_64BIT) {
  3835. /* copy elements from 32-bit IOCTL structure */
  3836. char cmd[16];
  3837. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  3838. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  3839. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  3840. gen.command.u.raw64.target = gen.command.u.raw.target;
  3841. memcpy(cmd, gen.command.u.raw.cmd, 16);
  3842. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  3843. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  3844. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  3845. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  3846. /* addresses */
  3847. if (ha->raw_feat & SCATTER_GATHER) {
  3848. gen.command.u.raw64.sdata = (ulong64)-1;
  3849. gen.command.u.raw64.sg_ranz = 1;
  3850. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  3851. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  3852. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  3853. } else {
  3854. gen.command.u.raw64.sdata = paddr;
  3855. gen.command.u.raw64.sg_ranz = 0;
  3856. }
  3857. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  3858. } else {
  3859. if (ha->raw_feat & SCATTER_GATHER) {
  3860. gen.command.u.raw.sdata = 0xffffffff;
  3861. gen.command.u.raw.sg_ranz = 1;
  3862. gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
  3863. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  3864. gen.command.u.raw.sg_lst[1].sg_len = 0;
  3865. } else {
  3866. gen.command.u.raw.sdata = paddr;
  3867. gen.command.u.raw.sg_ranz = 0;
  3868. }
  3869. gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
  3870. }
  3871. } else {
  3872. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3873. return -EFAULT;
  3874. }
  3875. }
  3876. rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
  3877. if (rval < 0)
  3878. return rval;
  3879. gen.status = rval;
  3880. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  3881. gen.data_len + gen.sense_len)) {
  3882. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3883. return -EFAULT;
  3884. }
  3885. if (copy_to_user(arg, &gen,
  3886. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  3887. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3888. return -EFAULT;
  3889. }
  3890. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3891. return 0;
  3892. }
  3893. static int ioc_hdrlist(void __user *arg, char *cmnd)
  3894. {
  3895. gdth_ioctl_rescan *rsc;
  3896. gdth_cmd_str *cmd;
  3897. gdth_ha_str *ha;
  3898. unchar i;
  3899. int rc = -ENOMEM;
  3900. u32 cluster_type = 0;
  3901. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3902. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3903. if (!rsc || !cmd)
  3904. goto free_fail;
  3905. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3906. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3907. rc = -EFAULT;
  3908. goto free_fail;
  3909. }
  3910. memset(cmd, 0, sizeof(gdth_cmd_str));
  3911. for (i = 0; i < MAX_HDRIVES; ++i) {
  3912. if (!ha->hdr[i].present) {
  3913. rsc->hdr_list[i].bus = 0xff;
  3914. continue;
  3915. }
  3916. rsc->hdr_list[i].bus = ha->virt_bus;
  3917. rsc->hdr_list[i].target = i;
  3918. rsc->hdr_list[i].lun = 0;
  3919. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  3920. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  3921. cmd->Service = CACHESERVICE;
  3922. cmd->OpCode = GDT_CLUST_INFO;
  3923. if (ha->cache_feat & GDT_64BIT)
  3924. cmd->u.cache64.DeviceNo = i;
  3925. else
  3926. cmd->u.cache.DeviceNo = i;
  3927. if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
  3928. rsc->hdr_list[i].cluster_type = cluster_type;
  3929. }
  3930. }
  3931. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  3932. rc = -EFAULT;
  3933. else
  3934. rc = 0;
  3935. free_fail:
  3936. kfree(rsc);
  3937. kfree(cmd);
  3938. return rc;
  3939. }
  3940. static int ioc_rescan(void __user *arg, char *cmnd)
  3941. {
  3942. gdth_ioctl_rescan *rsc;
  3943. gdth_cmd_str *cmd;
  3944. ushort i, status, hdr_cnt;
  3945. ulong32 info;
  3946. int cyls, hds, secs;
  3947. int rc = -ENOMEM;
  3948. ulong flags;
  3949. gdth_ha_str *ha;
  3950. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3951. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3952. if (!cmd || !rsc)
  3953. goto free_fail;
  3954. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3955. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3956. rc = -EFAULT;
  3957. goto free_fail;
  3958. }
  3959. memset(cmd, 0, sizeof(gdth_cmd_str));
  3960. if (rsc->flag == 0) {
  3961. /* old method: re-init. cache service */
  3962. cmd->Service = CACHESERVICE;
  3963. if (ha->cache_feat & GDT_64BIT) {
  3964. cmd->OpCode = GDT_X_INIT_HOST;
  3965. cmd->u.cache64.DeviceNo = LINUX_OS;
  3966. } else {
  3967. cmd->OpCode = GDT_INIT;
  3968. cmd->u.cache.DeviceNo = LINUX_OS;
  3969. }
  3970. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3971. i = 0;
  3972. hdr_cnt = (status == S_OK ? (ushort)info : 0);
  3973. } else {
  3974. i = rsc->hdr_no;
  3975. hdr_cnt = i + 1;
  3976. }
  3977. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  3978. cmd->Service = CACHESERVICE;
  3979. cmd->OpCode = GDT_INFO;
  3980. if (ha->cache_feat & GDT_64BIT)
  3981. cmd->u.cache64.DeviceNo = i;
  3982. else
  3983. cmd->u.cache.DeviceNo = i;
  3984. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3985. spin_lock_irqsave(&ha->smp_lock, flags);
  3986. rsc->hdr_list[i].bus = ha->virt_bus;
  3987. rsc->hdr_list[i].target = i;
  3988. rsc->hdr_list[i].lun = 0;
  3989. if (status != S_OK) {
  3990. ha->hdr[i].present = FALSE;
  3991. } else {
  3992. ha->hdr[i].present = TRUE;
  3993. ha->hdr[i].size = info;
  3994. /* evaluate mapping */
  3995. ha->hdr[i].size &= ~SECS32;
  3996. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  3997. ha->hdr[i].heads = hds;
  3998. ha->hdr[i].secs = secs;
  3999. /* round size */
  4000. ha->hdr[i].size = cyls * hds * secs;
  4001. }
  4002. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4003. if (status != S_OK)
  4004. continue;
  4005. /* extended info, if GDT_64BIT, for drives > 2 TB */
  4006. /* but we need ha->info2, not yet stored in scp->SCp */
  4007. /* devtype, cluster info, R/W attribs */
  4008. cmd->Service = CACHESERVICE;
  4009. cmd->OpCode = GDT_DEVTYPE;
  4010. if (ha->cache_feat & GDT_64BIT)
  4011. cmd->u.cache64.DeviceNo = i;
  4012. else
  4013. cmd->u.cache.DeviceNo = i;
  4014. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4015. spin_lock_irqsave(&ha->smp_lock, flags);
  4016. ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
  4017. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4018. cmd->Service = CACHESERVICE;
  4019. cmd->OpCode = GDT_CLUST_INFO;
  4020. if (ha->cache_feat & GDT_64BIT)
  4021. cmd->u.cache64.DeviceNo = i;
  4022. else
  4023. cmd->u.cache.DeviceNo = i;
  4024. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4025. spin_lock_irqsave(&ha->smp_lock, flags);
  4026. ha->hdr[i].cluster_type =
  4027. ((status == S_OK && !shared_access) ? (ushort)info : 0);
  4028. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4029. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4030. cmd->Service = CACHESERVICE;
  4031. cmd->OpCode = GDT_RW_ATTRIBS;
  4032. if (ha->cache_feat & GDT_64BIT)
  4033. cmd->u.cache64.DeviceNo = i;
  4034. else
  4035. cmd->u.cache.DeviceNo = i;
  4036. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4037. spin_lock_irqsave(&ha->smp_lock, flags);
  4038. ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
  4039. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4040. }
  4041. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4042. rc = -EFAULT;
  4043. else
  4044. rc = 0;
  4045. free_fail:
  4046. kfree(rsc);
  4047. kfree(cmd);
  4048. return rc;
  4049. }
  4050. static int gdth_ioctl(struct inode *inode, struct file *filep,
  4051. unsigned int cmd, unsigned long arg)
  4052. {
  4053. gdth_ha_str *ha;
  4054. Scsi_Cmnd *scp;
  4055. ulong flags;
  4056. char cmnd[MAX_COMMAND_SIZE];
  4057. void __user *argp = (void __user *)arg;
  4058. memset(cmnd, 0xff, 12);
  4059. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4060. switch (cmd) {
  4061. case GDTIOCTL_CTRCNT:
  4062. {
  4063. int cnt = gdth_ctr_count;
  4064. if (put_user(cnt, (int __user *)argp))
  4065. return -EFAULT;
  4066. break;
  4067. }
  4068. case GDTIOCTL_DRVERS:
  4069. {
  4070. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4071. if (put_user(ver, (int __user *)argp))
  4072. return -EFAULT;
  4073. break;
  4074. }
  4075. case GDTIOCTL_OSVERS:
  4076. {
  4077. gdth_ioctl_osvers osv;
  4078. osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
  4079. osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
  4080. osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
  4081. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4082. return -EFAULT;
  4083. break;
  4084. }
  4085. case GDTIOCTL_CTRTYPE:
  4086. {
  4087. gdth_ioctl_ctrtype ctrt;
  4088. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4089. (NULL == (ha = gdth_find_ha(ctrt.ionode))))
  4090. return -EFAULT;
  4091. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4092. ctrt.type = (unchar)((ha->stype>>20) - 0x10);
  4093. } else {
  4094. if (ha->type != GDT_PCIMPR) {
  4095. ctrt.type = (unchar)((ha->stype<<4) + 6);
  4096. } else {
  4097. ctrt.type =
  4098. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4099. if (ha->stype >= 0x300)
  4100. ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
  4101. else
  4102. ctrt.ext_type = 0x6000 | ha->stype;
  4103. }
  4104. ctrt.device_id = ha->pdev->device;
  4105. ctrt.sub_device_id = ha->pdev->subsystem_device;
  4106. }
  4107. ctrt.info = ha->brd_phys;
  4108. ctrt.oem_id = ha->oem_id;
  4109. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4110. return -EFAULT;
  4111. break;
  4112. }
  4113. case GDTIOCTL_GENERAL:
  4114. return ioc_general(argp, cmnd);
  4115. case GDTIOCTL_EVENT:
  4116. return ioc_event(argp);
  4117. case GDTIOCTL_LOCKDRV:
  4118. return ioc_lockdrv(argp);
  4119. case GDTIOCTL_LOCKCHN:
  4120. {
  4121. gdth_ioctl_lockchn lchn;
  4122. unchar i, j;
  4123. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  4124. (NULL == (ha = gdth_find_ha(lchn.ionode))))
  4125. return -EFAULT;
  4126. i = lchn.channel;
  4127. if (i < ha->bus_cnt) {
  4128. if (lchn.lock) {
  4129. spin_lock_irqsave(&ha->smp_lock, flags);
  4130. ha->raw[i].lock = 1;
  4131. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4132. for (j = 0; j < ha->tid_cnt; ++j) {
  4133. gdth_wait_completion(ha, i, j);
  4134. gdth_stop_timeout(ha, i, j);
  4135. }
  4136. } else {
  4137. spin_lock_irqsave(&ha->smp_lock, flags);
  4138. ha->raw[i].lock = 0;
  4139. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4140. for (j = 0; j < ha->tid_cnt; ++j) {
  4141. gdth_start_timeout(ha, i, j);
  4142. gdth_next(ha);
  4143. }
  4144. }
  4145. }
  4146. break;
  4147. }
  4148. case GDTIOCTL_RESCAN:
  4149. return ioc_rescan(argp, cmnd);
  4150. case GDTIOCTL_HDRLIST:
  4151. return ioc_hdrlist(argp, cmnd);
  4152. case GDTIOCTL_RESET_BUS:
  4153. {
  4154. gdth_ioctl_reset res;
  4155. int rval;
  4156. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  4157. (NULL == (ha = gdth_find_ha(res.ionode))))
  4158. return -EFAULT;
  4159. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  4160. if (!scp)
  4161. return -ENOMEM;
  4162. scp->device = ha->sdev;
  4163. scp->cmd_len = 12;
  4164. scp->device->channel = res.number;
  4165. rval = gdth_eh_bus_reset(scp);
  4166. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  4167. kfree(scp);
  4168. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  4169. return -EFAULT;
  4170. break;
  4171. }
  4172. case GDTIOCTL_RESET_DRV:
  4173. return ioc_resetdrv(argp, cmnd);
  4174. default:
  4175. break;
  4176. }
  4177. return 0;
  4178. }
  4179. /* flush routine */
  4180. static void gdth_flush(gdth_ha_str *ha)
  4181. {
  4182. int i;
  4183. gdth_cmd_str gdtcmd;
  4184. char cmnd[MAX_COMMAND_SIZE];
  4185. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4186. TRACE2(("gdth_flush() hanum %d\n", ha->hanum));
  4187. for (i = 0; i < MAX_HDRIVES; ++i) {
  4188. if (ha->hdr[i].present) {
  4189. gdtcmd.BoardNode = LOCALBOARD;
  4190. gdtcmd.Service = CACHESERVICE;
  4191. gdtcmd.OpCode = GDT_FLUSH;
  4192. if (ha->cache_feat & GDT_64BIT) {
  4193. gdtcmd.u.cache64.DeviceNo = i;
  4194. gdtcmd.u.cache64.BlockNo = 1;
  4195. gdtcmd.u.cache64.sg_canz = 0;
  4196. } else {
  4197. gdtcmd.u.cache.DeviceNo = i;
  4198. gdtcmd.u.cache.BlockNo = 1;
  4199. gdtcmd.u.cache.sg_canz = 0;
  4200. }
  4201. TRACE2(("gdth_flush(): flush ha %d drive %d\n", ha->hanum, i));
  4202. gdth_execute(ha->shost, &gdtcmd, cmnd, 30, NULL);
  4203. }
  4204. }
  4205. }
  4206. /* shutdown routine */
  4207. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
  4208. {
  4209. gdth_ha_str *ha;
  4210. #ifndef __alpha__
  4211. gdth_cmd_str gdtcmd;
  4212. char cmnd[MAX_COMMAND_SIZE];
  4213. #endif
  4214. if (notifier_disabled)
  4215. return NOTIFY_OK;
  4216. TRACE2(("gdth_halt() event %d\n",(int)event));
  4217. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  4218. return NOTIFY_DONE;
  4219. notifier_disabled = 1;
  4220. printk("GDT-HA: Flushing all host drives .. ");
  4221. list_for_each_entry(ha, &gdth_instances, list) {
  4222. gdth_flush(ha);
  4223. #ifndef __alpha__
  4224. /* controller reset */
  4225. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4226. gdtcmd.BoardNode = LOCALBOARD;
  4227. gdtcmd.Service = CACHESERVICE;
  4228. gdtcmd.OpCode = GDT_RESET;
  4229. TRACE2(("gdth_halt(): reset controller %d\n", ha->hanum));
  4230. gdth_execute(ha->shost, &gdtcmd, cmnd, 10, NULL);
  4231. #endif
  4232. }
  4233. printk("Done.\n");
  4234. #ifdef GDTH_STATISTICS
  4235. del_timer(&gdth_timer);
  4236. #endif
  4237. return NOTIFY_OK;
  4238. }
  4239. /* configure lun */
  4240. static int gdth_slave_configure(struct scsi_device *sdev)
  4241. {
  4242. scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
  4243. sdev->skip_ms_page_3f = 1;
  4244. sdev->skip_ms_page_8 = 1;
  4245. return 0;
  4246. }
  4247. static struct scsi_host_template gdth_template = {
  4248. .name = "GDT SCSI Disk Array Controller",
  4249. .info = gdth_info,
  4250. .queuecommand = gdth_queuecommand,
  4251. .eh_bus_reset_handler = gdth_eh_bus_reset,
  4252. .slave_configure = gdth_slave_configure,
  4253. .bios_param = gdth_bios_param,
  4254. .proc_info = gdth_proc_info,
  4255. .proc_name = "gdth",
  4256. .can_queue = GDTH_MAXCMDS,
  4257. .this_id = -1,
  4258. .sg_tablesize = GDTH_MAXSG,
  4259. .cmd_per_lun = GDTH_MAXC_P_L,
  4260. .unchecked_isa_dma = 1,
  4261. .use_clustering = ENABLE_CLUSTERING,
  4262. };
  4263. #ifdef CONFIG_ISA
  4264. static int __init gdth_isa_probe_one(ulong32 isa_bios)
  4265. {
  4266. struct Scsi_Host *shp;
  4267. gdth_ha_str *ha;
  4268. dma_addr_t scratch_dma_handle = 0;
  4269. int error, i;
  4270. if (!gdth_search_isa(isa_bios))
  4271. return -ENXIO;
  4272. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4273. if (!shp)
  4274. return -ENOMEM;
  4275. ha = shost_priv(shp);
  4276. error = -ENODEV;
  4277. if (!gdth_init_isa(isa_bios,ha))
  4278. goto out_host_put;
  4279. /* controller found and initialized */
  4280. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  4281. isa_bios, ha->irq, ha->drq);
  4282. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4283. if (error) {
  4284. printk("GDT-ISA: Unable to allocate IRQ\n");
  4285. goto out_host_put;
  4286. }
  4287. error = request_dma(ha->drq, "gdth");
  4288. if (error) {
  4289. printk("GDT-ISA: Unable to allocate DMA channel\n");
  4290. goto out_free_irq;
  4291. }
  4292. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  4293. enable_dma(ha->drq);
  4294. shp->unchecked_isa_dma = 1;
  4295. shp->irq = ha->irq;
  4296. shp->dma_channel = ha->drq;
  4297. ha->hanum = gdth_ctr_count++;
  4298. ha->shost = shp;
  4299. ha->pccb = &ha->cmdext;
  4300. ha->ccb_phys = 0L;
  4301. ha->pdev = NULL;
  4302. error = -ENOMEM;
  4303. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4304. &scratch_dma_handle);
  4305. if (!ha->pscratch)
  4306. goto out_dec_counters;
  4307. ha->scratch_phys = scratch_dma_handle;
  4308. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4309. &scratch_dma_handle);
  4310. if (!ha->pmsg)
  4311. goto out_free_pscratch;
  4312. ha->msg_phys = scratch_dma_handle;
  4313. #ifdef INT_COAL
  4314. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4315. sizeof(gdth_coal_status) * MAXOFFSETS,
  4316. &scratch_dma_handle);
  4317. if (!ha->coal_stat)
  4318. goto out_free_pmsg;
  4319. ha->coal_stat_phys = scratch_dma_handle;
  4320. #endif
  4321. ha->scratch_busy = FALSE;
  4322. ha->req_first = NULL;
  4323. ha->tid_cnt = MAX_HDRIVES;
  4324. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4325. ha->tid_cnt = max_ids;
  4326. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4327. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4328. ha->scan_mode = rescan ? 0x10 : 0;
  4329. error = -ENODEV;
  4330. if (!gdth_search_drives(ha)) {
  4331. printk("GDT-ISA: Error during device scan\n");
  4332. goto out_free_coal_stat;
  4333. }
  4334. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4335. hdr_channel = ha->bus_cnt;
  4336. ha->virt_bus = hdr_channel;
  4337. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4338. shp->max_cmd_len = 16;
  4339. shp->max_id = ha->tid_cnt;
  4340. shp->max_lun = MAXLUN;
  4341. shp->max_channel = ha->bus_cnt;
  4342. spin_lock_init(&ha->smp_lock);
  4343. gdth_enable_int(ha);
  4344. error = scsi_add_host(shp, NULL);
  4345. if (error)
  4346. goto out_free_coal_stat;
  4347. list_add_tail(&ha->list, &gdth_instances);
  4348. return 0;
  4349. out_free_coal_stat:
  4350. #ifdef INT_COAL
  4351. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4352. ha->coal_stat, ha->coal_stat_phys);
  4353. out_free_pmsg:
  4354. #endif
  4355. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4356. ha->pmsg, ha->msg_phys);
  4357. out_free_pscratch:
  4358. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4359. ha->pscratch, ha->scratch_phys);
  4360. out_dec_counters:
  4361. gdth_ctr_count--;
  4362. out_free_irq:
  4363. free_irq(ha->irq, ha);
  4364. out_host_put:
  4365. scsi_host_put(shp);
  4366. return error;
  4367. }
  4368. #endif /* CONFIG_ISA */
  4369. #ifdef CONFIG_EISA
  4370. static int __init gdth_eisa_probe_one(ushort eisa_slot)
  4371. {
  4372. struct Scsi_Host *shp;
  4373. gdth_ha_str *ha;
  4374. dma_addr_t scratch_dma_handle = 0;
  4375. int error, i;
  4376. if (!gdth_search_eisa(eisa_slot))
  4377. return -ENXIO;
  4378. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4379. if (!shp)
  4380. return -ENOMEM;
  4381. ha = shost_priv(shp);
  4382. error = -ENODEV;
  4383. if (!gdth_init_eisa(eisa_slot,ha))
  4384. goto out_host_put;
  4385. /* controller found and initialized */
  4386. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  4387. eisa_slot >> 12, ha->irq);
  4388. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4389. if (error) {
  4390. printk("GDT-EISA: Unable to allocate IRQ\n");
  4391. goto out_host_put;
  4392. }
  4393. shp->unchecked_isa_dma = 0;
  4394. shp->irq = ha->irq;
  4395. shp->dma_channel = 0xff;
  4396. ha->hanum = gdth_ctr_count++;
  4397. ha->shost = shp;
  4398. TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum));
  4399. ha->pccb = &ha->cmdext;
  4400. ha->ccb_phys = 0L;
  4401. error = -ENOMEM;
  4402. ha->pdev = NULL;
  4403. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4404. &scratch_dma_handle);
  4405. if (!ha->pscratch)
  4406. goto out_free_irq;
  4407. ha->scratch_phys = scratch_dma_handle;
  4408. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4409. &scratch_dma_handle);
  4410. if (!ha->pmsg)
  4411. goto out_free_pscratch;
  4412. ha->msg_phys = scratch_dma_handle;
  4413. #ifdef INT_COAL
  4414. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4415. sizeof(gdth_coal_status) * MAXOFFSETS,
  4416. &scratch_dma_handle);
  4417. if (!ha->coal_stat)
  4418. goto out_free_pmsg;
  4419. ha->coal_stat_phys = scratch_dma_handle;
  4420. #endif
  4421. ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
  4422. sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
  4423. if (!ha->ccb_phys)
  4424. goto out_free_coal_stat;
  4425. ha->scratch_busy = FALSE;
  4426. ha->req_first = NULL;
  4427. ha->tid_cnt = MAX_HDRIVES;
  4428. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4429. ha->tid_cnt = max_ids;
  4430. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4431. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4432. ha->scan_mode = rescan ? 0x10 : 0;
  4433. if (!gdth_search_drives(ha)) {
  4434. printk("GDT-EISA: Error during device scan\n");
  4435. error = -ENODEV;
  4436. goto out_free_ccb_phys;
  4437. }
  4438. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4439. hdr_channel = ha->bus_cnt;
  4440. ha->virt_bus = hdr_channel;
  4441. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4442. shp->max_cmd_len = 16;
  4443. shp->max_id = ha->tid_cnt;
  4444. shp->max_lun = MAXLUN;
  4445. shp->max_channel = ha->bus_cnt;
  4446. spin_lock_init(&ha->smp_lock);
  4447. gdth_enable_int(ha);
  4448. error = scsi_add_host(shp, NULL);
  4449. if (error)
  4450. goto out_free_coal_stat;
  4451. list_add_tail(&ha->list, &gdth_instances);
  4452. return 0;
  4453. out_free_ccb_phys:
  4454. pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
  4455. PCI_DMA_BIDIRECTIONAL);
  4456. out_free_coal_stat:
  4457. #ifdef INT_COAL
  4458. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4459. ha->coal_stat, ha->coal_stat_phys);
  4460. out_free_pmsg:
  4461. #endif
  4462. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4463. ha->pmsg, ha->msg_phys);
  4464. out_free_pscratch:
  4465. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4466. ha->pscratch, ha->scratch_phys);
  4467. out_free_irq:
  4468. free_irq(ha->irq, ha);
  4469. gdth_ctr_count--;
  4470. out_host_put:
  4471. scsi_host_put(shp);
  4472. return error;
  4473. }
  4474. #endif /* CONFIG_EISA */
  4475. #ifdef CONFIG_PCI
  4476. static int __init gdth_pci_probe_one(gdth_pci_str *pcistr, int ctr)
  4477. {
  4478. struct Scsi_Host *shp;
  4479. gdth_ha_str *ha;
  4480. dma_addr_t scratch_dma_handle = 0;
  4481. int error, i;
  4482. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4483. if (!shp)
  4484. return -ENOMEM;
  4485. ha = shost_priv(shp);
  4486. error = -ENODEV;
  4487. if (!gdth_init_pci(&pcistr[ctr],ha))
  4488. goto out_host_put;
  4489. /* controller found and initialized */
  4490. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4491. pcistr[ctr].pdev->bus->number,
  4492. PCI_SLOT(pcistr[ctr].pdev->devfn),
  4493. ha->irq);
  4494. error = request_irq(ha->irq, gdth_interrupt,
  4495. IRQF_DISABLED|IRQF_SHARED, "gdth", ha);
  4496. if (error) {
  4497. printk("GDT-PCI: Unable to allocate IRQ\n");
  4498. goto out_host_put;
  4499. }
  4500. shp->unchecked_isa_dma = 0;
  4501. shp->irq = ha->irq;
  4502. shp->dma_channel = 0xff;
  4503. ha->hanum = gdth_ctr_count++;
  4504. ha->shost = shp;
  4505. ha->pccb = &ha->cmdext;
  4506. ha->ccb_phys = 0L;
  4507. error = -ENOMEM;
  4508. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4509. &scratch_dma_handle);
  4510. if (!ha->pscratch)
  4511. goto out_free_irq;
  4512. ha->scratch_phys = scratch_dma_handle;
  4513. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4514. &scratch_dma_handle);
  4515. if (!ha->pmsg)
  4516. goto out_free_pscratch;
  4517. ha->msg_phys = scratch_dma_handle;
  4518. #ifdef INT_COAL
  4519. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4520. sizeof(gdth_coal_status) * MAXOFFSETS,
  4521. &scratch_dma_handle);
  4522. if (!ha->coal_stat)
  4523. goto out_free_pmsg;
  4524. ha->coal_stat_phys = scratch_dma_handle;
  4525. #endif
  4526. ha->scratch_busy = FALSE;
  4527. ha->req_first = NULL;
  4528. ha->tid_cnt = pcistr[ctr].pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
  4529. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4530. ha->tid_cnt = max_ids;
  4531. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4532. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4533. ha->scan_mode = rescan ? 0x10 : 0;
  4534. error = -ENODEV;
  4535. if (!gdth_search_drives(ha)) {
  4536. printk("GDT-PCI %d: Error during device scan\n", ha->hanum);
  4537. goto out_free_coal_stat;
  4538. }
  4539. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4540. hdr_channel = ha->bus_cnt;
  4541. ha->virt_bus = hdr_channel;
  4542. /* 64-bit DMA only supported from FW >= x.43 */
  4543. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
  4544. !ha->dma64_support) {
  4545. if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4546. printk(KERN_WARNING "GDT-PCI %d: "
  4547. "Unable to set 32-bit DMA\n", ha->hanum);
  4548. goto out_free_coal_stat;
  4549. }
  4550. } else {
  4551. shp->max_cmd_len = 16;
  4552. if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
  4553. printk("GDT-PCI %d: 64-bit DMA enabled\n", ha->hanum);
  4554. } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4555. printk(KERN_WARNING "GDT-PCI %d: "
  4556. "Unable to set 64/32-bit DMA\n", ha->hanum);
  4557. goto out_free_coal_stat;
  4558. }
  4559. }
  4560. shp->max_id = ha->tid_cnt;
  4561. shp->max_lun = MAXLUN;
  4562. shp->max_channel = ha->bus_cnt;
  4563. spin_lock_init(&ha->smp_lock);
  4564. gdth_enable_int(ha);
  4565. error = scsi_add_host(shp, &pcistr[ctr].pdev->dev);
  4566. if (error)
  4567. goto out_free_coal_stat;
  4568. list_add_tail(&ha->list, &gdth_instances);
  4569. return 0;
  4570. out_free_coal_stat:
  4571. #ifdef INT_COAL
  4572. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4573. ha->coal_stat, ha->coal_stat_phys);
  4574. out_free_pmsg:
  4575. #endif
  4576. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4577. ha->pmsg, ha->msg_phys);
  4578. out_free_pscratch:
  4579. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4580. ha->pscratch, ha->scratch_phys);
  4581. out_free_irq:
  4582. free_irq(ha->irq, ha);
  4583. gdth_ctr_count--;
  4584. out_host_put:
  4585. scsi_host_put(shp);
  4586. return error;
  4587. }
  4588. #endif /* CONFIG_PCI */
  4589. static void gdth_remove_one(gdth_ha_str *ha)
  4590. {
  4591. struct Scsi_Host *shp = ha->shost;
  4592. TRACE2(("gdth_remove_one()\n"));
  4593. scsi_remove_host(shp);
  4594. if (ha->sdev) {
  4595. scsi_free_host_dev(ha->sdev);
  4596. ha->sdev = NULL;
  4597. }
  4598. gdth_flush(ha);
  4599. if (shp->irq)
  4600. free_irq(shp->irq,ha);
  4601. #ifdef CONFIG_ISA
  4602. if (shp->dma_channel != 0xff)
  4603. free_dma(shp->dma_channel);
  4604. #endif
  4605. #ifdef INT_COAL
  4606. if (ha->coal_stat)
  4607. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4608. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  4609. #endif
  4610. if (ha->pscratch)
  4611. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4612. ha->pscratch, ha->scratch_phys);
  4613. if (ha->pmsg)
  4614. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4615. ha->pmsg, ha->msg_phys);
  4616. if (ha->ccb_phys)
  4617. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4618. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4619. scsi_host_put(shp);
  4620. }
  4621. static int __init gdth_init(void)
  4622. {
  4623. if (disable) {
  4624. printk("GDT-HA: Controller driver disabled from"
  4625. " command line !\n");
  4626. return 0;
  4627. }
  4628. printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",
  4629. GDTH_VERSION_STR);
  4630. /* initializations */
  4631. gdth_polling = TRUE;
  4632. gdth_clear_events();
  4633. /* As default we do not probe for EISA or ISA controllers */
  4634. if (probe_eisa_isa) {
  4635. /* scanning for controllers, at first: ISA controller */
  4636. #ifdef CONFIG_ISA
  4637. ulong32 isa_bios;
  4638. for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
  4639. isa_bios += 0x8000UL)
  4640. gdth_isa_probe_one(isa_bios);
  4641. #endif
  4642. #ifdef CONFIG_EISA
  4643. {
  4644. ushort eisa_slot;
  4645. for (eisa_slot = 0x1000; eisa_slot <= 0x8000;
  4646. eisa_slot += 0x1000)
  4647. gdth_eisa_probe_one(eisa_slot);
  4648. }
  4649. #endif
  4650. }
  4651. #ifdef CONFIG_PCI
  4652. /* scanning for PCI controllers */
  4653. {
  4654. gdth_pci_str pcistr[MAXHA];
  4655. int cnt,ctr;
  4656. cnt = gdth_search_pci(pcistr);
  4657. printk("GDT-HA: Found %d PCI Storage RAID Controllers\n", cnt);
  4658. gdth_sort_pci(pcistr,cnt);
  4659. for (ctr = 0; ctr < cnt; ++ctr)
  4660. gdth_pci_probe_one(pcistr, ctr);
  4661. }
  4662. #endif /* CONFIG_PCI */
  4663. TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count));
  4664. if (list_empty(&gdth_instances))
  4665. return -ENODEV;
  4666. #ifdef GDTH_STATISTICS
  4667. TRACE2(("gdth_detect(): Initializing timer !\n"));
  4668. init_timer(&gdth_timer);
  4669. gdth_timer.expires = jiffies + HZ;
  4670. gdth_timer.data = 0L;
  4671. gdth_timer.function = gdth_timeout;
  4672. add_timer(&gdth_timer);
  4673. #endif
  4674. major = register_chrdev(0,"gdth", &gdth_fops);
  4675. notifier_disabled = 0;
  4676. register_reboot_notifier(&gdth_notifier);
  4677. gdth_polling = FALSE;
  4678. return 0;
  4679. }
  4680. static void __exit gdth_exit(void)
  4681. {
  4682. gdth_ha_str *ha;
  4683. list_for_each_entry(ha, &gdth_instances, list)
  4684. gdth_remove_one(ha);
  4685. #ifdef GDTH_STATISTICS
  4686. del_timer(&gdth_timer);
  4687. #endif
  4688. unregister_chrdev(major,"gdth");
  4689. unregister_reboot_notifier(&gdth_notifier);
  4690. }
  4691. module_init(gdth_init);
  4692. module_exit(gdth_exit);
  4693. #ifndef MODULE
  4694. __setup("gdth=", option_setup);
  4695. #endif