arcmsr_hba.c 66 KB

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  1. /*
  2. *******************************************************************************
  3. ** O.S : Linux
  4. ** FILE NAME : arcmsr_hba.c
  5. ** BY : Erich Chen
  6. ** Description: SCSI RAID Device Driver for
  7. ** ARECA RAID Host adapter
  8. *******************************************************************************
  9. ** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved
  10. **
  11. ** Web site: www.areca.com.tw
  12. ** E-mail: support@areca.com.tw
  13. **
  14. ** This program is free software; you can redistribute it and/or modify
  15. ** it under the terms of the GNU General Public License version 2 as
  16. ** published by the Free Software Foundation.
  17. ** This program is distributed in the hope that it will be useful,
  18. ** but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. ** GNU General Public License for more details.
  21. *******************************************************************************
  22. ** Redistribution and use in source and binary forms, with or without
  23. ** modification, are permitted provided that the following conditions
  24. ** are met:
  25. ** 1. Redistributions of source code must retain the above copyright
  26. ** notice, this list of conditions and the following disclaimer.
  27. ** 2. Redistributions in binary form must reproduce the above copyright
  28. ** notice, this list of conditions and the following disclaimer in the
  29. ** documentation and/or other materials provided with the distribution.
  30. ** 3. The name of the author may not be used to endorse or promote products
  31. ** derived from this software without specific prior written permission.
  32. **
  33. ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  34. ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  35. ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  36. ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  37. ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
  38. ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  39. ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
  40. ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  41. ** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
  42. ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  43. *******************************************************************************
  44. ** For history of changes, see Documentation/scsi/ChangeLog.arcmsr
  45. ** Firmware Specification, see Documentation/scsi/arcmsr_spec.txt
  46. *******************************************************************************
  47. */
  48. #include <linux/module.h>
  49. #include <linux/reboot.h>
  50. #include <linux/spinlock.h>
  51. #include <linux/pci_ids.h>
  52. #include <linux/interrupt.h>
  53. #include <linux/moduleparam.h>
  54. #include <linux/errno.h>
  55. #include <linux/types.h>
  56. #include <linux/delay.h>
  57. #include <linux/dma-mapping.h>
  58. #include <linux/timer.h>
  59. #include <linux/pci.h>
  60. #include <linux/aer.h>
  61. #include <asm/dma.h>
  62. #include <asm/io.h>
  63. #include <asm/system.h>
  64. #include <asm/uaccess.h>
  65. #include <scsi/scsi_host.h>
  66. #include <scsi/scsi.h>
  67. #include <scsi/scsi_cmnd.h>
  68. #include <scsi/scsi_tcq.h>
  69. #include <scsi/scsi_device.h>
  70. #include <scsi/scsi_transport.h>
  71. #include <scsi/scsicam.h>
  72. #include "arcmsr.h"
  73. MODULE_AUTHOR("Erich Chen <support@areca.com.tw>");
  74. MODULE_DESCRIPTION("ARECA (ARC11xx/12xx/13xx/16xx) SATA/SAS RAID HOST Adapter");
  75. MODULE_LICENSE("Dual BSD/GPL");
  76. MODULE_VERSION(ARCMSR_DRIVER_VERSION);
  77. static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
  78. struct scsi_cmnd *cmd);
  79. static int arcmsr_iop_confirm(struct AdapterControlBlock *acb);
  80. static int arcmsr_abort(struct scsi_cmnd *);
  81. static int arcmsr_bus_reset(struct scsi_cmnd *);
  82. static int arcmsr_bios_param(struct scsi_device *sdev,
  83. struct block_device *bdev, sector_t capacity, int *info);
  84. static int arcmsr_queue_command(struct scsi_cmnd *cmd,
  85. void (*done) (struct scsi_cmnd *));
  86. static int arcmsr_probe(struct pci_dev *pdev,
  87. const struct pci_device_id *id);
  88. static void arcmsr_remove(struct pci_dev *pdev);
  89. static void arcmsr_shutdown(struct pci_dev *pdev);
  90. static void arcmsr_iop_init(struct AdapterControlBlock *acb);
  91. static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb);
  92. static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb);
  93. static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
  94. static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb);
  95. static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb);
  96. static const char *arcmsr_info(struct Scsi_Host *);
  97. static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb);
  98. static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev,
  99. int queue_depth)
  100. {
  101. if (queue_depth > ARCMSR_MAX_CMD_PERLUN)
  102. queue_depth = ARCMSR_MAX_CMD_PERLUN;
  103. scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, queue_depth);
  104. return queue_depth;
  105. }
  106. static struct scsi_host_template arcmsr_scsi_host_template = {
  107. .module = THIS_MODULE,
  108. .name = "ARCMSR ARECA SATA/SAS RAID HOST Adapter"
  109. ARCMSR_DRIVER_VERSION,
  110. .info = arcmsr_info,
  111. .queuecommand = arcmsr_queue_command,
  112. .eh_abort_handler = arcmsr_abort,
  113. .eh_bus_reset_handler = arcmsr_bus_reset,
  114. .bios_param = arcmsr_bios_param,
  115. .change_queue_depth = arcmsr_adjust_disk_queue_depth,
  116. .can_queue = ARCMSR_MAX_OUTSTANDING_CMD,
  117. .this_id = ARCMSR_SCSI_INITIATOR_ID,
  118. .sg_tablesize = ARCMSR_MAX_SG_ENTRIES,
  119. .max_sectors = ARCMSR_MAX_XFER_SECTORS,
  120. .cmd_per_lun = ARCMSR_MAX_CMD_PERLUN,
  121. .use_clustering = ENABLE_CLUSTERING,
  122. .use_sg_chaining = ENABLE_SG_CHAINING,
  123. .shost_attrs = arcmsr_host_attrs,
  124. };
  125. #ifdef CONFIG_SCSI_ARCMSR_AER
  126. static pci_ers_result_t arcmsr_pci_slot_reset(struct pci_dev *pdev);
  127. static pci_ers_result_t arcmsr_pci_error_detected(struct pci_dev *pdev,
  128. pci_channel_state_t state);
  129. static struct pci_error_handlers arcmsr_pci_error_handlers = {
  130. .error_detected = arcmsr_pci_error_detected,
  131. .slot_reset = arcmsr_pci_slot_reset,
  132. };
  133. #endif
  134. static struct pci_device_id arcmsr_device_id_table[] = {
  135. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110)},
  136. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120)},
  137. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130)},
  138. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160)},
  139. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170)},
  140. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200)},
  141. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201)},
  142. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202)},
  143. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210)},
  144. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220)},
  145. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230)},
  146. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260)},
  147. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270)},
  148. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280)},
  149. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380)},
  150. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381)},
  151. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680)},
  152. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681)},
  153. {0, 0}, /* Terminating entry */
  154. };
  155. MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
  156. static struct pci_driver arcmsr_pci_driver = {
  157. .name = "arcmsr",
  158. .id_table = arcmsr_device_id_table,
  159. .probe = arcmsr_probe,
  160. .remove = arcmsr_remove,
  161. .shutdown = arcmsr_shutdown,
  162. #ifdef CONFIG_SCSI_ARCMSR_AER
  163. .err_handler = &arcmsr_pci_error_handlers,
  164. #endif
  165. };
  166. static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id)
  167. {
  168. irqreturn_t handle_state;
  169. struct AdapterControlBlock *acb = dev_id;
  170. spin_lock(acb->host->host_lock);
  171. handle_state = arcmsr_interrupt(acb);
  172. spin_unlock(acb->host->host_lock);
  173. return handle_state;
  174. }
  175. static int arcmsr_bios_param(struct scsi_device *sdev,
  176. struct block_device *bdev, sector_t capacity, int *geom)
  177. {
  178. int ret, heads, sectors, cylinders, total_capacity;
  179. unsigned char *buffer;/* return copy of block device's partition table */
  180. buffer = scsi_bios_ptable(bdev);
  181. if (buffer) {
  182. ret = scsi_partsize(buffer, capacity, &geom[2], &geom[0], &geom[1]);
  183. kfree(buffer);
  184. if (ret != -1)
  185. return ret;
  186. }
  187. total_capacity = capacity;
  188. heads = 64;
  189. sectors = 32;
  190. cylinders = total_capacity / (heads * sectors);
  191. if (cylinders > 1024) {
  192. heads = 255;
  193. sectors = 63;
  194. cylinders = total_capacity / (heads * sectors);
  195. }
  196. geom[0] = heads;
  197. geom[1] = sectors;
  198. geom[2] = cylinders;
  199. return 0;
  200. }
  201. static void arcmsr_define_adapter_type(struct AdapterControlBlock *acb)
  202. {
  203. struct pci_dev *pdev = acb->pdev;
  204. u16 dev_id;
  205. pci_read_config_word(pdev, PCI_DEVICE_ID, &dev_id);
  206. switch (dev_id) {
  207. case 0x1201 : {
  208. acb->adapter_type = ACB_ADAPTER_TYPE_B;
  209. }
  210. break;
  211. default : acb->adapter_type = ACB_ADAPTER_TYPE_A;
  212. }
  213. }
  214. static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
  215. {
  216. switch (acb->adapter_type) {
  217. case ACB_ADAPTER_TYPE_A: {
  218. struct pci_dev *pdev = acb->pdev;
  219. void *dma_coherent;
  220. dma_addr_t dma_coherent_handle, dma_addr;
  221. struct CommandControlBlock *ccb_tmp;
  222. uint32_t intmask_org;
  223. int i, j;
  224. acb->pmuA = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
  225. if (!acb->pmuA) {
  226. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n",
  227. acb->host->host_no);
  228. return -ENOMEM;
  229. }
  230. dma_coherent = dma_alloc_coherent(&pdev->dev,
  231. ARCMSR_MAX_FREECCB_NUM *
  232. sizeof (struct CommandControlBlock) + 0x20,
  233. &dma_coherent_handle, GFP_KERNEL);
  234. if (!dma_coherent) {
  235. iounmap(acb->pmuA);
  236. return -ENOMEM;
  237. }
  238. acb->dma_coherent = dma_coherent;
  239. acb->dma_coherent_handle = dma_coherent_handle;
  240. if (((unsigned long)dma_coherent & 0x1F)) {
  241. dma_coherent = dma_coherent +
  242. (0x20 - ((unsigned long)dma_coherent & 0x1F));
  243. dma_coherent_handle = dma_coherent_handle +
  244. (0x20 - ((unsigned long)dma_coherent_handle & 0x1F));
  245. }
  246. dma_addr = dma_coherent_handle;
  247. ccb_tmp = (struct CommandControlBlock *)dma_coherent;
  248. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  249. ccb_tmp->cdb_shifted_phyaddr = dma_addr >> 5;
  250. ccb_tmp->acb = acb;
  251. acb->pccb_pool[i] = ccb_tmp;
  252. list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
  253. dma_addr = dma_addr + sizeof(struct CommandControlBlock);
  254. ccb_tmp++;
  255. }
  256. acb->vir2phy_offset = (unsigned long)ccb_tmp -(unsigned long)dma_addr;
  257. for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
  258. for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
  259. acb->devstate[i][j] = ARECA_RAID_GONE;
  260. /*
  261. ** here we need to tell iop 331 our ccb_tmp.HighPart
  262. ** if ccb_tmp.HighPart is not zero
  263. */
  264. intmask_org = arcmsr_disable_outbound_ints(acb);
  265. }
  266. break;
  267. case ACB_ADAPTER_TYPE_B: {
  268. struct pci_dev *pdev = acb->pdev;
  269. struct MessageUnit_B *reg;
  270. void __iomem *mem_base0, *mem_base1;
  271. void *dma_coherent;
  272. dma_addr_t dma_coherent_handle, dma_addr;
  273. uint32_t intmask_org;
  274. struct CommandControlBlock *ccb_tmp;
  275. int i, j;
  276. dma_coherent = dma_alloc_coherent(&pdev->dev,
  277. ((ARCMSR_MAX_FREECCB_NUM *
  278. sizeof(struct CommandControlBlock) + 0x20) +
  279. sizeof(struct MessageUnit_B)),
  280. &dma_coherent_handle, GFP_KERNEL);
  281. if (!dma_coherent)
  282. return -ENOMEM;
  283. acb->dma_coherent = dma_coherent;
  284. acb->dma_coherent_handle = dma_coherent_handle;
  285. if (((unsigned long)dma_coherent & 0x1F)) {
  286. dma_coherent = dma_coherent +
  287. (0x20 - ((unsigned long)dma_coherent & 0x1F));
  288. dma_coherent_handle = dma_coherent_handle +
  289. (0x20 - ((unsigned long)dma_coherent_handle & 0x1F));
  290. }
  291. reg = (struct MessageUnit_B *)(dma_coherent +
  292. ARCMSR_MAX_FREECCB_NUM * sizeof(struct CommandControlBlock));
  293. dma_addr = dma_coherent_handle;
  294. ccb_tmp = (struct CommandControlBlock *)dma_coherent;
  295. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  296. ccb_tmp->cdb_shifted_phyaddr = dma_addr >> 5;
  297. ccb_tmp->acb = acb;
  298. acb->pccb_pool[i] = ccb_tmp;
  299. list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
  300. dma_addr = dma_addr + sizeof(struct CommandControlBlock);
  301. ccb_tmp++;
  302. }
  303. reg = (struct MessageUnit_B *)(dma_coherent +
  304. ARCMSR_MAX_FREECCB_NUM * sizeof(struct CommandControlBlock));
  305. acb->pmuB = reg;
  306. mem_base0 = ioremap(pci_resource_start(pdev, 0),
  307. pci_resource_len(pdev, 0));
  308. if (!mem_base0)
  309. goto out;
  310. mem_base1 = ioremap(pci_resource_start(pdev, 2),
  311. pci_resource_len(pdev, 2));
  312. if (!mem_base1) {
  313. iounmap(mem_base0);
  314. goto out;
  315. }
  316. reg->drv2iop_doorbell_reg = mem_base0 + ARCMSR_DRV2IOP_DOORBELL;
  317. reg->drv2iop_doorbell_mask_reg = mem_base0 +
  318. ARCMSR_DRV2IOP_DOORBELL_MASK;
  319. reg->iop2drv_doorbell_reg = mem_base0 + ARCMSR_IOP2DRV_DOORBELL;
  320. reg->iop2drv_doorbell_mask_reg = mem_base0 +
  321. ARCMSR_IOP2DRV_DOORBELL_MASK;
  322. reg->ioctl_wbuffer_reg = mem_base1 + ARCMSR_IOCTL_WBUFFER;
  323. reg->ioctl_rbuffer_reg = mem_base1 + ARCMSR_IOCTL_RBUFFER;
  324. reg->msgcode_rwbuffer_reg = mem_base1 + ARCMSR_MSGCODE_RWBUFFER;
  325. acb->vir2phy_offset = (unsigned long)ccb_tmp -(unsigned long)dma_addr;
  326. for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
  327. for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
  328. acb->devstate[i][j] = ARECA_RAID_GOOD;
  329. /*
  330. ** here we need to tell iop 331 our ccb_tmp.HighPart
  331. ** if ccb_tmp.HighPart is not zero
  332. */
  333. intmask_org = arcmsr_disable_outbound_ints(acb);
  334. }
  335. break;
  336. }
  337. return 0;
  338. out:
  339. dma_free_coherent(&acb->pdev->dev,
  340. ARCMSR_MAX_FREECCB_NUM * sizeof(struct CommandControlBlock) + 0x20,
  341. acb->dma_coherent, acb->dma_coherent_handle);
  342. return -ENOMEM;
  343. }
  344. static int arcmsr_probe(struct pci_dev *pdev,
  345. const struct pci_device_id *id)
  346. {
  347. struct Scsi_Host *host;
  348. struct AdapterControlBlock *acb;
  349. uint8_t bus, dev_fun;
  350. int error;
  351. error = pci_enable_device(pdev);
  352. if (error)
  353. goto out;
  354. pci_set_master(pdev);
  355. host = scsi_host_alloc(&arcmsr_scsi_host_template,
  356. sizeof(struct AdapterControlBlock));
  357. if (!host) {
  358. error = -ENOMEM;
  359. goto out_disable_device;
  360. }
  361. acb = (struct AdapterControlBlock *)host->hostdata;
  362. memset(acb, 0, sizeof (struct AdapterControlBlock));
  363. error = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  364. if (error) {
  365. error = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  366. if (error) {
  367. printk(KERN_WARNING
  368. "scsi%d: No suitable DMA mask available\n",
  369. host->host_no);
  370. goto out_host_put;
  371. }
  372. }
  373. bus = pdev->bus->number;
  374. dev_fun = pdev->devfn;
  375. acb->host = host;
  376. acb->pdev = pdev;
  377. host->max_sectors = ARCMSR_MAX_XFER_SECTORS;
  378. host->max_lun = ARCMSR_MAX_TARGETLUN;
  379. host->max_id = ARCMSR_MAX_TARGETID;/*16:8*/
  380. host->max_cmd_len = 16; /*this is issue of 64bit LBA, over 2T byte*/
  381. host->sg_tablesize = ARCMSR_MAX_SG_ENTRIES;
  382. host->can_queue = ARCMSR_MAX_FREECCB_NUM; /* max simultaneous cmds */
  383. host->cmd_per_lun = ARCMSR_MAX_CMD_PERLUN;
  384. host->this_id = ARCMSR_SCSI_INITIATOR_ID;
  385. host->unique_id = (bus << 8) | dev_fun;
  386. host->irq = pdev->irq;
  387. error = pci_request_regions(pdev, "arcmsr");
  388. if (error) {
  389. goto out_host_put;
  390. }
  391. arcmsr_define_adapter_type(acb);
  392. acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  393. ACB_F_MESSAGE_RQBUFFER_CLEARED |
  394. ACB_F_MESSAGE_WQBUFFER_READED);
  395. acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
  396. INIT_LIST_HEAD(&acb->ccb_free_list);
  397. error = arcmsr_alloc_ccb_pool(acb);
  398. if (error)
  399. goto out_release_regions;
  400. error = request_irq(pdev->irq, arcmsr_do_interrupt,
  401. IRQF_SHARED, "arcmsr", acb);
  402. if (error)
  403. goto out_free_ccb_pool;
  404. arcmsr_iop_init(acb);
  405. pci_set_drvdata(pdev, host);
  406. if (strncmp(acb->firm_version, "V1.42", 5) >= 0)
  407. host->max_sectors= ARCMSR_MAX_XFER_SECTORS_B;
  408. error = scsi_add_host(host, &pdev->dev);
  409. if (error)
  410. goto out_free_irq;
  411. error = arcmsr_alloc_sysfs_attr(acb);
  412. if (error)
  413. goto out_free_sysfs;
  414. scsi_scan_host(host);
  415. #ifdef CONFIG_SCSI_ARCMSR_AER
  416. pci_enable_pcie_error_reporting(pdev);
  417. #endif
  418. return 0;
  419. out_free_sysfs:
  420. out_free_irq:
  421. free_irq(pdev->irq, acb);
  422. out_free_ccb_pool:
  423. arcmsr_free_ccb_pool(acb);
  424. out_release_regions:
  425. pci_release_regions(pdev);
  426. out_host_put:
  427. scsi_host_put(host);
  428. out_disable_device:
  429. pci_disable_device(pdev);
  430. out:
  431. return error;
  432. }
  433. static uint8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
  434. {
  435. struct MessageUnit_A __iomem *reg = acb->pmuA;
  436. uint32_t Index;
  437. uint8_t Retries = 0x00;
  438. do {
  439. for (Index = 0; Index < 100; Index++) {
  440. if (readl(&reg->outbound_intstatus) &
  441. ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
  442. writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
  443. &reg->outbound_intstatus);
  444. return 0x00;
  445. }
  446. msleep(10);
  447. }/*max 1 seconds*/
  448. } while (Retries++ < 20);/*max 20 sec*/
  449. return 0xff;
  450. }
  451. static uint8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
  452. {
  453. struct MessageUnit_B *reg = acb->pmuB;
  454. uint32_t Index;
  455. uint8_t Retries = 0x00;
  456. do {
  457. for (Index = 0; Index < 100; Index++) {
  458. if (readl(reg->iop2drv_doorbell_reg)
  459. & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
  460. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN
  461. , reg->iop2drv_doorbell_reg);
  462. return 0x00;
  463. }
  464. msleep(10);
  465. }/*max 1 seconds*/
  466. } while (Retries++ < 20);/*max 20 sec*/
  467. return 0xff;
  468. }
  469. static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
  470. {
  471. struct MessageUnit_A __iomem *reg = acb->pmuA;
  472. writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
  473. if (arcmsr_hba_wait_msgint_ready(acb))
  474. printk(KERN_NOTICE
  475. "arcmsr%d: wait 'abort all outstanding command' timeout \n"
  476. , acb->host->host_no);
  477. }
  478. static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
  479. {
  480. struct MessageUnit_B *reg = acb->pmuB;
  481. writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell_reg);
  482. if (arcmsr_hbb_wait_msgint_ready(acb))
  483. printk(KERN_NOTICE
  484. "arcmsr%d: wait 'abort all outstanding command' timeout \n"
  485. , acb->host->host_no);
  486. }
  487. static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
  488. {
  489. switch (acb->adapter_type) {
  490. case ACB_ADAPTER_TYPE_A: {
  491. arcmsr_abort_hba_allcmd(acb);
  492. }
  493. break;
  494. case ACB_ADAPTER_TYPE_B: {
  495. arcmsr_abort_hbb_allcmd(acb);
  496. }
  497. }
  498. }
  499. static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb)
  500. {
  501. struct scsi_cmnd *pcmd = ccb->pcmd;
  502. scsi_dma_unmap(pcmd);
  503. }
  504. static void arcmsr_ccb_complete(struct CommandControlBlock *ccb, int stand_flag)
  505. {
  506. struct AdapterControlBlock *acb = ccb->acb;
  507. struct scsi_cmnd *pcmd = ccb->pcmd;
  508. arcmsr_pci_unmap_dma(ccb);
  509. if (stand_flag == 1)
  510. atomic_dec(&acb->ccboutstandingcount);
  511. ccb->startdone = ARCMSR_CCB_DONE;
  512. ccb->ccb_flags = 0;
  513. list_add_tail(&ccb->list, &acb->ccb_free_list);
  514. pcmd->scsi_done(pcmd);
  515. }
  516. static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
  517. {
  518. struct MessageUnit_A __iomem *reg = acb->pmuA;
  519. int retry_count = 30;
  520. writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
  521. do {
  522. if (!arcmsr_hba_wait_msgint_ready(acb))
  523. break;
  524. else {
  525. retry_count--;
  526. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  527. timeout, retry count down = %d \n", acb->host->host_no, retry_count);
  528. }
  529. } while (retry_count != 0);
  530. }
  531. static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
  532. {
  533. struct MessageUnit_B *reg = acb->pmuB;
  534. int retry_count = 30;
  535. writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell_reg);
  536. do {
  537. if (!arcmsr_hbb_wait_msgint_ready(acb))
  538. break;
  539. else {
  540. retry_count--;
  541. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  542. timeout,retry count down = %d \n", acb->host->host_no, retry_count);
  543. }
  544. } while (retry_count != 0);
  545. }
  546. static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
  547. {
  548. switch (acb->adapter_type) {
  549. case ACB_ADAPTER_TYPE_A: {
  550. arcmsr_flush_hba_cache(acb);
  551. }
  552. break;
  553. case ACB_ADAPTER_TYPE_B: {
  554. arcmsr_flush_hbb_cache(acb);
  555. }
  556. }
  557. }
  558. static void arcmsr_report_sense_info(struct CommandControlBlock *ccb)
  559. {
  560. struct scsi_cmnd *pcmd = ccb->pcmd;
  561. struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer;
  562. pcmd->result = DID_OK << 16;
  563. if (sensebuffer) {
  564. int sense_data_length =
  565. sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE
  566. ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE;
  567. memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE);
  568. memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length);
  569. sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
  570. sensebuffer->Valid = 1;
  571. }
  572. }
  573. static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb)
  574. {
  575. u32 orig_mask = 0;
  576. switch (acb->adapter_type) {
  577. case ACB_ADAPTER_TYPE_A : {
  578. struct MessageUnit_A __iomem *reg = acb->pmuA;
  579. orig_mask = readl(&reg->outbound_intmask)|\
  580. ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE;
  581. writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
  582. &reg->outbound_intmask);
  583. }
  584. break;
  585. case ACB_ADAPTER_TYPE_B : {
  586. struct MessageUnit_B *reg = acb->pmuB;
  587. orig_mask = readl(reg->iop2drv_doorbell_mask_reg) & \
  588. (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
  589. writel(0, reg->iop2drv_doorbell_mask_reg);
  590. }
  591. break;
  592. }
  593. return orig_mask;
  594. }
  595. static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb, \
  596. struct CommandControlBlock *ccb, uint32_t flag_ccb)
  597. {
  598. uint8_t id, lun;
  599. id = ccb->pcmd->device->id;
  600. lun = ccb->pcmd->device->lun;
  601. if (!(flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR)) {
  602. if (acb->devstate[id][lun] == ARECA_RAID_GONE)
  603. acb->devstate[id][lun] = ARECA_RAID_GOOD;
  604. ccb->pcmd->result = DID_OK << 16;
  605. arcmsr_ccb_complete(ccb, 1);
  606. } else {
  607. switch (ccb->arcmsr_cdb.DeviceStatus) {
  608. case ARCMSR_DEV_SELECT_TIMEOUT: {
  609. acb->devstate[id][lun] = ARECA_RAID_GONE;
  610. ccb->pcmd->result = DID_NO_CONNECT << 16;
  611. arcmsr_ccb_complete(ccb, 1);
  612. }
  613. break;
  614. case ARCMSR_DEV_ABORTED:
  615. case ARCMSR_DEV_INIT_FAIL: {
  616. acb->devstate[id][lun] = ARECA_RAID_GONE;
  617. ccb->pcmd->result = DID_BAD_TARGET << 16;
  618. arcmsr_ccb_complete(ccb, 1);
  619. }
  620. break;
  621. case ARCMSR_DEV_CHECK_CONDITION: {
  622. acb->devstate[id][lun] = ARECA_RAID_GOOD;
  623. arcmsr_report_sense_info(ccb);
  624. arcmsr_ccb_complete(ccb, 1);
  625. }
  626. break;
  627. default:
  628. printk(KERN_NOTICE
  629. "arcmsr%d: scsi id = %d lun = %d"
  630. " isr get command error done, "
  631. "but got unknown DeviceStatus = 0x%x \n"
  632. , acb->host->host_no
  633. , id
  634. , lun
  635. , ccb->arcmsr_cdb.DeviceStatus);
  636. acb->devstate[id][lun] = ARECA_RAID_GONE;
  637. ccb->pcmd->result = DID_NO_CONNECT << 16;
  638. arcmsr_ccb_complete(ccb, 1);
  639. break;
  640. }
  641. }
  642. }
  643. static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, uint32_t flag_ccb)
  644. {
  645. struct CommandControlBlock *ccb;
  646. ccb = (struct CommandControlBlock *)(acb->vir2phy_offset + (flag_ccb << 5));
  647. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  648. if (ccb->startdone == ARCMSR_CCB_ABORTED) {
  649. struct scsi_cmnd *abortcmd = ccb->pcmd;
  650. if (abortcmd) {
  651. abortcmd->result |= DID_ABORT << 16;
  652. arcmsr_ccb_complete(ccb, 1);
  653. printk(KERN_NOTICE "arcmsr%d: ccb ='0x%p' \
  654. isr got aborted command \n", acb->host->host_no, ccb);
  655. }
  656. }
  657. printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \
  658. done acb = '0x%p'"
  659. "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x"
  660. " ccboutstandingcount = %d \n"
  661. , acb->host->host_no
  662. , acb
  663. , ccb
  664. , ccb->acb
  665. , ccb->startdone
  666. , atomic_read(&acb->ccboutstandingcount));
  667. }
  668. arcmsr_report_ccb_state(acb, ccb, flag_ccb);
  669. }
  670. static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
  671. {
  672. int i = 0;
  673. uint32_t flag_ccb;
  674. switch (acb->adapter_type) {
  675. case ACB_ADAPTER_TYPE_A: {
  676. struct MessageUnit_A __iomem *reg = acb->pmuA;
  677. uint32_t outbound_intstatus;
  678. outbound_intstatus = readl(&reg->outbound_intstatus) &
  679. acb->outbound_int_enable;
  680. /*clear and abort all outbound posted Q*/
  681. writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
  682. while (((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF)
  683. && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
  684. arcmsr_drain_donequeue(acb, flag_ccb);
  685. }
  686. }
  687. break;
  688. case ACB_ADAPTER_TYPE_B: {
  689. struct MessageUnit_B *reg = acb->pmuB;
  690. /*clear all outbound posted Q*/
  691. for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
  692. if ((flag_ccb = readl(&reg->done_qbuffer[i])) != 0) {
  693. writel(0, &reg->done_qbuffer[i]);
  694. arcmsr_drain_donequeue(acb, flag_ccb);
  695. }
  696. writel(0, &reg->post_qbuffer[i]);
  697. }
  698. reg->doneq_index = 0;
  699. reg->postq_index = 0;
  700. }
  701. break;
  702. }
  703. }
  704. static void arcmsr_remove(struct pci_dev *pdev)
  705. {
  706. struct Scsi_Host *host = pci_get_drvdata(pdev);
  707. struct AdapterControlBlock *acb =
  708. (struct AdapterControlBlock *) host->hostdata;
  709. int poll_count = 0;
  710. arcmsr_free_sysfs_attr(acb);
  711. scsi_remove_host(host);
  712. arcmsr_stop_adapter_bgrb(acb);
  713. arcmsr_flush_adapter_cache(acb);
  714. arcmsr_disable_outbound_ints(acb);
  715. acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
  716. acb->acb_flags &= ~ACB_F_IOP_INITED;
  717. for (poll_count = 0; poll_count < ARCMSR_MAX_OUTSTANDING_CMD; poll_count++) {
  718. if (!atomic_read(&acb->ccboutstandingcount))
  719. break;
  720. arcmsr_interrupt(acb);/* FIXME: need spinlock */
  721. msleep(25);
  722. }
  723. if (atomic_read(&acb->ccboutstandingcount)) {
  724. int i;
  725. arcmsr_abort_allcmd(acb);
  726. arcmsr_done4abort_postqueue(acb);
  727. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  728. struct CommandControlBlock *ccb = acb->pccb_pool[i];
  729. if (ccb->startdone == ARCMSR_CCB_START) {
  730. ccb->startdone = ARCMSR_CCB_ABORTED;
  731. ccb->pcmd->result = DID_ABORT << 16;
  732. arcmsr_ccb_complete(ccb, 1);
  733. }
  734. }
  735. }
  736. free_irq(pdev->irq, acb);
  737. arcmsr_free_ccb_pool(acb);
  738. pci_release_regions(pdev);
  739. scsi_host_put(host);
  740. pci_disable_device(pdev);
  741. pci_set_drvdata(pdev, NULL);
  742. }
  743. static void arcmsr_shutdown(struct pci_dev *pdev)
  744. {
  745. struct Scsi_Host *host = pci_get_drvdata(pdev);
  746. struct AdapterControlBlock *acb =
  747. (struct AdapterControlBlock *)host->hostdata;
  748. arcmsr_stop_adapter_bgrb(acb);
  749. arcmsr_flush_adapter_cache(acb);
  750. }
  751. static int arcmsr_module_init(void)
  752. {
  753. int error = 0;
  754. error = pci_register_driver(&arcmsr_pci_driver);
  755. return error;
  756. }
  757. static void arcmsr_module_exit(void)
  758. {
  759. pci_unregister_driver(&arcmsr_pci_driver);
  760. }
  761. module_init(arcmsr_module_init);
  762. module_exit(arcmsr_module_exit);
  763. static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb, \
  764. u32 intmask_org)
  765. {
  766. u32 mask;
  767. switch (acb->adapter_type) {
  768. case ACB_ADAPTER_TYPE_A : {
  769. struct MessageUnit_A __iomem *reg = acb->pmuA;
  770. mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
  771. ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE);
  772. writel(mask, &reg->outbound_intmask);
  773. acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
  774. }
  775. break;
  776. case ACB_ADAPTER_TYPE_B : {
  777. struct MessageUnit_B *reg = acb->pmuB;
  778. mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK | \
  779. ARCMSR_IOP2DRV_DATA_READ_OK | ARCMSR_IOP2DRV_CDB_DONE);
  780. writel(mask, reg->iop2drv_doorbell_mask_reg);
  781. acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
  782. }
  783. }
  784. }
  785. static void arcmsr_build_ccb(struct AdapterControlBlock *acb,
  786. struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd)
  787. {
  788. struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
  789. int8_t *psge = (int8_t *)&arcmsr_cdb->u;
  790. __le32 address_lo, address_hi;
  791. int arccdbsize = 0x30;
  792. int nseg;
  793. ccb->pcmd = pcmd;
  794. memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
  795. arcmsr_cdb->Bus = 0;
  796. arcmsr_cdb->TargetID = pcmd->device->id;
  797. arcmsr_cdb->LUN = pcmd->device->lun;
  798. arcmsr_cdb->Function = 1;
  799. arcmsr_cdb->CdbLength = (uint8_t)pcmd->cmd_len;
  800. arcmsr_cdb->Context = (unsigned long)arcmsr_cdb;
  801. memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len);
  802. nseg = scsi_dma_map(pcmd);
  803. BUG_ON(nseg < 0);
  804. if (nseg) {
  805. __le32 length;
  806. int i, cdb_sgcount = 0;
  807. struct scatterlist *sg;
  808. /* map stor port SG list to our iop SG List. */
  809. scsi_for_each_sg(pcmd, sg, nseg, i) {
  810. /* Get the physical address of the current data pointer */
  811. length = cpu_to_le32(sg_dma_len(sg));
  812. address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg)));
  813. address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg)));
  814. if (address_hi == 0) {
  815. struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
  816. pdma_sg->address = address_lo;
  817. pdma_sg->length = length;
  818. psge += sizeof (struct SG32ENTRY);
  819. arccdbsize += sizeof (struct SG32ENTRY);
  820. } else {
  821. struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
  822. pdma_sg->addresshigh = address_hi;
  823. pdma_sg->address = address_lo;
  824. pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR);
  825. psge += sizeof (struct SG64ENTRY);
  826. arccdbsize += sizeof (struct SG64ENTRY);
  827. }
  828. cdb_sgcount++;
  829. }
  830. arcmsr_cdb->sgcount = (uint8_t)cdb_sgcount;
  831. arcmsr_cdb->DataLength = scsi_bufflen(pcmd);
  832. if ( arccdbsize > 256)
  833. arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
  834. }
  835. if (pcmd->sc_data_direction == DMA_TO_DEVICE ) {
  836. arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
  837. ccb->ccb_flags |= CCB_FLAG_WRITE;
  838. }
  839. }
  840. static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb)
  841. {
  842. uint32_t cdb_shifted_phyaddr = ccb->cdb_shifted_phyaddr;
  843. struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
  844. atomic_inc(&acb->ccboutstandingcount);
  845. ccb->startdone = ARCMSR_CCB_START;
  846. switch (acb->adapter_type) {
  847. case ACB_ADAPTER_TYPE_A: {
  848. struct MessageUnit_A __iomem *reg = acb->pmuA;
  849. if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE)
  850. writel(cdb_shifted_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
  851. &reg->inbound_queueport);
  852. else {
  853. writel(cdb_shifted_phyaddr, &reg->inbound_queueport);
  854. }
  855. }
  856. break;
  857. case ACB_ADAPTER_TYPE_B: {
  858. struct MessageUnit_B *reg = acb->pmuB;
  859. uint32_t ending_index, index = reg->postq_index;
  860. ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE);
  861. writel(0, &reg->post_qbuffer[ending_index]);
  862. if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
  863. writel(cdb_shifted_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,\
  864. &reg->post_qbuffer[index]);
  865. }
  866. else {
  867. writel(cdb_shifted_phyaddr, &reg->post_qbuffer[index]);
  868. }
  869. index++;
  870. index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */
  871. reg->postq_index = index;
  872. writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell_reg);
  873. }
  874. break;
  875. }
  876. }
  877. static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
  878. {
  879. struct MessageUnit_A __iomem *reg = acb->pmuA;
  880. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  881. writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
  882. if (arcmsr_hba_wait_msgint_ready(acb)) {
  883. printk(KERN_NOTICE
  884. "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
  885. , acb->host->host_no);
  886. }
  887. }
  888. static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
  889. {
  890. struct MessageUnit_B *reg = acb->pmuB;
  891. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  892. writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell_reg);
  893. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  894. printk(KERN_NOTICE
  895. "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
  896. , acb->host->host_no);
  897. }
  898. }
  899. static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
  900. {
  901. switch (acb->adapter_type) {
  902. case ACB_ADAPTER_TYPE_A: {
  903. arcmsr_stop_hba_bgrb(acb);
  904. }
  905. break;
  906. case ACB_ADAPTER_TYPE_B: {
  907. arcmsr_stop_hbb_bgrb(acb);
  908. }
  909. break;
  910. }
  911. }
  912. static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb)
  913. {
  914. switch (acb->adapter_type) {
  915. case ACB_ADAPTER_TYPE_A: {
  916. iounmap(acb->pmuA);
  917. break;
  918. }
  919. case ACB_ADAPTER_TYPE_B: {
  920. struct MessageUnit_B *reg = acb->pmuB;
  921. iounmap(reg->drv2iop_doorbell_reg - ARCMSR_DRV2IOP_DOORBELL);
  922. iounmap(reg->ioctl_wbuffer_reg - ARCMSR_IOCTL_WBUFFER);
  923. }
  924. }
  925. dma_free_coherent(&acb->pdev->dev,
  926. ARCMSR_MAX_FREECCB_NUM * sizeof (struct CommandControlBlock) + 0x20,
  927. acb->dma_coherent,
  928. acb->dma_coherent_handle);
  929. }
  930. void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
  931. {
  932. switch (acb->adapter_type) {
  933. case ACB_ADAPTER_TYPE_A: {
  934. struct MessageUnit_A __iomem *reg = acb->pmuA;
  935. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  936. }
  937. break;
  938. case ACB_ADAPTER_TYPE_B: {
  939. struct MessageUnit_B *reg = acb->pmuB;
  940. writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell_reg);
  941. }
  942. break;
  943. }
  944. }
  945. static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
  946. {
  947. switch (acb->adapter_type) {
  948. case ACB_ADAPTER_TYPE_A: {
  949. struct MessageUnit_A __iomem *reg = acb->pmuA;
  950. /*
  951. ** push inbound doorbell tell iop, driver data write ok
  952. ** and wait reply on next hwinterrupt for next Qbuffer post
  953. */
  954. writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, &reg->inbound_doorbell);
  955. }
  956. break;
  957. case ACB_ADAPTER_TYPE_B: {
  958. struct MessageUnit_B *reg = acb->pmuB;
  959. /*
  960. ** push inbound doorbell tell iop, driver data write ok
  961. ** and wait reply on next hwinterrupt for next Qbuffer post
  962. */
  963. writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell_reg);
  964. }
  965. break;
  966. }
  967. }
  968. struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb)
  969. {
  970. struct QBUFFER __iomem *qbuffer = NULL;
  971. switch (acb->adapter_type) {
  972. case ACB_ADAPTER_TYPE_A: {
  973. struct MessageUnit_A __iomem *reg = acb->pmuA;
  974. qbuffer = (struct QBUFFER __iomem *)&reg->message_rbuffer;
  975. }
  976. break;
  977. case ACB_ADAPTER_TYPE_B: {
  978. struct MessageUnit_B *reg = acb->pmuB;
  979. qbuffer = (struct QBUFFER __iomem *)reg->ioctl_rbuffer_reg;
  980. }
  981. break;
  982. }
  983. return qbuffer;
  984. }
  985. static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb)
  986. {
  987. struct QBUFFER __iomem *pqbuffer = NULL;
  988. switch (acb->adapter_type) {
  989. case ACB_ADAPTER_TYPE_A: {
  990. struct MessageUnit_A __iomem *reg = acb->pmuA;
  991. pqbuffer = (struct QBUFFER __iomem *) &reg->message_wbuffer;
  992. }
  993. break;
  994. case ACB_ADAPTER_TYPE_B: {
  995. struct MessageUnit_B *reg = acb->pmuB;
  996. pqbuffer = (struct QBUFFER __iomem *)reg->ioctl_wbuffer_reg;
  997. }
  998. break;
  999. }
  1000. return pqbuffer;
  1001. }
  1002. static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
  1003. {
  1004. struct QBUFFER __iomem *prbuffer;
  1005. struct QBUFFER *pQbuffer;
  1006. uint8_t __iomem *iop_data;
  1007. int32_t my_empty_len, iop_len, rqbuf_firstindex, rqbuf_lastindex;
  1008. rqbuf_lastindex = acb->rqbuf_lastindex;
  1009. rqbuf_firstindex = acb->rqbuf_firstindex;
  1010. prbuffer = arcmsr_get_iop_rqbuffer(acb);
  1011. iop_data = (uint8_t __iomem *)prbuffer->data;
  1012. iop_len = prbuffer->data_len;
  1013. my_empty_len = (rqbuf_firstindex - rqbuf_lastindex -1)&(ARCMSR_MAX_QBUFFER -1);
  1014. if (my_empty_len >= iop_len)
  1015. {
  1016. while (iop_len > 0) {
  1017. pQbuffer = (struct QBUFFER *)&acb->rqbuffer[rqbuf_lastindex];
  1018. memcpy(pQbuffer, iop_data,1);
  1019. rqbuf_lastindex++;
  1020. rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
  1021. iop_data++;
  1022. iop_len--;
  1023. }
  1024. acb->rqbuf_lastindex = rqbuf_lastindex;
  1025. arcmsr_iop_message_read(acb);
  1026. }
  1027. else {
  1028. acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
  1029. }
  1030. }
  1031. static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
  1032. {
  1033. acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED;
  1034. if (acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
  1035. uint8_t *pQbuffer;
  1036. struct QBUFFER __iomem *pwbuffer;
  1037. uint8_t __iomem *iop_data;
  1038. int32_t allxfer_len = 0;
  1039. acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
  1040. pwbuffer = arcmsr_get_iop_wqbuffer(acb);
  1041. iop_data = (uint8_t __iomem *)pwbuffer->data;
  1042. while ((acb->wqbuf_firstindex != acb->wqbuf_lastindex) && \
  1043. (allxfer_len < 124)) {
  1044. pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
  1045. memcpy(iop_data, pQbuffer, 1);
  1046. acb->wqbuf_firstindex++;
  1047. acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
  1048. iop_data++;
  1049. allxfer_len++;
  1050. }
  1051. pwbuffer->data_len = allxfer_len;
  1052. arcmsr_iop_message_wrote(acb);
  1053. }
  1054. if (acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
  1055. acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
  1056. }
  1057. }
  1058. static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
  1059. {
  1060. uint32_t outbound_doorbell;
  1061. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1062. outbound_doorbell = readl(&reg->outbound_doorbell);
  1063. writel(outbound_doorbell, &reg->outbound_doorbell);
  1064. if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
  1065. arcmsr_iop2drv_data_wrote_handle(acb);
  1066. }
  1067. if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
  1068. arcmsr_iop2drv_data_read_handle(acb);
  1069. }
  1070. }
  1071. static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
  1072. {
  1073. uint32_t flag_ccb;
  1074. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1075. while ((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF) {
  1076. arcmsr_drain_donequeue(acb, flag_ccb);
  1077. }
  1078. }
  1079. static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
  1080. {
  1081. uint32_t index;
  1082. uint32_t flag_ccb;
  1083. struct MessageUnit_B *reg = acb->pmuB;
  1084. index = reg->doneq_index;
  1085. while ((flag_ccb = readl(&reg->done_qbuffer[index])) != 0) {
  1086. writel(0, &reg->done_qbuffer[index]);
  1087. arcmsr_drain_donequeue(acb, flag_ccb);
  1088. index++;
  1089. index %= ARCMSR_MAX_HBB_POSTQUEUE;
  1090. reg->doneq_index = index;
  1091. }
  1092. }
  1093. static int arcmsr_handle_hba_isr(struct AdapterControlBlock *acb)
  1094. {
  1095. uint32_t outbound_intstatus;
  1096. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1097. outbound_intstatus = readl(&reg->outbound_intstatus) & \
  1098. acb->outbound_int_enable;
  1099. if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT)) {
  1100. return 1;
  1101. }
  1102. writel(outbound_intstatus, &reg->outbound_intstatus);
  1103. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
  1104. arcmsr_hba_doorbell_isr(acb);
  1105. }
  1106. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
  1107. arcmsr_hba_postqueue_isr(acb);
  1108. }
  1109. return 0;
  1110. }
  1111. static int arcmsr_handle_hbb_isr(struct AdapterControlBlock *acb)
  1112. {
  1113. uint32_t outbound_doorbell;
  1114. struct MessageUnit_B *reg = acb->pmuB;
  1115. outbound_doorbell = readl(reg->iop2drv_doorbell_reg) & \
  1116. acb->outbound_int_enable;
  1117. if (!outbound_doorbell)
  1118. return 1;
  1119. writel(~outbound_doorbell, reg->iop2drv_doorbell_reg);
  1120. if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
  1121. arcmsr_iop2drv_data_wrote_handle(acb);
  1122. }
  1123. if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
  1124. arcmsr_iop2drv_data_read_handle(acb);
  1125. }
  1126. if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
  1127. arcmsr_hbb_postqueue_isr(acb);
  1128. }
  1129. return 0;
  1130. }
  1131. static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb)
  1132. {
  1133. switch (acb->adapter_type) {
  1134. case ACB_ADAPTER_TYPE_A: {
  1135. if (arcmsr_handle_hba_isr(acb)) {
  1136. return IRQ_NONE;
  1137. }
  1138. }
  1139. break;
  1140. case ACB_ADAPTER_TYPE_B: {
  1141. if (arcmsr_handle_hbb_isr(acb)) {
  1142. return IRQ_NONE;
  1143. }
  1144. }
  1145. break;
  1146. }
  1147. return IRQ_HANDLED;
  1148. }
  1149. static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
  1150. {
  1151. if (acb) {
  1152. /* stop adapter background rebuild */
  1153. if (acb->acb_flags & ACB_F_MSG_START_BGRB) {
  1154. uint32_t intmask_org;
  1155. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1156. intmask_org = arcmsr_disable_outbound_ints(acb);
  1157. arcmsr_stop_adapter_bgrb(acb);
  1158. arcmsr_flush_adapter_cache(acb);
  1159. arcmsr_enable_outbound_ints(acb, intmask_org);
  1160. }
  1161. }
  1162. }
  1163. void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *acb)
  1164. {
  1165. int32_t wqbuf_firstindex, wqbuf_lastindex;
  1166. uint8_t *pQbuffer;
  1167. struct QBUFFER __iomem *pwbuffer;
  1168. uint8_t __iomem *iop_data;
  1169. int32_t allxfer_len = 0;
  1170. pwbuffer = arcmsr_get_iop_wqbuffer(acb);
  1171. iop_data = (uint8_t __iomem *)pwbuffer->data;
  1172. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
  1173. acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
  1174. wqbuf_firstindex = acb->wqbuf_firstindex;
  1175. wqbuf_lastindex = acb->wqbuf_lastindex;
  1176. while ((wqbuf_firstindex != wqbuf_lastindex) && (allxfer_len < 124)) {
  1177. pQbuffer = &acb->wqbuffer[wqbuf_firstindex];
  1178. memcpy(iop_data, pQbuffer, 1);
  1179. wqbuf_firstindex++;
  1180. wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
  1181. iop_data++;
  1182. allxfer_len++;
  1183. }
  1184. acb->wqbuf_firstindex = wqbuf_firstindex;
  1185. pwbuffer->data_len = allxfer_len;
  1186. arcmsr_iop_message_wrote(acb);
  1187. }
  1188. }
  1189. static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, \
  1190. struct scsi_cmnd *cmd)
  1191. {
  1192. struct CMD_MESSAGE_FIELD *pcmdmessagefld;
  1193. int retvalue = 0, transfer_len = 0;
  1194. char *buffer;
  1195. struct scatterlist *sg;
  1196. uint32_t controlcode = (uint32_t ) cmd->cmnd[5] << 24 |
  1197. (uint32_t ) cmd->cmnd[6] << 16 |
  1198. (uint32_t ) cmd->cmnd[7] << 8 |
  1199. (uint32_t ) cmd->cmnd[8];
  1200. /* 4 bytes: Areca io control code */
  1201. sg = scsi_sglist(cmd);
  1202. buffer = kmap_atomic(sg_page(sg), KM_IRQ0) + sg->offset;
  1203. if (scsi_sg_count(cmd) > 1) {
  1204. retvalue = ARCMSR_MESSAGE_FAIL;
  1205. goto message_out;
  1206. }
  1207. transfer_len += sg->length;
  1208. if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
  1209. retvalue = ARCMSR_MESSAGE_FAIL;
  1210. goto message_out;
  1211. }
  1212. pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
  1213. switch(controlcode) {
  1214. case ARCMSR_MESSAGE_READ_RQBUFFER: {
  1215. unsigned long *ver_addr;
  1216. dma_addr_t buf_handle;
  1217. uint8_t *pQbuffer, *ptmpQbuffer;
  1218. int32_t allxfer_len = 0;
  1219. ver_addr = pci_alloc_consistent(acb->pdev, 1032, &buf_handle);
  1220. if (!ver_addr) {
  1221. retvalue = ARCMSR_MESSAGE_FAIL;
  1222. goto message_out;
  1223. }
  1224. ptmpQbuffer = (uint8_t *) ver_addr;
  1225. while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
  1226. && (allxfer_len < 1031)) {
  1227. pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
  1228. memcpy(ptmpQbuffer, pQbuffer, 1);
  1229. acb->rqbuf_firstindex++;
  1230. acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
  1231. ptmpQbuffer++;
  1232. allxfer_len++;
  1233. }
  1234. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1235. struct QBUFFER __iomem *prbuffer;
  1236. uint8_t __iomem *iop_data;
  1237. int32_t iop_len;
  1238. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1239. prbuffer = arcmsr_get_iop_rqbuffer(acb);
  1240. iop_data = prbuffer->data;
  1241. iop_len = readl(&prbuffer->data_len);
  1242. while (iop_len > 0) {
  1243. acb->rqbuffer[acb->rqbuf_lastindex] = readb(iop_data);
  1244. acb->rqbuf_lastindex++;
  1245. acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
  1246. iop_data++;
  1247. iop_len--;
  1248. }
  1249. arcmsr_iop_message_read(acb);
  1250. }
  1251. memcpy(pcmdmessagefld->messagedatabuffer, (uint8_t *)ver_addr, allxfer_len);
  1252. pcmdmessagefld->cmdmessage.Length = allxfer_len;
  1253. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
  1254. pci_free_consistent(acb->pdev, 1032, ver_addr, buf_handle);
  1255. }
  1256. break;
  1257. case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
  1258. unsigned long *ver_addr;
  1259. dma_addr_t buf_handle;
  1260. int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
  1261. uint8_t *pQbuffer, *ptmpuserbuffer;
  1262. ver_addr = pci_alloc_consistent(acb->pdev, 1032, &buf_handle);
  1263. if (!ver_addr) {
  1264. retvalue = ARCMSR_MESSAGE_FAIL;
  1265. goto message_out;
  1266. }
  1267. ptmpuserbuffer = (uint8_t *)ver_addr;
  1268. user_len = pcmdmessagefld->cmdmessage.Length;
  1269. memcpy(ptmpuserbuffer, pcmdmessagefld->messagedatabuffer, user_len);
  1270. wqbuf_lastindex = acb->wqbuf_lastindex;
  1271. wqbuf_firstindex = acb->wqbuf_firstindex;
  1272. if (wqbuf_lastindex != wqbuf_firstindex) {
  1273. struct SENSE_DATA *sensebuffer =
  1274. (struct SENSE_DATA *)cmd->sense_buffer;
  1275. arcmsr_post_ioctldata2iop(acb);
  1276. /* has error report sensedata */
  1277. sensebuffer->ErrorCode = 0x70;
  1278. sensebuffer->SenseKey = ILLEGAL_REQUEST;
  1279. sensebuffer->AdditionalSenseLength = 0x0A;
  1280. sensebuffer->AdditionalSenseCode = 0x20;
  1281. sensebuffer->Valid = 1;
  1282. retvalue = ARCMSR_MESSAGE_FAIL;
  1283. } else {
  1284. my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
  1285. &(ARCMSR_MAX_QBUFFER - 1);
  1286. if (my_empty_len >= user_len) {
  1287. while (user_len > 0) {
  1288. pQbuffer =
  1289. &acb->wqbuffer[acb->wqbuf_lastindex];
  1290. memcpy(pQbuffer, ptmpuserbuffer, 1);
  1291. acb->wqbuf_lastindex++;
  1292. acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
  1293. ptmpuserbuffer++;
  1294. user_len--;
  1295. }
  1296. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
  1297. acb->acb_flags &=
  1298. ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
  1299. arcmsr_post_ioctldata2iop(acb);
  1300. }
  1301. } else {
  1302. /* has error report sensedata */
  1303. struct SENSE_DATA *sensebuffer =
  1304. (struct SENSE_DATA *)cmd->sense_buffer;
  1305. sensebuffer->ErrorCode = 0x70;
  1306. sensebuffer->SenseKey = ILLEGAL_REQUEST;
  1307. sensebuffer->AdditionalSenseLength = 0x0A;
  1308. sensebuffer->AdditionalSenseCode = 0x20;
  1309. sensebuffer->Valid = 1;
  1310. retvalue = ARCMSR_MESSAGE_FAIL;
  1311. }
  1312. }
  1313. pci_free_consistent(acb->pdev, 1032, ver_addr, buf_handle);
  1314. }
  1315. break;
  1316. case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
  1317. uint8_t *pQbuffer = acb->rqbuffer;
  1318. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1319. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1320. arcmsr_iop_message_read(acb);
  1321. }
  1322. acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
  1323. acb->rqbuf_firstindex = 0;
  1324. acb->rqbuf_lastindex = 0;
  1325. memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
  1326. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
  1327. }
  1328. break;
  1329. case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
  1330. uint8_t *pQbuffer = acb->wqbuffer;
  1331. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1332. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1333. arcmsr_iop_message_read(acb);
  1334. }
  1335. acb->acb_flags |=
  1336. (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  1337. ACB_F_MESSAGE_WQBUFFER_READED);
  1338. acb->wqbuf_firstindex = 0;
  1339. acb->wqbuf_lastindex = 0;
  1340. memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
  1341. pcmdmessagefld->cmdmessage.ReturnCode =
  1342. ARCMSR_MESSAGE_RETURNCODE_OK;
  1343. }
  1344. break;
  1345. case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
  1346. uint8_t *pQbuffer;
  1347. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1348. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1349. arcmsr_iop_message_read(acb);
  1350. }
  1351. acb->acb_flags |=
  1352. (ACB_F_MESSAGE_WQBUFFER_CLEARED
  1353. | ACB_F_MESSAGE_RQBUFFER_CLEARED
  1354. | ACB_F_MESSAGE_WQBUFFER_READED);
  1355. acb->rqbuf_firstindex = 0;
  1356. acb->rqbuf_lastindex = 0;
  1357. acb->wqbuf_firstindex = 0;
  1358. acb->wqbuf_lastindex = 0;
  1359. pQbuffer = acb->rqbuffer;
  1360. memset(pQbuffer, 0, sizeof(struct QBUFFER));
  1361. pQbuffer = acb->wqbuffer;
  1362. memset(pQbuffer, 0, sizeof(struct QBUFFER));
  1363. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
  1364. }
  1365. break;
  1366. case ARCMSR_MESSAGE_RETURN_CODE_3F: {
  1367. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
  1368. }
  1369. break;
  1370. case ARCMSR_MESSAGE_SAY_HELLO: {
  1371. int8_t *hello_string = "Hello! I am ARCMSR";
  1372. memcpy(pcmdmessagefld->messagedatabuffer, hello_string
  1373. , (int16_t)strlen(hello_string));
  1374. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
  1375. }
  1376. break;
  1377. case ARCMSR_MESSAGE_SAY_GOODBYE:
  1378. arcmsr_iop_parking(acb);
  1379. break;
  1380. case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
  1381. arcmsr_flush_adapter_cache(acb);
  1382. break;
  1383. default:
  1384. retvalue = ARCMSR_MESSAGE_FAIL;
  1385. }
  1386. message_out:
  1387. sg = scsi_sglist(cmd);
  1388. kunmap_atomic(buffer - sg->offset, KM_IRQ0);
  1389. return retvalue;
  1390. }
  1391. static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb)
  1392. {
  1393. struct list_head *head = &acb->ccb_free_list;
  1394. struct CommandControlBlock *ccb = NULL;
  1395. if (!list_empty(head)) {
  1396. ccb = list_entry(head->next, struct CommandControlBlock, list);
  1397. list_del(head->next);
  1398. }
  1399. return ccb;
  1400. }
  1401. static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
  1402. struct scsi_cmnd *cmd)
  1403. {
  1404. switch (cmd->cmnd[0]) {
  1405. case INQUIRY: {
  1406. unsigned char inqdata[36];
  1407. char *buffer;
  1408. struct scatterlist *sg;
  1409. if (cmd->device->lun) {
  1410. cmd->result = (DID_TIME_OUT << 16);
  1411. cmd->scsi_done(cmd);
  1412. return;
  1413. }
  1414. inqdata[0] = TYPE_PROCESSOR;
  1415. /* Periph Qualifier & Periph Dev Type */
  1416. inqdata[1] = 0;
  1417. /* rem media bit & Dev Type Modifier */
  1418. inqdata[2] = 0;
  1419. /* ISO, ECMA, & ANSI versions */
  1420. inqdata[4] = 31;
  1421. /* length of additional data */
  1422. strncpy(&inqdata[8], "Areca ", 8);
  1423. /* Vendor Identification */
  1424. strncpy(&inqdata[16], "RAID controller ", 16);
  1425. /* Product Identification */
  1426. strncpy(&inqdata[32], "R001", 4); /* Product Revision */
  1427. sg = scsi_sglist(cmd);
  1428. buffer = kmap_atomic(sg_page(sg), KM_IRQ0) + sg->offset;
  1429. memcpy(buffer, inqdata, sizeof(inqdata));
  1430. sg = scsi_sglist(cmd);
  1431. kunmap_atomic(buffer - sg->offset, KM_IRQ0);
  1432. cmd->scsi_done(cmd);
  1433. }
  1434. break;
  1435. case WRITE_BUFFER:
  1436. case READ_BUFFER: {
  1437. if (arcmsr_iop_message_xfer(acb, cmd))
  1438. cmd->result = (DID_ERROR << 16);
  1439. cmd->scsi_done(cmd);
  1440. }
  1441. break;
  1442. default:
  1443. cmd->scsi_done(cmd);
  1444. }
  1445. }
  1446. static int arcmsr_queue_command(struct scsi_cmnd *cmd,
  1447. void (* done)(struct scsi_cmnd *))
  1448. {
  1449. struct Scsi_Host *host = cmd->device->host;
  1450. struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
  1451. struct CommandControlBlock *ccb;
  1452. int target = cmd->device->id;
  1453. int lun = cmd->device->lun;
  1454. cmd->scsi_done = done;
  1455. cmd->host_scribble = NULL;
  1456. cmd->result = 0;
  1457. if (acb->acb_flags & ACB_F_BUS_RESET) {
  1458. printk(KERN_NOTICE "arcmsr%d: bus reset"
  1459. " and return busy \n"
  1460. , acb->host->host_no);
  1461. return SCSI_MLQUEUE_HOST_BUSY;
  1462. }
  1463. if (target == 16) {
  1464. /* virtual device for iop message transfer */
  1465. arcmsr_handle_virtual_command(acb, cmd);
  1466. return 0;
  1467. }
  1468. if (acb->devstate[target][lun] == ARECA_RAID_GONE) {
  1469. uint8_t block_cmd;
  1470. block_cmd = cmd->cmnd[0] & 0x0f;
  1471. if (block_cmd == 0x08 || block_cmd == 0x0a) {
  1472. printk(KERN_NOTICE
  1473. "arcmsr%d: block 'read/write'"
  1474. "command with gone raid volume"
  1475. " Cmd = %2x, TargetId = %d, Lun = %d \n"
  1476. , acb->host->host_no
  1477. , cmd->cmnd[0]
  1478. , target, lun);
  1479. cmd->result = (DID_NO_CONNECT << 16);
  1480. cmd->scsi_done(cmd);
  1481. return 0;
  1482. }
  1483. }
  1484. if (atomic_read(&acb->ccboutstandingcount) >=
  1485. ARCMSR_MAX_OUTSTANDING_CMD)
  1486. return SCSI_MLQUEUE_HOST_BUSY;
  1487. ccb = arcmsr_get_freeccb(acb);
  1488. if (!ccb)
  1489. return SCSI_MLQUEUE_HOST_BUSY;
  1490. arcmsr_build_ccb(acb, ccb, cmd);
  1491. arcmsr_post_ccb(acb, ccb);
  1492. return 0;
  1493. }
  1494. static void arcmsr_get_hba_config(struct AdapterControlBlock *acb)
  1495. {
  1496. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1497. char *acb_firm_model = acb->firm_model;
  1498. char *acb_firm_version = acb->firm_version;
  1499. char __iomem *iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]);
  1500. char __iomem *iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]);
  1501. int count;
  1502. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  1503. if (arcmsr_hba_wait_msgint_ready(acb)) {
  1504. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  1505. miscellaneous data' timeout \n", acb->host->host_no);
  1506. }
  1507. count = 8;
  1508. while (count) {
  1509. *acb_firm_model = readb(iop_firm_model);
  1510. acb_firm_model++;
  1511. iop_firm_model++;
  1512. count--;
  1513. }
  1514. count = 16;
  1515. while (count) {
  1516. *acb_firm_version = readb(iop_firm_version);
  1517. acb_firm_version++;
  1518. iop_firm_version++;
  1519. count--;
  1520. }
  1521. printk(KERN_INFO "ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n"
  1522. , acb->host->host_no
  1523. , acb->firm_version);
  1524. acb->firm_request_len = readl(&reg->message_rwbuffer[1]);
  1525. acb->firm_numbers_queue = readl(&reg->message_rwbuffer[2]);
  1526. acb->firm_sdram_size = readl(&reg->message_rwbuffer[3]);
  1527. acb->firm_hd_channels = readl(&reg->message_rwbuffer[4]);
  1528. }
  1529. static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
  1530. {
  1531. struct MessageUnit_B *reg = acb->pmuB;
  1532. uint32_t __iomem *lrwbuffer = reg->msgcode_rwbuffer_reg;
  1533. char *acb_firm_model = acb->firm_model;
  1534. char *acb_firm_version = acb->firm_version;
  1535. char __iomem *iop_firm_model = (char __iomem *)(&lrwbuffer[15]);
  1536. /*firm_model,15,60-67*/
  1537. char __iomem *iop_firm_version = (char __iomem *)(&lrwbuffer[17]);
  1538. /*firm_version,17,68-83*/
  1539. int count;
  1540. writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell_reg);
  1541. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  1542. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  1543. miscellaneous data' timeout \n", acb->host->host_no);
  1544. }
  1545. count = 8;
  1546. while (count)
  1547. {
  1548. *acb_firm_model = readb(iop_firm_model);
  1549. acb_firm_model++;
  1550. iop_firm_model++;
  1551. count--;
  1552. }
  1553. count = 16;
  1554. while (count)
  1555. {
  1556. *acb_firm_version = readb(iop_firm_version);
  1557. acb_firm_version++;
  1558. iop_firm_version++;
  1559. count--;
  1560. }
  1561. printk(KERN_INFO "ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n",
  1562. acb->host->host_no,
  1563. acb->firm_version);
  1564. lrwbuffer++;
  1565. acb->firm_request_len = readl(lrwbuffer++);
  1566. /*firm_request_len,1,04-07*/
  1567. acb->firm_numbers_queue = readl(lrwbuffer++);
  1568. /*firm_numbers_queue,2,08-11*/
  1569. acb->firm_sdram_size = readl(lrwbuffer++);
  1570. /*firm_sdram_size,3,12-15*/
  1571. acb->firm_hd_channels = readl(lrwbuffer);
  1572. /*firm_ide_channels,4,16-19*/
  1573. }
  1574. static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
  1575. {
  1576. switch (acb->adapter_type) {
  1577. case ACB_ADAPTER_TYPE_A: {
  1578. arcmsr_get_hba_config(acb);
  1579. }
  1580. break;
  1581. case ACB_ADAPTER_TYPE_B: {
  1582. arcmsr_get_hbb_config(acb);
  1583. }
  1584. break;
  1585. }
  1586. }
  1587. static void arcmsr_polling_hba_ccbdone(struct AdapterControlBlock *acb,
  1588. struct CommandControlBlock *poll_ccb)
  1589. {
  1590. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1591. struct CommandControlBlock *ccb;
  1592. uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0;
  1593. polling_hba_ccb_retry:
  1594. poll_count++;
  1595. outbound_intstatus = readl(&reg->outbound_intstatus) & acb->outbound_int_enable;
  1596. writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
  1597. while (1) {
  1598. if ((flag_ccb = readl(&reg->outbound_queueport)) == 0xFFFFFFFF) {
  1599. if (poll_ccb_done)
  1600. break;
  1601. else {
  1602. msleep(25);
  1603. if (poll_count > 100)
  1604. break;
  1605. goto polling_hba_ccb_retry;
  1606. }
  1607. }
  1608. ccb = (struct CommandControlBlock *)(acb->vir2phy_offset + (flag_ccb << 5));
  1609. poll_ccb_done = (ccb == poll_ccb) ? 1:0;
  1610. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  1611. if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
  1612. printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
  1613. " poll command abort successfully \n"
  1614. , acb->host->host_no
  1615. , ccb->pcmd->device->id
  1616. , ccb->pcmd->device->lun
  1617. , ccb);
  1618. ccb->pcmd->result = DID_ABORT << 16;
  1619. arcmsr_ccb_complete(ccb, 1);
  1620. poll_ccb_done = 1;
  1621. continue;
  1622. }
  1623. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  1624. " command done ccb = '0x%p'"
  1625. "ccboutstandingcount = %d \n"
  1626. , acb->host->host_no
  1627. , ccb
  1628. , atomic_read(&acb->ccboutstandingcount));
  1629. continue;
  1630. }
  1631. arcmsr_report_ccb_state(acb, ccb, flag_ccb);
  1632. }
  1633. }
  1634. static void arcmsr_polling_hbb_ccbdone(struct AdapterControlBlock *acb, \
  1635. struct CommandControlBlock *poll_ccb)
  1636. {
  1637. struct MessageUnit_B *reg = acb->pmuB;
  1638. struct CommandControlBlock *ccb;
  1639. uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0;
  1640. int index;
  1641. polling_hbb_ccb_retry:
  1642. poll_count++;
  1643. /* clear doorbell interrupt */
  1644. writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell_reg);
  1645. while (1) {
  1646. index = reg->doneq_index;
  1647. if ((flag_ccb = readl(&reg->done_qbuffer[index])) == 0) {
  1648. if (poll_ccb_done)
  1649. break;
  1650. else {
  1651. msleep(25);
  1652. if (poll_count > 100)
  1653. break;
  1654. goto polling_hbb_ccb_retry;
  1655. }
  1656. }
  1657. writel(0, &reg->done_qbuffer[index]);
  1658. index++;
  1659. /*if last index number set it to 0 */
  1660. index %= ARCMSR_MAX_HBB_POSTQUEUE;
  1661. reg->doneq_index = index;
  1662. /* check ifcommand done with no error*/
  1663. ccb = (struct CommandControlBlock *)\
  1664. (acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
  1665. poll_ccb_done = (ccb == poll_ccb) ? 1:0;
  1666. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  1667. if (ccb->startdone == ARCMSR_CCB_ABORTED) {
  1668. printk(KERN_NOTICE "arcmsr%d: \
  1669. scsi id = %d lun = %d ccb = '0x%p' poll command abort successfully \n"
  1670. ,acb->host->host_no
  1671. ,ccb->pcmd->device->id
  1672. ,ccb->pcmd->device->lun
  1673. ,ccb);
  1674. ccb->pcmd->result = DID_ABORT << 16;
  1675. arcmsr_ccb_complete(ccb, 1);
  1676. continue;
  1677. }
  1678. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  1679. " command done ccb = '0x%p'"
  1680. "ccboutstandingcount = %d \n"
  1681. , acb->host->host_no
  1682. , ccb
  1683. , atomic_read(&acb->ccboutstandingcount));
  1684. continue;
  1685. }
  1686. arcmsr_report_ccb_state(acb, ccb, flag_ccb);
  1687. } /*drain reply FIFO*/
  1688. }
  1689. static void arcmsr_polling_ccbdone(struct AdapterControlBlock *acb, \
  1690. struct CommandControlBlock *poll_ccb)
  1691. {
  1692. switch (acb->adapter_type) {
  1693. case ACB_ADAPTER_TYPE_A: {
  1694. arcmsr_polling_hba_ccbdone(acb,poll_ccb);
  1695. }
  1696. break;
  1697. case ACB_ADAPTER_TYPE_B: {
  1698. arcmsr_polling_hbb_ccbdone(acb,poll_ccb);
  1699. }
  1700. }
  1701. }
  1702. static int arcmsr_iop_confirm(struct AdapterControlBlock *acb)
  1703. {
  1704. uint32_t cdb_phyaddr, ccb_phyaddr_hi32;
  1705. dma_addr_t dma_coherent_handle;
  1706. /*
  1707. ********************************************************************
  1708. ** here we need to tell iop 331 our freeccb.HighPart
  1709. ** if freeccb.HighPart is not zero
  1710. ********************************************************************
  1711. */
  1712. dma_coherent_handle = acb->dma_coherent_handle;
  1713. cdb_phyaddr = (uint32_t)(dma_coherent_handle);
  1714. ccb_phyaddr_hi32 = (uint32_t)((cdb_phyaddr >> 16) >> 16);
  1715. /*
  1716. ***********************************************************************
  1717. ** if adapter type B, set window of "post command Q"
  1718. ***********************************************************************
  1719. */
  1720. switch (acb->adapter_type) {
  1721. case ACB_ADAPTER_TYPE_A: {
  1722. if (ccb_phyaddr_hi32 != 0) {
  1723. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1724. uint32_t intmask_org;
  1725. intmask_org = arcmsr_disable_outbound_ints(acb);
  1726. writel(ARCMSR_SIGNATURE_SET_CONFIG, \
  1727. &reg->message_rwbuffer[0]);
  1728. writel(ccb_phyaddr_hi32, &reg->message_rwbuffer[1]);
  1729. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
  1730. &reg->inbound_msgaddr0);
  1731. if (arcmsr_hba_wait_msgint_ready(acb)) {
  1732. printk(KERN_NOTICE "arcmsr%d: ""set ccb high \
  1733. part physical address timeout\n",
  1734. acb->host->host_no);
  1735. return 1;
  1736. }
  1737. arcmsr_enable_outbound_ints(acb, intmask_org);
  1738. }
  1739. }
  1740. break;
  1741. case ACB_ADAPTER_TYPE_B: {
  1742. unsigned long post_queue_phyaddr;
  1743. uint32_t __iomem *rwbuffer;
  1744. struct MessageUnit_B *reg = acb->pmuB;
  1745. uint32_t intmask_org;
  1746. intmask_org = arcmsr_disable_outbound_ints(acb);
  1747. reg->postq_index = 0;
  1748. reg->doneq_index = 0;
  1749. writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell_reg);
  1750. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  1751. printk(KERN_NOTICE "arcmsr%d:can not set diver mode\n", \
  1752. acb->host->host_no);
  1753. return 1;
  1754. }
  1755. post_queue_phyaddr = cdb_phyaddr + ARCMSR_MAX_FREECCB_NUM * \
  1756. sizeof(struct CommandControlBlock) + offsetof(struct MessageUnit_B, post_qbuffer) ;
  1757. rwbuffer = reg->msgcode_rwbuffer_reg;
  1758. /* driver "set config" signature */
  1759. writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
  1760. /* normal should be zero */
  1761. writel(ccb_phyaddr_hi32, rwbuffer++);
  1762. /* postQ size (256 + 8)*4 */
  1763. writel(post_queue_phyaddr, rwbuffer++);
  1764. /* doneQ size (256 + 8)*4 */
  1765. writel(post_queue_phyaddr + 1056, rwbuffer++);
  1766. /* ccb maxQ size must be --> [(256 + 8)*4]*/
  1767. writel(1056, rwbuffer);
  1768. writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell_reg);
  1769. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  1770. printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
  1771. timeout \n",acb->host->host_no);
  1772. return 1;
  1773. }
  1774. writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell_reg);
  1775. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  1776. printk(KERN_NOTICE "arcmsr%d: 'can not set diver mode \n"\
  1777. ,acb->host->host_no);
  1778. return 1;
  1779. }
  1780. arcmsr_enable_outbound_ints(acb, intmask_org);
  1781. }
  1782. break;
  1783. }
  1784. return 0;
  1785. }
  1786. static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb)
  1787. {
  1788. uint32_t firmware_state = 0;
  1789. switch (acb->adapter_type) {
  1790. case ACB_ADAPTER_TYPE_A: {
  1791. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1792. do {
  1793. firmware_state = readl(&reg->outbound_msgaddr1);
  1794. } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0);
  1795. }
  1796. break;
  1797. case ACB_ADAPTER_TYPE_B: {
  1798. struct MessageUnit_B *reg = acb->pmuB;
  1799. do {
  1800. firmware_state = readl(reg->iop2drv_doorbell_reg);
  1801. } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0);
  1802. }
  1803. break;
  1804. }
  1805. }
  1806. static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
  1807. {
  1808. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1809. acb->acb_flags |= ACB_F_MSG_START_BGRB;
  1810. writel(ARCMSR_INBOUND_MESG0_START_BGRB, &reg->inbound_msgaddr0);
  1811. if (arcmsr_hba_wait_msgint_ready(acb)) {
  1812. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  1813. rebulid' timeout \n", acb->host->host_no);
  1814. }
  1815. }
  1816. static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
  1817. {
  1818. struct MessageUnit_B *reg = acb->pmuB;
  1819. acb->acb_flags |= ACB_F_MSG_START_BGRB;
  1820. writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell_reg);
  1821. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  1822. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  1823. rebulid' timeout \n",acb->host->host_no);
  1824. }
  1825. }
  1826. static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
  1827. {
  1828. switch (acb->adapter_type) {
  1829. case ACB_ADAPTER_TYPE_A:
  1830. arcmsr_start_hba_bgrb(acb);
  1831. break;
  1832. case ACB_ADAPTER_TYPE_B:
  1833. arcmsr_start_hbb_bgrb(acb);
  1834. break;
  1835. }
  1836. }
  1837. static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb)
  1838. {
  1839. switch (acb->adapter_type) {
  1840. case ACB_ADAPTER_TYPE_A: {
  1841. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1842. uint32_t outbound_doorbell;
  1843. /* empty doorbell Qbuffer if door bell ringed */
  1844. outbound_doorbell = readl(&reg->outbound_doorbell);
  1845. /*clear doorbell interrupt */
  1846. writel(outbound_doorbell, &reg->outbound_doorbell);
  1847. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  1848. }
  1849. break;
  1850. case ACB_ADAPTER_TYPE_B: {
  1851. struct MessageUnit_B *reg = acb->pmuB;
  1852. /*clear interrupt and message state*/
  1853. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell_reg);
  1854. writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell_reg);
  1855. /* let IOP know data has been read */
  1856. }
  1857. break;
  1858. }
  1859. }
  1860. static void arcmsr_iop_init(struct AdapterControlBlock *acb)
  1861. {
  1862. uint32_t intmask_org;
  1863. arcmsr_wait_firmware_ready(acb);
  1864. arcmsr_iop_confirm(acb);
  1865. /* disable all outbound interrupt */
  1866. intmask_org = arcmsr_disable_outbound_ints(acb);
  1867. arcmsr_get_firmware_spec(acb);
  1868. /*start background rebuild*/
  1869. arcmsr_start_adapter_bgrb(acb);
  1870. /* empty doorbell Qbuffer if door bell ringed */
  1871. arcmsr_clear_doorbell_queue_buffer(acb);
  1872. /* enable outbound Post Queue,outbound doorbell Interrupt */
  1873. arcmsr_enable_outbound_ints(acb, intmask_org);
  1874. acb->acb_flags |= ACB_F_IOP_INITED;
  1875. }
  1876. static void arcmsr_iop_reset(struct AdapterControlBlock *acb)
  1877. {
  1878. struct CommandControlBlock *ccb;
  1879. uint32_t intmask_org;
  1880. int i = 0;
  1881. if (atomic_read(&acb->ccboutstandingcount) != 0) {
  1882. /* talk to iop 331 outstanding command aborted */
  1883. arcmsr_abort_allcmd(acb);
  1884. /* wait for 3 sec for all command aborted*/
  1885. ssleep(3);
  1886. /* disable all outbound interrupt */
  1887. intmask_org = arcmsr_disable_outbound_ints(acb);
  1888. /* clear all outbound posted Q */
  1889. arcmsr_done4abort_postqueue(acb);
  1890. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  1891. ccb = acb->pccb_pool[i];
  1892. if (ccb->startdone == ARCMSR_CCB_START) {
  1893. ccb->startdone = ARCMSR_CCB_ABORTED;
  1894. arcmsr_ccb_complete(ccb, 1);
  1895. }
  1896. }
  1897. /* enable all outbound interrupt */
  1898. arcmsr_enable_outbound_ints(acb, intmask_org);
  1899. }
  1900. }
  1901. static int arcmsr_bus_reset(struct scsi_cmnd *cmd)
  1902. {
  1903. struct AdapterControlBlock *acb =
  1904. (struct AdapterControlBlock *)cmd->device->host->hostdata;
  1905. int i;
  1906. acb->num_resets++;
  1907. acb->acb_flags |= ACB_F_BUS_RESET;
  1908. for (i = 0; i < 400; i++) {
  1909. if (!atomic_read(&acb->ccboutstandingcount))
  1910. break;
  1911. arcmsr_interrupt(acb);/* FIXME: need spinlock */
  1912. msleep(25);
  1913. }
  1914. arcmsr_iop_reset(acb);
  1915. acb->acb_flags &= ~ACB_F_BUS_RESET;
  1916. return SUCCESS;
  1917. }
  1918. static void arcmsr_abort_one_cmd(struct AdapterControlBlock *acb,
  1919. struct CommandControlBlock *ccb)
  1920. {
  1921. u32 intmask;
  1922. ccb->startdone = ARCMSR_CCB_ABORTED;
  1923. /*
  1924. ** Wait for 3 sec for all command done.
  1925. */
  1926. ssleep(3);
  1927. intmask = arcmsr_disable_outbound_ints(acb);
  1928. arcmsr_polling_ccbdone(acb, ccb);
  1929. arcmsr_enable_outbound_ints(acb, intmask);
  1930. }
  1931. static int arcmsr_abort(struct scsi_cmnd *cmd)
  1932. {
  1933. struct AdapterControlBlock *acb =
  1934. (struct AdapterControlBlock *)cmd->device->host->hostdata;
  1935. int i = 0;
  1936. printk(KERN_NOTICE
  1937. "arcmsr%d: abort device command of scsi id = %d lun = %d \n",
  1938. acb->host->host_no, cmd->device->id, cmd->device->lun);
  1939. acb->num_aborts++;
  1940. /*
  1941. ************************************************
  1942. ** the all interrupt service routine is locked
  1943. ** we need to handle it as soon as possible and exit
  1944. ************************************************
  1945. */
  1946. if (!atomic_read(&acb->ccboutstandingcount))
  1947. return SUCCESS;
  1948. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  1949. struct CommandControlBlock *ccb = acb->pccb_pool[i];
  1950. if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) {
  1951. arcmsr_abort_one_cmd(acb, ccb);
  1952. break;
  1953. }
  1954. }
  1955. return SUCCESS;
  1956. }
  1957. static const char *arcmsr_info(struct Scsi_Host *host)
  1958. {
  1959. struct AdapterControlBlock *acb =
  1960. (struct AdapterControlBlock *) host->hostdata;
  1961. static char buf[256];
  1962. char *type;
  1963. int raid6 = 1;
  1964. switch (acb->pdev->device) {
  1965. case PCI_DEVICE_ID_ARECA_1110:
  1966. case PCI_DEVICE_ID_ARECA_1200:
  1967. case PCI_DEVICE_ID_ARECA_1202:
  1968. case PCI_DEVICE_ID_ARECA_1210:
  1969. raid6 = 0;
  1970. /*FALLTHRU*/
  1971. case PCI_DEVICE_ID_ARECA_1120:
  1972. case PCI_DEVICE_ID_ARECA_1130:
  1973. case PCI_DEVICE_ID_ARECA_1160:
  1974. case PCI_DEVICE_ID_ARECA_1170:
  1975. case PCI_DEVICE_ID_ARECA_1201:
  1976. case PCI_DEVICE_ID_ARECA_1220:
  1977. case PCI_DEVICE_ID_ARECA_1230:
  1978. case PCI_DEVICE_ID_ARECA_1260:
  1979. case PCI_DEVICE_ID_ARECA_1270:
  1980. case PCI_DEVICE_ID_ARECA_1280:
  1981. type = "SATA";
  1982. break;
  1983. case PCI_DEVICE_ID_ARECA_1380:
  1984. case PCI_DEVICE_ID_ARECA_1381:
  1985. case PCI_DEVICE_ID_ARECA_1680:
  1986. case PCI_DEVICE_ID_ARECA_1681:
  1987. type = "SAS";
  1988. break;
  1989. default:
  1990. type = "X-TYPE";
  1991. break;
  1992. }
  1993. sprintf(buf, "Areca %s Host Adapter RAID Controller%s\n %s",
  1994. type, raid6 ? "( RAID6 capable)" : "",
  1995. ARCMSR_DRIVER_VERSION);
  1996. return buf;
  1997. }
  1998. #ifdef CONFIG_SCSI_ARCMSR_AER
  1999. static pci_ers_result_t arcmsr_pci_slot_reset(struct pci_dev *pdev)
  2000. {
  2001. struct Scsi_Host *host = pci_get_drvdata(pdev);
  2002. struct AdapterControlBlock *acb =
  2003. (struct AdapterControlBlock *) host->hostdata;
  2004. uint32_t intmask_org;
  2005. int i, j;
  2006. if (pci_enable_device(pdev)) {
  2007. return PCI_ERS_RESULT_DISCONNECT;
  2008. }
  2009. pci_set_master(pdev);
  2010. intmask_org = arcmsr_disable_outbound_ints(acb);
  2011. acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  2012. ACB_F_MESSAGE_RQBUFFER_CLEARED |
  2013. ACB_F_MESSAGE_WQBUFFER_READED);
  2014. acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
  2015. for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
  2016. for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
  2017. acb->devstate[i][j] = ARECA_RAID_GONE;
  2018. arcmsr_wait_firmware_ready(acb);
  2019. arcmsr_iop_confirm(acb);
  2020. /* disable all outbound interrupt */
  2021. arcmsr_get_firmware_spec(acb);
  2022. /*start background rebuild*/
  2023. arcmsr_start_adapter_bgrb(acb);
  2024. /* empty doorbell Qbuffer if door bell ringed */
  2025. arcmsr_clear_doorbell_queue_buffer(acb);
  2026. /* enable outbound Post Queue,outbound doorbell Interrupt */
  2027. arcmsr_enable_outbound_ints(acb, intmask_org);
  2028. acb->acb_flags |= ACB_F_IOP_INITED;
  2029. pci_enable_pcie_error_reporting(pdev);
  2030. return PCI_ERS_RESULT_RECOVERED;
  2031. }
  2032. static void arcmsr_pci_ers_need_reset_forepart(struct pci_dev *pdev)
  2033. {
  2034. struct Scsi_Host *host = pci_get_drvdata(pdev);
  2035. struct AdapterControlBlock *acb = (struct AdapterControlBlock *)host->hostdata;
  2036. struct CommandControlBlock *ccb;
  2037. uint32_t intmask_org;
  2038. int i = 0;
  2039. if (atomic_read(&acb->ccboutstandingcount) != 0) {
  2040. /* talk to iop 331 outstanding command aborted */
  2041. arcmsr_abort_allcmd(acb);
  2042. /* wait for 3 sec for all command aborted*/
  2043. ssleep(3);
  2044. /* disable all outbound interrupt */
  2045. intmask_org = arcmsr_disable_outbound_ints(acb);
  2046. /* clear all outbound posted Q */
  2047. arcmsr_done4abort_postqueue(acb);
  2048. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  2049. ccb = acb->pccb_pool[i];
  2050. if (ccb->startdone == ARCMSR_CCB_START) {
  2051. ccb->startdone = ARCMSR_CCB_ABORTED;
  2052. arcmsr_ccb_complete(ccb, 1);
  2053. }
  2054. }
  2055. /* enable all outbound interrupt */
  2056. arcmsr_enable_outbound_ints(acb, intmask_org);
  2057. }
  2058. pci_disable_device(pdev);
  2059. }
  2060. static void arcmsr_pci_ers_disconnect_forepart(struct pci_dev *pdev)
  2061. {
  2062. struct Scsi_Host *host = pci_get_drvdata(pdev);
  2063. struct AdapterControlBlock *acb = \
  2064. (struct AdapterControlBlock *)host->hostdata;
  2065. arcmsr_stop_adapter_bgrb(acb);
  2066. arcmsr_flush_adapter_cache(acb);
  2067. }
  2068. static pci_ers_result_t arcmsr_pci_error_detected(struct pci_dev *pdev,
  2069. pci_channel_state_t state)
  2070. {
  2071. switch (state) {
  2072. case pci_channel_io_frozen:
  2073. arcmsr_pci_ers_need_reset_forepart(pdev);
  2074. return PCI_ERS_RESULT_NEED_RESET;
  2075. case pci_channel_io_perm_failure:
  2076. arcmsr_pci_ers_disconnect_forepart(pdev);
  2077. return PCI_ERS_RESULT_DISCONNECT;
  2078. break;
  2079. default:
  2080. return PCI_ERS_RESULT_NEED_RESET;
  2081. }
  2082. }
  2083. #endif