aic7xxx_osm_pci.c 12 KB

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  1. /*
  2. * Linux driver attachment glue for PCI based controllers.
  3. *
  4. * Copyright (c) 2000-2001 Adaptec Inc.
  5. * All rights reserved.
  6. *
  7. * Redistribution and use in source and binary forms, with or without
  8. * modification, are permitted provided that the following conditions
  9. * are met:
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions, and the following disclaimer,
  12. * without modification.
  13. * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14. * substantially similar to the "NO WARRANTY" disclaimer below
  15. * ("Disclaimer") and any redistribution must be conditioned upon
  16. * including a substantially similar Disclaimer requirement for further
  17. * binary redistribution.
  18. * 3. Neither the names of the above-listed copyright holders nor the names
  19. * of any contributors may be used to endorse or promote products derived
  20. * from this software without specific prior written permission.
  21. *
  22. * Alternatively, this software may be distributed under the terms of the
  23. * GNU General Public License ("GPL") version 2 as published by the Free
  24. * Software Foundation.
  25. *
  26. * NO WARRANTY
  27. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31. * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36. * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37. * POSSIBILITY OF SUCH DAMAGES.
  38. *
  39. * $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/aic7xxx_osm_pci.c#47 $
  40. */
  41. #include "aic7xxx_osm.h"
  42. #include "aic7xxx_pci.h"
  43. static int ahc_linux_pci_dev_probe(struct pci_dev *pdev,
  44. const struct pci_device_id *ent);
  45. static int ahc_linux_pci_reserve_io_region(struct ahc_softc *ahc,
  46. u_long *base);
  47. static int ahc_linux_pci_reserve_mem_region(struct ahc_softc *ahc,
  48. u_long *bus_addr,
  49. uint8_t __iomem **maddr);
  50. static int ahc_linux_pci_dev_suspend(struct pci_dev *pdev, pm_message_t mesg);
  51. static int ahc_linux_pci_dev_resume(struct pci_dev *pdev);
  52. static void ahc_linux_pci_dev_remove(struct pci_dev *pdev);
  53. /* Define the macro locally since it's different for different class of chips.
  54. */
  55. #define ID(x) ID_C(x, PCI_CLASS_STORAGE_SCSI)
  56. static struct pci_device_id ahc_linux_pci_id_table[] = {
  57. /* aic7850 based controllers */
  58. ID(ID_AHA_2902_04_10_15_20C_30C),
  59. /* aic7860 based controllers */
  60. ID(ID_AHA_2930CU),
  61. ID(ID_AHA_1480A & ID_DEV_VENDOR_MASK),
  62. ID(ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK),
  63. ID(ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK),
  64. ID(ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK),
  65. /* aic7870 based controllers */
  66. ID(ID_AHA_2940),
  67. ID(ID_AHA_3940),
  68. ID(ID_AHA_398X),
  69. ID(ID_AHA_2944),
  70. ID(ID_AHA_3944),
  71. ID(ID_AHA_4944),
  72. /* aic7880 based controllers */
  73. ID(ID_AHA_2940U & ID_DEV_VENDOR_MASK),
  74. ID(ID_AHA_3940U & ID_DEV_VENDOR_MASK),
  75. ID(ID_AHA_2944U & ID_DEV_VENDOR_MASK),
  76. ID(ID_AHA_3944U & ID_DEV_VENDOR_MASK),
  77. ID(ID_AHA_398XU & ID_DEV_VENDOR_MASK),
  78. ID(ID_AHA_4944U & ID_DEV_VENDOR_MASK),
  79. ID(ID_AHA_2930U & ID_DEV_VENDOR_MASK),
  80. ID(ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK),
  81. ID(ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK),
  82. /* aic7890 based controllers */
  83. ID(ID_AHA_2930U2),
  84. ID(ID_AHA_2940U2B),
  85. ID(ID_AHA_2940U2_OEM),
  86. ID(ID_AHA_2940U2),
  87. ID(ID_AHA_2950U2B),
  88. ID16(ID_AIC7890_ARO & ID_AIC7895_ARO_MASK),
  89. ID(ID_AAA_131U2),
  90. /* aic7890 based controllers */
  91. ID(ID_AHA_29160),
  92. ID(ID_AHA_29160_CPQ),
  93. ID(ID_AHA_29160N),
  94. ID(ID_AHA_29160C),
  95. ID(ID_AHA_29160B),
  96. ID(ID_AHA_19160B),
  97. ID(ID_AIC7892_ARO),
  98. /* aic7892 based controllers */
  99. ID(ID_AHA_2940U_DUAL),
  100. ID(ID_AHA_3940AU),
  101. ID(ID_AHA_3944AU),
  102. ID(ID_AIC7895_ARO),
  103. ID(ID_AHA_3950U2B_0),
  104. ID(ID_AHA_3950U2B_1),
  105. ID(ID_AHA_3950U2D_0),
  106. ID(ID_AHA_3950U2D_1),
  107. ID(ID_AIC7896_ARO),
  108. /* aic7899 based controllers */
  109. ID(ID_AHA_3960D),
  110. ID(ID_AHA_3960D_CPQ),
  111. ID(ID_AIC7899_ARO),
  112. /* Generic chip probes for devices we don't know exactly. */
  113. ID(ID_AIC7850 & ID_DEV_VENDOR_MASK),
  114. ID(ID_AIC7855 & ID_DEV_VENDOR_MASK),
  115. ID(ID_AIC7859 & ID_DEV_VENDOR_MASK),
  116. ID(ID_AIC7860 & ID_DEV_VENDOR_MASK),
  117. ID(ID_AIC7870 & ID_DEV_VENDOR_MASK),
  118. ID(ID_AIC7880 & ID_DEV_VENDOR_MASK),
  119. ID16(ID_AIC7890 & ID_9005_GENERIC_MASK),
  120. ID16(ID_AIC7892 & ID_9005_GENERIC_MASK),
  121. ID(ID_AIC7895 & ID_DEV_VENDOR_MASK),
  122. ID16(ID_AIC7896 & ID_9005_GENERIC_MASK),
  123. ID16(ID_AIC7899 & ID_9005_GENERIC_MASK),
  124. ID(ID_AIC7810 & ID_DEV_VENDOR_MASK),
  125. ID(ID_AIC7815 & ID_DEV_VENDOR_MASK),
  126. { 0 }
  127. };
  128. MODULE_DEVICE_TABLE(pci, ahc_linux_pci_id_table);
  129. static struct pci_driver aic7xxx_pci_driver = {
  130. .name = "aic7xxx",
  131. .probe = ahc_linux_pci_dev_probe,
  132. #ifdef CONFIG_PM
  133. .suspend = ahc_linux_pci_dev_suspend,
  134. .resume = ahc_linux_pci_dev_resume,
  135. #endif
  136. .remove = ahc_linux_pci_dev_remove,
  137. .id_table = ahc_linux_pci_id_table
  138. };
  139. static int
  140. ahc_linux_pci_dev_suspend(struct pci_dev *pdev, pm_message_t mesg)
  141. {
  142. struct ahc_softc *ahc = pci_get_drvdata(pdev);
  143. int rc;
  144. if ((rc = ahc_suspend(ahc)))
  145. return rc;
  146. pci_save_state(pdev);
  147. pci_disable_device(pdev);
  148. if (mesg.event == PM_EVENT_SUSPEND)
  149. pci_set_power_state(pdev, PCI_D3hot);
  150. return rc;
  151. }
  152. static int
  153. ahc_linux_pci_dev_resume(struct pci_dev *pdev)
  154. {
  155. struct ahc_softc *ahc = pci_get_drvdata(pdev);
  156. int rc;
  157. pci_set_power_state(pdev, PCI_D0);
  158. pci_restore_state(pdev);
  159. if ((rc = pci_enable_device(pdev))) {
  160. dev_printk(KERN_ERR, &pdev->dev,
  161. "failed to enable device after resume (%d)\n", rc);
  162. return rc;
  163. }
  164. pci_set_master(pdev);
  165. ahc_pci_resume(ahc);
  166. return (ahc_resume(ahc));
  167. }
  168. static void
  169. ahc_linux_pci_dev_remove(struct pci_dev *pdev)
  170. {
  171. struct ahc_softc *ahc = pci_get_drvdata(pdev);
  172. u_long s;
  173. if (ahc->platform_data && ahc->platform_data->host)
  174. scsi_remove_host(ahc->platform_data->host);
  175. ahc_lock(ahc, &s);
  176. ahc_intr_enable(ahc, FALSE);
  177. ahc_unlock(ahc, &s);
  178. ahc_free(ahc);
  179. }
  180. static void
  181. ahc_linux_pci_inherit_flags(struct ahc_softc *ahc)
  182. {
  183. struct pci_dev *pdev = ahc->dev_softc, *master_pdev;
  184. unsigned int master_devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
  185. master_pdev = pci_get_slot(pdev->bus, master_devfn);
  186. if (master_pdev) {
  187. struct ahc_softc *master = pci_get_drvdata(master_pdev);
  188. if (master) {
  189. ahc->flags &= ~AHC_BIOS_ENABLED;
  190. ahc->flags |= master->flags & AHC_BIOS_ENABLED;
  191. ahc->flags &= ~AHC_PRIMARY_CHANNEL;
  192. ahc->flags |= master->flags & AHC_PRIMARY_CHANNEL;
  193. } else
  194. printk(KERN_ERR "aic7xxx: no multichannel peer found!\n");
  195. pci_dev_put(master_pdev);
  196. }
  197. }
  198. static int
  199. ahc_linux_pci_dev_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  200. {
  201. char buf[80];
  202. const uint64_t mask_39bit = 0x7FFFFFFFFFULL;
  203. struct ahc_softc *ahc;
  204. ahc_dev_softc_t pci;
  205. struct ahc_pci_identity *entry;
  206. char *name;
  207. int error;
  208. struct device *dev = &pdev->dev;
  209. pci = pdev;
  210. entry = ahc_find_pci_device(pci);
  211. if (entry == NULL)
  212. return (-ENODEV);
  213. /*
  214. * Allocate a softc for this card and
  215. * set it up for attachment by our
  216. * common detect routine.
  217. */
  218. sprintf(buf, "ahc_pci:%d:%d:%d",
  219. ahc_get_pci_bus(pci),
  220. ahc_get_pci_slot(pci),
  221. ahc_get_pci_function(pci));
  222. name = malloc(strlen(buf) + 1, M_DEVBUF, M_NOWAIT);
  223. if (name == NULL)
  224. return (-ENOMEM);
  225. strcpy(name, buf);
  226. ahc = ahc_alloc(NULL, name);
  227. if (ahc == NULL)
  228. return (-ENOMEM);
  229. if (pci_enable_device(pdev)) {
  230. ahc_free(ahc);
  231. return (-ENODEV);
  232. }
  233. pci_set_master(pdev);
  234. if (sizeof(dma_addr_t) > 4
  235. && ahc->features & AHC_LARGE_SCBS
  236. && dma_set_mask(dev, mask_39bit) == 0
  237. && dma_get_required_mask(dev) > DMA_32BIT_MASK) {
  238. ahc->flags |= AHC_39BIT_ADDRESSING;
  239. } else {
  240. if (dma_set_mask(dev, DMA_32BIT_MASK)) {
  241. ahc_free(ahc);
  242. printk(KERN_WARNING "aic7xxx: No suitable DMA available.\n");
  243. return (-ENODEV);
  244. }
  245. }
  246. ahc->dev_softc = pci;
  247. error = ahc_pci_config(ahc, entry);
  248. if (error != 0) {
  249. ahc_free(ahc);
  250. return (-error);
  251. }
  252. /*
  253. * Second Function PCI devices need to inherit some
  254. * settings from function 0.
  255. */
  256. if ((ahc->features & AHC_MULTI_FUNC) && PCI_FUNC(pdev->devfn) != 0)
  257. ahc_linux_pci_inherit_flags(ahc);
  258. pci_set_drvdata(pdev, ahc);
  259. ahc_linux_register_host(ahc, &aic7xxx_driver_template);
  260. return (0);
  261. }
  262. int
  263. ahc_linux_pci_init(void)
  264. {
  265. return pci_register_driver(&aic7xxx_pci_driver);
  266. }
  267. void
  268. ahc_linux_pci_exit(void)
  269. {
  270. pci_unregister_driver(&aic7xxx_pci_driver);
  271. }
  272. static int
  273. ahc_linux_pci_reserve_io_region(struct ahc_softc *ahc, u_long *base)
  274. {
  275. if (aic7xxx_allow_memio == 0)
  276. return (ENOMEM);
  277. *base = pci_resource_start(ahc->dev_softc, 0);
  278. if (*base == 0)
  279. return (ENOMEM);
  280. if (request_region(*base, 256, "aic7xxx") == 0)
  281. return (ENOMEM);
  282. return (0);
  283. }
  284. static int
  285. ahc_linux_pci_reserve_mem_region(struct ahc_softc *ahc,
  286. u_long *bus_addr,
  287. uint8_t __iomem **maddr)
  288. {
  289. u_long start;
  290. int error;
  291. error = 0;
  292. start = pci_resource_start(ahc->dev_softc, 1);
  293. if (start != 0) {
  294. *bus_addr = start;
  295. if (request_mem_region(start, 0x1000, "aic7xxx") == 0)
  296. error = ENOMEM;
  297. if (error == 0) {
  298. *maddr = ioremap_nocache(start, 256);
  299. if (*maddr == NULL) {
  300. error = ENOMEM;
  301. release_mem_region(start, 0x1000);
  302. }
  303. }
  304. } else
  305. error = ENOMEM;
  306. return (error);
  307. }
  308. int
  309. ahc_pci_map_registers(struct ahc_softc *ahc)
  310. {
  311. uint32_t command;
  312. u_long base;
  313. uint8_t __iomem *maddr;
  314. int error;
  315. /*
  316. * If its allowed, we prefer memory mapped access.
  317. */
  318. command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, 4);
  319. command &= ~(PCIM_CMD_PORTEN|PCIM_CMD_MEMEN);
  320. base = 0;
  321. maddr = NULL;
  322. error = ahc_linux_pci_reserve_mem_region(ahc, &base, &maddr);
  323. if (error == 0) {
  324. ahc->platform_data->mem_busaddr = base;
  325. ahc->tag = BUS_SPACE_MEMIO;
  326. ahc->bsh.maddr = maddr;
  327. ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
  328. command | PCIM_CMD_MEMEN, 4);
  329. /*
  330. * Do a quick test to see if memory mapped
  331. * I/O is functioning correctly.
  332. */
  333. if (ahc_pci_test_register_access(ahc) != 0) {
  334. printf("aic7xxx: PCI Device %d:%d:%d "
  335. "failed memory mapped test. Using PIO.\n",
  336. ahc_get_pci_bus(ahc->dev_softc),
  337. ahc_get_pci_slot(ahc->dev_softc),
  338. ahc_get_pci_function(ahc->dev_softc));
  339. iounmap(maddr);
  340. release_mem_region(ahc->platform_data->mem_busaddr,
  341. 0x1000);
  342. ahc->bsh.maddr = NULL;
  343. maddr = NULL;
  344. } else
  345. command |= PCIM_CMD_MEMEN;
  346. } else {
  347. printf("aic7xxx: PCI%d:%d:%d MEM region 0x%lx "
  348. "unavailable. Cannot memory map device.\n",
  349. ahc_get_pci_bus(ahc->dev_softc),
  350. ahc_get_pci_slot(ahc->dev_softc),
  351. ahc_get_pci_function(ahc->dev_softc),
  352. base);
  353. }
  354. /*
  355. * We always prefer memory mapped access.
  356. */
  357. if (maddr == NULL) {
  358. error = ahc_linux_pci_reserve_io_region(ahc, &base);
  359. if (error == 0) {
  360. ahc->tag = BUS_SPACE_PIO;
  361. ahc->bsh.ioport = base;
  362. command |= PCIM_CMD_PORTEN;
  363. } else {
  364. printf("aic7xxx: PCI%d:%d:%d IO region 0x%lx[0..255] "
  365. "unavailable. Cannot map device.\n",
  366. ahc_get_pci_bus(ahc->dev_softc),
  367. ahc_get_pci_slot(ahc->dev_softc),
  368. ahc_get_pci_function(ahc->dev_softc),
  369. base);
  370. }
  371. }
  372. ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, 4);
  373. return (error);
  374. }
  375. int
  376. ahc_pci_map_int(struct ahc_softc *ahc)
  377. {
  378. int error;
  379. error = request_irq(ahc->dev_softc->irq, ahc_linux_isr,
  380. IRQF_SHARED, "aic7xxx", ahc);
  381. if (error == 0)
  382. ahc->platform_data->irq = ahc->dev_softc->irq;
  383. return (-error);
  384. }