zd_rf_al2230.c 12 KB

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  1. /* zd_rf_al2230.c: Functions for the AL2230 RF controller
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License as published by
  5. * the Free Software Foundation; either version 2 of the License, or
  6. * (at your option) any later version.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  16. */
  17. #include <linux/kernel.h>
  18. #include "zd_rf.h"
  19. #include "zd_usb.h"
  20. #include "zd_chip.h"
  21. #define IS_AL2230S(chip) ((chip)->al2230s_bit || (chip)->rf.type == AL2230S_RF)
  22. static const u32 zd1211_al2230_table[][3] = {
  23. RF_CHANNEL( 1) = { 0x03f790, 0x033331, 0x00000d, },
  24. RF_CHANNEL( 2) = { 0x03f790, 0x0b3331, 0x00000d, },
  25. RF_CHANNEL( 3) = { 0x03e790, 0x033331, 0x00000d, },
  26. RF_CHANNEL( 4) = { 0x03e790, 0x0b3331, 0x00000d, },
  27. RF_CHANNEL( 5) = { 0x03f7a0, 0x033331, 0x00000d, },
  28. RF_CHANNEL( 6) = { 0x03f7a0, 0x0b3331, 0x00000d, },
  29. RF_CHANNEL( 7) = { 0x03e7a0, 0x033331, 0x00000d, },
  30. RF_CHANNEL( 8) = { 0x03e7a0, 0x0b3331, 0x00000d, },
  31. RF_CHANNEL( 9) = { 0x03f7b0, 0x033331, 0x00000d, },
  32. RF_CHANNEL(10) = { 0x03f7b0, 0x0b3331, 0x00000d, },
  33. RF_CHANNEL(11) = { 0x03e7b0, 0x033331, 0x00000d, },
  34. RF_CHANNEL(12) = { 0x03e7b0, 0x0b3331, 0x00000d, },
  35. RF_CHANNEL(13) = { 0x03f7c0, 0x033331, 0x00000d, },
  36. RF_CHANNEL(14) = { 0x03e7c0, 0x066661, 0x00000d, },
  37. };
  38. static const u32 zd1211b_al2230_table[][3] = {
  39. RF_CHANNEL( 1) = { 0x09efc0, 0x8cccc0, 0xb00000, },
  40. RF_CHANNEL( 2) = { 0x09efc0, 0x8cccd0, 0xb00000, },
  41. RF_CHANNEL( 3) = { 0x09e7c0, 0x8cccc0, 0xb00000, },
  42. RF_CHANNEL( 4) = { 0x09e7c0, 0x8cccd0, 0xb00000, },
  43. RF_CHANNEL( 5) = { 0x05efc0, 0x8cccc0, 0xb00000, },
  44. RF_CHANNEL( 6) = { 0x05efc0, 0x8cccd0, 0xb00000, },
  45. RF_CHANNEL( 7) = { 0x05e7c0, 0x8cccc0, 0xb00000, },
  46. RF_CHANNEL( 8) = { 0x05e7c0, 0x8cccd0, 0xb00000, },
  47. RF_CHANNEL( 9) = { 0x0defc0, 0x8cccc0, 0xb00000, },
  48. RF_CHANNEL(10) = { 0x0defc0, 0x8cccd0, 0xb00000, },
  49. RF_CHANNEL(11) = { 0x0de7c0, 0x8cccc0, 0xb00000, },
  50. RF_CHANNEL(12) = { 0x0de7c0, 0x8cccd0, 0xb00000, },
  51. RF_CHANNEL(13) = { 0x03efc0, 0x8cccc0, 0xb00000, },
  52. RF_CHANNEL(14) = { 0x03e7c0, 0x866660, 0xb00000, },
  53. };
  54. static const struct zd_ioreq16 zd1211b_ioreqs_shared_1[] = {
  55. { CR240, 0x57 }, { CR9, 0xe0 },
  56. };
  57. static const struct zd_ioreq16 ioreqs_init_al2230s[] = {
  58. { CR47, 0x1e }, /* MARK_002 */
  59. { CR106, 0x22 },
  60. { CR107, 0x2a }, /* MARK_002 */
  61. { CR109, 0x13 }, /* MARK_002 */
  62. { CR118, 0xf8 }, /* MARK_002 */
  63. { CR119, 0x12 }, { CR122, 0xe0 },
  64. { CR128, 0x10 }, /* MARK_001 from 0xe->0x10 */
  65. { CR129, 0x0e }, /* MARK_001 from 0xd->0x0e */
  66. { CR130, 0x10 }, /* MARK_001 from 0xb->0x0d */
  67. };
  68. static int zd1211b_al2230_finalize_rf(struct zd_chip *chip)
  69. {
  70. int r;
  71. static const struct zd_ioreq16 ioreqs[] = {
  72. { CR80, 0x30 }, { CR81, 0x30 }, { CR79, 0x58 },
  73. { CR12, 0xf0 }, { CR77, 0x1b }, { CR78, 0x58 },
  74. { CR203, 0x06 },
  75. { },
  76. { CR240, 0x80 },
  77. };
  78. r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  79. if (r)
  80. return r;
  81. /* related to antenna selection? */
  82. if (chip->new_phy_layout) {
  83. r = zd_iowrite16_locked(chip, 0xe1, CR9);
  84. if (r)
  85. return r;
  86. }
  87. return zd_iowrite16_locked(chip, 0x06, CR203);
  88. }
  89. static int zd1211_al2230_init_hw(struct zd_rf *rf)
  90. {
  91. int r;
  92. struct zd_chip *chip = zd_rf_to_chip(rf);
  93. static const struct zd_ioreq16 ioreqs_init[] = {
  94. { CR15, 0x20 }, { CR23, 0x40 }, { CR24, 0x20 },
  95. { CR26, 0x11 }, { CR28, 0x3e }, { CR29, 0x00 },
  96. { CR44, 0x33 }, { CR106, 0x2a }, { CR107, 0x1a },
  97. { CR109, 0x09 }, { CR110, 0x27 }, { CR111, 0x2b },
  98. { CR112, 0x2b }, { CR119, 0x0a }, { CR10, 0x89 },
  99. /* for newest (3rd cut) AL2300 */
  100. { CR17, 0x28 },
  101. { CR26, 0x93 }, { CR34, 0x30 },
  102. /* for newest (3rd cut) AL2300 */
  103. { CR35, 0x3e },
  104. { CR41, 0x24 }, { CR44, 0x32 },
  105. /* for newest (3rd cut) AL2300 */
  106. { CR46, 0x96 },
  107. { CR47, 0x1e }, { CR79, 0x58 }, { CR80, 0x30 },
  108. { CR81, 0x30 }, { CR87, 0x0a }, { CR89, 0x04 },
  109. { CR92, 0x0a }, { CR99, 0x28 }, { CR100, 0x00 },
  110. { CR101, 0x13 }, { CR102, 0x27 }, { CR106, 0x24 },
  111. { CR107, 0x2a }, { CR109, 0x09 }, { CR110, 0x13 },
  112. { CR111, 0x1f }, { CR112, 0x1f }, { CR113, 0x27 },
  113. { CR114, 0x27 },
  114. /* for newest (3rd cut) AL2300 */
  115. { CR115, 0x24 },
  116. { CR116, 0x24 }, { CR117, 0xf4 }, { CR118, 0xfc },
  117. { CR119, 0x10 }, { CR120, 0x4f }, { CR121, 0x77 },
  118. { CR122, 0xe0 }, { CR137, 0x88 }, { CR252, 0xff },
  119. { CR253, 0xff },
  120. };
  121. static const struct zd_ioreq16 ioreqs_pll[] = {
  122. /* shdnb(PLL_ON)=0 */
  123. { CR251, 0x2f },
  124. /* shdnb(PLL_ON)=1 */
  125. { CR251, 0x3f },
  126. { CR138, 0x28 }, { CR203, 0x06 },
  127. };
  128. static const u32 rv1[] = {
  129. /* Channel 1 */
  130. 0x03f790,
  131. 0x033331,
  132. 0x00000d,
  133. 0x0b3331,
  134. 0x03b812,
  135. 0x00fff3,
  136. };
  137. static const u32 rv2[] = {
  138. 0x000da4,
  139. 0x0f4dc5, /* fix freq shift, 0x04edc5 */
  140. 0x0805b6,
  141. 0x011687,
  142. 0x000688,
  143. 0x0403b9, /* external control TX power (CR31) */
  144. 0x00dbba,
  145. 0x00099b,
  146. 0x0bdffc,
  147. 0x00000d,
  148. 0x00500f,
  149. };
  150. static const u32 rv3[] = {
  151. 0x00d00f,
  152. 0x004c0f,
  153. 0x00540f,
  154. 0x00700f,
  155. 0x00500f,
  156. };
  157. r = zd_iowrite16a_locked(chip, ioreqs_init, ARRAY_SIZE(ioreqs_init));
  158. if (r)
  159. return r;
  160. if (IS_AL2230S(chip)) {
  161. r = zd_iowrite16a_locked(chip, ioreqs_init_al2230s,
  162. ARRAY_SIZE(ioreqs_init_al2230s));
  163. if (r)
  164. return r;
  165. }
  166. r = zd_rfwritev_locked(chip, rv1, ARRAY_SIZE(rv1), RF_RV_BITS);
  167. if (r)
  168. return r;
  169. /* improve band edge for AL2230S */
  170. if (IS_AL2230S(chip))
  171. r = zd_rfwrite_locked(chip, 0x000824, RF_RV_BITS);
  172. else
  173. r = zd_rfwrite_locked(chip, 0x0005a4, RF_RV_BITS);
  174. if (r)
  175. return r;
  176. r = zd_rfwritev_locked(chip, rv2, ARRAY_SIZE(rv2), RF_RV_BITS);
  177. if (r)
  178. return r;
  179. r = zd_iowrite16a_locked(chip, ioreqs_pll, ARRAY_SIZE(ioreqs_pll));
  180. if (r)
  181. return r;
  182. r = zd_rfwritev_locked(chip, rv3, ARRAY_SIZE(rv3), RF_RV_BITS);
  183. if (r)
  184. return r;
  185. return 0;
  186. }
  187. static int zd1211b_al2230_init_hw(struct zd_rf *rf)
  188. {
  189. int r;
  190. struct zd_chip *chip = zd_rf_to_chip(rf);
  191. static const struct zd_ioreq16 ioreqs1[] = {
  192. { CR10, 0x89 }, { CR15, 0x20 },
  193. { CR17, 0x2B }, /* for newest(3rd cut) AL2230 */
  194. { CR23, 0x40 }, { CR24, 0x20 }, { CR26, 0x93 },
  195. { CR28, 0x3e }, { CR29, 0x00 },
  196. { CR33, 0x28 }, /* 5621 */
  197. { CR34, 0x30 },
  198. { CR35, 0x3e }, /* for newest(3rd cut) AL2230 */
  199. { CR41, 0x24 }, { CR44, 0x32 },
  200. { CR46, 0x99 }, /* for newest(3rd cut) AL2230 */
  201. { CR47, 0x1e },
  202. /* ZD1211B 05.06.10 */
  203. { CR48, 0x06 }, { CR49, 0xf9 }, { CR51, 0x01 },
  204. { CR52, 0x80 }, { CR53, 0x7e }, { CR65, 0x00 },
  205. { CR66, 0x00 }, { CR67, 0x00 }, { CR68, 0x00 },
  206. { CR69, 0x28 },
  207. { CR79, 0x58 }, { CR80, 0x30 }, { CR81, 0x30 },
  208. { CR87, 0x0a }, { CR89, 0x04 },
  209. { CR91, 0x00 }, /* 5621 */
  210. { CR92, 0x0a },
  211. { CR98, 0x8d }, /* 4804, for 1212 new algorithm */
  212. { CR99, 0x00 }, /* 5621 */
  213. { CR101, 0x13 }, { CR102, 0x27 },
  214. { CR106, 0x24 }, /* for newest(3rd cut) AL2230 */
  215. { CR107, 0x2a },
  216. { CR109, 0x13 }, /* 4804, for 1212 new algorithm */
  217. { CR110, 0x1f }, /* 4804, for 1212 new algorithm */
  218. { CR111, 0x1f }, { CR112, 0x1f }, { CR113, 0x27 },
  219. { CR114, 0x27 },
  220. { CR115, 0x26 }, /* 24->26 at 4902 for newest(3rd cut) AL2230 */
  221. { CR116, 0x24 },
  222. { CR117, 0xfa }, /* for 1211b */
  223. { CR118, 0xfa }, /* for 1211b */
  224. { CR119, 0x10 },
  225. { CR120, 0x4f },
  226. { CR121, 0x6c }, /* for 1211b */
  227. { CR122, 0xfc }, /* E0->FC at 4902 */
  228. { CR123, 0x57 }, /* 5623 */
  229. { CR125, 0xad }, /* 4804, for 1212 new algorithm */
  230. { CR126, 0x6c }, /* 5614 */
  231. { CR127, 0x03 }, /* 4804, for 1212 new algorithm */
  232. { CR137, 0x50 }, /* 5614 */
  233. { CR138, 0xa8 },
  234. { CR144, 0xac }, /* 5621 */
  235. { CR150, 0x0d }, { CR252, 0x34 }, { CR253, 0x34 },
  236. };
  237. static const u32 rv1[] = {
  238. 0x8cccd0,
  239. 0x481dc0,
  240. 0xcfff00,
  241. 0x25a000,
  242. };
  243. static const u32 rv2[] = {
  244. /* To improve AL2230 yield, improve phase noise, 4713 */
  245. 0x25a000,
  246. 0xa3b2f0,
  247. 0x6da010, /* Reg6 update for MP versio */
  248. 0xe36280, /* Modified by jxiao for Bor-Chin on 2004/08/02 */
  249. 0x116000,
  250. 0x9dc020, /* External control TX power (CR31) */
  251. 0x5ddb00, /* RegA update for MP version */
  252. 0xd99000, /* RegB update for MP version */
  253. 0x3ffbd0, /* RegC update for MP version */
  254. 0xb00000, /* RegD update for MP version */
  255. /* improve phase noise and remove phase calibration,4713 */
  256. 0xf01a00,
  257. };
  258. static const struct zd_ioreq16 ioreqs2[] = {
  259. { CR251, 0x2f }, /* shdnb(PLL_ON)=0 */
  260. { CR251, 0x7f }, /* shdnb(PLL_ON)=1 */
  261. };
  262. static const u32 rv3[] = {
  263. /* To improve AL2230 yield, 4713 */
  264. 0xf01b00,
  265. 0xf01e00,
  266. 0xf01a00,
  267. };
  268. static const struct zd_ioreq16 ioreqs3[] = {
  269. /* related to 6M band edge patching, happens unconditionally */
  270. { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
  271. };
  272. r = zd_iowrite16a_locked(chip, zd1211b_ioreqs_shared_1,
  273. ARRAY_SIZE(zd1211b_ioreqs_shared_1));
  274. if (r)
  275. return r;
  276. r = zd_iowrite16a_locked(chip, ioreqs1, ARRAY_SIZE(ioreqs1));
  277. if (r)
  278. return r;
  279. if (IS_AL2230S(chip)) {
  280. r = zd_iowrite16a_locked(chip, ioreqs_init_al2230s,
  281. ARRAY_SIZE(ioreqs_init_al2230s));
  282. if (r)
  283. return r;
  284. }
  285. r = zd_rfwritev_cr_locked(chip, zd1211b_al2230_table[0], 3);
  286. if (r)
  287. return r;
  288. r = zd_rfwritev_cr_locked(chip, rv1, ARRAY_SIZE(rv1));
  289. if (r)
  290. return r;
  291. if (IS_AL2230S(chip))
  292. r = zd_rfwrite_locked(chip, 0x241000, RF_RV_BITS);
  293. else
  294. r = zd_rfwrite_locked(chip, 0x25a000, RF_RV_BITS);
  295. if (r)
  296. return r;
  297. r = zd_rfwritev_cr_locked(chip, rv2, ARRAY_SIZE(rv2));
  298. if (r)
  299. return r;
  300. r = zd_iowrite16a_locked(chip, ioreqs2, ARRAY_SIZE(ioreqs2));
  301. if (r)
  302. return r;
  303. r = zd_rfwritev_cr_locked(chip, rv3, ARRAY_SIZE(rv3));
  304. if (r)
  305. return r;
  306. r = zd_iowrite16a_locked(chip, ioreqs3, ARRAY_SIZE(ioreqs3));
  307. if (r)
  308. return r;
  309. return zd1211b_al2230_finalize_rf(chip);
  310. }
  311. static int zd1211_al2230_set_channel(struct zd_rf *rf, u8 channel)
  312. {
  313. int r;
  314. const u32 *rv = zd1211_al2230_table[channel-1];
  315. struct zd_chip *chip = zd_rf_to_chip(rf);
  316. static const struct zd_ioreq16 ioreqs[] = {
  317. { CR138, 0x28 },
  318. { CR203, 0x06 },
  319. };
  320. r = zd_rfwritev_locked(chip, rv, 3, RF_RV_BITS);
  321. if (r)
  322. return r;
  323. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  324. }
  325. static int zd1211b_al2230_set_channel(struct zd_rf *rf, u8 channel)
  326. {
  327. int r;
  328. const u32 *rv = zd1211b_al2230_table[channel-1];
  329. struct zd_chip *chip = zd_rf_to_chip(rf);
  330. r = zd_iowrite16a_locked(chip, zd1211b_ioreqs_shared_1,
  331. ARRAY_SIZE(zd1211b_ioreqs_shared_1));
  332. if (r)
  333. return r;
  334. r = zd_rfwritev_cr_locked(chip, rv, 3);
  335. if (r)
  336. return r;
  337. return zd1211b_al2230_finalize_rf(chip);
  338. }
  339. static int zd1211_al2230_switch_radio_on(struct zd_rf *rf)
  340. {
  341. struct zd_chip *chip = zd_rf_to_chip(rf);
  342. static const struct zd_ioreq16 ioreqs[] = {
  343. { CR11, 0x00 },
  344. { CR251, 0x3f },
  345. };
  346. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  347. }
  348. static int zd1211b_al2230_switch_radio_on(struct zd_rf *rf)
  349. {
  350. struct zd_chip *chip = zd_rf_to_chip(rf);
  351. static const struct zd_ioreq16 ioreqs[] = {
  352. { CR11, 0x00 },
  353. { CR251, 0x7f },
  354. };
  355. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  356. }
  357. static int al2230_switch_radio_off(struct zd_rf *rf)
  358. {
  359. struct zd_chip *chip = zd_rf_to_chip(rf);
  360. static const struct zd_ioreq16 ioreqs[] = {
  361. { CR11, 0x04 },
  362. { CR251, 0x2f },
  363. };
  364. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  365. }
  366. int zd_rf_init_al2230(struct zd_rf *rf)
  367. {
  368. struct zd_chip *chip = zd_rf_to_chip(rf);
  369. rf->switch_radio_off = al2230_switch_radio_off;
  370. if (zd_chip_is_zd1211b(chip)) {
  371. rf->init_hw = zd1211b_al2230_init_hw;
  372. rf->set_channel = zd1211b_al2230_set_channel;
  373. rf->switch_radio_on = zd1211b_al2230_switch_radio_on;
  374. } else {
  375. rf->init_hw = zd1211_al2230_init_hw;
  376. rf->set_channel = zd1211_al2230_set_channel;
  377. rf->switch_radio_on = zd1211_al2230_switch_radio_on;
  378. }
  379. rf->patch_6m_band_edge = zd_rf_generic_patch_6m;
  380. rf->patch_cck_gain = 1;
  381. return 0;
  382. }