main.c 103 KB

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  1. /*
  2. *
  3. * Broadcom B43legacy wireless driver
  4. *
  5. * Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
  6. * Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
  7. * Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
  8. * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
  9. * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10. * Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
  11. *
  12. * Some parts of the code in this file are derived from the ipw2200
  13. * driver Copyright(c) 2003 - 2004 Intel Corporation.
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; see the file COPYING. If not, write to
  26. * the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  27. * Boston, MA 02110-1301, USA.
  28. *
  29. */
  30. #include <linux/delay.h>
  31. #include <linux/init.h>
  32. #include <linux/moduleparam.h>
  33. #include <linux/if_arp.h>
  34. #include <linux/etherdevice.h>
  35. #include <linux/version.h>
  36. #include <linux/firmware.h>
  37. #include <linux/wireless.h>
  38. #include <linux/workqueue.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/dma-mapping.h>
  41. #include <net/dst.h>
  42. #include <asm/unaligned.h>
  43. #include "b43legacy.h"
  44. #include "main.h"
  45. #include "debugfs.h"
  46. #include "phy.h"
  47. #include "dma.h"
  48. #include "pio.h"
  49. #include "sysfs.h"
  50. #include "xmit.h"
  51. #include "radio.h"
  52. MODULE_DESCRIPTION("Broadcom B43legacy wireless driver");
  53. MODULE_AUTHOR("Martin Langer");
  54. MODULE_AUTHOR("Stefano Brivio");
  55. MODULE_AUTHOR("Michael Buesch");
  56. MODULE_LICENSE("GPL");
  57. #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
  58. static int modparam_pio;
  59. module_param_named(pio, modparam_pio, int, 0444);
  60. MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
  61. #elif defined(CONFIG_B43LEGACY_DMA)
  62. # define modparam_pio 0
  63. #elif defined(CONFIG_B43LEGACY_PIO)
  64. # define modparam_pio 1
  65. #endif
  66. static int modparam_bad_frames_preempt;
  67. module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  68. MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
  69. " Preemption");
  70. static int modparam_short_retry = B43legacy_DEFAULT_SHORT_RETRY_LIMIT;
  71. module_param_named(short_retry, modparam_short_retry, int, 0444);
  72. MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
  73. static int modparam_long_retry = B43legacy_DEFAULT_LONG_RETRY_LIMIT;
  74. module_param_named(long_retry, modparam_long_retry, int, 0444);
  75. MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
  76. static int modparam_noleds;
  77. module_param_named(noleds, modparam_noleds, int, 0444);
  78. MODULE_PARM_DESC(noleds, "Turn off all LED activity");
  79. static char modparam_fwpostfix[16];
  80. module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  81. MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load.");
  82. /* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */
  83. static const struct ssb_device_id b43legacy_ssb_tbl[] = {
  84. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2),
  85. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4),
  86. SSB_DEVTABLE_END
  87. };
  88. MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl);
  89. /* Channel and ratetables are shared for all devices.
  90. * They can't be const, because ieee80211 puts some precalculated
  91. * data in there. This data is the same for all devices, so we don't
  92. * get concurrency issues */
  93. #define RATETAB_ENT(_rateid, _flags) \
  94. { \
  95. .rate = B43legacy_RATE_TO_100KBPS(_rateid), \
  96. .val = (_rateid), \
  97. .val2 = (_rateid), \
  98. .flags = (_flags), \
  99. }
  100. static struct ieee80211_rate __b43legacy_ratetable[] = {
  101. RATETAB_ENT(B43legacy_CCK_RATE_1MB, IEEE80211_RATE_CCK),
  102. RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
  103. RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
  104. RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
  105. RATETAB_ENT(B43legacy_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
  106. RATETAB_ENT(B43legacy_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
  107. RATETAB_ENT(B43legacy_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
  108. RATETAB_ENT(B43legacy_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
  109. RATETAB_ENT(B43legacy_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
  110. RATETAB_ENT(B43legacy_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
  111. RATETAB_ENT(B43legacy_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
  112. RATETAB_ENT(B43legacy_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
  113. };
  114. #define b43legacy_a_ratetable (__b43legacy_ratetable + 4)
  115. #define b43legacy_a_ratetable_size 8
  116. #define b43legacy_b_ratetable (__b43legacy_ratetable + 0)
  117. #define b43legacy_b_ratetable_size 4
  118. #define b43legacy_g_ratetable (__b43legacy_ratetable + 0)
  119. #define b43legacy_g_ratetable_size 12
  120. #define CHANTAB_ENT(_chanid, _freq) \
  121. { \
  122. .chan = (_chanid), \
  123. .freq = (_freq), \
  124. .val = (_chanid), \
  125. .flag = IEEE80211_CHAN_W_SCAN | \
  126. IEEE80211_CHAN_W_ACTIVE_SCAN | \
  127. IEEE80211_CHAN_W_IBSS, \
  128. .power_level = 0x0A, \
  129. .antenna_max = 0xFF, \
  130. }
  131. static struct ieee80211_channel b43legacy_bg_chantable[] = {
  132. CHANTAB_ENT(1, 2412),
  133. CHANTAB_ENT(2, 2417),
  134. CHANTAB_ENT(3, 2422),
  135. CHANTAB_ENT(4, 2427),
  136. CHANTAB_ENT(5, 2432),
  137. CHANTAB_ENT(6, 2437),
  138. CHANTAB_ENT(7, 2442),
  139. CHANTAB_ENT(8, 2447),
  140. CHANTAB_ENT(9, 2452),
  141. CHANTAB_ENT(10, 2457),
  142. CHANTAB_ENT(11, 2462),
  143. CHANTAB_ENT(12, 2467),
  144. CHANTAB_ENT(13, 2472),
  145. CHANTAB_ENT(14, 2484),
  146. };
  147. #define b43legacy_bg_chantable_size ARRAY_SIZE(b43legacy_bg_chantable)
  148. static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev);
  149. static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev);
  150. static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev);
  151. static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev);
  152. static int b43legacy_ratelimit(struct b43legacy_wl *wl)
  153. {
  154. if (!wl || !wl->current_dev)
  155. return 1;
  156. if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED)
  157. return 1;
  158. /* We are up and running.
  159. * Ratelimit the messages to avoid DoS over the net. */
  160. return net_ratelimit();
  161. }
  162. void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
  163. {
  164. va_list args;
  165. if (!b43legacy_ratelimit(wl))
  166. return;
  167. va_start(args, fmt);
  168. printk(KERN_INFO "b43legacy-%s: ",
  169. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  170. vprintk(fmt, args);
  171. va_end(args);
  172. }
  173. void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
  174. {
  175. va_list args;
  176. if (!b43legacy_ratelimit(wl))
  177. return;
  178. va_start(args, fmt);
  179. printk(KERN_ERR "b43legacy-%s ERROR: ",
  180. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  181. vprintk(fmt, args);
  182. va_end(args);
  183. }
  184. void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
  185. {
  186. va_list args;
  187. if (!b43legacy_ratelimit(wl))
  188. return;
  189. va_start(args, fmt);
  190. printk(KERN_WARNING "b43legacy-%s warning: ",
  191. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  192. vprintk(fmt, args);
  193. va_end(args);
  194. }
  195. #if B43legacy_DEBUG
  196. void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
  197. {
  198. va_list args;
  199. va_start(args, fmt);
  200. printk(KERN_DEBUG "b43legacy-%s debug: ",
  201. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  202. vprintk(fmt, args);
  203. va_end(args);
  204. }
  205. #endif /* DEBUG */
  206. static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset,
  207. u32 val)
  208. {
  209. u32 status;
  210. B43legacy_WARN_ON(offset % 4 != 0);
  211. status = b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
  212. if (status & B43legacy_SBF_XFER_REG_BYTESWAP)
  213. val = swab32(val);
  214. b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset);
  215. mmiowb();
  216. b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val);
  217. }
  218. static inline
  219. void b43legacy_shm_control_word(struct b43legacy_wldev *dev,
  220. u16 routing, u16 offset)
  221. {
  222. u32 control;
  223. /* "offset" is the WORD offset. */
  224. control = routing;
  225. control <<= 16;
  226. control |= offset;
  227. b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
  228. }
  229. u32 b43legacy_shm_read32(struct b43legacy_wldev *dev,
  230. u16 routing, u16 offset)
  231. {
  232. u32 ret;
  233. if (routing == B43legacy_SHM_SHARED) {
  234. B43legacy_WARN_ON((offset & 0x0001) != 0);
  235. if (offset & 0x0003) {
  236. /* Unaligned access */
  237. b43legacy_shm_control_word(dev, routing, offset >> 2);
  238. ret = b43legacy_read16(dev,
  239. B43legacy_MMIO_SHM_DATA_UNALIGNED);
  240. ret <<= 16;
  241. b43legacy_shm_control_word(dev, routing,
  242. (offset >> 2) + 1);
  243. ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
  244. return ret;
  245. }
  246. offset >>= 2;
  247. }
  248. b43legacy_shm_control_word(dev, routing, offset);
  249. ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA);
  250. return ret;
  251. }
  252. u16 b43legacy_shm_read16(struct b43legacy_wldev *dev,
  253. u16 routing, u16 offset)
  254. {
  255. u16 ret;
  256. if (routing == B43legacy_SHM_SHARED) {
  257. B43legacy_WARN_ON((offset & 0x0001) != 0);
  258. if (offset & 0x0003) {
  259. /* Unaligned access */
  260. b43legacy_shm_control_word(dev, routing, offset >> 2);
  261. ret = b43legacy_read16(dev,
  262. B43legacy_MMIO_SHM_DATA_UNALIGNED);
  263. return ret;
  264. }
  265. offset >>= 2;
  266. }
  267. b43legacy_shm_control_word(dev, routing, offset);
  268. ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
  269. return ret;
  270. }
  271. void b43legacy_shm_write32(struct b43legacy_wldev *dev,
  272. u16 routing, u16 offset,
  273. u32 value)
  274. {
  275. if (routing == B43legacy_SHM_SHARED) {
  276. B43legacy_WARN_ON((offset & 0x0001) != 0);
  277. if (offset & 0x0003) {
  278. /* Unaligned access */
  279. b43legacy_shm_control_word(dev, routing, offset >> 2);
  280. mmiowb();
  281. b43legacy_write16(dev,
  282. B43legacy_MMIO_SHM_DATA_UNALIGNED,
  283. (value >> 16) & 0xffff);
  284. mmiowb();
  285. b43legacy_shm_control_word(dev, routing,
  286. (offset >> 2) + 1);
  287. mmiowb();
  288. b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA,
  289. value & 0xffff);
  290. return;
  291. }
  292. offset >>= 2;
  293. }
  294. b43legacy_shm_control_word(dev, routing, offset);
  295. mmiowb();
  296. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value);
  297. }
  298. void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset,
  299. u16 value)
  300. {
  301. if (routing == B43legacy_SHM_SHARED) {
  302. B43legacy_WARN_ON((offset & 0x0001) != 0);
  303. if (offset & 0x0003) {
  304. /* Unaligned access */
  305. b43legacy_shm_control_word(dev, routing, offset >> 2);
  306. mmiowb();
  307. b43legacy_write16(dev,
  308. B43legacy_MMIO_SHM_DATA_UNALIGNED,
  309. value);
  310. return;
  311. }
  312. offset >>= 2;
  313. }
  314. b43legacy_shm_control_word(dev, routing, offset);
  315. mmiowb();
  316. b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value);
  317. }
  318. /* Read HostFlags */
  319. u32 b43legacy_hf_read(struct b43legacy_wldev *dev)
  320. {
  321. u32 ret;
  322. ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  323. B43legacy_SHM_SH_HOSTFHI);
  324. ret <<= 16;
  325. ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  326. B43legacy_SHM_SH_HOSTFLO);
  327. return ret;
  328. }
  329. /* Write HostFlags */
  330. void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value)
  331. {
  332. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  333. B43legacy_SHM_SH_HOSTFLO,
  334. (value & 0x0000FFFF));
  335. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  336. B43legacy_SHM_SH_HOSTFHI,
  337. ((value & 0xFFFF0000) >> 16));
  338. }
  339. void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
  340. {
  341. /* We need to be careful. As we read the TSF from multiple
  342. * registers, we should take care of register overflows.
  343. * In theory, the whole tsf read process should be atomic.
  344. * We try to be atomic here, by restaring the read process,
  345. * if any of the high registers changed (overflew).
  346. */
  347. if (dev->dev->id.revision >= 3) {
  348. u32 low;
  349. u32 high;
  350. u32 high2;
  351. do {
  352. high = b43legacy_read32(dev,
  353. B43legacy_MMIO_REV3PLUS_TSF_HIGH);
  354. low = b43legacy_read32(dev,
  355. B43legacy_MMIO_REV3PLUS_TSF_LOW);
  356. high2 = b43legacy_read32(dev,
  357. B43legacy_MMIO_REV3PLUS_TSF_HIGH);
  358. } while (unlikely(high != high2));
  359. *tsf = high;
  360. *tsf <<= 32;
  361. *tsf |= low;
  362. } else {
  363. u64 tmp;
  364. u16 v0;
  365. u16 v1;
  366. u16 v2;
  367. u16 v3;
  368. u16 test1;
  369. u16 test2;
  370. u16 test3;
  371. do {
  372. v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
  373. v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
  374. v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
  375. v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
  376. test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
  377. test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
  378. test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
  379. } while (v3 != test3 || v2 != test2 || v1 != test1);
  380. *tsf = v3;
  381. *tsf <<= 48;
  382. tmp = v2;
  383. tmp <<= 32;
  384. *tsf |= tmp;
  385. tmp = v1;
  386. tmp <<= 16;
  387. *tsf |= tmp;
  388. *tsf |= v0;
  389. }
  390. }
  391. static void b43legacy_time_lock(struct b43legacy_wldev *dev)
  392. {
  393. u32 status;
  394. status = b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
  395. status |= B43legacy_SBF_TIME_UPDATE;
  396. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, status);
  397. mmiowb();
  398. }
  399. static void b43legacy_time_unlock(struct b43legacy_wldev *dev)
  400. {
  401. u32 status;
  402. status = b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
  403. status &= ~B43legacy_SBF_TIME_UPDATE;
  404. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, status);
  405. }
  406. static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf)
  407. {
  408. /* Be careful with the in-progress timer.
  409. * First zero out the low register, so we have a full
  410. * register-overflow duration to complete the operation.
  411. */
  412. if (dev->dev->id.revision >= 3) {
  413. u32 lo = (tsf & 0x00000000FFFFFFFFULL);
  414. u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
  415. b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0);
  416. mmiowb();
  417. b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH,
  418. hi);
  419. mmiowb();
  420. b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW,
  421. lo);
  422. } else {
  423. u16 v0 = (tsf & 0x000000000000FFFFULL);
  424. u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
  425. u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
  426. u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
  427. b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0);
  428. mmiowb();
  429. b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3);
  430. mmiowb();
  431. b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2);
  432. mmiowb();
  433. b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1);
  434. mmiowb();
  435. b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
  436. }
  437. }
  438. void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf)
  439. {
  440. b43legacy_time_lock(dev);
  441. b43legacy_tsf_write_locked(dev, tsf);
  442. b43legacy_time_unlock(dev);
  443. }
  444. static
  445. void b43legacy_macfilter_set(struct b43legacy_wldev *dev,
  446. u16 offset, const u8 *mac)
  447. {
  448. static const u8 zero_addr[ETH_ALEN] = { 0 };
  449. u16 data;
  450. if (!mac)
  451. mac = zero_addr;
  452. offset |= 0x0020;
  453. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset);
  454. data = mac[0];
  455. data |= mac[1] << 8;
  456. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
  457. data = mac[2];
  458. data |= mac[3] << 8;
  459. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
  460. data = mac[4];
  461. data |= mac[5] << 8;
  462. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
  463. }
  464. static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev)
  465. {
  466. static const u8 zero_addr[ETH_ALEN] = { 0 };
  467. const u8 *mac = dev->wl->mac_addr;
  468. const u8 *bssid = dev->wl->bssid;
  469. u8 mac_bssid[ETH_ALEN * 2];
  470. int i;
  471. u32 tmp;
  472. if (!bssid)
  473. bssid = zero_addr;
  474. if (!mac)
  475. mac = zero_addr;
  476. b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid);
  477. memcpy(mac_bssid, mac, ETH_ALEN);
  478. memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
  479. /* Write our MAC address and BSSID to template ram */
  480. for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
  481. tmp = (u32)(mac_bssid[i + 0]);
  482. tmp |= (u32)(mac_bssid[i + 1]) << 8;
  483. tmp |= (u32)(mac_bssid[i + 2]) << 16;
  484. tmp |= (u32)(mac_bssid[i + 3]) << 24;
  485. b43legacy_ram_write(dev, 0x20 + i, tmp);
  486. b43legacy_ram_write(dev, 0x78 + i, tmp);
  487. b43legacy_ram_write(dev, 0x478 + i, tmp);
  488. }
  489. }
  490. static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev)
  491. {
  492. b43legacy_write_mac_bssid_templates(dev);
  493. b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF,
  494. dev->wl->mac_addr);
  495. }
  496. static void b43legacy_set_slot_time(struct b43legacy_wldev *dev,
  497. u16 slot_time)
  498. {
  499. /* slot_time is in usec. */
  500. if (dev->phy.type != B43legacy_PHYTYPE_G)
  501. return;
  502. b43legacy_write16(dev, 0x684, 510 + slot_time);
  503. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010,
  504. slot_time);
  505. }
  506. static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev)
  507. {
  508. b43legacy_set_slot_time(dev, 9);
  509. dev->short_slot = 1;
  510. }
  511. static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev)
  512. {
  513. b43legacy_set_slot_time(dev, 20);
  514. dev->short_slot = 0;
  515. }
  516. /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
  517. * Returns the _previously_ enabled IRQ mask.
  518. */
  519. static inline u32 b43legacy_interrupt_enable(struct b43legacy_wldev *dev,
  520. u32 mask)
  521. {
  522. u32 old_mask;
  523. old_mask = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
  524. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, old_mask |
  525. mask);
  526. return old_mask;
  527. }
  528. /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
  529. * Returns the _previously_ enabled IRQ mask.
  530. */
  531. static inline u32 b43legacy_interrupt_disable(struct b43legacy_wldev *dev,
  532. u32 mask)
  533. {
  534. u32 old_mask;
  535. old_mask = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
  536. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
  537. return old_mask;
  538. }
  539. /* Synchronize IRQ top- and bottom-half.
  540. * IRQs must be masked before calling this.
  541. * This must not be called with the irq_lock held.
  542. */
  543. static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev)
  544. {
  545. synchronize_irq(dev->dev->irq);
  546. tasklet_kill(&dev->isr_tasklet);
  547. }
  548. /* DummyTransmission function, as documented on
  549. * http://bcm-specs.sipsolutions.net/DummyTransmission
  550. */
  551. void b43legacy_dummy_transmission(struct b43legacy_wldev *dev)
  552. {
  553. struct b43legacy_phy *phy = &dev->phy;
  554. unsigned int i;
  555. unsigned int max_loop;
  556. u16 value;
  557. u32 buffer[5] = {
  558. 0x00000000,
  559. 0x00D40000,
  560. 0x00000000,
  561. 0x01000000,
  562. 0x00000000,
  563. };
  564. switch (phy->type) {
  565. case B43legacy_PHYTYPE_B:
  566. case B43legacy_PHYTYPE_G:
  567. max_loop = 0xFA;
  568. buffer[0] = 0x000B846E;
  569. break;
  570. default:
  571. B43legacy_BUG_ON(1);
  572. return;
  573. }
  574. for (i = 0; i < 5; i++)
  575. b43legacy_ram_write(dev, i * 4, buffer[i]);
  576. /* dummy read follows */
  577. b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
  578. b43legacy_write16(dev, 0x0568, 0x0000);
  579. b43legacy_write16(dev, 0x07C0, 0x0000);
  580. b43legacy_write16(dev, 0x050C, 0x0000);
  581. b43legacy_write16(dev, 0x0508, 0x0000);
  582. b43legacy_write16(dev, 0x050A, 0x0000);
  583. b43legacy_write16(dev, 0x054C, 0x0000);
  584. b43legacy_write16(dev, 0x056A, 0x0014);
  585. b43legacy_write16(dev, 0x0568, 0x0826);
  586. b43legacy_write16(dev, 0x0500, 0x0000);
  587. b43legacy_write16(dev, 0x0502, 0x0030);
  588. if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
  589. b43legacy_radio_write16(dev, 0x0051, 0x0017);
  590. for (i = 0x00; i < max_loop; i++) {
  591. value = b43legacy_read16(dev, 0x050E);
  592. if (value & 0x0080)
  593. break;
  594. udelay(10);
  595. }
  596. for (i = 0x00; i < 0x0A; i++) {
  597. value = b43legacy_read16(dev, 0x050E);
  598. if (value & 0x0400)
  599. break;
  600. udelay(10);
  601. }
  602. for (i = 0x00; i < 0x0A; i++) {
  603. value = b43legacy_read16(dev, 0x0690);
  604. if (!(value & 0x0100))
  605. break;
  606. udelay(10);
  607. }
  608. if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
  609. b43legacy_radio_write16(dev, 0x0051, 0x0037);
  610. }
  611. /* Turn the Analog ON/OFF */
  612. static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on)
  613. {
  614. b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4);
  615. }
  616. void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags)
  617. {
  618. u32 tmslow;
  619. u32 macctl;
  620. flags |= B43legacy_TMSLOW_PHYCLKEN;
  621. flags |= B43legacy_TMSLOW_PHYRESET;
  622. ssb_device_enable(dev->dev, flags);
  623. msleep(2); /* Wait for the PLL to turn on. */
  624. /* Now take the PHY out of Reset again */
  625. tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
  626. tmslow |= SSB_TMSLOW_FGC;
  627. tmslow &= ~B43legacy_TMSLOW_PHYRESET;
  628. ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
  629. ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
  630. msleep(1);
  631. tmslow &= ~SSB_TMSLOW_FGC;
  632. ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
  633. ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
  634. msleep(1);
  635. /* Turn Analog ON */
  636. b43legacy_switch_analog(dev, 1);
  637. macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  638. macctl &= ~B43legacy_MACCTL_GMODE;
  639. if (flags & B43legacy_TMSLOW_GMODE) {
  640. macctl |= B43legacy_MACCTL_GMODE;
  641. dev->phy.gmode = 1;
  642. } else
  643. dev->phy.gmode = 0;
  644. macctl |= B43legacy_MACCTL_IHR_ENABLED;
  645. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
  646. }
  647. static void handle_irq_transmit_status(struct b43legacy_wldev *dev)
  648. {
  649. u32 v0;
  650. u32 v1;
  651. u16 tmp;
  652. struct b43legacy_txstatus stat;
  653. while (1) {
  654. v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
  655. if (!(v0 & 0x00000001))
  656. break;
  657. v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
  658. stat.cookie = (v0 >> 16);
  659. stat.seq = (v1 & 0x0000FFFF);
  660. stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
  661. tmp = (v0 & 0x0000FFFF);
  662. stat.frame_count = ((tmp & 0xF000) >> 12);
  663. stat.rts_count = ((tmp & 0x0F00) >> 8);
  664. stat.supp_reason = ((tmp & 0x001C) >> 2);
  665. stat.pm_indicated = !!(tmp & 0x0080);
  666. stat.intermediate = !!(tmp & 0x0040);
  667. stat.for_ampdu = !!(tmp & 0x0020);
  668. stat.acked = !!(tmp & 0x0002);
  669. b43legacy_handle_txstatus(dev, &stat);
  670. }
  671. }
  672. static void drain_txstatus_queue(struct b43legacy_wldev *dev)
  673. {
  674. u32 dummy;
  675. if (dev->dev->id.revision < 5)
  676. return;
  677. /* Read all entries from the microcode TXstatus FIFO
  678. * and throw them away.
  679. */
  680. while (1) {
  681. dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
  682. if (!(dummy & 0x00000001))
  683. break;
  684. dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
  685. }
  686. }
  687. static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev)
  688. {
  689. u32 val = 0;
  690. val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A);
  691. val <<= 16;
  692. val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408);
  693. return val;
  694. }
  695. static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi)
  696. {
  697. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408,
  698. (jssi & 0x0000FFFF));
  699. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A,
  700. (jssi & 0xFFFF0000) >> 16);
  701. }
  702. static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev)
  703. {
  704. b43legacy_jssi_write(dev, 0x7F7F7F7F);
  705. b43legacy_write32(dev, B43legacy_MMIO_STATUS2_BITFIELD,
  706. b43legacy_read32(dev,
  707. B43legacy_MMIO_STATUS2_BITFIELD)
  708. | (1 << 4));
  709. B43legacy_WARN_ON(dev->noisecalc.channel_at_start !=
  710. dev->phy.channel);
  711. }
  712. static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev)
  713. {
  714. /* Top half of Link Quality calculation. */
  715. if (dev->noisecalc.calculation_running)
  716. return;
  717. dev->noisecalc.channel_at_start = dev->phy.channel;
  718. dev->noisecalc.calculation_running = 1;
  719. dev->noisecalc.nr_samples = 0;
  720. b43legacy_generate_noise_sample(dev);
  721. }
  722. static void handle_irq_noise(struct b43legacy_wldev *dev)
  723. {
  724. struct b43legacy_phy *phy = &dev->phy;
  725. u16 tmp;
  726. u8 noise[4];
  727. u8 i;
  728. u8 j;
  729. s32 average;
  730. /* Bottom half of Link Quality calculation. */
  731. B43legacy_WARN_ON(!dev->noisecalc.calculation_running);
  732. if (dev->noisecalc.channel_at_start != phy->channel)
  733. goto drop_calculation;
  734. *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev));
  735. if (noise[0] == 0x7F || noise[1] == 0x7F ||
  736. noise[2] == 0x7F || noise[3] == 0x7F)
  737. goto generate_new;
  738. /* Get the noise samples. */
  739. B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
  740. i = dev->noisecalc.nr_samples;
  741. noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  742. noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  743. noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  744. noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  745. dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
  746. dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
  747. dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
  748. dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
  749. dev->noisecalc.nr_samples++;
  750. if (dev->noisecalc.nr_samples == 8) {
  751. /* Calculate the Link Quality by the noise samples. */
  752. average = 0;
  753. for (i = 0; i < 8; i++) {
  754. for (j = 0; j < 4; j++)
  755. average += dev->noisecalc.samples[i][j];
  756. }
  757. average /= (8 * 4);
  758. average *= 125;
  759. average += 64;
  760. average /= 128;
  761. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  762. 0x40C);
  763. tmp = (tmp / 128) & 0x1F;
  764. if (tmp >= 8)
  765. average += 2;
  766. else
  767. average -= 25;
  768. if (tmp == 8)
  769. average -= 72;
  770. else
  771. average -= 48;
  772. dev->stats.link_noise = average;
  773. drop_calculation:
  774. dev->noisecalc.calculation_running = 0;
  775. return;
  776. }
  777. generate_new:
  778. b43legacy_generate_noise_sample(dev);
  779. }
  780. static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev)
  781. {
  782. if (b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
  783. /* TODO: PS TBTT */
  784. } else {
  785. if (1/*FIXME: the last PSpoll frame was sent successfully */)
  786. b43legacy_power_saving_ctl_bits(dev, -1, -1);
  787. }
  788. dev->reg124_set_0x4 = 0;
  789. if (b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
  790. dev->reg124_set_0x4 = 1;
  791. }
  792. static void handle_irq_atim_end(struct b43legacy_wldev *dev)
  793. {
  794. if (!dev->reg124_set_0x4) /*FIXME rename this variable*/
  795. return;
  796. b43legacy_write32(dev, B43legacy_MMIO_STATUS2_BITFIELD,
  797. b43legacy_read32(dev, B43legacy_MMIO_STATUS2_BITFIELD)
  798. | 0x4);
  799. }
  800. static void handle_irq_pmq(struct b43legacy_wldev *dev)
  801. {
  802. u32 tmp;
  803. /* TODO: AP mode. */
  804. while (1) {
  805. tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS);
  806. if (!(tmp & 0x00000008))
  807. break;
  808. }
  809. /* 16bit write is odd, but correct. */
  810. b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002);
  811. }
  812. static void b43legacy_write_template_common(struct b43legacy_wldev *dev,
  813. const u8 *data, u16 size,
  814. u16 ram_offset,
  815. u16 shm_size_offset, u8 rate)
  816. {
  817. u32 i;
  818. u32 tmp;
  819. struct b43legacy_plcp_hdr4 plcp;
  820. plcp.data = 0;
  821. b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
  822. b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
  823. ram_offset += sizeof(u32);
  824. /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
  825. * So leave the first two bytes of the next write blank.
  826. */
  827. tmp = (u32)(data[0]) << 16;
  828. tmp |= (u32)(data[1]) << 24;
  829. b43legacy_ram_write(dev, ram_offset, tmp);
  830. ram_offset += sizeof(u32);
  831. for (i = 2; i < size; i += sizeof(u32)) {
  832. tmp = (u32)(data[i + 0]);
  833. if (i + 1 < size)
  834. tmp |= (u32)(data[i + 1]) << 8;
  835. if (i + 2 < size)
  836. tmp |= (u32)(data[i + 2]) << 16;
  837. if (i + 3 < size)
  838. tmp |= (u32)(data[i + 3]) << 24;
  839. b43legacy_ram_write(dev, ram_offset + i - 2, tmp);
  840. }
  841. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset,
  842. size + sizeof(struct b43legacy_plcp_hdr6));
  843. }
  844. static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev,
  845. u16 ram_offset,
  846. u16 shm_size_offset, u8 rate)
  847. {
  848. int len;
  849. const u8 *data;
  850. B43legacy_WARN_ON(!dev->cached_beacon);
  851. len = min((size_t)dev->cached_beacon->len,
  852. 0x200 - sizeof(struct b43legacy_plcp_hdr6));
  853. data = (const u8 *)(dev->cached_beacon->data);
  854. b43legacy_write_template_common(dev, data,
  855. len, ram_offset,
  856. shm_size_offset, rate);
  857. }
  858. static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev,
  859. u16 shm_offset, u16 size,
  860. u8 rate)
  861. {
  862. struct b43legacy_plcp_hdr4 plcp;
  863. u32 tmp;
  864. __le16 dur;
  865. plcp.data = 0;
  866. b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
  867. dur = ieee80211_generic_frame_duration(dev->wl->hw,
  868. dev->wl->if_id,
  869. size,
  870. B43legacy_RATE_TO_100KBPS(rate));
  871. /* Write PLCP in two parts and timing for packet transfer */
  872. tmp = le32_to_cpu(plcp.data);
  873. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset,
  874. tmp & 0xFFFF);
  875. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2,
  876. tmp >> 16);
  877. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6,
  878. le16_to_cpu(dur));
  879. }
  880. /* Instead of using custom probe response template, this function
  881. * just patches custom beacon template by:
  882. * 1) Changing packet type
  883. * 2) Patching duration field
  884. * 3) Stripping TIM
  885. */
  886. static u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev,
  887. u16 *dest_size, u8 rate)
  888. {
  889. const u8 *src_data;
  890. u8 *dest_data;
  891. u16 src_size;
  892. u16 elem_size;
  893. u16 src_pos;
  894. u16 dest_pos;
  895. __le16 dur;
  896. struct ieee80211_hdr *hdr;
  897. B43legacy_WARN_ON(!dev->cached_beacon);
  898. src_size = dev->cached_beacon->len;
  899. src_data = (const u8 *)dev->cached_beacon->data;
  900. if (unlikely(src_size < 0x24)) {
  901. b43legacydbg(dev->wl, "b43legacy_generate_probe_resp: "
  902. "invalid beacon\n");
  903. return NULL;
  904. }
  905. dest_data = kmalloc(src_size, GFP_ATOMIC);
  906. if (unlikely(!dest_data))
  907. return NULL;
  908. /* 0x24 is offset of first variable-len Information-Element
  909. * in beacon frame.
  910. */
  911. memcpy(dest_data, src_data, 0x24);
  912. src_pos = 0x24;
  913. dest_pos = 0x24;
  914. for (; src_pos < src_size - 2; src_pos += elem_size) {
  915. elem_size = src_data[src_pos + 1] + 2;
  916. if (src_data[src_pos] != 0x05) { /* TIM */
  917. memcpy(dest_data + dest_pos, src_data + src_pos,
  918. elem_size);
  919. dest_pos += elem_size;
  920. }
  921. }
  922. *dest_size = dest_pos;
  923. hdr = (struct ieee80211_hdr *)dest_data;
  924. /* Set the frame control. */
  925. hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
  926. IEEE80211_STYPE_PROBE_RESP);
  927. dur = ieee80211_generic_frame_duration(dev->wl->hw,
  928. dev->wl->if_id,
  929. *dest_size,
  930. B43legacy_RATE_TO_100KBPS(rate));
  931. hdr->duration_id = dur;
  932. return dest_data;
  933. }
  934. static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
  935. u16 ram_offset,
  936. u16 shm_size_offset, u8 rate)
  937. {
  938. u8 *probe_resp_data;
  939. u16 size;
  940. B43legacy_WARN_ON(!dev->cached_beacon);
  941. size = dev->cached_beacon->len;
  942. probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate);
  943. if (unlikely(!probe_resp_data))
  944. return;
  945. /* Looks like PLCP headers plus packet timings are stored for
  946. * all possible basic rates
  947. */
  948. b43legacy_write_probe_resp_plcp(dev, 0x31A, size,
  949. B43legacy_CCK_RATE_1MB);
  950. b43legacy_write_probe_resp_plcp(dev, 0x32C, size,
  951. B43legacy_CCK_RATE_2MB);
  952. b43legacy_write_probe_resp_plcp(dev, 0x33E, size,
  953. B43legacy_CCK_RATE_5MB);
  954. b43legacy_write_probe_resp_plcp(dev, 0x350, size,
  955. B43legacy_CCK_RATE_11MB);
  956. size = min((size_t)size,
  957. 0x200 - sizeof(struct b43legacy_plcp_hdr6));
  958. b43legacy_write_template_common(dev, probe_resp_data,
  959. size, ram_offset,
  960. shm_size_offset, rate);
  961. kfree(probe_resp_data);
  962. }
  963. static int b43legacy_refresh_cached_beacon(struct b43legacy_wldev *dev,
  964. struct sk_buff *beacon)
  965. {
  966. if (dev->cached_beacon)
  967. kfree_skb(dev->cached_beacon);
  968. dev->cached_beacon = beacon;
  969. return 0;
  970. }
  971. static void b43legacy_update_templates(struct b43legacy_wldev *dev)
  972. {
  973. u32 status;
  974. B43legacy_WARN_ON(!dev->cached_beacon);
  975. b43legacy_write_beacon_template(dev, 0x68, 0x18,
  976. B43legacy_CCK_RATE_1MB);
  977. b43legacy_write_beacon_template(dev, 0x468, 0x1A,
  978. B43legacy_CCK_RATE_1MB);
  979. b43legacy_write_probe_resp_template(dev, 0x268, 0x4A,
  980. B43legacy_CCK_RATE_11MB);
  981. status = b43legacy_read32(dev, B43legacy_MMIO_STATUS2_BITFIELD);
  982. status |= 0x03;
  983. b43legacy_write32(dev, B43legacy_MMIO_STATUS2_BITFIELD, status);
  984. }
  985. static void b43legacy_refresh_templates(struct b43legacy_wldev *dev,
  986. struct sk_buff *beacon)
  987. {
  988. int err;
  989. err = b43legacy_refresh_cached_beacon(dev, beacon);
  990. if (unlikely(err))
  991. return;
  992. b43legacy_update_templates(dev);
  993. }
  994. static void b43legacy_set_ssid(struct b43legacy_wldev *dev,
  995. const u8 *ssid, u8 ssid_len)
  996. {
  997. u32 tmp;
  998. u16 i;
  999. u16 len;
  1000. len = min((u16)ssid_len, (u16)0x100);
  1001. for (i = 0; i < len; i += sizeof(u32)) {
  1002. tmp = (u32)(ssid[i + 0]);
  1003. if (i + 1 < len)
  1004. tmp |= (u32)(ssid[i + 1]) << 8;
  1005. if (i + 2 < len)
  1006. tmp |= (u32)(ssid[i + 2]) << 16;
  1007. if (i + 3 < len)
  1008. tmp |= (u32)(ssid[i + 3]) << 24;
  1009. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED,
  1010. 0x380 + i, tmp);
  1011. }
  1012. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1013. 0x48, len);
  1014. }
  1015. static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev,
  1016. u16 beacon_int)
  1017. {
  1018. b43legacy_time_lock(dev);
  1019. if (dev->dev->id.revision >= 3)
  1020. b43legacy_write32(dev, 0x188, (beacon_int << 16));
  1021. else {
  1022. b43legacy_write16(dev, 0x606, (beacon_int >> 6));
  1023. b43legacy_write16(dev, 0x610, beacon_int);
  1024. }
  1025. b43legacy_time_unlock(dev);
  1026. }
  1027. static void handle_irq_beacon(struct b43legacy_wldev *dev)
  1028. {
  1029. u32 status;
  1030. if (!b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
  1031. return;
  1032. dev->irq_savedstate &= ~B43legacy_IRQ_BEACON;
  1033. status = b43legacy_read32(dev, B43legacy_MMIO_STATUS2_BITFIELD);
  1034. if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
  1035. /* ACK beacon IRQ. */
  1036. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
  1037. B43legacy_IRQ_BEACON);
  1038. dev->irq_savedstate |= B43legacy_IRQ_BEACON;
  1039. if (dev->cached_beacon)
  1040. kfree_skb(dev->cached_beacon);
  1041. dev->cached_beacon = NULL;
  1042. return;
  1043. }
  1044. if (!(status & 0x1)) {
  1045. b43legacy_write_beacon_template(dev, 0x68, 0x18,
  1046. B43legacy_CCK_RATE_1MB);
  1047. status |= 0x1;
  1048. b43legacy_write32(dev, B43legacy_MMIO_STATUS2_BITFIELD,
  1049. status);
  1050. }
  1051. if (!(status & 0x2)) {
  1052. b43legacy_write_beacon_template(dev, 0x468, 0x1A,
  1053. B43legacy_CCK_RATE_1MB);
  1054. status |= 0x2;
  1055. b43legacy_write32(dev, B43legacy_MMIO_STATUS2_BITFIELD,
  1056. status);
  1057. }
  1058. }
  1059. static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
  1060. {
  1061. }
  1062. /* Interrupt handler bottom-half */
  1063. static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
  1064. {
  1065. u32 reason;
  1066. u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
  1067. u32 merged_dma_reason = 0;
  1068. int i;
  1069. int activity = 0;
  1070. unsigned long flags;
  1071. spin_lock_irqsave(&dev->wl->irq_lock, flags);
  1072. B43legacy_WARN_ON(b43legacy_status(dev) <
  1073. B43legacy_STAT_INITIALIZED);
  1074. reason = dev->irq_reason;
  1075. for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
  1076. dma_reason[i] = dev->dma_reason[i];
  1077. merged_dma_reason |= dma_reason[i];
  1078. }
  1079. if (unlikely(reason & B43legacy_IRQ_MAC_TXERR))
  1080. b43legacyerr(dev->wl, "MAC transmission error\n");
  1081. if (unlikely(reason & B43legacy_IRQ_PHY_TXERR))
  1082. b43legacyerr(dev->wl, "PHY transmission error\n");
  1083. if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK |
  1084. B43legacy_DMAIRQ_NONFATALMASK))) {
  1085. if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) {
  1086. b43legacyerr(dev->wl, "Fatal DMA error: "
  1087. "0x%08X, 0x%08X, 0x%08X, "
  1088. "0x%08X, 0x%08X, 0x%08X\n",
  1089. dma_reason[0], dma_reason[1],
  1090. dma_reason[2], dma_reason[3],
  1091. dma_reason[4], dma_reason[5]);
  1092. b43legacy_controller_restart(dev, "DMA error");
  1093. mmiowb();
  1094. spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
  1095. return;
  1096. }
  1097. if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK)
  1098. b43legacyerr(dev->wl, "DMA error: "
  1099. "0x%08X, 0x%08X, 0x%08X, "
  1100. "0x%08X, 0x%08X, 0x%08X\n",
  1101. dma_reason[0], dma_reason[1],
  1102. dma_reason[2], dma_reason[3],
  1103. dma_reason[4], dma_reason[5]);
  1104. }
  1105. if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG))
  1106. handle_irq_ucode_debug(dev);
  1107. if (reason & B43legacy_IRQ_TBTT_INDI)
  1108. handle_irq_tbtt_indication(dev);
  1109. if (reason & B43legacy_IRQ_ATIM_END)
  1110. handle_irq_atim_end(dev);
  1111. if (reason & B43legacy_IRQ_BEACON)
  1112. handle_irq_beacon(dev);
  1113. if (reason & B43legacy_IRQ_PMQ)
  1114. handle_irq_pmq(dev);
  1115. if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK)
  1116. ;/*TODO*/
  1117. if (reason & B43legacy_IRQ_NOISESAMPLE_OK)
  1118. handle_irq_noise(dev);
  1119. /* Check the DMA reason registers for received data. */
  1120. if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) {
  1121. if (b43legacy_using_pio(dev))
  1122. b43legacy_pio_rx(dev->pio.queue0);
  1123. else
  1124. b43legacy_dma_rx(dev->dma.rx_ring0);
  1125. /* We intentionally don't set "activity" to 1, here. */
  1126. }
  1127. B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE);
  1128. B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE);
  1129. if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) {
  1130. if (b43legacy_using_pio(dev))
  1131. b43legacy_pio_rx(dev->pio.queue3);
  1132. else
  1133. b43legacy_dma_rx(dev->dma.rx_ring3);
  1134. activity = 1;
  1135. }
  1136. B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE);
  1137. B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE);
  1138. if (reason & B43legacy_IRQ_TX_OK) {
  1139. handle_irq_transmit_status(dev);
  1140. activity = 1;
  1141. /* TODO: In AP mode, this also causes sending of powersave
  1142. responses. */
  1143. }
  1144. if (!modparam_noleds)
  1145. b43legacy_leds_update(dev, activity);
  1146. b43legacy_interrupt_enable(dev, dev->irq_savedstate);
  1147. mmiowb();
  1148. spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
  1149. }
  1150. static void pio_irq_workaround(struct b43legacy_wldev *dev,
  1151. u16 base, int queueidx)
  1152. {
  1153. u16 rxctl;
  1154. rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL);
  1155. if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE)
  1156. dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE;
  1157. else
  1158. dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE;
  1159. }
  1160. static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason)
  1161. {
  1162. if (b43legacy_using_pio(dev) &&
  1163. (dev->dev->id.revision < 3) &&
  1164. (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) {
  1165. /* Apply a PIO specific workaround to the dma_reasons */
  1166. pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0);
  1167. pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1);
  1168. pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2);
  1169. pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3);
  1170. }
  1171. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason);
  1172. b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON,
  1173. dev->dma_reason[0]);
  1174. b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON,
  1175. dev->dma_reason[1]);
  1176. b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON,
  1177. dev->dma_reason[2]);
  1178. b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON,
  1179. dev->dma_reason[3]);
  1180. b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON,
  1181. dev->dma_reason[4]);
  1182. b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON,
  1183. dev->dma_reason[5]);
  1184. }
  1185. /* Interrupt handler top-half */
  1186. static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id)
  1187. {
  1188. irqreturn_t ret = IRQ_NONE;
  1189. struct b43legacy_wldev *dev = dev_id;
  1190. u32 reason;
  1191. if (!dev)
  1192. return IRQ_NONE;
  1193. spin_lock(&dev->wl->irq_lock);
  1194. if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
  1195. goto out;
  1196. reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1197. if (reason == 0xffffffff) /* shared IRQ */
  1198. goto out;
  1199. ret = IRQ_HANDLED;
  1200. reason &= b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
  1201. if (!reason)
  1202. goto out;
  1203. dev->dma_reason[0] = b43legacy_read32(dev,
  1204. B43legacy_MMIO_DMA0_REASON)
  1205. & 0x0001DC00;
  1206. dev->dma_reason[1] = b43legacy_read32(dev,
  1207. B43legacy_MMIO_DMA1_REASON)
  1208. & 0x0000DC00;
  1209. dev->dma_reason[2] = b43legacy_read32(dev,
  1210. B43legacy_MMIO_DMA2_REASON)
  1211. & 0x0000DC00;
  1212. dev->dma_reason[3] = b43legacy_read32(dev,
  1213. B43legacy_MMIO_DMA3_REASON)
  1214. & 0x0001DC00;
  1215. dev->dma_reason[4] = b43legacy_read32(dev,
  1216. B43legacy_MMIO_DMA4_REASON)
  1217. & 0x0000DC00;
  1218. dev->dma_reason[5] = b43legacy_read32(dev,
  1219. B43legacy_MMIO_DMA5_REASON)
  1220. & 0x0000DC00;
  1221. b43legacy_interrupt_ack(dev, reason);
  1222. /* disable all IRQs. They are enabled again in the bottom half. */
  1223. dev->irq_savedstate = b43legacy_interrupt_disable(dev,
  1224. B43legacy_IRQ_ALL);
  1225. /* save the reason code and call our bottom half. */
  1226. dev->irq_reason = reason;
  1227. tasklet_schedule(&dev->isr_tasklet);
  1228. out:
  1229. mmiowb();
  1230. spin_unlock(&dev->wl->irq_lock);
  1231. return ret;
  1232. }
  1233. static void b43legacy_release_firmware(struct b43legacy_wldev *dev)
  1234. {
  1235. release_firmware(dev->fw.ucode);
  1236. dev->fw.ucode = NULL;
  1237. release_firmware(dev->fw.pcm);
  1238. dev->fw.pcm = NULL;
  1239. release_firmware(dev->fw.initvals);
  1240. dev->fw.initvals = NULL;
  1241. release_firmware(dev->fw.initvals_band);
  1242. dev->fw.initvals_band = NULL;
  1243. }
  1244. static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
  1245. {
  1246. b43legacyerr(wl, "You must go to http://linuxwireless.org/en/users/"
  1247. "Drivers/b43#devicefirmware "
  1248. "and download the correct firmware (version 3).\n");
  1249. }
  1250. static int do_request_fw(struct b43legacy_wldev *dev,
  1251. const char *name,
  1252. const struct firmware **fw)
  1253. {
  1254. char path[sizeof(modparam_fwpostfix) + 32];
  1255. struct b43legacy_fw_header *hdr;
  1256. u32 size;
  1257. int err;
  1258. if (!name)
  1259. return 0;
  1260. snprintf(path, ARRAY_SIZE(path),
  1261. "b43legacy%s/%s.fw",
  1262. modparam_fwpostfix, name);
  1263. err = request_firmware(fw, path, dev->dev->dev);
  1264. if (err) {
  1265. b43legacyerr(dev->wl, "Firmware file \"%s\" not found "
  1266. "or load failed.\n", path);
  1267. return err;
  1268. }
  1269. if ((*fw)->size < sizeof(struct b43legacy_fw_header))
  1270. goto err_format;
  1271. hdr = (struct b43legacy_fw_header *)((*fw)->data);
  1272. switch (hdr->type) {
  1273. case B43legacy_FW_TYPE_UCODE:
  1274. case B43legacy_FW_TYPE_PCM:
  1275. size = be32_to_cpu(hdr->size);
  1276. if (size != (*fw)->size - sizeof(struct b43legacy_fw_header))
  1277. goto err_format;
  1278. /* fallthrough */
  1279. case B43legacy_FW_TYPE_IV:
  1280. if (hdr->ver != 1)
  1281. goto err_format;
  1282. break;
  1283. default:
  1284. goto err_format;
  1285. }
  1286. return err;
  1287. err_format:
  1288. b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path);
  1289. return -EPROTO;
  1290. }
  1291. static int b43legacy_request_firmware(struct b43legacy_wldev *dev)
  1292. {
  1293. struct b43legacy_firmware *fw = &dev->fw;
  1294. const u8 rev = dev->dev->id.revision;
  1295. const char *filename;
  1296. u32 tmshigh;
  1297. int err;
  1298. tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
  1299. if (!fw->ucode) {
  1300. if (rev == 2)
  1301. filename = "ucode2";
  1302. else if (rev == 4)
  1303. filename = "ucode4";
  1304. else
  1305. filename = "ucode5";
  1306. err = do_request_fw(dev, filename, &fw->ucode);
  1307. if (err)
  1308. goto err_load;
  1309. }
  1310. if (!fw->pcm) {
  1311. if (rev < 5)
  1312. filename = "pcm4";
  1313. else
  1314. filename = "pcm5";
  1315. err = do_request_fw(dev, filename, &fw->pcm);
  1316. if (err)
  1317. goto err_load;
  1318. }
  1319. if (!fw->initvals) {
  1320. switch (dev->phy.type) {
  1321. case B43legacy_PHYTYPE_G:
  1322. if ((rev >= 5) && (rev <= 10))
  1323. filename = "b0g0initvals5";
  1324. else if (rev == 2 || rev == 4)
  1325. filename = "b0g0initvals2";
  1326. else
  1327. goto err_no_initvals;
  1328. break;
  1329. default:
  1330. goto err_no_initvals;
  1331. }
  1332. err = do_request_fw(dev, filename, &fw->initvals);
  1333. if (err)
  1334. goto err_load;
  1335. }
  1336. if (!fw->initvals_band) {
  1337. switch (dev->phy.type) {
  1338. case B43legacy_PHYTYPE_G:
  1339. if ((rev >= 5) && (rev <= 10))
  1340. filename = "b0g0bsinitvals5";
  1341. else if (rev >= 11)
  1342. filename = NULL;
  1343. else if (rev == 2 || rev == 4)
  1344. filename = NULL;
  1345. else
  1346. goto err_no_initvals;
  1347. break;
  1348. default:
  1349. goto err_no_initvals;
  1350. }
  1351. err = do_request_fw(dev, filename, &fw->initvals_band);
  1352. if (err)
  1353. goto err_load;
  1354. }
  1355. return 0;
  1356. err_load:
  1357. b43legacy_print_fw_helptext(dev->wl);
  1358. goto error;
  1359. err_no_initvals:
  1360. err = -ENODEV;
  1361. b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, "
  1362. "core rev %u\n", dev->phy.type, rev);
  1363. goto error;
  1364. error:
  1365. b43legacy_release_firmware(dev);
  1366. return err;
  1367. }
  1368. static int b43legacy_upload_microcode(struct b43legacy_wldev *dev)
  1369. {
  1370. const size_t hdr_len = sizeof(struct b43legacy_fw_header);
  1371. const __be32 *data;
  1372. unsigned int i;
  1373. unsigned int len;
  1374. u16 fwrev;
  1375. u16 fwpatch;
  1376. u16 fwdate;
  1377. u16 fwtime;
  1378. u32 tmp;
  1379. int err = 0;
  1380. /* Upload Microcode. */
  1381. data = (__be32 *) (dev->fw.ucode->data + hdr_len);
  1382. len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
  1383. b43legacy_shm_control_word(dev,
  1384. B43legacy_SHM_UCODE |
  1385. B43legacy_SHM_AUTOINC_W,
  1386. 0x0000);
  1387. for (i = 0; i < len; i++) {
  1388. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
  1389. be32_to_cpu(data[i]));
  1390. udelay(10);
  1391. }
  1392. if (dev->fw.pcm) {
  1393. /* Upload PCM data. */
  1394. data = (__be32 *) (dev->fw.pcm->data + hdr_len);
  1395. len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
  1396. b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA);
  1397. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000);
  1398. /* No need for autoinc bit in SHM_HW */
  1399. b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB);
  1400. for (i = 0; i < len; i++) {
  1401. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
  1402. be32_to_cpu(data[i]));
  1403. udelay(10);
  1404. }
  1405. }
  1406. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
  1407. B43legacy_IRQ_ALL);
  1408. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, 0x00020402);
  1409. /* Wait for the microcode to load and respond */
  1410. i = 0;
  1411. while (1) {
  1412. tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1413. if (tmp == B43legacy_IRQ_MAC_SUSPENDED)
  1414. break;
  1415. i++;
  1416. if (i >= B43legacy_IRQWAIT_MAX_RETRIES) {
  1417. b43legacyerr(dev->wl, "Microcode not responding\n");
  1418. b43legacy_print_fw_helptext(dev->wl);
  1419. err = -ENODEV;
  1420. goto out;
  1421. }
  1422. udelay(10);
  1423. }
  1424. /* dummy read follows */
  1425. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1426. /* Get and check the revisions. */
  1427. fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1428. B43legacy_SHM_SH_UCODEREV);
  1429. fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1430. B43legacy_SHM_SH_UCODEPATCH);
  1431. fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1432. B43legacy_SHM_SH_UCODEDATE);
  1433. fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1434. B43legacy_SHM_SH_UCODETIME);
  1435. if (fwrev > 0x128) {
  1436. b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE."
  1437. " Only firmware from binary drivers version 3.x"
  1438. " is supported. You must change your firmware"
  1439. " files.\n");
  1440. b43legacy_print_fw_helptext(dev->wl);
  1441. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, 0);
  1442. err = -EOPNOTSUPP;
  1443. goto out;
  1444. }
  1445. b43legacydbg(dev->wl, "Loading firmware version 0x%X, patch level %u "
  1446. "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch,
  1447. (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
  1448. (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
  1449. dev->fw.rev = fwrev;
  1450. dev->fw.patch = fwpatch;
  1451. out:
  1452. return err;
  1453. }
  1454. static int b43legacy_write_initvals(struct b43legacy_wldev *dev,
  1455. const struct b43legacy_iv *ivals,
  1456. size_t count,
  1457. size_t array_size)
  1458. {
  1459. const struct b43legacy_iv *iv;
  1460. u16 offset;
  1461. size_t i;
  1462. bool bit32;
  1463. BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6);
  1464. iv = ivals;
  1465. for (i = 0; i < count; i++) {
  1466. if (array_size < sizeof(iv->offset_size))
  1467. goto err_format;
  1468. array_size -= sizeof(iv->offset_size);
  1469. offset = be16_to_cpu(iv->offset_size);
  1470. bit32 = !!(offset & B43legacy_IV_32BIT);
  1471. offset &= B43legacy_IV_OFFSET_MASK;
  1472. if (offset >= 0x1000)
  1473. goto err_format;
  1474. if (bit32) {
  1475. u32 value;
  1476. if (array_size < sizeof(iv->data.d32))
  1477. goto err_format;
  1478. array_size -= sizeof(iv->data.d32);
  1479. value = be32_to_cpu(get_unaligned(&iv->data.d32));
  1480. b43legacy_write32(dev, offset, value);
  1481. iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
  1482. sizeof(__be16) +
  1483. sizeof(__be32));
  1484. } else {
  1485. u16 value;
  1486. if (array_size < sizeof(iv->data.d16))
  1487. goto err_format;
  1488. array_size -= sizeof(iv->data.d16);
  1489. value = be16_to_cpu(iv->data.d16);
  1490. b43legacy_write16(dev, offset, value);
  1491. iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
  1492. sizeof(__be16) +
  1493. sizeof(__be16));
  1494. }
  1495. }
  1496. if (array_size)
  1497. goto err_format;
  1498. return 0;
  1499. err_format:
  1500. b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n");
  1501. b43legacy_print_fw_helptext(dev->wl);
  1502. return -EPROTO;
  1503. }
  1504. static int b43legacy_upload_initvals(struct b43legacy_wldev *dev)
  1505. {
  1506. const size_t hdr_len = sizeof(struct b43legacy_fw_header);
  1507. const struct b43legacy_fw_header *hdr;
  1508. struct b43legacy_firmware *fw = &dev->fw;
  1509. const struct b43legacy_iv *ivals;
  1510. size_t count;
  1511. int err;
  1512. hdr = (const struct b43legacy_fw_header *)(fw->initvals->data);
  1513. ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len);
  1514. count = be32_to_cpu(hdr->size);
  1515. err = b43legacy_write_initvals(dev, ivals, count,
  1516. fw->initvals->size - hdr_len);
  1517. if (err)
  1518. goto out;
  1519. if (fw->initvals_band) {
  1520. hdr = (const struct b43legacy_fw_header *)
  1521. (fw->initvals_band->data);
  1522. ivals = (const struct b43legacy_iv *)(fw->initvals_band->data
  1523. + hdr_len);
  1524. count = be32_to_cpu(hdr->size);
  1525. err = b43legacy_write_initvals(dev, ivals, count,
  1526. fw->initvals_band->size - hdr_len);
  1527. if (err)
  1528. goto out;
  1529. }
  1530. out:
  1531. return err;
  1532. }
  1533. /* Initialize the GPIOs
  1534. * http://bcm-specs.sipsolutions.net/GPIO
  1535. */
  1536. static int b43legacy_gpio_init(struct b43legacy_wldev *dev)
  1537. {
  1538. struct ssb_bus *bus = dev->dev->bus;
  1539. struct ssb_device *gpiodev, *pcidev = NULL;
  1540. u32 mask;
  1541. u32 set;
  1542. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD,
  1543. b43legacy_read32(dev,
  1544. B43legacy_MMIO_STATUS_BITFIELD)
  1545. & 0xFFFF3FFF);
  1546. b43legacy_leds_switch_all(dev, 0);
  1547. b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
  1548. b43legacy_read16(dev,
  1549. B43legacy_MMIO_GPIO_MASK)
  1550. | 0x000F);
  1551. mask = 0x0000001F;
  1552. set = 0x0000000F;
  1553. if (dev->dev->bus->chip_id == 0x4301) {
  1554. mask |= 0x0060;
  1555. set |= 0x0060;
  1556. }
  1557. if (dev->dev->bus->sprom.r1.boardflags_lo & B43legacy_BFL_PACTRL) {
  1558. b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
  1559. b43legacy_read16(dev,
  1560. B43legacy_MMIO_GPIO_MASK)
  1561. | 0x0200);
  1562. mask |= 0x0200;
  1563. set |= 0x0200;
  1564. }
  1565. if (dev->dev->id.revision >= 2)
  1566. mask |= 0x0010; /* FIXME: This is redundant. */
  1567. #ifdef CONFIG_SSB_DRIVER_PCICORE
  1568. pcidev = bus->pcicore.dev;
  1569. #endif
  1570. gpiodev = bus->chipco.dev ? : pcidev;
  1571. if (!gpiodev)
  1572. return 0;
  1573. ssb_write32(gpiodev, B43legacy_GPIO_CONTROL,
  1574. (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
  1575. & mask) | set);
  1576. return 0;
  1577. }
  1578. /* Turn off all GPIO stuff. Call this on module unload, for example. */
  1579. static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev)
  1580. {
  1581. struct ssb_bus *bus = dev->dev->bus;
  1582. struct ssb_device *gpiodev, *pcidev = NULL;
  1583. #ifdef CONFIG_SSB_DRIVER_PCICORE
  1584. pcidev = bus->pcicore.dev;
  1585. #endif
  1586. gpiodev = bus->chipco.dev ? : pcidev;
  1587. if (!gpiodev)
  1588. return;
  1589. ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0);
  1590. }
  1591. /* http://bcm-specs.sipsolutions.net/EnableMac */
  1592. void b43legacy_mac_enable(struct b43legacy_wldev *dev)
  1593. {
  1594. dev->mac_suspended--;
  1595. B43legacy_WARN_ON(dev->mac_suspended < 0);
  1596. if (dev->mac_suspended == 0) {
  1597. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD,
  1598. b43legacy_read32(dev,
  1599. B43legacy_MMIO_STATUS_BITFIELD)
  1600. | B43legacy_SBF_MAC_ENABLED);
  1601. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
  1602. B43legacy_IRQ_MAC_SUSPENDED);
  1603. /* the next two are dummy reads */
  1604. b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
  1605. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1606. b43legacy_power_saving_ctl_bits(dev, -1, -1);
  1607. }
  1608. }
  1609. /* http://bcm-specs.sipsolutions.net/SuspendMAC */
  1610. void b43legacy_mac_suspend(struct b43legacy_wldev *dev)
  1611. {
  1612. int i;
  1613. u32 tmp;
  1614. B43legacy_WARN_ON(dev->mac_suspended < 0);
  1615. if (dev->mac_suspended == 0) {
  1616. b43legacy_power_saving_ctl_bits(dev, -1, 1);
  1617. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD,
  1618. b43legacy_read32(dev,
  1619. B43legacy_MMIO_STATUS_BITFIELD)
  1620. & ~B43legacy_SBF_MAC_ENABLED);
  1621. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1622. for (i = 10000; i; i--) {
  1623. tmp = b43legacy_read32(dev,
  1624. B43legacy_MMIO_GEN_IRQ_REASON);
  1625. if (tmp & B43legacy_IRQ_MAC_SUSPENDED)
  1626. goto out;
  1627. udelay(1);
  1628. }
  1629. b43legacyerr(dev->wl, "MAC suspend failed\n");
  1630. }
  1631. out:
  1632. dev->mac_suspended++;
  1633. }
  1634. static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev)
  1635. {
  1636. struct b43legacy_wl *wl = dev->wl;
  1637. u32 ctl;
  1638. u16 cfp_pretbtt;
  1639. ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1640. /* Reset status to STA infrastructure mode. */
  1641. ctl &= ~B43legacy_MACCTL_AP;
  1642. ctl &= ~B43legacy_MACCTL_KEEP_CTL;
  1643. ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP;
  1644. ctl &= ~B43legacy_MACCTL_KEEP_BAD;
  1645. ctl &= ~B43legacy_MACCTL_PROMISC;
  1646. ctl &= ~B43legacy_MACCTL_BEACPROMISC;
  1647. ctl |= B43legacy_MACCTL_INFRA;
  1648. if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP))
  1649. ctl |= B43legacy_MACCTL_AP;
  1650. else if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
  1651. ctl &= ~B43legacy_MACCTL_INFRA;
  1652. if (wl->filter_flags & FIF_CONTROL)
  1653. ctl |= B43legacy_MACCTL_KEEP_CTL;
  1654. if (wl->filter_flags & FIF_FCSFAIL)
  1655. ctl |= B43legacy_MACCTL_KEEP_BAD;
  1656. if (wl->filter_flags & FIF_PLCPFAIL)
  1657. ctl |= B43legacy_MACCTL_KEEP_BADPLCP;
  1658. if (wl->filter_flags & FIF_PROMISC_IN_BSS)
  1659. ctl |= B43legacy_MACCTL_PROMISC;
  1660. if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
  1661. ctl |= B43legacy_MACCTL_BEACPROMISC;
  1662. /* Workaround: On old hardware the HW-MAC-address-filter
  1663. * doesn't work properly, so always run promisc in filter
  1664. * it in software. */
  1665. if (dev->dev->id.revision <= 4)
  1666. ctl |= B43legacy_MACCTL_PROMISC;
  1667. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl);
  1668. cfp_pretbtt = 2;
  1669. if ((ctl & B43legacy_MACCTL_INFRA) &&
  1670. !(ctl & B43legacy_MACCTL_AP)) {
  1671. if (dev->dev->bus->chip_id == 0x4306 &&
  1672. dev->dev->bus->chip_rev == 3)
  1673. cfp_pretbtt = 100;
  1674. else
  1675. cfp_pretbtt = 50;
  1676. }
  1677. b43legacy_write16(dev, 0x612, cfp_pretbtt);
  1678. }
  1679. static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev,
  1680. u16 rate,
  1681. int is_ofdm)
  1682. {
  1683. u16 offset;
  1684. if (is_ofdm) {
  1685. offset = 0x480;
  1686. offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
  1687. } else {
  1688. offset = 0x4C0;
  1689. offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
  1690. }
  1691. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20,
  1692. b43legacy_shm_read16(dev,
  1693. B43legacy_SHM_SHARED, offset));
  1694. }
  1695. static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev)
  1696. {
  1697. switch (dev->phy.type) {
  1698. case B43legacy_PHYTYPE_G:
  1699. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1);
  1700. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1);
  1701. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1);
  1702. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1);
  1703. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1);
  1704. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1);
  1705. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1);
  1706. /* fallthrough */
  1707. case B43legacy_PHYTYPE_B:
  1708. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0);
  1709. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0);
  1710. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0);
  1711. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0);
  1712. break;
  1713. default:
  1714. B43legacy_BUG_ON(1);
  1715. }
  1716. }
  1717. /* Set the TX-Antenna for management frames sent by firmware. */
  1718. static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev,
  1719. int antenna)
  1720. {
  1721. u16 ant = 0;
  1722. u16 tmp;
  1723. switch (antenna) {
  1724. case B43legacy_ANTENNA0:
  1725. ant |= B43legacy_TX4_PHY_ANT0;
  1726. break;
  1727. case B43legacy_ANTENNA1:
  1728. ant |= B43legacy_TX4_PHY_ANT1;
  1729. break;
  1730. case B43legacy_ANTENNA_AUTO:
  1731. ant |= B43legacy_TX4_PHY_ANTLAST;
  1732. break;
  1733. default:
  1734. B43legacy_BUG_ON(1);
  1735. }
  1736. /* FIXME We also need to set the other flags of the PHY control
  1737. * field somewhere. */
  1738. /* For Beacons */
  1739. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1740. B43legacy_SHM_SH_BEACPHYCTL);
  1741. tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
  1742. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1743. B43legacy_SHM_SH_BEACPHYCTL, tmp);
  1744. /* For ACK/CTS */
  1745. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1746. B43legacy_SHM_SH_ACKCTSPHYCTL);
  1747. tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
  1748. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1749. B43legacy_SHM_SH_ACKCTSPHYCTL, tmp);
  1750. /* For Probe Resposes */
  1751. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1752. B43legacy_SHM_SH_PRPHYCTL);
  1753. tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
  1754. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1755. B43legacy_SHM_SH_PRPHYCTL, tmp);
  1756. }
  1757. /* Returns TRUE, if the radio is enabled in hardware. */
  1758. static bool b43legacy_is_hw_radio_enabled(struct b43legacy_wldev *dev)
  1759. {
  1760. if (dev->phy.rev >= 3) {
  1761. if (!(b43legacy_read32(dev, B43legacy_MMIO_RADIO_HWENABLED_HI)
  1762. & B43legacy_MMIO_RADIO_HWENABLED_HI_MASK))
  1763. return 1;
  1764. } else {
  1765. if (b43legacy_read16(dev, B43legacy_MMIO_RADIO_HWENABLED_LO)
  1766. & B43legacy_MMIO_RADIO_HWENABLED_LO_MASK)
  1767. return 1;
  1768. }
  1769. return 0;
  1770. }
  1771. /* This is the opposite of b43legacy_chip_init() */
  1772. static void b43legacy_chip_exit(struct b43legacy_wldev *dev)
  1773. {
  1774. b43legacy_radio_turn_off(dev);
  1775. if (!modparam_noleds)
  1776. b43legacy_leds_exit(dev);
  1777. b43legacy_gpio_cleanup(dev);
  1778. /* firmware is released later */
  1779. }
  1780. /* Initialize the chip
  1781. * http://bcm-specs.sipsolutions.net/ChipInit
  1782. */
  1783. static int b43legacy_chip_init(struct b43legacy_wldev *dev)
  1784. {
  1785. struct b43legacy_phy *phy = &dev->phy;
  1786. int err;
  1787. int tmp;
  1788. u32 value32;
  1789. u16 value16;
  1790. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD,
  1791. B43legacy_SBF_CORE_READY
  1792. | B43legacy_SBF_400);
  1793. err = b43legacy_request_firmware(dev);
  1794. if (err)
  1795. goto out;
  1796. err = b43legacy_upload_microcode(dev);
  1797. if (err)
  1798. goto out; /* firmware is released later */
  1799. err = b43legacy_gpio_init(dev);
  1800. if (err)
  1801. goto out; /* firmware is released later */
  1802. err = b43legacy_upload_initvals(dev);
  1803. if (err)
  1804. goto err_gpio_cleanup;
  1805. b43legacy_radio_turn_on(dev);
  1806. b43legacy_write16(dev, 0x03E6, 0x0000);
  1807. err = b43legacy_phy_init(dev);
  1808. if (err)
  1809. goto err_radio_off;
  1810. /* Select initial Interference Mitigation. */
  1811. tmp = phy->interfmode;
  1812. phy->interfmode = B43legacy_INTERFMODE_NONE;
  1813. b43legacy_radio_set_interference_mitigation(dev, tmp);
  1814. b43legacy_phy_set_antenna_diversity(dev);
  1815. b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT);
  1816. if (phy->type == B43legacy_PHYTYPE_B) {
  1817. value16 = b43legacy_read16(dev, 0x005E);
  1818. value16 |= 0x0004;
  1819. b43legacy_write16(dev, 0x005E, value16);
  1820. }
  1821. b43legacy_write32(dev, 0x0100, 0x01000000);
  1822. if (dev->dev->id.revision < 5)
  1823. b43legacy_write32(dev, 0x010C, 0x01000000);
  1824. value32 = b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
  1825. value32 &= ~B43legacy_SBF_MODE_NOTADHOC;
  1826. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, value32);
  1827. value32 = b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
  1828. value32 |= B43legacy_SBF_MODE_NOTADHOC;
  1829. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, value32);
  1830. if (b43legacy_using_pio(dev)) {
  1831. b43legacy_write32(dev, 0x0210, 0x00000100);
  1832. b43legacy_write32(dev, 0x0230, 0x00000100);
  1833. b43legacy_write32(dev, 0x0250, 0x00000100);
  1834. b43legacy_write32(dev, 0x0270, 0x00000100);
  1835. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034,
  1836. 0x0000);
  1837. }
  1838. /* Probe Response Timeout value */
  1839. /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
  1840. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000);
  1841. /* Initially set the wireless operation mode. */
  1842. b43legacy_adjust_opmode(dev);
  1843. if (dev->dev->id.revision < 3) {
  1844. b43legacy_write16(dev, 0x060E, 0x0000);
  1845. b43legacy_write16(dev, 0x0610, 0x8000);
  1846. b43legacy_write16(dev, 0x0604, 0x0000);
  1847. b43legacy_write16(dev, 0x0606, 0x0200);
  1848. } else {
  1849. b43legacy_write32(dev, 0x0188, 0x80000000);
  1850. b43legacy_write32(dev, 0x018C, 0x02000000);
  1851. }
  1852. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000);
  1853. b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
  1854. b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
  1855. b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
  1856. b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
  1857. b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
  1858. b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
  1859. value32 = ssb_read32(dev->dev, SSB_TMSLOW);
  1860. value32 |= 0x00100000;
  1861. ssb_write32(dev->dev, SSB_TMSLOW, value32);
  1862. b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY,
  1863. dev->dev->bus->chipco.fast_pwrup_delay);
  1864. B43legacy_WARN_ON(err != 0);
  1865. b43legacydbg(dev->wl, "Chip initialized\n");
  1866. out:
  1867. return err;
  1868. err_radio_off:
  1869. b43legacy_radio_turn_off(dev);
  1870. err_gpio_cleanup:
  1871. b43legacy_gpio_cleanup(dev);
  1872. goto out;
  1873. }
  1874. static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev)
  1875. {
  1876. struct b43legacy_phy *phy = &dev->phy;
  1877. if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2)
  1878. return;
  1879. b43legacy_mac_suspend(dev);
  1880. b43legacy_phy_lo_g_measure(dev);
  1881. b43legacy_mac_enable(dev);
  1882. }
  1883. static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev)
  1884. {
  1885. b43legacy_phy_lo_mark_all_unused(dev);
  1886. if (dev->dev->bus->sprom.r1.boardflags_lo & B43legacy_BFL_RSSI) {
  1887. b43legacy_mac_suspend(dev);
  1888. b43legacy_calc_nrssi_slope(dev);
  1889. b43legacy_mac_enable(dev);
  1890. }
  1891. }
  1892. static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev)
  1893. {
  1894. /* Update device statistics. */
  1895. b43legacy_calculate_link_quality(dev);
  1896. }
  1897. static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev)
  1898. {
  1899. b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */
  1900. }
  1901. static void b43legacy_periodic_every1sec(struct b43legacy_wldev *dev)
  1902. {
  1903. bool radio_hw_enable;
  1904. /* check if radio hardware enabled status changed */
  1905. radio_hw_enable = b43legacy_is_hw_radio_enabled(dev);
  1906. if (unlikely(dev->radio_hw_enable != radio_hw_enable)) {
  1907. dev->radio_hw_enable = radio_hw_enable;
  1908. b43legacyinfo(dev->wl, "Radio hardware status changed to %s\n",
  1909. (radio_hw_enable) ? "enabled" : "disabled");
  1910. b43legacy_leds_update(dev, 0);
  1911. }
  1912. }
  1913. static void do_periodic_work(struct b43legacy_wldev *dev)
  1914. {
  1915. unsigned int state;
  1916. state = dev->periodic_state;
  1917. if (state % 120 == 0)
  1918. b43legacy_periodic_every120sec(dev);
  1919. if (state % 60 == 0)
  1920. b43legacy_periodic_every60sec(dev);
  1921. if (state % 30 == 0)
  1922. b43legacy_periodic_every30sec(dev);
  1923. if (state % 15 == 0)
  1924. b43legacy_periodic_every15sec(dev);
  1925. b43legacy_periodic_every1sec(dev);
  1926. }
  1927. /* Estimate a "Badness" value based on the periodic work
  1928. * state-machine state. "Badness" is worse (bigger), if the
  1929. * periodic work will take longer.
  1930. */
  1931. static int estimate_periodic_work_badness(unsigned int state)
  1932. {
  1933. int badness = 0;
  1934. if (state % 120 == 0) /* every 120 sec */
  1935. badness += 10;
  1936. if (state % 60 == 0) /* every 60 sec */
  1937. badness += 5;
  1938. if (state % 30 == 0) /* every 30 sec */
  1939. badness += 1;
  1940. if (state % 15 == 0) /* every 15 sec */
  1941. badness += 1;
  1942. #define BADNESS_LIMIT 4
  1943. return badness;
  1944. }
  1945. static void b43legacy_periodic_work_handler(struct work_struct *work)
  1946. {
  1947. struct b43legacy_wldev *dev =
  1948. container_of(work, struct b43legacy_wldev,
  1949. periodic_work.work);
  1950. unsigned long flags;
  1951. unsigned long delay;
  1952. u32 savedirqs = 0;
  1953. int badness;
  1954. mutex_lock(&dev->wl->mutex);
  1955. if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED))
  1956. goto out;
  1957. if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP))
  1958. goto out_requeue;
  1959. badness = estimate_periodic_work_badness(dev->periodic_state);
  1960. if (badness > BADNESS_LIMIT) {
  1961. spin_lock_irqsave(&dev->wl->irq_lock, flags);
  1962. /* Suspend TX as we don't want to transmit packets while
  1963. * we recalibrate the hardware. */
  1964. b43legacy_tx_suspend(dev);
  1965. savedirqs = b43legacy_interrupt_disable(dev,
  1966. B43legacy_IRQ_ALL);
  1967. /* Periodic work will take a long time, so we want it to
  1968. * be preemtible and release the spinlock. */
  1969. spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
  1970. b43legacy_synchronize_irq(dev);
  1971. do_periodic_work(dev);
  1972. spin_lock_irqsave(&dev->wl->irq_lock, flags);
  1973. b43legacy_interrupt_enable(dev, savedirqs);
  1974. b43legacy_tx_resume(dev);
  1975. mmiowb();
  1976. spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
  1977. } else {
  1978. /* Take the global driver lock. This will lock any operation. */
  1979. spin_lock_irqsave(&dev->wl->irq_lock, flags);
  1980. do_periodic_work(dev);
  1981. mmiowb();
  1982. spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
  1983. }
  1984. dev->periodic_state++;
  1985. out_requeue:
  1986. if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST))
  1987. delay = msecs_to_jiffies(50);
  1988. else
  1989. delay = round_jiffies_relative(HZ);
  1990. queue_delayed_work(dev->wl->hw->workqueue,
  1991. &dev->periodic_work, delay);
  1992. out:
  1993. mutex_unlock(&dev->wl->mutex);
  1994. }
  1995. static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev)
  1996. {
  1997. struct delayed_work *work = &dev->periodic_work;
  1998. dev->periodic_state = 0;
  1999. INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler);
  2000. queue_delayed_work(dev->wl->hw->workqueue, work, 0);
  2001. }
  2002. /* Validate access to the chip (SHM) */
  2003. static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev)
  2004. {
  2005. u32 value;
  2006. u32 shm_backup;
  2007. shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0);
  2008. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA);
  2009. if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
  2010. 0xAA5555AA)
  2011. goto error;
  2012. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55);
  2013. if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
  2014. 0x55AAAA55)
  2015. goto error;
  2016. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup);
  2017. value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  2018. if ((value | B43legacy_MACCTL_GMODE) !=
  2019. (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED))
  2020. goto error;
  2021. value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  2022. if (value)
  2023. goto error;
  2024. return 0;
  2025. error:
  2026. b43legacyerr(dev->wl, "Failed to validate the chipaccess\n");
  2027. return -ENODEV;
  2028. }
  2029. static void b43legacy_security_init(struct b43legacy_wldev *dev)
  2030. {
  2031. dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
  2032. B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
  2033. dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  2034. 0x0056);
  2035. /* KTP is a word address, but we address SHM bytewise.
  2036. * So multiply by two.
  2037. */
  2038. dev->ktp *= 2;
  2039. if (dev->dev->id.revision >= 5)
  2040. /* Number of RCMTA address slots */
  2041. b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT,
  2042. dev->max_nr_keys - 8);
  2043. }
  2044. static int b43legacy_rng_read(struct hwrng *rng, u32 *data)
  2045. {
  2046. struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv;
  2047. unsigned long flags;
  2048. /* Don't take wl->mutex here, as it could deadlock with
  2049. * hwrng internal locking. It's not needed to take
  2050. * wl->mutex here, anyway. */
  2051. spin_lock_irqsave(&wl->irq_lock, flags);
  2052. *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG);
  2053. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2054. return (sizeof(u16));
  2055. }
  2056. static void b43legacy_rng_exit(struct b43legacy_wl *wl)
  2057. {
  2058. if (wl->rng_initialized)
  2059. hwrng_unregister(&wl->rng);
  2060. }
  2061. static int b43legacy_rng_init(struct b43legacy_wl *wl)
  2062. {
  2063. int err;
  2064. snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
  2065. "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
  2066. wl->rng.name = wl->rng_name;
  2067. wl->rng.data_read = b43legacy_rng_read;
  2068. wl->rng.priv = (unsigned long)wl;
  2069. wl->rng_initialized = 1;
  2070. err = hwrng_register(&wl->rng);
  2071. if (err) {
  2072. wl->rng_initialized = 0;
  2073. b43legacyerr(wl, "Failed to register the random "
  2074. "number generator (%d)\n", err);
  2075. }
  2076. return err;
  2077. }
  2078. static int b43legacy_tx(struct ieee80211_hw *hw,
  2079. struct sk_buff *skb,
  2080. struct ieee80211_tx_control *ctl)
  2081. {
  2082. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2083. struct b43legacy_wldev *dev = wl->current_dev;
  2084. int err = -ENODEV;
  2085. unsigned long flags;
  2086. if (unlikely(!dev))
  2087. goto out;
  2088. if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
  2089. goto out;
  2090. /* DMA-TX is done without a global lock. */
  2091. if (b43legacy_using_pio(dev)) {
  2092. spin_lock_irqsave(&wl->irq_lock, flags);
  2093. err = b43legacy_pio_tx(dev, skb, ctl);
  2094. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2095. } else
  2096. err = b43legacy_dma_tx(dev, skb, ctl);
  2097. out:
  2098. if (unlikely(err))
  2099. return NETDEV_TX_BUSY;
  2100. return NETDEV_TX_OK;
  2101. }
  2102. static int b43legacy_conf_tx(struct ieee80211_hw *hw,
  2103. int queue,
  2104. const struct ieee80211_tx_queue_params *params)
  2105. {
  2106. return 0;
  2107. }
  2108. static int b43legacy_get_tx_stats(struct ieee80211_hw *hw,
  2109. struct ieee80211_tx_queue_stats *stats)
  2110. {
  2111. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2112. struct b43legacy_wldev *dev = wl->current_dev;
  2113. unsigned long flags;
  2114. int err = -ENODEV;
  2115. if (!dev)
  2116. goto out;
  2117. spin_lock_irqsave(&wl->irq_lock, flags);
  2118. if (likely(b43legacy_status(dev) >= B43legacy_STAT_STARTED)) {
  2119. if (b43legacy_using_pio(dev))
  2120. b43legacy_pio_get_tx_stats(dev, stats);
  2121. else
  2122. b43legacy_dma_get_tx_stats(dev, stats);
  2123. err = 0;
  2124. }
  2125. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2126. out:
  2127. return err;
  2128. }
  2129. static int b43legacy_get_stats(struct ieee80211_hw *hw,
  2130. struct ieee80211_low_level_stats *stats)
  2131. {
  2132. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2133. unsigned long flags;
  2134. spin_lock_irqsave(&wl->irq_lock, flags);
  2135. memcpy(stats, &wl->ieee_stats, sizeof(*stats));
  2136. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2137. return 0;
  2138. }
  2139. static const char *phymode_to_string(unsigned int phymode)
  2140. {
  2141. switch (phymode) {
  2142. case B43legacy_PHYMODE_B:
  2143. return "B";
  2144. case B43legacy_PHYMODE_G:
  2145. return "G";
  2146. default:
  2147. B43legacy_BUG_ON(1);
  2148. }
  2149. return "";
  2150. }
  2151. static int find_wldev_for_phymode(struct b43legacy_wl *wl,
  2152. unsigned int phymode,
  2153. struct b43legacy_wldev **dev,
  2154. bool *gmode)
  2155. {
  2156. struct b43legacy_wldev *d;
  2157. list_for_each_entry(d, &wl->devlist, list) {
  2158. if (d->phy.possible_phymodes & phymode) {
  2159. /* Ok, this device supports the PHY-mode.
  2160. * Set the gmode bit. */
  2161. *gmode = 1;
  2162. *dev = d;
  2163. return 0;
  2164. }
  2165. }
  2166. return -ESRCH;
  2167. }
  2168. static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev)
  2169. {
  2170. struct ssb_device *sdev = dev->dev;
  2171. u32 tmslow;
  2172. tmslow = ssb_read32(sdev, SSB_TMSLOW);
  2173. tmslow &= ~B43legacy_TMSLOW_GMODE;
  2174. tmslow |= B43legacy_TMSLOW_PHYRESET;
  2175. tmslow |= SSB_TMSLOW_FGC;
  2176. ssb_write32(sdev, SSB_TMSLOW, tmslow);
  2177. msleep(1);
  2178. tmslow = ssb_read32(sdev, SSB_TMSLOW);
  2179. tmslow &= ~SSB_TMSLOW_FGC;
  2180. tmslow |= B43legacy_TMSLOW_PHYRESET;
  2181. ssb_write32(sdev, SSB_TMSLOW, tmslow);
  2182. msleep(1);
  2183. }
  2184. /* Expects wl->mutex locked */
  2185. static int b43legacy_switch_phymode(struct b43legacy_wl *wl,
  2186. unsigned int new_mode)
  2187. {
  2188. struct b43legacy_wldev *up_dev;
  2189. struct b43legacy_wldev *down_dev;
  2190. int err;
  2191. bool gmode = 0;
  2192. int prev_status;
  2193. err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
  2194. if (err) {
  2195. b43legacyerr(wl, "Could not find a device for %s-PHY mode\n",
  2196. phymode_to_string(new_mode));
  2197. return err;
  2198. }
  2199. if ((up_dev == wl->current_dev) &&
  2200. (!!wl->current_dev->phy.gmode == !!gmode))
  2201. /* This device is already running. */
  2202. return 0;
  2203. b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
  2204. phymode_to_string(new_mode));
  2205. down_dev = wl->current_dev;
  2206. prev_status = b43legacy_status(down_dev);
  2207. /* Shutdown the currently running core. */
  2208. if (prev_status >= B43legacy_STAT_STARTED)
  2209. b43legacy_wireless_core_stop(down_dev);
  2210. if (prev_status >= B43legacy_STAT_INITIALIZED)
  2211. b43legacy_wireless_core_exit(down_dev);
  2212. if (down_dev != up_dev)
  2213. /* We switch to a different core, so we put PHY into
  2214. * RESET on the old core. */
  2215. b43legacy_put_phy_into_reset(down_dev);
  2216. /* Now start the new core. */
  2217. up_dev->phy.gmode = gmode;
  2218. if (prev_status >= B43legacy_STAT_INITIALIZED) {
  2219. err = b43legacy_wireless_core_init(up_dev);
  2220. if (err) {
  2221. b43legacyerr(wl, "Fatal: Could not initialize device"
  2222. " for newly selected %s-PHY mode\n",
  2223. phymode_to_string(new_mode));
  2224. goto init_failure;
  2225. }
  2226. }
  2227. if (prev_status >= B43legacy_STAT_STARTED) {
  2228. err = b43legacy_wireless_core_start(up_dev);
  2229. if (err) {
  2230. b43legacyerr(wl, "Fatal: Coult not start device for "
  2231. "newly selected %s-PHY mode\n",
  2232. phymode_to_string(new_mode));
  2233. b43legacy_wireless_core_exit(up_dev);
  2234. goto init_failure;
  2235. }
  2236. }
  2237. B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status);
  2238. b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0);
  2239. wl->current_dev = up_dev;
  2240. return 0;
  2241. init_failure:
  2242. /* Whoops, failed to init the new core. No core is operating now. */
  2243. wl->current_dev = NULL;
  2244. return err;
  2245. }
  2246. static int b43legacy_antenna_from_ieee80211(u8 antenna)
  2247. {
  2248. switch (antenna) {
  2249. case 0: /* default/diversity */
  2250. return B43legacy_ANTENNA_DEFAULT;
  2251. case 1: /* Antenna 0 */
  2252. return B43legacy_ANTENNA0;
  2253. case 2: /* Antenna 1 */
  2254. return B43legacy_ANTENNA1;
  2255. default:
  2256. return B43legacy_ANTENNA_DEFAULT;
  2257. }
  2258. }
  2259. static int b43legacy_dev_config(struct ieee80211_hw *hw,
  2260. struct ieee80211_conf *conf)
  2261. {
  2262. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2263. struct b43legacy_wldev *dev;
  2264. struct b43legacy_phy *phy;
  2265. unsigned long flags;
  2266. unsigned int new_phymode = 0xFFFF;
  2267. int antenna_tx;
  2268. int antenna_rx;
  2269. int err = 0;
  2270. u32 savedirqs;
  2271. antenna_tx = b43legacy_antenna_from_ieee80211(conf->antenna_sel_tx);
  2272. antenna_rx = b43legacy_antenna_from_ieee80211(conf->antenna_sel_rx);
  2273. mutex_lock(&wl->mutex);
  2274. /* Switch the PHY mode (if necessary). */
  2275. switch (conf->phymode) {
  2276. case MODE_IEEE80211B:
  2277. new_phymode = B43legacy_PHYMODE_B;
  2278. break;
  2279. case MODE_IEEE80211G:
  2280. new_phymode = B43legacy_PHYMODE_G;
  2281. break;
  2282. default:
  2283. B43legacy_WARN_ON(1);
  2284. }
  2285. err = b43legacy_switch_phymode(wl, new_phymode);
  2286. if (err)
  2287. goto out_unlock_mutex;
  2288. dev = wl->current_dev;
  2289. phy = &dev->phy;
  2290. /* Disable IRQs while reconfiguring the device.
  2291. * This makes it possible to drop the spinlock throughout
  2292. * the reconfiguration process. */
  2293. spin_lock_irqsave(&wl->irq_lock, flags);
  2294. if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
  2295. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2296. goto out_unlock_mutex;
  2297. }
  2298. savedirqs = b43legacy_interrupt_disable(dev, B43legacy_IRQ_ALL);
  2299. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2300. b43legacy_synchronize_irq(dev);
  2301. /* Switch to the requested channel.
  2302. * The firmware takes care of races with the TX handler. */
  2303. if (conf->channel_val != phy->channel)
  2304. b43legacy_radio_selectchannel(dev, conf->channel_val, 0);
  2305. /* Enable/Disable ShortSlot timing. */
  2306. if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME))
  2307. != dev->short_slot) {
  2308. B43legacy_WARN_ON(phy->type != B43legacy_PHYTYPE_G);
  2309. if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
  2310. b43legacy_short_slot_timing_enable(dev);
  2311. else
  2312. b43legacy_short_slot_timing_disable(dev);
  2313. }
  2314. /* Adjust the desired TX power level. */
  2315. if (conf->power_level != 0) {
  2316. if (conf->power_level != phy->power_level) {
  2317. phy->power_level = conf->power_level;
  2318. b43legacy_phy_xmitpower(dev);
  2319. }
  2320. }
  2321. /* Antennas for RX and management frame TX. */
  2322. b43legacy_mgmtframe_txantenna(dev, antenna_tx);
  2323. /* Update templates for AP mode. */
  2324. if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP))
  2325. b43legacy_set_beacon_int(dev, conf->beacon_int);
  2326. if (!!conf->radio_enabled != phy->radio_on) {
  2327. if (conf->radio_enabled) {
  2328. b43legacy_radio_turn_on(dev);
  2329. b43legacyinfo(dev->wl, "Radio turned on by software\n");
  2330. if (!dev->radio_hw_enable)
  2331. b43legacyinfo(dev->wl, "The hardware RF-kill"
  2332. " button still turns the radio"
  2333. " physically off. Press the"
  2334. " button to turn it on.\n");
  2335. } else {
  2336. b43legacy_radio_turn_off(dev);
  2337. b43legacyinfo(dev->wl, "Radio turned off by"
  2338. " software\n");
  2339. }
  2340. }
  2341. spin_lock_irqsave(&wl->irq_lock, flags);
  2342. b43legacy_interrupt_enable(dev, savedirqs);
  2343. mmiowb();
  2344. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2345. out_unlock_mutex:
  2346. mutex_unlock(&wl->mutex);
  2347. return err;
  2348. }
  2349. static int b43legacy_dev_set_key(struct ieee80211_hw *hw,
  2350. enum set_key_cmd cmd,
  2351. const u8 *local_addr, const u8 *addr,
  2352. struct ieee80211_key_conf *key)
  2353. {
  2354. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2355. struct b43legacy_wldev *dev = wl->current_dev;
  2356. unsigned long flags;
  2357. int err = -EOPNOTSUPP;
  2358. DECLARE_MAC_BUF(mac);
  2359. if (!dev)
  2360. return -ENODEV;
  2361. mutex_lock(&wl->mutex);
  2362. spin_lock_irqsave(&wl->irq_lock, flags);
  2363. if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED) {
  2364. err = -ENODEV;
  2365. }
  2366. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2367. mutex_unlock(&wl->mutex);
  2368. b43legacydbg(wl, "Using software based encryption for "
  2369. "mac: %s\n", print_mac(mac, addr));
  2370. return err;
  2371. }
  2372. static void b43legacy_configure_filter(struct ieee80211_hw *hw,
  2373. unsigned int changed,
  2374. unsigned int *fflags,
  2375. int mc_count,
  2376. struct dev_addr_list *mc_list)
  2377. {
  2378. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2379. struct b43legacy_wldev *dev = wl->current_dev;
  2380. unsigned long flags;
  2381. if (!dev) {
  2382. *fflags = 0;
  2383. return;
  2384. }
  2385. spin_lock_irqsave(&wl->irq_lock, flags);
  2386. *fflags &= FIF_PROMISC_IN_BSS |
  2387. FIF_ALLMULTI |
  2388. FIF_FCSFAIL |
  2389. FIF_PLCPFAIL |
  2390. FIF_CONTROL |
  2391. FIF_OTHER_BSS |
  2392. FIF_BCN_PRBRESP_PROMISC;
  2393. changed &= FIF_PROMISC_IN_BSS |
  2394. FIF_ALLMULTI |
  2395. FIF_FCSFAIL |
  2396. FIF_PLCPFAIL |
  2397. FIF_CONTROL |
  2398. FIF_OTHER_BSS |
  2399. FIF_BCN_PRBRESP_PROMISC;
  2400. wl->filter_flags = *fflags;
  2401. if (changed && b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED)
  2402. b43legacy_adjust_opmode(dev);
  2403. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2404. }
  2405. static int b43legacy_config_interface(struct ieee80211_hw *hw,
  2406. int if_id,
  2407. struct ieee80211_if_conf *conf)
  2408. {
  2409. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2410. struct b43legacy_wldev *dev = wl->current_dev;
  2411. unsigned long flags;
  2412. if (!dev)
  2413. return -ENODEV;
  2414. mutex_lock(&wl->mutex);
  2415. spin_lock_irqsave(&wl->irq_lock, flags);
  2416. B43legacy_WARN_ON(wl->if_id != if_id);
  2417. if (conf->bssid)
  2418. memcpy(wl->bssid, conf->bssid, ETH_ALEN);
  2419. else
  2420. memset(wl->bssid, 0, ETH_ALEN);
  2421. if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
  2422. if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
  2423. B43legacy_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
  2424. b43legacy_set_ssid(dev, conf->ssid, conf->ssid_len);
  2425. if (conf->beacon)
  2426. b43legacy_refresh_templates(dev, conf->beacon);
  2427. }
  2428. b43legacy_write_mac_bssid_templates(dev);
  2429. }
  2430. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2431. mutex_unlock(&wl->mutex);
  2432. return 0;
  2433. }
  2434. /* Locking: wl->mutex */
  2435. static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev)
  2436. {
  2437. struct b43legacy_wl *wl = dev->wl;
  2438. unsigned long flags;
  2439. if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
  2440. return;
  2441. /* Disable and sync interrupts. We must do this before than
  2442. * setting the status to INITIALIZED, as the interrupt handler
  2443. * won't care about IRQs then. */
  2444. spin_lock_irqsave(&wl->irq_lock, flags);
  2445. dev->irq_savedstate = b43legacy_interrupt_disable(dev,
  2446. B43legacy_IRQ_ALL);
  2447. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */
  2448. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2449. b43legacy_synchronize_irq(dev);
  2450. b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
  2451. mutex_unlock(&wl->mutex);
  2452. /* Must unlock as it would otherwise deadlock. No races here.
  2453. * Cancel the possibly running self-rearming periodic work. */
  2454. cancel_delayed_work_sync(&dev->periodic_work);
  2455. mutex_lock(&wl->mutex);
  2456. ieee80211_stop_queues(wl->hw); /* FIXME this could cause a deadlock */
  2457. b43legacy_mac_suspend(dev);
  2458. free_irq(dev->dev->irq, dev);
  2459. b43legacydbg(wl, "Wireless interface stopped\n");
  2460. }
  2461. /* Locking: wl->mutex */
  2462. static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
  2463. {
  2464. int err;
  2465. B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED);
  2466. drain_txstatus_queue(dev);
  2467. err = request_irq(dev->dev->irq, b43legacy_interrupt_handler,
  2468. IRQF_SHARED, KBUILD_MODNAME, dev);
  2469. if (err) {
  2470. b43legacyerr(dev->wl, "Cannot request IRQ-%d\n",
  2471. dev->dev->irq);
  2472. goto out;
  2473. }
  2474. /* We are ready to run. */
  2475. b43legacy_set_status(dev, B43legacy_STAT_STARTED);
  2476. /* Start data flow (TX/RX) */
  2477. b43legacy_mac_enable(dev);
  2478. b43legacy_interrupt_enable(dev, dev->irq_savedstate);
  2479. ieee80211_start_queues(dev->wl->hw);
  2480. /* Start maintenance work */
  2481. b43legacy_periodic_tasks_setup(dev);
  2482. b43legacydbg(dev->wl, "Wireless interface started\n");
  2483. out:
  2484. return err;
  2485. }
  2486. /* Get PHY and RADIO versioning numbers */
  2487. static int b43legacy_phy_versioning(struct b43legacy_wldev *dev)
  2488. {
  2489. struct b43legacy_phy *phy = &dev->phy;
  2490. u32 tmp;
  2491. u8 analog_type;
  2492. u8 phy_type;
  2493. u8 phy_rev;
  2494. u16 radio_manuf;
  2495. u16 radio_ver;
  2496. u16 radio_rev;
  2497. int unsupported = 0;
  2498. /* Get PHY versioning */
  2499. tmp = b43legacy_read16(dev, B43legacy_MMIO_PHY_VER);
  2500. analog_type = (tmp & B43legacy_PHYVER_ANALOG)
  2501. >> B43legacy_PHYVER_ANALOG_SHIFT;
  2502. phy_type = (tmp & B43legacy_PHYVER_TYPE) >> B43legacy_PHYVER_TYPE_SHIFT;
  2503. phy_rev = (tmp & B43legacy_PHYVER_VERSION);
  2504. switch (phy_type) {
  2505. case B43legacy_PHYTYPE_B:
  2506. if (phy_rev != 2 && phy_rev != 4
  2507. && phy_rev != 6 && phy_rev != 7)
  2508. unsupported = 1;
  2509. break;
  2510. case B43legacy_PHYTYPE_G:
  2511. if (phy_rev > 8)
  2512. unsupported = 1;
  2513. break;
  2514. default:
  2515. unsupported = 1;
  2516. };
  2517. if (unsupported) {
  2518. b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY "
  2519. "(Analog %u, Type %u, Revision %u)\n",
  2520. analog_type, phy_type, phy_rev);
  2521. return -EOPNOTSUPP;
  2522. }
  2523. b43legacydbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
  2524. analog_type, phy_type, phy_rev);
  2525. /* Get RADIO versioning */
  2526. if (dev->dev->bus->chip_id == 0x4317) {
  2527. if (dev->dev->bus->chip_rev == 0)
  2528. tmp = 0x3205017F;
  2529. else if (dev->dev->bus->chip_rev == 1)
  2530. tmp = 0x4205017F;
  2531. else
  2532. tmp = 0x5205017F;
  2533. } else {
  2534. b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
  2535. B43legacy_RADIOCTL_ID);
  2536. tmp = b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_HIGH);
  2537. tmp <<= 16;
  2538. b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
  2539. B43legacy_RADIOCTL_ID);
  2540. tmp |= b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_LOW);
  2541. }
  2542. radio_manuf = (tmp & 0x00000FFF);
  2543. radio_ver = (tmp & 0x0FFFF000) >> 12;
  2544. radio_rev = (tmp & 0xF0000000) >> 28;
  2545. switch (phy_type) {
  2546. case B43legacy_PHYTYPE_B:
  2547. if ((radio_ver & 0xFFF0) != 0x2050)
  2548. unsupported = 1;
  2549. break;
  2550. case B43legacy_PHYTYPE_G:
  2551. if (radio_ver != 0x2050)
  2552. unsupported = 1;
  2553. break;
  2554. default:
  2555. B43legacy_BUG_ON(1);
  2556. }
  2557. if (unsupported) {
  2558. b43legacyerr(dev->wl, "FOUND UNSUPPORTED RADIO "
  2559. "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
  2560. radio_manuf, radio_ver, radio_rev);
  2561. return -EOPNOTSUPP;
  2562. }
  2563. b43legacydbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X,"
  2564. " Revision %u\n", radio_manuf, radio_ver, radio_rev);
  2565. phy->radio_manuf = radio_manuf;
  2566. phy->radio_ver = radio_ver;
  2567. phy->radio_rev = radio_rev;
  2568. phy->analog = analog_type;
  2569. phy->type = phy_type;
  2570. phy->rev = phy_rev;
  2571. return 0;
  2572. }
  2573. static void setup_struct_phy_for_init(struct b43legacy_wldev *dev,
  2574. struct b43legacy_phy *phy)
  2575. {
  2576. struct b43legacy_lopair *lo;
  2577. int i;
  2578. memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
  2579. memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
  2580. /* Flags */
  2581. phy->locked = 0;
  2582. /* Assume the radio is enabled. If it's not enabled, the state will
  2583. * immediately get fixed on the first periodic work run. */
  2584. dev->radio_hw_enable = 1;
  2585. phy->savedpctlreg = 0xFFFF;
  2586. phy->aci_enable = 0;
  2587. phy->aci_wlan_automatic = 0;
  2588. phy->aci_hw_rssi = 0;
  2589. lo = phy->_lo_pairs;
  2590. if (lo)
  2591. memset(lo, 0, sizeof(struct b43legacy_lopair) *
  2592. B43legacy_LO_COUNT);
  2593. phy->max_lb_gain = 0;
  2594. phy->trsw_rx_gain = 0;
  2595. /* Set default attenuation values. */
  2596. phy->bbatt = b43legacy_default_baseband_attenuation(dev);
  2597. phy->rfatt = b43legacy_default_radio_attenuation(dev);
  2598. phy->txctl1 = b43legacy_default_txctl1(dev);
  2599. phy->txpwr_offset = 0;
  2600. /* NRSSI */
  2601. phy->nrssislope = 0;
  2602. for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
  2603. phy->nrssi[i] = -1000;
  2604. for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
  2605. phy->nrssi_lt[i] = i;
  2606. phy->lofcal = 0xFFFF;
  2607. phy->initval = 0xFFFF;
  2608. spin_lock_init(&phy->lock);
  2609. phy->interfmode = B43legacy_INTERFMODE_NONE;
  2610. phy->channel = 0xFF;
  2611. }
  2612. static void setup_struct_wldev_for_init(struct b43legacy_wldev *dev)
  2613. {
  2614. /* Flags */
  2615. dev->reg124_set_0x4 = 0;
  2616. /* Stats */
  2617. memset(&dev->stats, 0, sizeof(dev->stats));
  2618. setup_struct_phy_for_init(dev, &dev->phy);
  2619. /* IRQ related flags */
  2620. dev->irq_reason = 0;
  2621. memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
  2622. dev->irq_savedstate = B43legacy_IRQ_MASKTEMPLATE;
  2623. dev->mac_suspended = 1;
  2624. /* Noise calculation context */
  2625. memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
  2626. }
  2627. static void b43legacy_imcfglo_timeouts_workaround(struct b43legacy_wldev *dev)
  2628. {
  2629. #ifdef CONFIG_SSB_DRIVER_PCICORE
  2630. struct ssb_bus *bus = dev->dev->bus;
  2631. u32 tmp;
  2632. if (bus->pcicore.dev &&
  2633. bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
  2634. bus->pcicore.dev->id.revision <= 5) {
  2635. /* IMCFGLO timeouts workaround. */
  2636. tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
  2637. tmp &= ~SSB_IMCFGLO_REQTO;
  2638. tmp &= ~SSB_IMCFGLO_SERTO;
  2639. switch (bus->bustype) {
  2640. case SSB_BUSTYPE_PCI:
  2641. case SSB_BUSTYPE_PCMCIA:
  2642. tmp |= 0x32;
  2643. break;
  2644. case SSB_BUSTYPE_SSB:
  2645. tmp |= 0x53;
  2646. break;
  2647. }
  2648. ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
  2649. }
  2650. #endif /* CONFIG_SSB_DRIVER_PCICORE */
  2651. }
  2652. /* Shutdown a wireless core */
  2653. /* Locking: wl->mutex */
  2654. static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev)
  2655. {
  2656. struct b43legacy_wl *wl = dev->wl;
  2657. struct b43legacy_phy *phy = &dev->phy;
  2658. B43legacy_WARN_ON(b43legacy_status(dev) > B43legacy_STAT_INITIALIZED);
  2659. if (b43legacy_status(dev) != B43legacy_STAT_INITIALIZED)
  2660. return;
  2661. b43legacy_set_status(dev, B43legacy_STAT_UNINIT);
  2662. mutex_unlock(&wl->mutex);
  2663. /* Must unlock as it would otherwise deadlock. No races here.
  2664. * Cancel possibly pending workqueues. */
  2665. cancel_work_sync(&dev->restart_work);
  2666. mutex_lock(&wl->mutex);
  2667. b43legacy_rng_exit(dev->wl);
  2668. b43legacy_pio_free(dev);
  2669. b43legacy_dma_free(dev);
  2670. b43legacy_chip_exit(dev);
  2671. b43legacy_radio_turn_off(dev);
  2672. b43legacy_switch_analog(dev, 0);
  2673. if (phy->dyn_tssi_tbl)
  2674. kfree(phy->tssi2dbm);
  2675. kfree(phy->lo_control);
  2676. phy->lo_control = NULL;
  2677. ssb_device_disable(dev->dev, 0);
  2678. ssb_bus_may_powerdown(dev->dev->bus);
  2679. }
  2680. static void prepare_phy_data_for_init(struct b43legacy_wldev *dev)
  2681. {
  2682. struct b43legacy_phy *phy = &dev->phy;
  2683. int i;
  2684. /* Set default attenuation values. */
  2685. phy->bbatt = b43legacy_default_baseband_attenuation(dev);
  2686. phy->rfatt = b43legacy_default_radio_attenuation(dev);
  2687. phy->txctl1 = b43legacy_default_txctl1(dev);
  2688. phy->txctl2 = 0xFFFF;
  2689. phy->txpwr_offset = 0;
  2690. /* NRSSI */
  2691. phy->nrssislope = 0;
  2692. for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
  2693. phy->nrssi[i] = -1000;
  2694. for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
  2695. phy->nrssi_lt[i] = i;
  2696. phy->lofcal = 0xFFFF;
  2697. phy->initval = 0xFFFF;
  2698. phy->aci_enable = 0;
  2699. phy->aci_wlan_automatic = 0;
  2700. phy->aci_hw_rssi = 0;
  2701. phy->antenna_diversity = 0xFFFF;
  2702. memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
  2703. memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
  2704. /* Flags */
  2705. phy->calibrated = 0;
  2706. phy->locked = 0;
  2707. if (phy->_lo_pairs)
  2708. memset(phy->_lo_pairs, 0,
  2709. sizeof(struct b43legacy_lopair) * B43legacy_LO_COUNT);
  2710. memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
  2711. }
  2712. /* Initialize a wireless core */
  2713. static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev)
  2714. {
  2715. struct b43legacy_wl *wl = dev->wl;
  2716. struct ssb_bus *bus = dev->dev->bus;
  2717. struct b43legacy_phy *phy = &dev->phy;
  2718. struct ssb_sprom *sprom = &dev->dev->bus->sprom;
  2719. int err;
  2720. u32 hf;
  2721. u32 tmp;
  2722. B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
  2723. err = ssb_bus_powerup(bus, 0);
  2724. if (err)
  2725. goto out;
  2726. if (!ssb_device_is_enabled(dev->dev)) {
  2727. tmp = phy->gmode ? B43legacy_TMSLOW_GMODE : 0;
  2728. b43legacy_wireless_core_reset(dev, tmp);
  2729. }
  2730. if ((phy->type == B43legacy_PHYTYPE_B) ||
  2731. (phy->type == B43legacy_PHYTYPE_G)) {
  2732. phy->_lo_pairs = kzalloc(sizeof(struct b43legacy_lopair)
  2733. * B43legacy_LO_COUNT,
  2734. GFP_KERNEL);
  2735. if (!phy->_lo_pairs)
  2736. return -ENOMEM;
  2737. }
  2738. setup_struct_wldev_for_init(dev);
  2739. err = b43legacy_phy_init_tssi2dbm_table(dev);
  2740. if (err)
  2741. goto err_kfree_lo_control;
  2742. /* Enable IRQ routing to this device. */
  2743. ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
  2744. b43legacy_imcfglo_timeouts_workaround(dev);
  2745. prepare_phy_data_for_init(dev);
  2746. b43legacy_phy_calibrate(dev);
  2747. err = b43legacy_chip_init(dev);
  2748. if (err)
  2749. goto err_kfree_tssitbl;
  2750. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2751. B43legacy_SHM_SH_WLCOREREV,
  2752. dev->dev->id.revision);
  2753. hf = b43legacy_hf_read(dev);
  2754. if (phy->type == B43legacy_PHYTYPE_G) {
  2755. hf |= B43legacy_HF_SYMW;
  2756. if (phy->rev == 1)
  2757. hf |= B43legacy_HF_GDCW;
  2758. if (sprom->r1.boardflags_lo & B43legacy_BFL_PACTRL)
  2759. hf |= B43legacy_HF_OFDMPABOOST;
  2760. } else if (phy->type == B43legacy_PHYTYPE_B) {
  2761. hf |= B43legacy_HF_SYMW;
  2762. if (phy->rev >= 2 && phy->radio_ver == 0x2050)
  2763. hf &= ~B43legacy_HF_GDCW;
  2764. }
  2765. b43legacy_hf_write(dev, hf);
  2766. /* Short/Long Retry Limit.
  2767. * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
  2768. * the chip-internal counter.
  2769. */
  2770. tmp = limit_value(modparam_short_retry, 0, 0xF);
  2771. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
  2772. 0x0006, tmp);
  2773. tmp = limit_value(modparam_long_retry, 0, 0xF);
  2774. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
  2775. 0x0007, tmp);
  2776. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2777. 0x0044, 3);
  2778. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2779. 0x0046, 2);
  2780. /* Disable sending probe responses from firmware.
  2781. * Setting the MaxTime to one usec will always trigger
  2782. * a timeout, so we never send any probe resp.
  2783. * A timeout of zero is infinite. */
  2784. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2785. B43legacy_SHM_SH_PRMAXTIME, 1);
  2786. b43legacy_rate_memory_init(dev);
  2787. /* Minimum Contention Window */
  2788. if (phy->type == B43legacy_PHYTYPE_B)
  2789. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
  2790. 0x0003, 31);
  2791. else
  2792. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
  2793. 0x0003, 15);
  2794. /* Maximum Contention Window */
  2795. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
  2796. 0x0004, 1023);
  2797. do {
  2798. if (b43legacy_using_pio(dev))
  2799. err = b43legacy_pio_init(dev);
  2800. else {
  2801. err = b43legacy_dma_init(dev);
  2802. if (!err)
  2803. b43legacy_qos_init(dev);
  2804. }
  2805. } while (err == -EAGAIN);
  2806. if (err)
  2807. goto err_chip_exit;
  2808. b43legacy_write16(dev, 0x0612, 0x0050);
  2809. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0416, 0x0050);
  2810. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0414, 0x01F4);
  2811. ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
  2812. memset(wl->bssid, 0, ETH_ALEN);
  2813. memset(wl->mac_addr, 0, ETH_ALEN);
  2814. b43legacy_upload_card_macaddress(dev);
  2815. b43legacy_security_init(dev);
  2816. b43legacy_rng_init(wl);
  2817. b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
  2818. out:
  2819. return err;
  2820. err_chip_exit:
  2821. b43legacy_chip_exit(dev);
  2822. err_kfree_tssitbl:
  2823. if (phy->dyn_tssi_tbl)
  2824. kfree(phy->tssi2dbm);
  2825. err_kfree_lo_control:
  2826. kfree(phy->lo_control);
  2827. phy->lo_control = NULL;
  2828. ssb_bus_may_powerdown(bus);
  2829. B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
  2830. return err;
  2831. }
  2832. static int b43legacy_add_interface(struct ieee80211_hw *hw,
  2833. struct ieee80211_if_init_conf *conf)
  2834. {
  2835. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2836. struct b43legacy_wldev *dev;
  2837. unsigned long flags;
  2838. int err = -EOPNOTSUPP;
  2839. /* TODO: allow WDS/AP devices to coexist */
  2840. if (conf->type != IEEE80211_IF_TYPE_AP &&
  2841. conf->type != IEEE80211_IF_TYPE_STA &&
  2842. conf->type != IEEE80211_IF_TYPE_WDS &&
  2843. conf->type != IEEE80211_IF_TYPE_IBSS)
  2844. return -EOPNOTSUPP;
  2845. mutex_lock(&wl->mutex);
  2846. if (wl->operating)
  2847. goto out_mutex_unlock;
  2848. b43legacydbg(wl, "Adding Interface type %d\n", conf->type);
  2849. dev = wl->current_dev;
  2850. wl->operating = 1;
  2851. wl->if_id = conf->if_id;
  2852. wl->if_type = conf->type;
  2853. memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
  2854. spin_lock_irqsave(&wl->irq_lock, flags);
  2855. b43legacy_adjust_opmode(dev);
  2856. b43legacy_upload_card_macaddress(dev);
  2857. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2858. err = 0;
  2859. out_mutex_unlock:
  2860. mutex_unlock(&wl->mutex);
  2861. return err;
  2862. }
  2863. static void b43legacy_remove_interface(struct ieee80211_hw *hw,
  2864. struct ieee80211_if_init_conf *conf)
  2865. {
  2866. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2867. struct b43legacy_wldev *dev = wl->current_dev;
  2868. unsigned long flags;
  2869. b43legacydbg(wl, "Removing Interface type %d\n", conf->type);
  2870. mutex_lock(&wl->mutex);
  2871. B43legacy_WARN_ON(!wl->operating);
  2872. B43legacy_WARN_ON(wl->if_id != conf->if_id);
  2873. wl->operating = 0;
  2874. spin_lock_irqsave(&wl->irq_lock, flags);
  2875. b43legacy_adjust_opmode(dev);
  2876. memset(wl->mac_addr, 0, ETH_ALEN);
  2877. b43legacy_upload_card_macaddress(dev);
  2878. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2879. mutex_unlock(&wl->mutex);
  2880. }
  2881. static int b43legacy_start(struct ieee80211_hw *hw)
  2882. {
  2883. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2884. struct b43legacy_wldev *dev = wl->current_dev;
  2885. int did_init = 0;
  2886. int err = 0;
  2887. mutex_lock(&wl->mutex);
  2888. if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED) {
  2889. err = b43legacy_wireless_core_init(dev);
  2890. if (err)
  2891. goto out_mutex_unlock;
  2892. did_init = 1;
  2893. }
  2894. if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
  2895. err = b43legacy_wireless_core_start(dev);
  2896. if (err) {
  2897. if (did_init)
  2898. b43legacy_wireless_core_exit(dev);
  2899. goto out_mutex_unlock;
  2900. }
  2901. }
  2902. out_mutex_unlock:
  2903. mutex_unlock(&wl->mutex);
  2904. return err;
  2905. }
  2906. static void b43legacy_stop(struct ieee80211_hw *hw)
  2907. {
  2908. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2909. struct b43legacy_wldev *dev = wl->current_dev;
  2910. mutex_lock(&wl->mutex);
  2911. if (b43legacy_status(dev) >= B43legacy_STAT_STARTED)
  2912. b43legacy_wireless_core_stop(dev);
  2913. b43legacy_wireless_core_exit(dev);
  2914. mutex_unlock(&wl->mutex);
  2915. }
  2916. static const struct ieee80211_ops b43legacy_hw_ops = {
  2917. .tx = b43legacy_tx,
  2918. .conf_tx = b43legacy_conf_tx,
  2919. .add_interface = b43legacy_add_interface,
  2920. .remove_interface = b43legacy_remove_interface,
  2921. .config = b43legacy_dev_config,
  2922. .config_interface = b43legacy_config_interface,
  2923. .set_key = b43legacy_dev_set_key,
  2924. .configure_filter = b43legacy_configure_filter,
  2925. .get_stats = b43legacy_get_stats,
  2926. .get_tx_stats = b43legacy_get_tx_stats,
  2927. .start = b43legacy_start,
  2928. .stop = b43legacy_stop,
  2929. };
  2930. /* Hard-reset the chip. Do not call this directly.
  2931. * Use b43legacy_controller_restart()
  2932. */
  2933. static void b43legacy_chip_reset(struct work_struct *work)
  2934. {
  2935. struct b43legacy_wldev *dev =
  2936. container_of(work, struct b43legacy_wldev, restart_work);
  2937. struct b43legacy_wl *wl = dev->wl;
  2938. int err = 0;
  2939. int prev_status;
  2940. mutex_lock(&wl->mutex);
  2941. prev_status = b43legacy_status(dev);
  2942. /* Bring the device down... */
  2943. if (prev_status >= B43legacy_STAT_STARTED)
  2944. b43legacy_wireless_core_stop(dev);
  2945. if (prev_status >= B43legacy_STAT_INITIALIZED)
  2946. b43legacy_wireless_core_exit(dev);
  2947. /* ...and up again. */
  2948. if (prev_status >= B43legacy_STAT_INITIALIZED) {
  2949. err = b43legacy_wireless_core_init(dev);
  2950. if (err)
  2951. goto out;
  2952. }
  2953. if (prev_status >= B43legacy_STAT_STARTED) {
  2954. err = b43legacy_wireless_core_start(dev);
  2955. if (err) {
  2956. b43legacy_wireless_core_exit(dev);
  2957. goto out;
  2958. }
  2959. }
  2960. out:
  2961. mutex_unlock(&wl->mutex);
  2962. if (err)
  2963. b43legacyerr(wl, "Controller restart FAILED\n");
  2964. else
  2965. b43legacyinfo(wl, "Controller restarted\n");
  2966. }
  2967. static int b43legacy_setup_modes(struct b43legacy_wldev *dev,
  2968. int have_bphy,
  2969. int have_gphy)
  2970. {
  2971. struct ieee80211_hw *hw = dev->wl->hw;
  2972. struct ieee80211_hw_mode *mode;
  2973. struct b43legacy_phy *phy = &dev->phy;
  2974. int cnt = 0;
  2975. int err;
  2976. phy->possible_phymodes = 0;
  2977. for (; 1; cnt++) {
  2978. if (have_bphy) {
  2979. B43legacy_WARN_ON(cnt >= B43legacy_MAX_PHYHWMODES);
  2980. mode = &phy->hwmodes[cnt];
  2981. mode->mode = MODE_IEEE80211B;
  2982. mode->num_channels = b43legacy_bg_chantable_size;
  2983. mode->channels = b43legacy_bg_chantable;
  2984. mode->num_rates = b43legacy_b_ratetable_size;
  2985. mode->rates = b43legacy_b_ratetable;
  2986. err = ieee80211_register_hwmode(hw, mode);
  2987. if (err)
  2988. return err;
  2989. phy->possible_phymodes |= B43legacy_PHYMODE_B;
  2990. have_bphy = 0;
  2991. continue;
  2992. }
  2993. if (have_gphy) {
  2994. B43legacy_WARN_ON(cnt >= B43legacy_MAX_PHYHWMODES);
  2995. mode = &phy->hwmodes[cnt];
  2996. mode->mode = MODE_IEEE80211G;
  2997. mode->num_channels = b43legacy_bg_chantable_size;
  2998. mode->channels = b43legacy_bg_chantable;
  2999. mode->num_rates = b43legacy_g_ratetable_size;
  3000. mode->rates = b43legacy_g_ratetable;
  3001. err = ieee80211_register_hwmode(hw, mode);
  3002. if (err)
  3003. return err;
  3004. phy->possible_phymodes |= B43legacy_PHYMODE_G;
  3005. have_gphy = 0;
  3006. continue;
  3007. }
  3008. break;
  3009. }
  3010. return 0;
  3011. }
  3012. static void b43legacy_wireless_core_detach(struct b43legacy_wldev *dev)
  3013. {
  3014. /* We release firmware that late to not be required to re-request
  3015. * is all the time when we reinit the core. */
  3016. b43legacy_release_firmware(dev);
  3017. }
  3018. static int b43legacy_wireless_core_attach(struct b43legacy_wldev *dev)
  3019. {
  3020. struct b43legacy_wl *wl = dev->wl;
  3021. struct ssb_bus *bus = dev->dev->bus;
  3022. struct pci_dev *pdev = bus->host_pci;
  3023. int err;
  3024. int have_bphy = 0;
  3025. int have_gphy = 0;
  3026. u32 tmp;
  3027. /* Do NOT do any device initialization here.
  3028. * Do it in wireless_core_init() instead.
  3029. * This function is for gathering basic information about the HW, only.
  3030. * Also some structs may be set up here. But most likely you want to
  3031. * have that in core_init(), too.
  3032. */
  3033. err = ssb_bus_powerup(bus, 0);
  3034. if (err) {
  3035. b43legacyerr(wl, "Bus powerup failed\n");
  3036. goto out;
  3037. }
  3038. /* Get the PHY type. */
  3039. if (dev->dev->id.revision >= 5) {
  3040. u32 tmshigh;
  3041. tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
  3042. have_gphy = !!(tmshigh & B43legacy_TMSHIGH_GPHY);
  3043. if (!have_gphy)
  3044. have_bphy = 1;
  3045. } else if (dev->dev->id.revision == 4)
  3046. have_gphy = 1;
  3047. else
  3048. have_bphy = 1;
  3049. /* Initialize LEDs structs. */
  3050. err = b43legacy_leds_init(dev);
  3051. if (err)
  3052. goto err_powerdown;
  3053. dev->phy.gmode = (have_gphy || have_bphy);
  3054. tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
  3055. b43legacy_wireless_core_reset(dev, tmp);
  3056. err = b43legacy_phy_versioning(dev);
  3057. if (err)
  3058. goto err_leds_exit;
  3059. /* Check if this device supports multiband. */
  3060. if (!pdev ||
  3061. (pdev->device != 0x4312 &&
  3062. pdev->device != 0x4319 &&
  3063. pdev->device != 0x4324)) {
  3064. /* No multiband support. */
  3065. have_bphy = 0;
  3066. have_gphy = 0;
  3067. switch (dev->phy.type) {
  3068. case B43legacy_PHYTYPE_B:
  3069. have_bphy = 1;
  3070. break;
  3071. case B43legacy_PHYTYPE_G:
  3072. have_gphy = 1;
  3073. break;
  3074. default:
  3075. B43legacy_BUG_ON(1);
  3076. }
  3077. }
  3078. dev->phy.gmode = (have_gphy || have_bphy);
  3079. tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
  3080. b43legacy_wireless_core_reset(dev, tmp);
  3081. err = b43legacy_validate_chipaccess(dev);
  3082. if (err)
  3083. goto err_leds_exit;
  3084. err = b43legacy_setup_modes(dev, have_bphy, have_gphy);
  3085. if (err)
  3086. goto err_leds_exit;
  3087. /* Now set some default "current_dev" */
  3088. if (!wl->current_dev)
  3089. wl->current_dev = dev;
  3090. INIT_WORK(&dev->restart_work, b43legacy_chip_reset);
  3091. b43legacy_radio_turn_off(dev);
  3092. b43legacy_switch_analog(dev, 0);
  3093. ssb_device_disable(dev->dev, 0);
  3094. ssb_bus_may_powerdown(bus);
  3095. out:
  3096. return err;
  3097. err_leds_exit:
  3098. b43legacy_leds_exit(dev);
  3099. err_powerdown:
  3100. ssb_bus_may_powerdown(bus);
  3101. return err;
  3102. }
  3103. static void b43legacy_one_core_detach(struct ssb_device *dev)
  3104. {
  3105. struct b43legacy_wldev *wldev;
  3106. struct b43legacy_wl *wl;
  3107. wldev = ssb_get_drvdata(dev);
  3108. wl = wldev->wl;
  3109. cancel_work_sync(&wldev->restart_work);
  3110. b43legacy_debugfs_remove_device(wldev);
  3111. b43legacy_wireless_core_detach(wldev);
  3112. list_del(&wldev->list);
  3113. wl->nr_devs--;
  3114. ssb_set_drvdata(dev, NULL);
  3115. kfree(wldev);
  3116. }
  3117. static int b43legacy_one_core_attach(struct ssb_device *dev,
  3118. struct b43legacy_wl *wl)
  3119. {
  3120. struct b43legacy_wldev *wldev;
  3121. struct pci_dev *pdev;
  3122. int err = -ENOMEM;
  3123. if (!list_empty(&wl->devlist)) {
  3124. /* We are not the first core on this chip. */
  3125. pdev = dev->bus->host_pci;
  3126. /* Only special chips support more than one wireless
  3127. * core, although some of the other chips have more than
  3128. * one wireless core as well. Check for this and
  3129. * bail out early.
  3130. */
  3131. if (!pdev ||
  3132. ((pdev->device != 0x4321) &&
  3133. (pdev->device != 0x4313) &&
  3134. (pdev->device != 0x431A))) {
  3135. b43legacydbg(wl, "Ignoring unconnected 802.11 core\n");
  3136. return -ENODEV;
  3137. }
  3138. }
  3139. wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
  3140. if (!wldev)
  3141. goto out;
  3142. wldev->dev = dev;
  3143. wldev->wl = wl;
  3144. b43legacy_set_status(wldev, B43legacy_STAT_UNINIT);
  3145. wldev->bad_frames_preempt = modparam_bad_frames_preempt;
  3146. tasklet_init(&wldev->isr_tasklet,
  3147. (void (*)(unsigned long))b43legacy_interrupt_tasklet,
  3148. (unsigned long)wldev);
  3149. if (modparam_pio)
  3150. wldev->__using_pio = 1;
  3151. INIT_LIST_HEAD(&wldev->list);
  3152. err = b43legacy_wireless_core_attach(wldev);
  3153. if (err)
  3154. goto err_kfree_wldev;
  3155. list_add(&wldev->list, &wl->devlist);
  3156. wl->nr_devs++;
  3157. ssb_set_drvdata(dev, wldev);
  3158. b43legacy_debugfs_add_device(wldev);
  3159. out:
  3160. return err;
  3161. err_kfree_wldev:
  3162. kfree(wldev);
  3163. return err;
  3164. }
  3165. static void b43legacy_sprom_fixup(struct ssb_bus *bus)
  3166. {
  3167. /* boardflags workarounds */
  3168. if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
  3169. bus->boardinfo.type == 0x4E &&
  3170. bus->boardinfo.rev > 0x40)
  3171. bus->sprom.r1.boardflags_lo |= B43legacy_BFL_PACTRL;
  3172. /* Convert Antennagain values to Q5.2 */
  3173. if (bus->sprom.r1.antenna_gain_bg == 0xFF)
  3174. bus->sprom.r1.antenna_gain_bg = 2; /* if unset, use 2 dBm */
  3175. bus->sprom.r1.antenna_gain_bg <<= 2;
  3176. }
  3177. static void b43legacy_wireless_exit(struct ssb_device *dev,
  3178. struct b43legacy_wl *wl)
  3179. {
  3180. struct ieee80211_hw *hw = wl->hw;
  3181. ssb_set_devtypedata(dev, NULL);
  3182. ieee80211_free_hw(hw);
  3183. }
  3184. static int b43legacy_wireless_init(struct ssb_device *dev)
  3185. {
  3186. struct ssb_sprom *sprom = &dev->bus->sprom;
  3187. struct ieee80211_hw *hw;
  3188. struct b43legacy_wl *wl;
  3189. int err = -ENOMEM;
  3190. b43legacy_sprom_fixup(dev->bus);
  3191. hw = ieee80211_alloc_hw(sizeof(*wl), &b43legacy_hw_ops);
  3192. if (!hw) {
  3193. b43legacyerr(NULL, "Could not allocate ieee80211 device\n");
  3194. goto out;
  3195. }
  3196. /* fill hw info */
  3197. hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
  3198. IEEE80211_HW_RX_INCLUDES_FCS;
  3199. hw->max_signal = 100;
  3200. hw->max_rssi = -110;
  3201. hw->max_noise = -110;
  3202. hw->queues = 1; /* FIXME: hardware has more queues */
  3203. SET_IEEE80211_DEV(hw, dev->dev);
  3204. if (is_valid_ether_addr(sprom->r1.et1mac))
  3205. SET_IEEE80211_PERM_ADDR(hw, sprom->r1.et1mac);
  3206. else
  3207. SET_IEEE80211_PERM_ADDR(hw, sprom->r1.il0mac);
  3208. /* Get and initialize struct b43legacy_wl */
  3209. wl = hw_to_b43legacy_wl(hw);
  3210. memset(wl, 0, sizeof(*wl));
  3211. wl->hw = hw;
  3212. spin_lock_init(&wl->irq_lock);
  3213. spin_lock_init(&wl->leds_lock);
  3214. mutex_init(&wl->mutex);
  3215. INIT_LIST_HEAD(&wl->devlist);
  3216. ssb_set_devtypedata(dev, wl);
  3217. b43legacyinfo(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
  3218. err = 0;
  3219. out:
  3220. return err;
  3221. }
  3222. static int b43legacy_probe(struct ssb_device *dev,
  3223. const struct ssb_device_id *id)
  3224. {
  3225. struct b43legacy_wl *wl;
  3226. int err;
  3227. int first = 0;
  3228. wl = ssb_get_devtypedata(dev);
  3229. if (!wl) {
  3230. /* Probing the first core - setup common struct b43legacy_wl */
  3231. first = 1;
  3232. err = b43legacy_wireless_init(dev);
  3233. if (err)
  3234. goto out;
  3235. wl = ssb_get_devtypedata(dev);
  3236. B43legacy_WARN_ON(!wl);
  3237. }
  3238. err = b43legacy_one_core_attach(dev, wl);
  3239. if (err)
  3240. goto err_wireless_exit;
  3241. if (first) {
  3242. err = ieee80211_register_hw(wl->hw);
  3243. if (err)
  3244. goto err_one_core_detach;
  3245. }
  3246. out:
  3247. return err;
  3248. err_one_core_detach:
  3249. b43legacy_one_core_detach(dev);
  3250. err_wireless_exit:
  3251. if (first)
  3252. b43legacy_wireless_exit(dev, wl);
  3253. return err;
  3254. }
  3255. static void b43legacy_remove(struct ssb_device *dev)
  3256. {
  3257. struct b43legacy_wl *wl = ssb_get_devtypedata(dev);
  3258. struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
  3259. B43legacy_WARN_ON(!wl);
  3260. if (wl->current_dev == wldev)
  3261. ieee80211_unregister_hw(wl->hw);
  3262. b43legacy_one_core_detach(dev);
  3263. if (list_empty(&wl->devlist))
  3264. /* Last core on the chip unregistered.
  3265. * We can destroy common struct b43legacy_wl.
  3266. */
  3267. b43legacy_wireless_exit(dev, wl);
  3268. }
  3269. /* Perform a hardware reset. This can be called from any context. */
  3270. void b43legacy_controller_restart(struct b43legacy_wldev *dev,
  3271. const char *reason)
  3272. {
  3273. /* Must avoid requeueing, if we are in shutdown. */
  3274. if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED)
  3275. return;
  3276. b43legacyinfo(dev->wl, "Controller RESET (%s) ...\n", reason);
  3277. queue_work(dev->wl->hw->workqueue, &dev->restart_work);
  3278. }
  3279. #ifdef CONFIG_PM
  3280. static int b43legacy_suspend(struct ssb_device *dev, pm_message_t state)
  3281. {
  3282. struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
  3283. struct b43legacy_wl *wl = wldev->wl;
  3284. b43legacydbg(wl, "Suspending...\n");
  3285. mutex_lock(&wl->mutex);
  3286. wldev->suspend_init_status = b43legacy_status(wldev);
  3287. if (wldev->suspend_init_status >= B43legacy_STAT_STARTED)
  3288. b43legacy_wireless_core_stop(wldev);
  3289. if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED)
  3290. b43legacy_wireless_core_exit(wldev);
  3291. mutex_unlock(&wl->mutex);
  3292. b43legacydbg(wl, "Device suspended.\n");
  3293. return 0;
  3294. }
  3295. static int b43legacy_resume(struct ssb_device *dev)
  3296. {
  3297. struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
  3298. struct b43legacy_wl *wl = wldev->wl;
  3299. int err = 0;
  3300. b43legacydbg(wl, "Resuming...\n");
  3301. mutex_lock(&wl->mutex);
  3302. if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED) {
  3303. err = b43legacy_wireless_core_init(wldev);
  3304. if (err) {
  3305. b43legacyerr(wl, "Resume failed at core init\n");
  3306. goto out;
  3307. }
  3308. }
  3309. if (wldev->suspend_init_status >= B43legacy_STAT_STARTED) {
  3310. err = b43legacy_wireless_core_start(wldev);
  3311. if (err) {
  3312. b43legacy_wireless_core_exit(wldev);
  3313. b43legacyerr(wl, "Resume failed at core start\n");
  3314. goto out;
  3315. }
  3316. }
  3317. mutex_unlock(&wl->mutex);
  3318. b43legacydbg(wl, "Device resumed.\n");
  3319. out:
  3320. return err;
  3321. }
  3322. #else /* CONFIG_PM */
  3323. # define b43legacy_suspend NULL
  3324. # define b43legacy_resume NULL
  3325. #endif /* CONFIG_PM */
  3326. static struct ssb_driver b43legacy_ssb_driver = {
  3327. .name = KBUILD_MODNAME,
  3328. .id_table = b43legacy_ssb_tbl,
  3329. .probe = b43legacy_probe,
  3330. .remove = b43legacy_remove,
  3331. .suspend = b43legacy_suspend,
  3332. .resume = b43legacy_resume,
  3333. };
  3334. static int __init b43legacy_init(void)
  3335. {
  3336. int err;
  3337. b43legacy_debugfs_init();
  3338. err = ssb_driver_register(&b43legacy_ssb_driver);
  3339. if (err)
  3340. goto err_dfs_exit;
  3341. return err;
  3342. err_dfs_exit:
  3343. b43legacy_debugfs_exit();
  3344. return err;
  3345. }
  3346. static void __exit b43legacy_exit(void)
  3347. {
  3348. ssb_driver_unregister(&b43legacy_ssb_driver);
  3349. b43legacy_debugfs_exit();
  3350. }
  3351. module_init(b43legacy_init)
  3352. module_exit(b43legacy_exit)