xmit.h 8.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257
  1. #ifndef B43_XMIT_H_
  2. #define B43_XMIT_H_
  3. #include "main.h"
  4. #define _b43_declare_plcp_hdr(size) \
  5. struct b43_plcp_hdr##size { \
  6. union { \
  7. __le32 data; \
  8. __u8 raw[size]; \
  9. } __attribute__((__packed__)); \
  10. } __attribute__((__packed__))
  11. /* struct b43_plcp_hdr4 */
  12. _b43_declare_plcp_hdr(4);
  13. /* struct b43_plcp_hdr6 */
  14. _b43_declare_plcp_hdr(6);
  15. #undef _b43_declare_plcp_hdr
  16. /* TX header for v4 firmware */
  17. struct b43_txhdr_fw4 {
  18. __le32 mac_ctl; /* MAC TX control */
  19. __le16 mac_frame_ctl; /* Copy of the FrameControl field */
  20. __le16 tx_fes_time_norm; /* TX FES Time Normal */
  21. __le16 phy_ctl; /* PHY TX control */
  22. __le16 phy_ctl_0; /* Unused */
  23. __le16 phy_ctl_1; /* Unused */
  24. __le16 phy_ctl_rts_0; /* Unused */
  25. __le16 phy_ctl_rts_1; /* Unused */
  26. __u8 phy_rate; /* PHY rate */
  27. __u8 phy_rate_rts; /* PHY rate for RTS/CTS */
  28. __u8 extra_ft; /* Extra Frame Types */
  29. __u8 chan_radio_code; /* Channel Radio Code */
  30. __u8 iv[16]; /* Encryption IV */
  31. __u8 tx_receiver[6]; /* TX Frame Receiver address */
  32. __le16 tx_fes_time_fb; /* TX FES Time Fallback */
  33. struct b43_plcp_hdr6 rts_plcp_fb; /* RTS fallback PLCP */
  34. __le16 rts_dur_fb; /* RTS fallback duration */
  35. struct b43_plcp_hdr6 plcp_fb; /* Fallback PLCP */
  36. __le16 dur_fb; /* Fallback duration */
  37. __le16 mm_dur_time; /* Unused */
  38. __le16 mm_dur_time_fb; /* Unused */
  39. __le32 time_stamp; /* Timestamp */
  40. PAD_BYTES(2);
  41. __le16 cookie; /* TX frame cookie */
  42. __le16 tx_status; /* TX status */
  43. struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP */
  44. __u8 rts_frame[16]; /* The RTS frame (if used) */
  45. PAD_BYTES(2);
  46. struct b43_plcp_hdr6 plcp; /* Main PLCP */
  47. } __attribute__ ((__packed__));
  48. /* MAC TX control */
  49. #define B43_TX4_MAC_KEYIDX 0x0FF00000 /* Security key index */
  50. #define B43_TX4_MAC_KEYIDX_SHIFT 20
  51. #define B43_TX4_MAC_KEYALG 0x00070000 /* Security key algorithm */
  52. #define B43_TX4_MAC_KEYALG_SHIFT 16
  53. #define B43_TX4_MAC_LIFETIME 0x00001000
  54. #define B43_TX4_MAC_FRAMEBURST 0x00000800
  55. #define B43_TX4_MAC_SENDCTS 0x00000400
  56. #define B43_TX4_MAC_AMPDU 0x00000300
  57. #define B43_TX4_MAC_AMPDU_SHIFT 8
  58. #define B43_TX4_MAC_5GHZ 0x00000080
  59. #define B43_TX4_MAC_IGNPMQ 0x00000020
  60. #define B43_TX4_MAC_HWSEQ 0x00000010 /* Use Hardware Sequence Number */
  61. #define B43_TX4_MAC_STMSDU 0x00000008 /* Start MSDU */
  62. #define B43_TX4_MAC_SENDRTS 0x00000004
  63. #define B43_TX4_MAC_LONGFRAME 0x00000002
  64. #define B43_TX4_MAC_ACK 0x00000001
  65. /* Extra Frame Types */
  66. #define B43_TX4_EFT_FBOFDM 0x0001 /* Data frame fallback rate type */
  67. #define B43_TX4_EFT_RTSOFDM 0x0004 /* RTS/CTS rate type */
  68. #define B43_TX4_EFT_RTSFBOFDM 0x0010 /* RTS/CTS fallback rate type */
  69. /* PHY TX control word */
  70. #define B43_TX4_PHY_OFDM 0x0001 /* Data frame rate type */
  71. #define B43_TX4_PHY_SHORTPRMBL 0x0010 /* Use short preamble */
  72. #define B43_TX4_PHY_ANT 0x03C0 /* Antenna selection */
  73. #define B43_TX4_PHY_ANT0 0x0000 /* Use antenna 0 */
  74. #define B43_TX4_PHY_ANT1 0x0100 /* Use antenna 1 */
  75. #define B43_TX4_PHY_ANTLAST 0x0300 /* Use last used antenna */
  76. void b43_generate_txhdr(struct b43_wldev *dev,
  77. u8 * txhdr,
  78. const unsigned char *fragment_data,
  79. unsigned int fragment_len,
  80. const struct ieee80211_tx_control *txctl, u16 cookie);
  81. /* Transmit Status */
  82. struct b43_txstatus {
  83. u16 cookie; /* The cookie from the txhdr */
  84. u16 seq; /* Sequence number */
  85. u8 phy_stat; /* PHY TX status */
  86. u8 frame_count; /* Frame transmit count */
  87. u8 rts_count; /* RTS transmit count */
  88. u8 supp_reason; /* Suppression reason */
  89. /* flags */
  90. u8 pm_indicated; /* PM mode indicated to AP */
  91. u8 intermediate; /* Intermediate status notification (not final) */
  92. u8 for_ampdu; /* Status is for an AMPDU (afterburner) */
  93. u8 acked; /* Wireless ACK received */
  94. };
  95. /* txstatus supp_reason values */
  96. enum {
  97. B43_TXST_SUPP_NONE, /* Not suppressed */
  98. B43_TXST_SUPP_PMQ, /* Suppressed due to PMQ entry */
  99. B43_TXST_SUPP_FLUSH, /* Suppressed due to flush request */
  100. B43_TXST_SUPP_PREV, /* Previous fragment failed */
  101. B43_TXST_SUPP_CHAN, /* Channel mismatch */
  102. B43_TXST_SUPP_LIFE, /* Lifetime expired */
  103. B43_TXST_SUPP_UNDER, /* Buffer underflow */
  104. B43_TXST_SUPP_ABNACK, /* Afterburner NACK */
  105. };
  106. /* Transmit Status as received through DMA/PIO on old chips */
  107. struct b43_hwtxstatus {
  108. PAD_BYTES(4);
  109. __le16 cookie;
  110. u8 flags;
  111. u8 count;
  112. PAD_BYTES(2);
  113. __le16 seq;
  114. u8 phy_stat;
  115. PAD_BYTES(1);
  116. } __attribute__ ((__packed__));
  117. /* Receive header for v4 firmware. */
  118. struct b43_rxhdr_fw4 {
  119. __le16 frame_len; /* Frame length */
  120. PAD_BYTES(2);
  121. __le16 phy_status0; /* PHY RX Status 0 */
  122. __u8 jssi; /* PHY RX Status 1: JSSI */
  123. __u8 sig_qual; /* PHY RX Status 1: Signal Quality */
  124. __le16 phy_status2; /* PHY RX Status 2 */
  125. __le16 phy_status3; /* PHY RX Status 3 */
  126. __le32 mac_status; /* MAC RX status */
  127. __le16 mac_time;
  128. __le16 channel;
  129. } __attribute__ ((__packed__));
  130. /* PHY RX Status 0 */
  131. #define B43_RX_PHYST0_GAINCTL 0x4000 /* Gain Control */
  132. #define B43_RX_PHYST0_PLCPHCF 0x0200
  133. #define B43_RX_PHYST0_PLCPFV 0x0100
  134. #define B43_RX_PHYST0_SHORTPRMBL 0x0080 /* Received with Short Preamble */
  135. #define B43_RX_PHYST0_LCRS 0x0040
  136. #define B43_RX_PHYST0_ANT 0x0020 /* Antenna */
  137. #define B43_RX_PHYST0_UNSRATE 0x0010
  138. #define B43_RX_PHYST0_CLIP 0x000C
  139. #define B43_RX_PHYST0_CLIP_SHIFT 2
  140. #define B43_RX_PHYST0_FTYPE 0x0003 /* Frame type */
  141. #define B43_RX_PHYST0_CCK 0x0000 /* Frame type: CCK */
  142. #define B43_RX_PHYST0_OFDM 0x0001 /* Frame type: OFDM */
  143. #define B43_RX_PHYST0_PRE_N 0x0002 /* Pre-standard N-PHY frame */
  144. #define B43_RX_PHYST0_STD_N 0x0003 /* Standard N-PHY frame */
  145. /* PHY RX Status 2 */
  146. #define B43_RX_PHYST2_LNAG 0xC000 /* LNA Gain */
  147. #define B43_RX_PHYST2_LNAG_SHIFT 14
  148. #define B43_RX_PHYST2_PNAG 0x3C00 /* PNA Gain */
  149. #define B43_RX_PHYST2_PNAG_SHIFT 10
  150. #define B43_RX_PHYST2_FOFF 0x03FF /* F offset */
  151. /* PHY RX Status 3 */
  152. #define B43_RX_PHYST3_DIGG 0x1800 /* DIG Gain */
  153. #define B43_RX_PHYST3_DIGG_SHIFT 11
  154. #define B43_RX_PHYST3_TRSTATE 0x0400 /* TR state */
  155. /* MAC RX Status */
  156. #define B43_RX_MAC_RXST_VALID 0x01000000 /* PHY RXST valid */
  157. #define B43_RX_MAC_TKIP_MICERR 0x00100000 /* TKIP MIC error */
  158. #define B43_RX_MAC_TKIP_MICATT 0x00080000 /* TKIP MIC attempted */
  159. #define B43_RX_MAC_AGGTYPE 0x00060000 /* Aggregation type */
  160. #define B43_RX_MAC_AGGTYPE_SHIFT 17
  161. #define B43_RX_MAC_AMSDU 0x00010000 /* A-MSDU mask */
  162. #define B43_RX_MAC_BEACONSENT 0x00008000 /* Beacon sent flag */
  163. #define B43_RX_MAC_KEYIDX 0x000007E0 /* Key index */
  164. #define B43_RX_MAC_KEYIDX_SHIFT 5
  165. #define B43_RX_MAC_DECERR 0x00000010 /* Decrypt error */
  166. #define B43_RX_MAC_DEC 0x00000008 /* Decryption attempted */
  167. #define B43_RX_MAC_PADDING 0x00000004 /* Pad bytes present */
  168. #define B43_RX_MAC_RESP 0x00000002 /* Response frame transmitted */
  169. #define B43_RX_MAC_FCSERR 0x00000001 /* FCS error */
  170. /* RX channel */
  171. #define B43_RX_CHAN_40MHZ 0x1000 /* 40 Mhz channel width */
  172. #define B43_RX_CHAN_5GHZ 0x0800 /* 5 Ghz band */
  173. #define B43_RX_CHAN_ID 0x07F8 /* Channel ID */
  174. #define B43_RX_CHAN_ID_SHIFT 3
  175. #define B43_RX_CHAN_PHYTYPE 0x0007 /* PHY type */
  176. u8 b43_plcp_get_ratecode_cck(const u8 bitrate);
  177. u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate);
  178. void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp,
  179. const u16 octets, const u8 bitrate);
  180. void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr);
  181. void b43_handle_txstatus(struct b43_wldev *dev,
  182. const struct b43_txstatus *status);
  183. void b43_handle_hwtxstatus(struct b43_wldev *dev,
  184. const struct b43_hwtxstatus *hw);
  185. void b43_tx_suspend(struct b43_wldev *dev);
  186. void b43_tx_resume(struct b43_wldev *dev);
  187. #define B43_NR_QOSPARMS 22
  188. enum {
  189. B43_QOSPARM_TXOP = 0,
  190. B43_QOSPARM_CWMIN,
  191. B43_QOSPARM_CWMAX,
  192. B43_QOSPARM_CWCUR,
  193. B43_QOSPARM_AIFS,
  194. B43_QOSPARM_BSLOTS,
  195. B43_QOSPARM_REGGAP,
  196. B43_QOSPARM_STATUS,
  197. };
  198. void b43_qos_init(struct b43_wldev *dev);
  199. /* Helper functions for converting the key-table index from "firmware-format"
  200. * to "raw-format" and back. The firmware API changed for this at some revision.
  201. * We need to account for that here. */
  202. static inline int b43_new_kidx_api(struct b43_wldev *dev)
  203. {
  204. /* FIXME: Not sure the change was at rev 351 */
  205. return (dev->fw.rev >= 351);
  206. }
  207. static inline u8 b43_kidx_to_fw(struct b43_wldev *dev, u8 raw_kidx)
  208. {
  209. u8 firmware_kidx;
  210. if (b43_new_kidx_api(dev)) {
  211. firmware_kidx = raw_kidx;
  212. } else {
  213. if (raw_kidx >= 4) /* Is per STA key? */
  214. firmware_kidx = raw_kidx - 4;
  215. else
  216. firmware_kidx = raw_kidx; /* TX default key */
  217. }
  218. return firmware_kidx;
  219. }
  220. static inline u8 b43_kidx_to_raw(struct b43_wldev *dev, u8 firmware_kidx)
  221. {
  222. u8 raw_kidx;
  223. if (b43_new_kidx_api(dev))
  224. raw_kidx = firmware_kidx;
  225. else
  226. raw_kidx = firmware_kidx + 4; /* RX default keys or per STA keys */
  227. return raw_kidx;
  228. }
  229. #endif /* B43_XMIT_H_ */