pasemi_mac.c 37 KB

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  1. /*
  2. * Copyright (C) 2006-2007 PA Semi, Inc
  3. *
  4. * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/init.h>
  20. #include <linux/module.h>
  21. #include <linux/pci.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/dmaengine.h>
  24. #include <linux/delay.h>
  25. #include <linux/netdevice.h>
  26. #include <linux/etherdevice.h>
  27. #include <asm/dma-mapping.h>
  28. #include <linux/in.h>
  29. #include <linux/skbuff.h>
  30. #include <linux/ip.h>
  31. #include <linux/tcp.h>
  32. #include <net/checksum.h>
  33. #include <asm/irq.h>
  34. #include <asm/firmware.h>
  35. #include "pasemi_mac.h"
  36. /* We have our own align, since ppc64 in general has it at 0 because
  37. * of design flaws in some of the server bridge chips. However, for
  38. * PWRficient doing the unaligned copies is more expensive than doing
  39. * unaligned DMA, so make sure the data is aligned instead.
  40. */
  41. #define LOCAL_SKB_ALIGN 2
  42. /* TODO list
  43. *
  44. * - Multicast support
  45. * - Large MTU support
  46. * - SW LRO
  47. * - Multiqueue RX/TX
  48. */
  49. /* Must be a power of two */
  50. #define RX_RING_SIZE 4096
  51. #define TX_RING_SIZE 4096
  52. #define DEFAULT_MSG_ENABLE \
  53. (NETIF_MSG_DRV | \
  54. NETIF_MSG_PROBE | \
  55. NETIF_MSG_LINK | \
  56. NETIF_MSG_TIMER | \
  57. NETIF_MSG_IFDOWN | \
  58. NETIF_MSG_IFUP | \
  59. NETIF_MSG_RX_ERR | \
  60. NETIF_MSG_TX_ERR)
  61. #define TX_RING(mac, num) ((mac)->tx->ring[(num) & (TX_RING_SIZE-1)])
  62. #define TX_RING_INFO(mac, num) ((mac)->tx->ring_info[(num) & (TX_RING_SIZE-1)])
  63. #define RX_RING(mac, num) ((mac)->rx->ring[(num) & (RX_RING_SIZE-1)])
  64. #define RX_RING_INFO(mac, num) ((mac)->rx->ring_info[(num) & (RX_RING_SIZE-1)])
  65. #define RX_BUFF(mac, num) ((mac)->rx->buffers[(num) & (RX_RING_SIZE-1)])
  66. #define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \
  67. & ((ring)->size - 1))
  68. #define RING_AVAIL(ring) ((ring->size) - RING_USED(ring))
  69. #define BUF_SIZE 1646 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
  70. MODULE_LICENSE("GPL");
  71. MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
  72. MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver");
  73. static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */
  74. module_param(debug, int, 0);
  75. MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value");
  76. static struct pasdma_status *dma_status;
  77. static int translation_enabled(void)
  78. {
  79. #if defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE)
  80. return 1;
  81. #else
  82. return firmware_has_feature(FW_FEATURE_LPAR);
  83. #endif
  84. }
  85. static void write_iob_reg(struct pasemi_mac *mac, unsigned int reg,
  86. unsigned int val)
  87. {
  88. out_le32(mac->iob_regs+reg, val);
  89. }
  90. static unsigned int read_mac_reg(struct pasemi_mac *mac, unsigned int reg)
  91. {
  92. return in_le32(mac->regs+reg);
  93. }
  94. static void write_mac_reg(struct pasemi_mac *mac, unsigned int reg,
  95. unsigned int val)
  96. {
  97. out_le32(mac->regs+reg, val);
  98. }
  99. static unsigned int read_dma_reg(struct pasemi_mac *mac, unsigned int reg)
  100. {
  101. return in_le32(mac->dma_regs+reg);
  102. }
  103. static void write_dma_reg(struct pasemi_mac *mac, unsigned int reg,
  104. unsigned int val)
  105. {
  106. out_le32(mac->dma_regs+reg, val);
  107. }
  108. static int pasemi_get_mac_addr(struct pasemi_mac *mac)
  109. {
  110. struct pci_dev *pdev = mac->pdev;
  111. struct device_node *dn = pci_device_to_OF_node(pdev);
  112. int len;
  113. const u8 *maddr;
  114. u8 addr[6];
  115. if (!dn) {
  116. dev_dbg(&pdev->dev,
  117. "No device node for mac, not configuring\n");
  118. return -ENOENT;
  119. }
  120. maddr = of_get_property(dn, "local-mac-address", &len);
  121. if (maddr && len == 6) {
  122. memcpy(mac->mac_addr, maddr, 6);
  123. return 0;
  124. }
  125. /* Some old versions of firmware mistakenly uses mac-address
  126. * (and as a string) instead of a byte array in local-mac-address.
  127. */
  128. if (maddr == NULL)
  129. maddr = of_get_property(dn, "mac-address", NULL);
  130. if (maddr == NULL) {
  131. dev_warn(&pdev->dev,
  132. "no mac address in device tree, not configuring\n");
  133. return -ENOENT;
  134. }
  135. if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0],
  136. &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) {
  137. dev_warn(&pdev->dev,
  138. "can't parse mac address, not configuring\n");
  139. return -EINVAL;
  140. }
  141. memcpy(mac->mac_addr, addr, 6);
  142. return 0;
  143. }
  144. static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac,
  145. struct sk_buff *skb,
  146. dma_addr_t *dmas)
  147. {
  148. int f;
  149. int nfrags = skb_shinfo(skb)->nr_frags;
  150. pci_unmap_single(mac->dma_pdev, dmas[0], skb_headlen(skb),
  151. PCI_DMA_TODEVICE);
  152. for (f = 0; f < nfrags; f++) {
  153. skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
  154. pci_unmap_page(mac->dma_pdev, dmas[f+1], frag->size,
  155. PCI_DMA_TODEVICE);
  156. }
  157. dev_kfree_skb_irq(skb);
  158. /* Freed descriptor slot + main SKB ptr + nfrags additional ptrs,
  159. * aligned up to a power of 2
  160. */
  161. return (nfrags + 3) & ~1;
  162. }
  163. static int pasemi_mac_setup_rx_resources(struct net_device *dev)
  164. {
  165. struct pasemi_mac_rxring *ring;
  166. struct pasemi_mac *mac = netdev_priv(dev);
  167. int chan_id = mac->dma_rxch;
  168. unsigned int cfg;
  169. ring = kzalloc(sizeof(*ring), GFP_KERNEL);
  170. if (!ring)
  171. goto out_ring;
  172. spin_lock_init(&ring->lock);
  173. ring->size = RX_RING_SIZE;
  174. ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
  175. RX_RING_SIZE, GFP_KERNEL);
  176. if (!ring->ring_info)
  177. goto out_ring_info;
  178. /* Allocate descriptors */
  179. ring->ring = dma_alloc_coherent(&mac->dma_pdev->dev,
  180. RX_RING_SIZE * sizeof(u64),
  181. &ring->dma, GFP_KERNEL);
  182. if (!ring->ring)
  183. goto out_ring_desc;
  184. memset(ring->ring, 0, RX_RING_SIZE * sizeof(u64));
  185. ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev,
  186. RX_RING_SIZE * sizeof(u64),
  187. &ring->buf_dma, GFP_KERNEL);
  188. if (!ring->buffers)
  189. goto out_buffers;
  190. memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64));
  191. write_dma_reg(mac, PAS_DMA_RXCHAN_BASEL(chan_id), PAS_DMA_RXCHAN_BASEL_BRBL(ring->dma));
  192. write_dma_reg(mac, PAS_DMA_RXCHAN_BASEU(chan_id),
  193. PAS_DMA_RXCHAN_BASEU_BRBH(ring->dma >> 32) |
  194. PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 3));
  195. cfg = PAS_DMA_RXCHAN_CFG_HBU(2);
  196. if (translation_enabled())
  197. cfg |= PAS_DMA_RXCHAN_CFG_CTR;
  198. write_dma_reg(mac, PAS_DMA_RXCHAN_CFG(chan_id), cfg);
  199. write_dma_reg(mac, PAS_DMA_RXINT_BASEL(mac->dma_if),
  200. PAS_DMA_RXINT_BASEL_BRBL(ring->buf_dma));
  201. write_dma_reg(mac, PAS_DMA_RXINT_BASEU(mac->dma_if),
  202. PAS_DMA_RXINT_BASEU_BRBH(ring->buf_dma >> 32) |
  203. PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3));
  204. cfg = PAS_DMA_RXINT_CFG_DHL(3) | PAS_DMA_RXINT_CFG_L2 |
  205. PAS_DMA_RXINT_CFG_LW | PAS_DMA_RXINT_CFG_RBP |
  206. PAS_DMA_RXINT_CFG_HEN;
  207. if (translation_enabled())
  208. cfg |= PAS_DMA_RXINT_CFG_ITRR | PAS_DMA_RXINT_CFG_ITR;
  209. write_dma_reg(mac, PAS_DMA_RXINT_CFG(mac->dma_if), cfg);
  210. ring->next_to_fill = 0;
  211. ring->next_to_clean = 0;
  212. snprintf(ring->irq_name, sizeof(ring->irq_name),
  213. "%s rx", dev->name);
  214. mac->rx = ring;
  215. return 0;
  216. out_buffers:
  217. dma_free_coherent(&mac->dma_pdev->dev,
  218. RX_RING_SIZE * sizeof(u64),
  219. mac->rx->ring, mac->rx->dma);
  220. out_ring_desc:
  221. kfree(ring->ring_info);
  222. out_ring_info:
  223. kfree(ring);
  224. out_ring:
  225. return -ENOMEM;
  226. }
  227. static int pasemi_mac_setup_tx_resources(struct net_device *dev)
  228. {
  229. struct pasemi_mac *mac = netdev_priv(dev);
  230. u32 val;
  231. int chan_id = mac->dma_txch;
  232. struct pasemi_mac_txring *ring;
  233. unsigned int cfg;
  234. ring = kzalloc(sizeof(*ring), GFP_KERNEL);
  235. if (!ring)
  236. goto out_ring;
  237. spin_lock_init(&ring->lock);
  238. ring->size = TX_RING_SIZE;
  239. ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
  240. TX_RING_SIZE, GFP_KERNEL);
  241. if (!ring->ring_info)
  242. goto out_ring_info;
  243. /* Allocate descriptors */
  244. ring->ring = dma_alloc_coherent(&mac->dma_pdev->dev,
  245. TX_RING_SIZE * sizeof(u64),
  246. &ring->dma, GFP_KERNEL);
  247. if (!ring->ring)
  248. goto out_ring_desc;
  249. memset(ring->ring, 0, TX_RING_SIZE * sizeof(u64));
  250. write_dma_reg(mac, PAS_DMA_TXCHAN_BASEL(chan_id),
  251. PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma));
  252. val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32);
  253. val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3);
  254. write_dma_reg(mac, PAS_DMA_TXCHAN_BASEU(chan_id), val);
  255. cfg = PAS_DMA_TXCHAN_CFG_TY_IFACE |
  256. PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) |
  257. PAS_DMA_TXCHAN_CFG_UP |
  258. PAS_DMA_TXCHAN_CFG_WT(2);
  259. if (translation_enabled())
  260. cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR;
  261. write_dma_reg(mac, PAS_DMA_TXCHAN_CFG(chan_id), cfg);
  262. ring->next_to_fill = 0;
  263. ring->next_to_clean = 0;
  264. snprintf(ring->irq_name, sizeof(ring->irq_name),
  265. "%s tx", dev->name);
  266. mac->tx = ring;
  267. return 0;
  268. out_ring_desc:
  269. kfree(ring->ring_info);
  270. out_ring_info:
  271. kfree(ring);
  272. out_ring:
  273. return -ENOMEM;
  274. }
  275. static void pasemi_mac_free_tx_resources(struct net_device *dev)
  276. {
  277. struct pasemi_mac *mac = netdev_priv(dev);
  278. unsigned int i, j;
  279. struct pasemi_mac_buffer *info;
  280. dma_addr_t dmas[MAX_SKB_FRAGS+1];
  281. int freed;
  282. int start, limit;
  283. start = mac->tx->next_to_clean;
  284. limit = mac->tx->next_to_fill;
  285. /* Compensate for when fill has wrapped and clean has not */
  286. if (start > limit)
  287. limit += TX_RING_SIZE;
  288. for (i = start; i < limit; i += freed) {
  289. info = &TX_RING_INFO(mac, i+1);
  290. if (info->dma && info->skb) {
  291. for (j = 0; j <= skb_shinfo(info->skb)->nr_frags; j++)
  292. dmas[j] = TX_RING_INFO(mac, i+1+j).dma;
  293. freed = pasemi_mac_unmap_tx_skb(mac, info->skb, dmas);
  294. } else
  295. freed = 2;
  296. }
  297. for (i = 0; i < TX_RING_SIZE; i++)
  298. TX_RING(mac, i) = 0;
  299. dma_free_coherent(&mac->dma_pdev->dev,
  300. TX_RING_SIZE * sizeof(u64),
  301. mac->tx->ring, mac->tx->dma);
  302. kfree(mac->tx->ring_info);
  303. kfree(mac->tx);
  304. mac->tx = NULL;
  305. }
  306. static void pasemi_mac_free_rx_resources(struct net_device *dev)
  307. {
  308. struct pasemi_mac *mac = netdev_priv(dev);
  309. unsigned int i;
  310. struct pasemi_mac_buffer *info;
  311. for (i = 0; i < RX_RING_SIZE; i++) {
  312. info = &RX_RING_INFO(mac, i);
  313. if (info->skb && info->dma) {
  314. pci_unmap_single(mac->dma_pdev,
  315. info->dma,
  316. info->skb->len,
  317. PCI_DMA_FROMDEVICE);
  318. dev_kfree_skb_any(info->skb);
  319. }
  320. info->dma = 0;
  321. info->skb = NULL;
  322. }
  323. for (i = 0; i < RX_RING_SIZE; i++)
  324. RX_RING(mac, i) = 0;
  325. dma_free_coherent(&mac->dma_pdev->dev,
  326. RX_RING_SIZE * sizeof(u64),
  327. mac->rx->ring, mac->rx->dma);
  328. dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64),
  329. mac->rx->buffers, mac->rx->buf_dma);
  330. kfree(mac->rx->ring_info);
  331. kfree(mac->rx);
  332. mac->rx = NULL;
  333. }
  334. static void pasemi_mac_replenish_rx_ring(struct net_device *dev, int limit)
  335. {
  336. struct pasemi_mac *mac = netdev_priv(dev);
  337. int fill, count;
  338. if (limit <= 0)
  339. return;
  340. fill = mac->rx->next_to_fill;
  341. for (count = 0; count < limit; count++) {
  342. struct pasemi_mac_buffer *info = &RX_RING_INFO(mac, fill);
  343. u64 *buff = &RX_BUFF(mac, fill);
  344. struct sk_buff *skb;
  345. dma_addr_t dma;
  346. /* Entry in use? */
  347. WARN_ON(*buff);
  348. /* skb might still be in there for recycle on short receives */
  349. if (info->skb)
  350. skb = info->skb;
  351. else {
  352. skb = dev_alloc_skb(BUF_SIZE);
  353. skb_reserve(skb, LOCAL_SKB_ALIGN);
  354. }
  355. if (unlikely(!skb))
  356. break;
  357. dma = pci_map_single(mac->dma_pdev, skb->data,
  358. BUF_SIZE - LOCAL_SKB_ALIGN,
  359. PCI_DMA_FROMDEVICE);
  360. if (unlikely(dma_mapping_error(dma))) {
  361. dev_kfree_skb_irq(info->skb);
  362. break;
  363. }
  364. info->skb = skb;
  365. info->dma = dma;
  366. *buff = XCT_RXB_LEN(BUF_SIZE) | XCT_RXB_ADDR(dma);
  367. fill++;
  368. }
  369. wmb();
  370. write_dma_reg(mac, PAS_DMA_RXINT_INCR(mac->dma_if), count);
  371. mac->rx->next_to_fill = (mac->rx->next_to_fill + count) &
  372. (RX_RING_SIZE - 1);
  373. }
  374. static void pasemi_mac_restart_rx_intr(struct pasemi_mac *mac)
  375. {
  376. unsigned int reg, pcnt;
  377. /* Re-enable packet count interrupts: finally
  378. * ack the packet count interrupt we got in rx_intr.
  379. */
  380. pcnt = *mac->rx_status & PAS_STATUS_PCNT_M;
  381. reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC;
  382. write_iob_reg(mac, PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch), reg);
  383. }
  384. static void pasemi_mac_restart_tx_intr(struct pasemi_mac *mac)
  385. {
  386. unsigned int reg, pcnt;
  387. /* Re-enable packet count interrupts */
  388. pcnt = *mac->tx_status & PAS_STATUS_PCNT_M;
  389. reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC;
  390. write_iob_reg(mac, PAS_IOB_DMA_TXCH_RESET(mac->dma_txch), reg);
  391. }
  392. static inline void pasemi_mac_rx_error(struct pasemi_mac *mac, u64 macrx)
  393. {
  394. unsigned int rcmdsta, ccmdsta;
  395. if (!netif_msg_rx_err(mac))
  396. return;
  397. rcmdsta = read_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
  398. ccmdsta = read_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch));
  399. printk(KERN_ERR "pasemi_mac: rx error. macrx %016lx, rx status %lx\n",
  400. macrx, *mac->rx_status);
  401. printk(KERN_ERR "pasemi_mac: rcmdsta %08x ccmdsta %08x\n",
  402. rcmdsta, ccmdsta);
  403. }
  404. static inline void pasemi_mac_tx_error(struct pasemi_mac *mac, u64 mactx)
  405. {
  406. unsigned int cmdsta;
  407. if (!netif_msg_tx_err(mac))
  408. return;
  409. cmdsta = read_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch));
  410. printk(KERN_ERR "pasemi_mac: tx error. mactx 0x%016lx, "\
  411. "tx status 0x%016lx\n", mactx, *mac->tx_status);
  412. printk(KERN_ERR "pasemi_mac: tcmdsta 0x%08x\n", cmdsta);
  413. }
  414. static int pasemi_mac_clean_rx(struct pasemi_mac *mac, int limit)
  415. {
  416. unsigned int n;
  417. int count;
  418. struct pasemi_mac_buffer *info;
  419. struct sk_buff *skb;
  420. unsigned int len;
  421. u64 macrx;
  422. dma_addr_t dma;
  423. int buf_index;
  424. u64 eval;
  425. spin_lock(&mac->rx->lock);
  426. n = mac->rx->next_to_clean;
  427. prefetch(&RX_RING(mac, n));
  428. for (count = 0; count < limit; count++) {
  429. macrx = RX_RING(mac, n);
  430. if ((macrx & XCT_MACRX_E) ||
  431. (*mac->rx_status & PAS_STATUS_ERROR))
  432. pasemi_mac_rx_error(mac, macrx);
  433. if (!(macrx & XCT_MACRX_O))
  434. break;
  435. info = NULL;
  436. BUG_ON(!(macrx & XCT_MACRX_RR_8BRES));
  437. eval = (RX_RING(mac, n+1) & XCT_RXRES_8B_EVAL_M) >>
  438. XCT_RXRES_8B_EVAL_S;
  439. buf_index = eval-1;
  440. dma = (RX_RING(mac, n+2) & XCT_PTR_ADDR_M);
  441. info = &RX_RING_INFO(mac, buf_index);
  442. skb = info->skb;
  443. prefetch(skb);
  444. prefetch(&skb->data_len);
  445. len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S;
  446. pci_unmap_single(mac->dma_pdev, dma, len, PCI_DMA_FROMDEVICE);
  447. if (macrx & XCT_MACRX_CRC) {
  448. /* CRC error flagged */
  449. mac->netdev->stats.rx_errors++;
  450. mac->netdev->stats.rx_crc_errors++;
  451. /* No need to free skb, it'll be reused */
  452. goto next;
  453. }
  454. if (len < 256) {
  455. struct sk_buff *new_skb;
  456. new_skb = netdev_alloc_skb(mac->netdev,
  457. len + LOCAL_SKB_ALIGN);
  458. if (new_skb) {
  459. skb_reserve(new_skb, LOCAL_SKB_ALIGN);
  460. memcpy(new_skb->data, skb->data, len);
  461. /* save the skb in buffer_info as good */
  462. skb = new_skb;
  463. }
  464. /* else just continue with the old one */
  465. } else
  466. info->skb = NULL;
  467. info->dma = 0;
  468. /* Don't include CRC */
  469. skb_put(skb, len-4);
  470. if (likely((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK)) {
  471. skb->ip_summed = CHECKSUM_UNNECESSARY;
  472. skb->csum = (macrx & XCT_MACRX_CSUM_M) >>
  473. XCT_MACRX_CSUM_S;
  474. } else
  475. skb->ip_summed = CHECKSUM_NONE;
  476. mac->netdev->stats.rx_bytes += len;
  477. mac->netdev->stats.rx_packets++;
  478. skb->protocol = eth_type_trans(skb, mac->netdev);
  479. netif_receive_skb(skb);
  480. next:
  481. RX_RING(mac, n) = 0;
  482. RX_RING(mac, n+1) = 0;
  483. /* Need to zero it out since hardware doesn't, since the
  484. * replenish loop uses it to tell when it's done.
  485. */
  486. RX_BUFF(mac, buf_index) = 0;
  487. n += 4;
  488. }
  489. if (n > RX_RING_SIZE) {
  490. /* Errata 5971 workaround: L2 target of headers */
  491. write_iob_reg(mac, PAS_IOB_COM_PKTHDRCNT, 0);
  492. n &= (RX_RING_SIZE-1);
  493. }
  494. mac->rx->next_to_clean = n;
  495. /* Increase is in number of 16-byte entries, and since each descriptor
  496. * with an 8BRES takes up 3x8 bytes (padded to 4x8), increase with
  497. * count*2.
  498. */
  499. write_dma_reg(mac, PAS_DMA_RXCHAN_INCR(mac->dma_rxch), count << 1);
  500. pasemi_mac_replenish_rx_ring(mac->netdev, count);
  501. spin_unlock(&mac->rx->lock);
  502. return count;
  503. }
  504. /* Can't make this too large or we blow the kernel stack limits */
  505. #define TX_CLEAN_BATCHSIZE (128/MAX_SKB_FRAGS)
  506. static int pasemi_mac_clean_tx(struct pasemi_mac *mac)
  507. {
  508. int i, j;
  509. unsigned int start, descr_count, buf_count, batch_limit;
  510. unsigned int ring_limit;
  511. unsigned int total_count;
  512. unsigned long flags;
  513. struct sk_buff *skbs[TX_CLEAN_BATCHSIZE];
  514. dma_addr_t dmas[TX_CLEAN_BATCHSIZE][MAX_SKB_FRAGS+1];
  515. total_count = 0;
  516. batch_limit = TX_CLEAN_BATCHSIZE;
  517. restart:
  518. spin_lock_irqsave(&mac->tx->lock, flags);
  519. start = mac->tx->next_to_clean;
  520. ring_limit = mac->tx->next_to_fill;
  521. /* Compensate for when fill has wrapped but clean has not */
  522. if (start > ring_limit)
  523. ring_limit += TX_RING_SIZE;
  524. buf_count = 0;
  525. descr_count = 0;
  526. for (i = start;
  527. descr_count < batch_limit && i < ring_limit;
  528. i += buf_count) {
  529. u64 mactx = TX_RING(mac, i);
  530. struct sk_buff *skb;
  531. if ((mactx & XCT_MACTX_E) ||
  532. (*mac->tx_status & PAS_STATUS_ERROR))
  533. pasemi_mac_tx_error(mac, mactx);
  534. if (unlikely(mactx & XCT_MACTX_O))
  535. /* Not yet transmitted */
  536. break;
  537. skb = TX_RING_INFO(mac, i+1).skb;
  538. skbs[descr_count] = skb;
  539. buf_count = 2 + skb_shinfo(skb)->nr_frags;
  540. for (j = 0; j <= skb_shinfo(skb)->nr_frags; j++)
  541. dmas[descr_count][j] = TX_RING_INFO(mac, i+1+j).dma;
  542. TX_RING(mac, i) = 0;
  543. TX_RING(mac, i+1) = 0;
  544. /* Since we always fill with an even number of entries, make
  545. * sure we skip any unused one at the end as well.
  546. */
  547. if (buf_count & 1)
  548. buf_count++;
  549. descr_count++;
  550. }
  551. mac->tx->next_to_clean = i & (TX_RING_SIZE-1);
  552. spin_unlock_irqrestore(&mac->tx->lock, flags);
  553. netif_wake_queue(mac->netdev);
  554. for (i = 0; i < descr_count; i++)
  555. pasemi_mac_unmap_tx_skb(mac, skbs[i], dmas[i]);
  556. total_count += descr_count;
  557. /* If the batch was full, try to clean more */
  558. if (descr_count == batch_limit)
  559. goto restart;
  560. return total_count;
  561. }
  562. static irqreturn_t pasemi_mac_rx_intr(int irq, void *data)
  563. {
  564. struct net_device *dev = data;
  565. struct pasemi_mac *mac = netdev_priv(dev);
  566. unsigned int reg;
  567. if (!(*mac->rx_status & PAS_STATUS_CAUSE_M))
  568. return IRQ_NONE;
  569. /* Don't reset packet count so it won't fire again but clear
  570. * all others.
  571. */
  572. reg = 0;
  573. if (*mac->rx_status & PAS_STATUS_SOFT)
  574. reg |= PAS_IOB_DMA_RXCH_RESET_SINTC;
  575. if (*mac->rx_status & PAS_STATUS_ERROR)
  576. reg |= PAS_IOB_DMA_RXCH_RESET_DINTC;
  577. if (*mac->rx_status & PAS_STATUS_TIMER)
  578. reg |= PAS_IOB_DMA_RXCH_RESET_TINTC;
  579. netif_rx_schedule(dev, &mac->napi);
  580. write_iob_reg(mac, PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch), reg);
  581. return IRQ_HANDLED;
  582. }
  583. static irqreturn_t pasemi_mac_tx_intr(int irq, void *data)
  584. {
  585. struct net_device *dev = data;
  586. struct pasemi_mac *mac = netdev_priv(dev);
  587. unsigned int reg, pcnt;
  588. if (!(*mac->tx_status & PAS_STATUS_CAUSE_M))
  589. return IRQ_NONE;
  590. pasemi_mac_clean_tx(mac);
  591. pcnt = *mac->tx_status & PAS_STATUS_PCNT_M;
  592. reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC;
  593. if (*mac->tx_status & PAS_STATUS_SOFT)
  594. reg |= PAS_IOB_DMA_TXCH_RESET_SINTC;
  595. if (*mac->tx_status & PAS_STATUS_ERROR)
  596. reg |= PAS_IOB_DMA_TXCH_RESET_DINTC;
  597. write_iob_reg(mac, PAS_IOB_DMA_TXCH_RESET(mac->dma_txch), reg);
  598. return IRQ_HANDLED;
  599. }
  600. static void pasemi_adjust_link(struct net_device *dev)
  601. {
  602. struct pasemi_mac *mac = netdev_priv(dev);
  603. int msg;
  604. unsigned int flags;
  605. unsigned int new_flags;
  606. if (!mac->phydev->link) {
  607. /* If no link, MAC speed settings don't matter. Just report
  608. * link down and return.
  609. */
  610. if (mac->link && netif_msg_link(mac))
  611. printk(KERN_INFO "%s: Link is down.\n", dev->name);
  612. netif_carrier_off(dev);
  613. mac->link = 0;
  614. return;
  615. } else
  616. netif_carrier_on(dev);
  617. flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
  618. new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M |
  619. PAS_MAC_CFG_PCFG_TSR_M);
  620. if (!mac->phydev->duplex)
  621. new_flags |= PAS_MAC_CFG_PCFG_HD;
  622. switch (mac->phydev->speed) {
  623. case 1000:
  624. new_flags |= PAS_MAC_CFG_PCFG_SPD_1G |
  625. PAS_MAC_CFG_PCFG_TSR_1G;
  626. break;
  627. case 100:
  628. new_flags |= PAS_MAC_CFG_PCFG_SPD_100M |
  629. PAS_MAC_CFG_PCFG_TSR_100M;
  630. break;
  631. case 10:
  632. new_flags |= PAS_MAC_CFG_PCFG_SPD_10M |
  633. PAS_MAC_CFG_PCFG_TSR_10M;
  634. break;
  635. default:
  636. printk("Unsupported speed %d\n", mac->phydev->speed);
  637. }
  638. /* Print on link or speed/duplex change */
  639. msg = mac->link != mac->phydev->link || flags != new_flags;
  640. mac->duplex = mac->phydev->duplex;
  641. mac->speed = mac->phydev->speed;
  642. mac->link = mac->phydev->link;
  643. if (new_flags != flags)
  644. write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags);
  645. if (msg && netif_msg_link(mac))
  646. printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n",
  647. dev->name, mac->speed, mac->duplex ? "full" : "half");
  648. }
  649. static int pasemi_mac_phy_init(struct net_device *dev)
  650. {
  651. struct pasemi_mac *mac = netdev_priv(dev);
  652. struct device_node *dn, *phy_dn;
  653. struct phy_device *phydev;
  654. unsigned int phy_id;
  655. const phandle *ph;
  656. const unsigned int *prop;
  657. struct resource r;
  658. int ret;
  659. dn = pci_device_to_OF_node(mac->pdev);
  660. ph = of_get_property(dn, "phy-handle", NULL);
  661. if (!ph)
  662. return -ENODEV;
  663. phy_dn = of_find_node_by_phandle(*ph);
  664. prop = of_get_property(phy_dn, "reg", NULL);
  665. ret = of_address_to_resource(phy_dn->parent, 0, &r);
  666. if (ret)
  667. goto err;
  668. phy_id = *prop;
  669. snprintf(mac->phy_id, BUS_ID_SIZE, PHY_ID_FMT, (int)r.start, phy_id);
  670. of_node_put(phy_dn);
  671. mac->link = 0;
  672. mac->speed = 0;
  673. mac->duplex = -1;
  674. phydev = phy_connect(dev, mac->phy_id, &pasemi_adjust_link, 0, PHY_INTERFACE_MODE_SGMII);
  675. if (IS_ERR(phydev)) {
  676. printk(KERN_ERR "%s: Could not attach to phy\n", dev->name);
  677. return PTR_ERR(phydev);
  678. }
  679. mac->phydev = phydev;
  680. return 0;
  681. err:
  682. of_node_put(phy_dn);
  683. return -ENODEV;
  684. }
  685. static int pasemi_mac_open(struct net_device *dev)
  686. {
  687. struct pasemi_mac *mac = netdev_priv(dev);
  688. int base_irq;
  689. unsigned int flags;
  690. int ret;
  691. /* enable rx section */
  692. write_dma_reg(mac, PAS_DMA_COM_RXCMD, PAS_DMA_COM_RXCMD_EN);
  693. /* enable tx section */
  694. write_dma_reg(mac, PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN);
  695. flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) |
  696. PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) |
  697. PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12);
  698. write_mac_reg(mac, PAS_MAC_CFG_TXP, flags);
  699. write_iob_reg(mac, PAS_IOB_DMA_RXCH_CFG(mac->dma_rxch),
  700. PAS_IOB_DMA_RXCH_CFG_CNTTH(0));
  701. write_iob_reg(mac, PAS_IOB_DMA_TXCH_CFG(mac->dma_txch),
  702. PAS_IOB_DMA_TXCH_CFG_CNTTH(128));
  703. /* Clear out any residual packet count state from firmware */
  704. pasemi_mac_restart_rx_intr(mac);
  705. pasemi_mac_restart_tx_intr(mac);
  706. /* 0xffffff is max value, about 16ms */
  707. write_iob_reg(mac, PAS_IOB_DMA_COM_TIMEOUTCFG,
  708. PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0xffffff));
  709. ret = pasemi_mac_setup_rx_resources(dev);
  710. if (ret)
  711. goto out_rx_resources;
  712. ret = pasemi_mac_setup_tx_resources(dev);
  713. if (ret)
  714. goto out_tx_resources;
  715. write_mac_reg(mac, PAS_MAC_IPC_CHNL,
  716. PAS_MAC_IPC_CHNL_DCHNO(mac->dma_rxch) |
  717. PAS_MAC_IPC_CHNL_BCH(mac->dma_rxch));
  718. /* enable rx if */
  719. write_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
  720. PAS_DMA_RXINT_RCMDSTA_EN |
  721. PAS_DMA_RXINT_RCMDSTA_DROPS_M |
  722. PAS_DMA_RXINT_RCMDSTA_BP |
  723. PAS_DMA_RXINT_RCMDSTA_OO |
  724. PAS_DMA_RXINT_RCMDSTA_BT);
  725. /* enable rx channel */
  726. write_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch),
  727. PAS_DMA_RXCHAN_CCMDSTA_EN |
  728. PAS_DMA_RXCHAN_CCMDSTA_DU |
  729. PAS_DMA_RXCHAN_CCMDSTA_OD |
  730. PAS_DMA_RXCHAN_CCMDSTA_FD |
  731. PAS_DMA_RXCHAN_CCMDSTA_DT);
  732. /* enable tx channel */
  733. write_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch),
  734. PAS_DMA_TXCHAN_TCMDSTA_EN |
  735. PAS_DMA_TXCHAN_TCMDSTA_SZ |
  736. PAS_DMA_TXCHAN_TCMDSTA_DB |
  737. PAS_DMA_TXCHAN_TCMDSTA_DE |
  738. PAS_DMA_TXCHAN_TCMDSTA_DA);
  739. pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE);
  740. write_dma_reg(mac, PAS_DMA_RXCHAN_INCR(mac->dma_rxch), RX_RING_SIZE>>1);
  741. flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PE |
  742. PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE;
  743. if (mac->type == MAC_TYPE_GMAC)
  744. flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G;
  745. else
  746. flags |= PAS_MAC_CFG_PCFG_TSR_10G | PAS_MAC_CFG_PCFG_SPD_10G;
  747. /* Enable interface in MAC */
  748. write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
  749. ret = pasemi_mac_phy_init(dev);
  750. /* Some configs don't have PHYs (XAUI etc), so don't complain about
  751. * failed init due to -ENODEV.
  752. */
  753. if (ret && ret != -ENODEV)
  754. dev_warn(&mac->pdev->dev, "phy init failed: %d\n", ret);
  755. netif_start_queue(dev);
  756. napi_enable(&mac->napi);
  757. /* Interrupts are a bit different for our DMA controller: While
  758. * it's got one a regular PCI device header, the interrupt there
  759. * is really the base of the range it's using. Each tx and rx
  760. * channel has it's own interrupt source.
  761. */
  762. base_irq = virq_to_hw(mac->dma_pdev->irq);
  763. mac->tx_irq = irq_create_mapping(NULL, base_irq + mac->dma_txch);
  764. mac->rx_irq = irq_create_mapping(NULL, base_irq + 20 + mac->dma_txch);
  765. ret = request_irq(mac->tx_irq, &pasemi_mac_tx_intr, IRQF_DISABLED,
  766. mac->tx->irq_name, dev);
  767. if (ret) {
  768. dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
  769. base_irq + mac->dma_txch, ret);
  770. goto out_tx_int;
  771. }
  772. ret = request_irq(mac->rx_irq, &pasemi_mac_rx_intr, IRQF_DISABLED,
  773. mac->rx->irq_name, dev);
  774. if (ret) {
  775. dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
  776. base_irq + 20 + mac->dma_rxch, ret);
  777. goto out_rx_int;
  778. }
  779. if (mac->phydev)
  780. phy_start(mac->phydev);
  781. return 0;
  782. out_rx_int:
  783. free_irq(mac->tx_irq, dev);
  784. out_tx_int:
  785. napi_disable(&mac->napi);
  786. netif_stop_queue(dev);
  787. pasemi_mac_free_tx_resources(dev);
  788. out_tx_resources:
  789. pasemi_mac_free_rx_resources(dev);
  790. out_rx_resources:
  791. return ret;
  792. }
  793. #define MAX_RETRIES 5000
  794. static int pasemi_mac_close(struct net_device *dev)
  795. {
  796. struct pasemi_mac *mac = netdev_priv(dev);
  797. unsigned int sta;
  798. int retries;
  799. if (mac->phydev) {
  800. phy_stop(mac->phydev);
  801. phy_disconnect(mac->phydev);
  802. }
  803. netif_stop_queue(dev);
  804. napi_disable(&mac->napi);
  805. sta = read_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
  806. if (sta & (PAS_DMA_RXINT_RCMDSTA_BP |
  807. PAS_DMA_RXINT_RCMDSTA_OO |
  808. PAS_DMA_RXINT_RCMDSTA_BT))
  809. printk(KERN_DEBUG "pasemi_mac: rcmdsta error: 0x%08x\n", sta);
  810. sta = read_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch));
  811. if (sta & (PAS_DMA_RXCHAN_CCMDSTA_DU |
  812. PAS_DMA_RXCHAN_CCMDSTA_OD |
  813. PAS_DMA_RXCHAN_CCMDSTA_FD |
  814. PAS_DMA_RXCHAN_CCMDSTA_DT))
  815. printk(KERN_DEBUG "pasemi_mac: ccmdsta error: 0x%08x\n", sta);
  816. sta = read_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch));
  817. if (sta & (PAS_DMA_TXCHAN_TCMDSTA_SZ |
  818. PAS_DMA_TXCHAN_TCMDSTA_DB |
  819. PAS_DMA_TXCHAN_TCMDSTA_DE |
  820. PAS_DMA_TXCHAN_TCMDSTA_DA))
  821. printk(KERN_DEBUG "pasemi_mac: tcmdsta error: 0x%08x\n", sta);
  822. /* Clean out any pending buffers */
  823. pasemi_mac_clean_tx(mac);
  824. pasemi_mac_clean_rx(mac, RX_RING_SIZE);
  825. /* Disable interface */
  826. write_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), PAS_DMA_TXCHAN_TCMDSTA_ST);
  827. write_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if), PAS_DMA_RXINT_RCMDSTA_ST);
  828. write_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), PAS_DMA_RXCHAN_CCMDSTA_ST);
  829. for (retries = 0; retries < MAX_RETRIES; retries++) {
  830. sta = read_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch));
  831. if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT))
  832. break;
  833. cond_resched();
  834. }
  835. if (sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)
  836. dev_err(&mac->dma_pdev->dev, "Failed to stop tx channel\n");
  837. for (retries = 0; retries < MAX_RETRIES; retries++) {
  838. sta = read_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch));
  839. if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT))
  840. break;
  841. cond_resched();
  842. }
  843. if (sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)
  844. dev_err(&mac->dma_pdev->dev, "Failed to stop rx channel\n");
  845. for (retries = 0; retries < MAX_RETRIES; retries++) {
  846. sta = read_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
  847. if (!(sta & PAS_DMA_RXINT_RCMDSTA_ACT))
  848. break;
  849. cond_resched();
  850. }
  851. if (sta & PAS_DMA_RXINT_RCMDSTA_ACT)
  852. dev_err(&mac->dma_pdev->dev, "Failed to stop rx interface\n");
  853. /* Then, disable the channel. This must be done separately from
  854. * stopping, since you can't disable when active.
  855. */
  856. write_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), 0);
  857. write_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), 0);
  858. write_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0);
  859. free_irq(mac->tx_irq, dev);
  860. free_irq(mac->rx_irq, dev);
  861. /* Free resources */
  862. pasemi_mac_free_rx_resources(dev);
  863. pasemi_mac_free_tx_resources(dev);
  864. return 0;
  865. }
  866. static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev)
  867. {
  868. struct pasemi_mac *mac = netdev_priv(dev);
  869. struct pasemi_mac_txring *txring;
  870. u64 dflags, mactx;
  871. dma_addr_t map[MAX_SKB_FRAGS+1];
  872. unsigned int map_size[MAX_SKB_FRAGS+1];
  873. unsigned long flags;
  874. int i, nfrags;
  875. dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_CRC_PAD;
  876. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  877. const unsigned char *nh = skb_network_header(skb);
  878. switch (ip_hdr(skb)->protocol) {
  879. case IPPROTO_TCP:
  880. dflags |= XCT_MACTX_CSUM_TCP;
  881. dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
  882. dflags |= XCT_MACTX_IPO(nh - skb->data);
  883. break;
  884. case IPPROTO_UDP:
  885. dflags |= XCT_MACTX_CSUM_UDP;
  886. dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
  887. dflags |= XCT_MACTX_IPO(nh - skb->data);
  888. break;
  889. }
  890. }
  891. nfrags = skb_shinfo(skb)->nr_frags;
  892. map[0] = pci_map_single(mac->dma_pdev, skb->data, skb_headlen(skb),
  893. PCI_DMA_TODEVICE);
  894. map_size[0] = skb_headlen(skb);
  895. if (dma_mapping_error(map[0]))
  896. goto out_err_nolock;
  897. for (i = 0; i < nfrags; i++) {
  898. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  899. map[i+1] = pci_map_page(mac->dma_pdev, frag->page,
  900. frag->page_offset, frag->size,
  901. PCI_DMA_TODEVICE);
  902. map_size[i+1] = frag->size;
  903. if (dma_mapping_error(map[i+1])) {
  904. nfrags = i;
  905. goto out_err_nolock;
  906. }
  907. }
  908. mactx = dflags | XCT_MACTX_LLEN(skb->len);
  909. txring = mac->tx;
  910. spin_lock_irqsave(&txring->lock, flags);
  911. /* Avoid stepping on the same cache line that the DMA controller
  912. * is currently about to send, so leave at least 8 words available.
  913. * Total free space needed is mactx + fragments + 8
  914. */
  915. if (RING_AVAIL(txring) < nfrags + 10) {
  916. /* no room -- stop the queue and wait for tx intr */
  917. netif_stop_queue(dev);
  918. goto out_err;
  919. }
  920. TX_RING(mac, txring->next_to_fill) = mactx;
  921. txring->next_to_fill++;
  922. TX_RING_INFO(mac, txring->next_to_fill).skb = skb;
  923. for (i = 0; i <= nfrags; i++) {
  924. TX_RING(mac, txring->next_to_fill+i) =
  925. XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]);
  926. TX_RING_INFO(mac, txring->next_to_fill+i).dma = map[i];
  927. }
  928. /* We have to add an even number of 8-byte entries to the ring
  929. * even if the last one is unused. That means always an odd number
  930. * of pointers + one mactx descriptor.
  931. */
  932. if (nfrags & 1)
  933. nfrags++;
  934. txring->next_to_fill = (txring->next_to_fill + nfrags + 1) &
  935. (TX_RING_SIZE-1);
  936. dev->stats.tx_packets++;
  937. dev->stats.tx_bytes += skb->len;
  938. spin_unlock_irqrestore(&txring->lock, flags);
  939. write_dma_reg(mac, PAS_DMA_TXCHAN_INCR(mac->dma_txch), (nfrags+2) >> 1);
  940. return NETDEV_TX_OK;
  941. out_err:
  942. spin_unlock_irqrestore(&txring->lock, flags);
  943. out_err_nolock:
  944. while (nfrags--)
  945. pci_unmap_single(mac->dma_pdev, map[nfrags], map_size[nfrags],
  946. PCI_DMA_TODEVICE);
  947. return NETDEV_TX_BUSY;
  948. }
  949. static void pasemi_mac_set_rx_mode(struct net_device *dev)
  950. {
  951. struct pasemi_mac *mac = netdev_priv(dev);
  952. unsigned int flags;
  953. flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
  954. /* Set promiscuous */
  955. if (dev->flags & IFF_PROMISC)
  956. flags |= PAS_MAC_CFG_PCFG_PR;
  957. else
  958. flags &= ~PAS_MAC_CFG_PCFG_PR;
  959. write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
  960. }
  961. static int pasemi_mac_poll(struct napi_struct *napi, int budget)
  962. {
  963. struct pasemi_mac *mac = container_of(napi, struct pasemi_mac, napi);
  964. struct net_device *dev = mac->netdev;
  965. int pkts;
  966. pasemi_mac_clean_tx(mac);
  967. pkts = pasemi_mac_clean_rx(mac, budget);
  968. if (pkts < budget) {
  969. /* all done, no more packets present */
  970. netif_rx_complete(dev, napi);
  971. pasemi_mac_restart_rx_intr(mac);
  972. }
  973. return pkts;
  974. }
  975. static void __iomem * __devinit map_onedev(struct pci_dev *p, int index)
  976. {
  977. struct device_node *dn;
  978. void __iomem *ret;
  979. dn = pci_device_to_OF_node(p);
  980. if (!dn)
  981. goto fallback;
  982. ret = of_iomap(dn, index);
  983. if (!ret)
  984. goto fallback;
  985. return ret;
  986. fallback:
  987. /* This is hardcoded and ugly, but we have some firmware versions
  988. * that don't provide the register space in the device tree. Luckily
  989. * they are at well-known locations so we can just do the math here.
  990. */
  991. return ioremap(0xe0000000 + (p->devfn << 12), 0x2000);
  992. }
  993. static int __devinit pasemi_mac_map_regs(struct pasemi_mac *mac)
  994. {
  995. struct resource res;
  996. struct device_node *dn;
  997. int err;
  998. mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
  999. if (!mac->dma_pdev) {
  1000. dev_err(&mac->pdev->dev, "Can't find DMA Controller\n");
  1001. return -ENODEV;
  1002. }
  1003. mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
  1004. if (!mac->iob_pdev) {
  1005. dev_err(&mac->pdev->dev, "Can't find I/O Bridge\n");
  1006. return -ENODEV;
  1007. }
  1008. mac->regs = map_onedev(mac->pdev, 0);
  1009. mac->dma_regs = map_onedev(mac->dma_pdev, 0);
  1010. mac->iob_regs = map_onedev(mac->iob_pdev, 0);
  1011. if (!mac->regs || !mac->dma_regs || !mac->iob_regs) {
  1012. dev_err(&mac->pdev->dev, "Can't map registers\n");
  1013. return -ENODEV;
  1014. }
  1015. /* The dma status structure is located in the I/O bridge, and
  1016. * is cache coherent.
  1017. */
  1018. if (!dma_status) {
  1019. dn = pci_device_to_OF_node(mac->iob_pdev);
  1020. if (dn)
  1021. err = of_address_to_resource(dn, 1, &res);
  1022. if (!dn || err) {
  1023. /* Fallback for old firmware */
  1024. res.start = 0xfd800000;
  1025. res.end = res.start + 0x1000;
  1026. }
  1027. dma_status = __ioremap(res.start, res.end-res.start, 0);
  1028. }
  1029. return 0;
  1030. }
  1031. static int __devinit
  1032. pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  1033. {
  1034. static int index = 0;
  1035. struct net_device *dev;
  1036. struct pasemi_mac *mac;
  1037. int err;
  1038. DECLARE_MAC_BUF(mac_buf);
  1039. err = pci_enable_device(pdev);
  1040. if (err)
  1041. return err;
  1042. dev = alloc_etherdev(sizeof(struct pasemi_mac));
  1043. if (dev == NULL) {
  1044. dev_err(&pdev->dev,
  1045. "pasemi_mac: Could not allocate ethernet device.\n");
  1046. err = -ENOMEM;
  1047. goto out_disable_device;
  1048. }
  1049. pci_set_drvdata(pdev, dev);
  1050. SET_NETDEV_DEV(dev, &pdev->dev);
  1051. mac = netdev_priv(dev);
  1052. mac->pdev = pdev;
  1053. mac->netdev = dev;
  1054. netif_napi_add(dev, &mac->napi, pasemi_mac_poll, 64);
  1055. dev->features = NETIF_F_IP_CSUM | NETIF_F_LLTX | NETIF_F_SG;
  1056. /* These should come out of the device tree eventually */
  1057. mac->dma_txch = index;
  1058. mac->dma_rxch = index;
  1059. /* We probe GMAC before XAUI, but the DMA interfaces are
  1060. * in XAUI, GMAC order.
  1061. */
  1062. if (index < 4)
  1063. mac->dma_if = index + 2;
  1064. else
  1065. mac->dma_if = index - 4;
  1066. index++;
  1067. switch (pdev->device) {
  1068. case 0xa005:
  1069. mac->type = MAC_TYPE_GMAC;
  1070. break;
  1071. case 0xa006:
  1072. mac->type = MAC_TYPE_XAUI;
  1073. break;
  1074. default:
  1075. err = -ENODEV;
  1076. goto out;
  1077. }
  1078. /* get mac addr from device tree */
  1079. if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) {
  1080. err = -ENODEV;
  1081. goto out;
  1082. }
  1083. memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr));
  1084. dev->open = pasemi_mac_open;
  1085. dev->stop = pasemi_mac_close;
  1086. dev->hard_start_xmit = pasemi_mac_start_tx;
  1087. dev->set_multicast_list = pasemi_mac_set_rx_mode;
  1088. err = pasemi_mac_map_regs(mac);
  1089. if (err)
  1090. goto out;
  1091. mac->rx_status = &dma_status->rx_sta[mac->dma_rxch];
  1092. mac->tx_status = &dma_status->tx_sta[mac->dma_txch];
  1093. mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
  1094. /* Enable most messages by default */
  1095. mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
  1096. err = register_netdev(dev);
  1097. if (err) {
  1098. dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n",
  1099. err);
  1100. goto out;
  1101. } else if netif_msg_probe(mac)
  1102. printk(KERN_INFO "%s: PA Semi %s: intf %d, txch %d, rxch %d, "
  1103. "hw addr %s\n",
  1104. dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI",
  1105. mac->dma_if, mac->dma_txch, mac->dma_rxch,
  1106. print_mac(mac_buf, dev->dev_addr));
  1107. return err;
  1108. out:
  1109. if (mac->iob_pdev)
  1110. pci_dev_put(mac->iob_pdev);
  1111. if (mac->dma_pdev)
  1112. pci_dev_put(mac->dma_pdev);
  1113. if (mac->dma_regs)
  1114. iounmap(mac->dma_regs);
  1115. if (mac->iob_regs)
  1116. iounmap(mac->iob_regs);
  1117. if (mac->regs)
  1118. iounmap(mac->regs);
  1119. free_netdev(dev);
  1120. out_disable_device:
  1121. pci_disable_device(pdev);
  1122. return err;
  1123. }
  1124. static void __devexit pasemi_mac_remove(struct pci_dev *pdev)
  1125. {
  1126. struct net_device *netdev = pci_get_drvdata(pdev);
  1127. struct pasemi_mac *mac;
  1128. if (!netdev)
  1129. return;
  1130. mac = netdev_priv(netdev);
  1131. unregister_netdev(netdev);
  1132. pci_disable_device(pdev);
  1133. pci_dev_put(mac->dma_pdev);
  1134. pci_dev_put(mac->iob_pdev);
  1135. iounmap(mac->regs);
  1136. iounmap(mac->dma_regs);
  1137. iounmap(mac->iob_regs);
  1138. pci_set_drvdata(pdev, NULL);
  1139. free_netdev(netdev);
  1140. }
  1141. static struct pci_device_id pasemi_mac_pci_tbl[] = {
  1142. { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) },
  1143. { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) },
  1144. { },
  1145. };
  1146. MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl);
  1147. static struct pci_driver pasemi_mac_driver = {
  1148. .name = "pasemi_mac",
  1149. .id_table = pasemi_mac_pci_tbl,
  1150. .probe = pasemi_mac_probe,
  1151. .remove = __devexit_p(pasemi_mac_remove),
  1152. };
  1153. static void __exit pasemi_mac_cleanup_module(void)
  1154. {
  1155. pci_unregister_driver(&pasemi_mac_driver);
  1156. __iounmap(dma_status);
  1157. dma_status = NULL;
  1158. }
  1159. int pasemi_mac_init_module(void)
  1160. {
  1161. return pci_register_driver(&pasemi_mac_driver);
  1162. }
  1163. module_init(pasemi_mac_init_module);
  1164. module_exit(pasemi_mac_cleanup_module);