gianfar_mii.c 6.3 KB

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  1. /*
  2. * drivers/net/gianfar_mii.c
  3. *
  4. * Gianfar Ethernet Driver -- MIIM bus implementation
  5. * Provides Bus interface for MIIM regs
  6. *
  7. * Author: Andy Fleming
  8. * Maintainer: Kumar Gala
  9. *
  10. * Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms of the GNU General Public License as published by the
  14. * Free Software Foundation; either version 2 of the License, or (at your
  15. * option) any later version.
  16. *
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/string.h>
  20. #include <linux/errno.h>
  21. #include <linux/unistd.h>
  22. #include <linux/slab.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/init.h>
  25. #include <linux/delay.h>
  26. #include <linux/netdevice.h>
  27. #include <linux/etherdevice.h>
  28. #include <linux/skbuff.h>
  29. #include <linux/spinlock.h>
  30. #include <linux/mm.h>
  31. #include <linux/module.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/crc32.h>
  34. #include <linux/mii.h>
  35. #include <linux/phy.h>
  36. #include <asm/io.h>
  37. #include <asm/irq.h>
  38. #include <asm/uaccess.h>
  39. #include "gianfar.h"
  40. #include "gianfar_mii.h"
  41. /*
  42. * Write value to the PHY at mii_id at register regnum,
  43. * on the bus attached to the local interface, which may be different from the
  44. * generic mdio bus (tied to a single interface), waiting until the write is
  45. * done before returning. This is helpful in programming interfaces like
  46. * the TBI which control interfaces like onchip SERDES and are always tied to
  47. * the local mdio pins, which may not be the same as system mdio bus, used for
  48. * controlling the external PHYs, for example.
  49. */
  50. int gfar_local_mdio_write(struct gfar_mii *regs, int mii_id,
  51. int regnum, u16 value)
  52. {
  53. /* Set the PHY address and the register address we want to write */
  54. gfar_write(&regs->miimadd, (mii_id << 8) | regnum);
  55. /* Write out the value we want */
  56. gfar_write(&regs->miimcon, value);
  57. /* Wait for the transaction to finish */
  58. while (gfar_read(&regs->miimind) & MIIMIND_BUSY)
  59. cpu_relax();
  60. return 0;
  61. }
  62. /*
  63. * Read the bus for PHY at addr mii_id, register regnum, and
  64. * return the value. Clears miimcom first. All PHY operation
  65. * done on the bus attached to the local interface,
  66. * which may be different from the generic mdio bus
  67. * This is helpful in programming interfaces like
  68. * the TBI which, inturn, control interfaces like onchip SERDES
  69. * and are always tied to the local mdio pins, which may not be the
  70. * same as system mdio bus, used for controlling the external PHYs, for eg.
  71. */
  72. int gfar_local_mdio_read(struct gfar_mii *regs, int mii_id, int regnum)
  73. {
  74. u16 value;
  75. /* Set the PHY address and the register address we want to read */
  76. gfar_write(&regs->miimadd, (mii_id << 8) | regnum);
  77. /* Clear miimcom, and then initiate a read */
  78. gfar_write(&regs->miimcom, 0);
  79. gfar_write(&regs->miimcom, MII_READ_COMMAND);
  80. /* Wait for the transaction to finish */
  81. while (gfar_read(&regs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
  82. cpu_relax();
  83. /* Grab the value of the register from miimstat */
  84. value = gfar_read(&regs->miimstat);
  85. return value;
  86. }
  87. /* Write value to the PHY at mii_id at register regnum,
  88. * on the bus, waiting until the write is done before returning.
  89. * All PHY configuration is done through the TSEC1 MIIM regs */
  90. int gfar_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value)
  91. {
  92. struct gfar_mii __iomem *regs = (void __iomem *)bus->priv;
  93. /* Write to the local MII regs */
  94. return(gfar_local_mdio_write(regs, mii_id, regnum, value));
  95. }
  96. /* Read the bus for PHY at addr mii_id, register regnum, and
  97. * return the value. Clears miimcom first. All PHY
  98. * configuration has to be done through the TSEC1 MIIM regs */
  99. int gfar_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
  100. {
  101. struct gfar_mii __iomem *regs = (void __iomem *)bus->priv;
  102. /* Read the local MII regs */
  103. return(gfar_local_mdio_read(regs, mii_id, regnum));
  104. }
  105. /* Reset the MIIM registers, and wait for the bus to free */
  106. int gfar_mdio_reset(struct mii_bus *bus)
  107. {
  108. struct gfar_mii __iomem *regs = (void __iomem *)bus->priv;
  109. unsigned int timeout = PHY_INIT_TIMEOUT;
  110. spin_lock_bh(&bus->mdio_lock);
  111. /* Reset the management interface */
  112. gfar_write(&regs->miimcfg, MIIMCFG_RESET);
  113. /* Setup the MII Mgmt clock speed */
  114. gfar_write(&regs->miimcfg, MIIMCFG_INIT_VALUE);
  115. /* Wait until the bus is free */
  116. while ((gfar_read(&regs->miimind) & MIIMIND_BUSY) &&
  117. timeout--)
  118. cpu_relax();
  119. spin_unlock_bh(&bus->mdio_lock);
  120. if(timeout <= 0) {
  121. printk(KERN_ERR "%s: The MII Bus is stuck!\n",
  122. bus->name);
  123. return -EBUSY;
  124. }
  125. return 0;
  126. }
  127. int gfar_mdio_probe(struct device *dev)
  128. {
  129. struct platform_device *pdev = to_platform_device(dev);
  130. struct gianfar_mdio_data *pdata;
  131. struct gfar_mii __iomem *regs;
  132. struct mii_bus *new_bus;
  133. struct resource *r;
  134. int err = 0;
  135. if (NULL == dev)
  136. return -EINVAL;
  137. new_bus = kzalloc(sizeof(struct mii_bus), GFP_KERNEL);
  138. if (NULL == new_bus)
  139. return -ENOMEM;
  140. new_bus->name = "Gianfar MII Bus",
  141. new_bus->read = &gfar_mdio_read,
  142. new_bus->write = &gfar_mdio_write,
  143. new_bus->reset = &gfar_mdio_reset,
  144. new_bus->id = pdev->id;
  145. pdata = (struct gianfar_mdio_data *)pdev->dev.platform_data;
  146. if (NULL == pdata) {
  147. printk(KERN_ERR "gfar mdio %d: Missing platform data!\n", pdev->id);
  148. return -ENODEV;
  149. }
  150. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  151. /* Set the PHY base address */
  152. regs = ioremap(r->start, sizeof (struct gfar_mii));
  153. if (NULL == regs) {
  154. err = -ENOMEM;
  155. goto reg_map_fail;
  156. }
  157. new_bus->priv = (void __force *)regs;
  158. new_bus->irq = pdata->irq;
  159. new_bus->dev = dev;
  160. dev_set_drvdata(dev, new_bus);
  161. err = mdiobus_register(new_bus);
  162. if (0 != err) {
  163. printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
  164. new_bus->name);
  165. goto bus_register_fail;
  166. }
  167. return 0;
  168. bus_register_fail:
  169. iounmap(regs);
  170. reg_map_fail:
  171. kfree(new_bus);
  172. return err;
  173. }
  174. int gfar_mdio_remove(struct device *dev)
  175. {
  176. struct mii_bus *bus = dev_get_drvdata(dev);
  177. mdiobus_unregister(bus);
  178. dev_set_drvdata(dev, NULL);
  179. iounmap((void __iomem *)bus->priv);
  180. bus->priv = NULL;
  181. kfree(bus);
  182. return 0;
  183. }
  184. static struct device_driver gianfar_mdio_driver = {
  185. .name = "fsl-gianfar_mdio",
  186. .bus = &platform_bus_type,
  187. .probe = gfar_mdio_probe,
  188. .remove = gfar_mdio_remove,
  189. };
  190. int __init gfar_mdio_init(void)
  191. {
  192. return driver_register(&gianfar_mdio_driver);
  193. }
  194. void gfar_mdio_exit(void)
  195. {
  196. driver_unregister(&gianfar_mdio_driver);
  197. }