mthca_memfree.c 18 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Cisco Systems. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. *
  34. * $Id$
  35. */
  36. #include <linux/mm.h>
  37. #include <linux/scatterlist.h>
  38. #include <linux/sched.h>
  39. #include <asm/page.h>
  40. #include "mthca_memfree.h"
  41. #include "mthca_dev.h"
  42. #include "mthca_cmd.h"
  43. /*
  44. * We allocate in as big chunks as we can, up to a maximum of 256 KB
  45. * per chunk.
  46. */
  47. enum {
  48. MTHCA_ICM_ALLOC_SIZE = 1 << 18,
  49. MTHCA_TABLE_CHUNK_SIZE = 1 << 18
  50. };
  51. struct mthca_user_db_table {
  52. struct mutex mutex;
  53. struct {
  54. u64 uvirt;
  55. struct scatterlist mem;
  56. int refcount;
  57. } page[0];
  58. };
  59. static void mthca_free_icm_pages(struct mthca_dev *dev, struct mthca_icm_chunk *chunk)
  60. {
  61. int i;
  62. if (chunk->nsg > 0)
  63. pci_unmap_sg(dev->pdev, chunk->mem, chunk->npages,
  64. PCI_DMA_BIDIRECTIONAL);
  65. for (i = 0; i < chunk->npages; ++i)
  66. __free_pages(sg_page(&chunk->mem[i]),
  67. get_order(chunk->mem[i].length));
  68. }
  69. static void mthca_free_icm_coherent(struct mthca_dev *dev, struct mthca_icm_chunk *chunk)
  70. {
  71. int i;
  72. for (i = 0; i < chunk->npages; ++i) {
  73. dma_free_coherent(&dev->pdev->dev, chunk->mem[i].length,
  74. lowmem_page_address(sg_page(&chunk->mem[i])),
  75. sg_dma_address(&chunk->mem[i]));
  76. }
  77. }
  78. void mthca_free_icm(struct mthca_dev *dev, struct mthca_icm *icm, int coherent)
  79. {
  80. struct mthca_icm_chunk *chunk, *tmp;
  81. if (!icm)
  82. return;
  83. list_for_each_entry_safe(chunk, tmp, &icm->chunk_list, list) {
  84. if (coherent)
  85. mthca_free_icm_coherent(dev, chunk);
  86. else
  87. mthca_free_icm_pages(dev, chunk);
  88. kfree(chunk);
  89. }
  90. kfree(icm);
  91. }
  92. static int mthca_alloc_icm_pages(struct scatterlist *mem, int order, gfp_t gfp_mask)
  93. {
  94. struct page *page;
  95. page = alloc_pages(gfp_mask, order);
  96. if (!page)
  97. return -ENOMEM;
  98. sg_set_page(mem, page, PAGE_SIZE << order, 0);
  99. return 0;
  100. }
  101. static int mthca_alloc_icm_coherent(struct device *dev, struct scatterlist *mem,
  102. int order, gfp_t gfp_mask)
  103. {
  104. void *buf = dma_alloc_coherent(dev, PAGE_SIZE << order, &sg_dma_address(mem),
  105. gfp_mask);
  106. if (!buf)
  107. return -ENOMEM;
  108. sg_set_buf(mem, buf, PAGE_SIZE << order);
  109. BUG_ON(mem->offset);
  110. sg_dma_len(mem) = PAGE_SIZE << order;
  111. return 0;
  112. }
  113. struct mthca_icm *mthca_alloc_icm(struct mthca_dev *dev, int npages,
  114. gfp_t gfp_mask, int coherent)
  115. {
  116. struct mthca_icm *icm;
  117. struct mthca_icm_chunk *chunk = NULL;
  118. int cur_order;
  119. int ret;
  120. /* We use sg_set_buf for coherent allocs, which assumes low memory */
  121. BUG_ON(coherent && (gfp_mask & __GFP_HIGHMEM));
  122. icm = kmalloc(sizeof *icm, gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
  123. if (!icm)
  124. return icm;
  125. icm->refcount = 0;
  126. INIT_LIST_HEAD(&icm->chunk_list);
  127. cur_order = get_order(MTHCA_ICM_ALLOC_SIZE);
  128. while (npages > 0) {
  129. if (!chunk) {
  130. chunk = kmalloc(sizeof *chunk,
  131. gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
  132. if (!chunk)
  133. goto fail;
  134. sg_init_table(chunk->mem, MTHCA_ICM_CHUNK_LEN);
  135. chunk->npages = 0;
  136. chunk->nsg = 0;
  137. list_add_tail(&chunk->list, &icm->chunk_list);
  138. }
  139. while (1 << cur_order > npages)
  140. --cur_order;
  141. if (coherent)
  142. ret = mthca_alloc_icm_coherent(&dev->pdev->dev,
  143. &chunk->mem[chunk->npages],
  144. cur_order, gfp_mask);
  145. else
  146. ret = mthca_alloc_icm_pages(&chunk->mem[chunk->npages],
  147. cur_order, gfp_mask);
  148. if (!ret) {
  149. ++chunk->npages;
  150. if (coherent)
  151. ++chunk->nsg;
  152. else if (chunk->npages == MTHCA_ICM_CHUNK_LEN) {
  153. chunk->nsg = pci_map_sg(dev->pdev, chunk->mem,
  154. chunk->npages,
  155. PCI_DMA_BIDIRECTIONAL);
  156. if (chunk->nsg <= 0)
  157. goto fail;
  158. }
  159. if (chunk->npages == MTHCA_ICM_CHUNK_LEN)
  160. chunk = NULL;
  161. npages -= 1 << cur_order;
  162. } else {
  163. --cur_order;
  164. if (cur_order < 0)
  165. goto fail;
  166. }
  167. }
  168. if (!coherent && chunk) {
  169. chunk->nsg = pci_map_sg(dev->pdev, chunk->mem,
  170. chunk->npages,
  171. PCI_DMA_BIDIRECTIONAL);
  172. if (chunk->nsg <= 0)
  173. goto fail;
  174. }
  175. return icm;
  176. fail:
  177. mthca_free_icm(dev, icm, coherent);
  178. return NULL;
  179. }
  180. int mthca_table_get(struct mthca_dev *dev, struct mthca_icm_table *table, int obj)
  181. {
  182. int i = (obj & (table->num_obj - 1)) * table->obj_size / MTHCA_TABLE_CHUNK_SIZE;
  183. int ret = 0;
  184. u8 status;
  185. mutex_lock(&table->mutex);
  186. if (table->icm[i]) {
  187. ++table->icm[i]->refcount;
  188. goto out;
  189. }
  190. table->icm[i] = mthca_alloc_icm(dev, MTHCA_TABLE_CHUNK_SIZE >> PAGE_SHIFT,
  191. (table->lowmem ? GFP_KERNEL : GFP_HIGHUSER) |
  192. __GFP_NOWARN, table->coherent);
  193. if (!table->icm[i]) {
  194. ret = -ENOMEM;
  195. goto out;
  196. }
  197. if (mthca_MAP_ICM(dev, table->icm[i], table->virt + i * MTHCA_TABLE_CHUNK_SIZE,
  198. &status) || status) {
  199. mthca_free_icm(dev, table->icm[i], table->coherent);
  200. table->icm[i] = NULL;
  201. ret = -ENOMEM;
  202. goto out;
  203. }
  204. ++table->icm[i]->refcount;
  205. out:
  206. mutex_unlock(&table->mutex);
  207. return ret;
  208. }
  209. void mthca_table_put(struct mthca_dev *dev, struct mthca_icm_table *table, int obj)
  210. {
  211. int i;
  212. u8 status;
  213. if (!mthca_is_memfree(dev))
  214. return;
  215. i = (obj & (table->num_obj - 1)) * table->obj_size / MTHCA_TABLE_CHUNK_SIZE;
  216. mutex_lock(&table->mutex);
  217. if (--table->icm[i]->refcount == 0) {
  218. mthca_UNMAP_ICM(dev, table->virt + i * MTHCA_TABLE_CHUNK_SIZE,
  219. MTHCA_TABLE_CHUNK_SIZE / MTHCA_ICM_PAGE_SIZE,
  220. &status);
  221. mthca_free_icm(dev, table->icm[i], table->coherent);
  222. table->icm[i] = NULL;
  223. }
  224. mutex_unlock(&table->mutex);
  225. }
  226. void *mthca_table_find(struct mthca_icm_table *table, int obj, dma_addr_t *dma_handle)
  227. {
  228. int idx, offset, dma_offset, i;
  229. struct mthca_icm_chunk *chunk;
  230. struct mthca_icm *icm;
  231. struct page *page = NULL;
  232. if (!table->lowmem)
  233. return NULL;
  234. mutex_lock(&table->mutex);
  235. idx = (obj & (table->num_obj - 1)) * table->obj_size;
  236. icm = table->icm[idx / MTHCA_TABLE_CHUNK_SIZE];
  237. dma_offset = offset = idx % MTHCA_TABLE_CHUNK_SIZE;
  238. if (!icm)
  239. goto out;
  240. list_for_each_entry(chunk, &icm->chunk_list, list) {
  241. for (i = 0; i < chunk->npages; ++i) {
  242. if (dma_handle && dma_offset >= 0) {
  243. if (sg_dma_len(&chunk->mem[i]) > dma_offset)
  244. *dma_handle = sg_dma_address(&chunk->mem[i]) +
  245. dma_offset;
  246. dma_offset -= sg_dma_len(&chunk->mem[i]);
  247. }
  248. /* DMA mapping can merge pages but not split them,
  249. * so if we found the page, dma_handle has already
  250. * been assigned to. */
  251. if (chunk->mem[i].length > offset) {
  252. page = sg_page(&chunk->mem[i]);
  253. goto out;
  254. }
  255. offset -= chunk->mem[i].length;
  256. }
  257. }
  258. out:
  259. mutex_unlock(&table->mutex);
  260. return page ? lowmem_page_address(page) + offset : NULL;
  261. }
  262. int mthca_table_get_range(struct mthca_dev *dev, struct mthca_icm_table *table,
  263. int start, int end)
  264. {
  265. int inc = MTHCA_TABLE_CHUNK_SIZE / table->obj_size;
  266. int i, err;
  267. for (i = start; i <= end; i += inc) {
  268. err = mthca_table_get(dev, table, i);
  269. if (err)
  270. goto fail;
  271. }
  272. return 0;
  273. fail:
  274. while (i > start) {
  275. i -= inc;
  276. mthca_table_put(dev, table, i);
  277. }
  278. return err;
  279. }
  280. void mthca_table_put_range(struct mthca_dev *dev, struct mthca_icm_table *table,
  281. int start, int end)
  282. {
  283. int i;
  284. if (!mthca_is_memfree(dev))
  285. return;
  286. for (i = start; i <= end; i += MTHCA_TABLE_CHUNK_SIZE / table->obj_size)
  287. mthca_table_put(dev, table, i);
  288. }
  289. struct mthca_icm_table *mthca_alloc_icm_table(struct mthca_dev *dev,
  290. u64 virt, int obj_size,
  291. int nobj, int reserved,
  292. int use_lowmem, int use_coherent)
  293. {
  294. struct mthca_icm_table *table;
  295. int num_icm;
  296. unsigned chunk_size;
  297. int i;
  298. u8 status;
  299. num_icm = (obj_size * nobj + MTHCA_TABLE_CHUNK_SIZE - 1) / MTHCA_TABLE_CHUNK_SIZE;
  300. table = kmalloc(sizeof *table + num_icm * sizeof *table->icm, GFP_KERNEL);
  301. if (!table)
  302. return NULL;
  303. table->virt = virt;
  304. table->num_icm = num_icm;
  305. table->num_obj = nobj;
  306. table->obj_size = obj_size;
  307. table->lowmem = use_lowmem;
  308. table->coherent = use_coherent;
  309. mutex_init(&table->mutex);
  310. for (i = 0; i < num_icm; ++i)
  311. table->icm[i] = NULL;
  312. for (i = 0; i * MTHCA_TABLE_CHUNK_SIZE < reserved * obj_size; ++i) {
  313. chunk_size = MTHCA_TABLE_CHUNK_SIZE;
  314. if ((i + 1) * MTHCA_TABLE_CHUNK_SIZE > nobj * obj_size)
  315. chunk_size = nobj * obj_size - i * MTHCA_TABLE_CHUNK_SIZE;
  316. table->icm[i] = mthca_alloc_icm(dev, chunk_size >> PAGE_SHIFT,
  317. (use_lowmem ? GFP_KERNEL : GFP_HIGHUSER) |
  318. __GFP_NOWARN, use_coherent);
  319. if (!table->icm[i])
  320. goto err;
  321. if (mthca_MAP_ICM(dev, table->icm[i], virt + i * MTHCA_TABLE_CHUNK_SIZE,
  322. &status) || status) {
  323. mthca_free_icm(dev, table->icm[i], table->coherent);
  324. table->icm[i] = NULL;
  325. goto err;
  326. }
  327. /*
  328. * Add a reference to this ICM chunk so that it never
  329. * gets freed (since it contains reserved firmware objects).
  330. */
  331. ++table->icm[i]->refcount;
  332. }
  333. return table;
  334. err:
  335. for (i = 0; i < num_icm; ++i)
  336. if (table->icm[i]) {
  337. mthca_UNMAP_ICM(dev, virt + i * MTHCA_TABLE_CHUNK_SIZE,
  338. MTHCA_TABLE_CHUNK_SIZE / MTHCA_ICM_PAGE_SIZE,
  339. &status);
  340. mthca_free_icm(dev, table->icm[i], table->coherent);
  341. }
  342. kfree(table);
  343. return NULL;
  344. }
  345. void mthca_free_icm_table(struct mthca_dev *dev, struct mthca_icm_table *table)
  346. {
  347. int i;
  348. u8 status;
  349. for (i = 0; i < table->num_icm; ++i)
  350. if (table->icm[i]) {
  351. mthca_UNMAP_ICM(dev, table->virt + i * MTHCA_TABLE_CHUNK_SIZE,
  352. MTHCA_TABLE_CHUNK_SIZE / MTHCA_ICM_PAGE_SIZE,
  353. &status);
  354. mthca_free_icm(dev, table->icm[i], table->coherent);
  355. }
  356. kfree(table);
  357. }
  358. static u64 mthca_uarc_virt(struct mthca_dev *dev, struct mthca_uar *uar, int page)
  359. {
  360. return dev->uar_table.uarc_base +
  361. uar->index * dev->uar_table.uarc_size +
  362. page * MTHCA_ICM_PAGE_SIZE;
  363. }
  364. int mthca_map_user_db(struct mthca_dev *dev, struct mthca_uar *uar,
  365. struct mthca_user_db_table *db_tab, int index, u64 uaddr)
  366. {
  367. struct page *pages[1];
  368. int ret = 0;
  369. u8 status;
  370. int i;
  371. if (!mthca_is_memfree(dev))
  372. return 0;
  373. if (index < 0 || index > dev->uar_table.uarc_size / 8)
  374. return -EINVAL;
  375. mutex_lock(&db_tab->mutex);
  376. i = index / MTHCA_DB_REC_PER_PAGE;
  377. if ((db_tab->page[i].refcount >= MTHCA_DB_REC_PER_PAGE) ||
  378. (db_tab->page[i].uvirt && db_tab->page[i].uvirt != uaddr) ||
  379. (uaddr & 4095)) {
  380. ret = -EINVAL;
  381. goto out;
  382. }
  383. if (db_tab->page[i].refcount) {
  384. ++db_tab->page[i].refcount;
  385. goto out;
  386. }
  387. ret = get_user_pages(current, current->mm, uaddr & PAGE_MASK, 1, 1, 0,
  388. pages, NULL);
  389. if (ret < 0)
  390. goto out;
  391. sg_set_page(&db_tab->page[i].mem, pages[0], MTHCA_ICM_PAGE_SIZE,
  392. uaddr & ~PAGE_MASK);
  393. ret = pci_map_sg(dev->pdev, &db_tab->page[i].mem, 1, PCI_DMA_TODEVICE);
  394. if (ret < 0) {
  395. put_page(pages[0]);
  396. goto out;
  397. }
  398. ret = mthca_MAP_ICM_page(dev, sg_dma_address(&db_tab->page[i].mem),
  399. mthca_uarc_virt(dev, uar, i), &status);
  400. if (!ret && status)
  401. ret = -EINVAL;
  402. if (ret) {
  403. pci_unmap_sg(dev->pdev, &db_tab->page[i].mem, 1, PCI_DMA_TODEVICE);
  404. put_page(sg_page(&db_tab->page[i].mem));
  405. goto out;
  406. }
  407. db_tab->page[i].uvirt = uaddr;
  408. db_tab->page[i].refcount = 1;
  409. out:
  410. mutex_unlock(&db_tab->mutex);
  411. return ret;
  412. }
  413. void mthca_unmap_user_db(struct mthca_dev *dev, struct mthca_uar *uar,
  414. struct mthca_user_db_table *db_tab, int index)
  415. {
  416. if (!mthca_is_memfree(dev))
  417. return;
  418. /*
  419. * To make our bookkeeping simpler, we don't unmap DB
  420. * pages until we clean up the whole db table.
  421. */
  422. mutex_lock(&db_tab->mutex);
  423. --db_tab->page[index / MTHCA_DB_REC_PER_PAGE].refcount;
  424. mutex_unlock(&db_tab->mutex);
  425. }
  426. struct mthca_user_db_table *mthca_init_user_db_tab(struct mthca_dev *dev)
  427. {
  428. struct mthca_user_db_table *db_tab;
  429. int npages;
  430. int i;
  431. if (!mthca_is_memfree(dev))
  432. return NULL;
  433. npages = dev->uar_table.uarc_size / MTHCA_ICM_PAGE_SIZE;
  434. db_tab = kmalloc(sizeof *db_tab + npages * sizeof *db_tab->page, GFP_KERNEL);
  435. if (!db_tab)
  436. return ERR_PTR(-ENOMEM);
  437. mutex_init(&db_tab->mutex);
  438. for (i = 0; i < npages; ++i) {
  439. db_tab->page[i].refcount = 0;
  440. db_tab->page[i].uvirt = 0;
  441. }
  442. return db_tab;
  443. }
  444. void mthca_cleanup_user_db_tab(struct mthca_dev *dev, struct mthca_uar *uar,
  445. struct mthca_user_db_table *db_tab)
  446. {
  447. int i;
  448. u8 status;
  449. if (!mthca_is_memfree(dev))
  450. return;
  451. for (i = 0; i < dev->uar_table.uarc_size / MTHCA_ICM_PAGE_SIZE; ++i) {
  452. if (db_tab->page[i].uvirt) {
  453. mthca_UNMAP_ICM(dev, mthca_uarc_virt(dev, uar, i), 1, &status);
  454. pci_unmap_sg(dev->pdev, &db_tab->page[i].mem, 1, PCI_DMA_TODEVICE);
  455. put_page(sg_page(&db_tab->page[i].mem));
  456. }
  457. }
  458. kfree(db_tab);
  459. }
  460. int mthca_alloc_db(struct mthca_dev *dev, enum mthca_db_type type,
  461. u32 qn, __be32 **db)
  462. {
  463. int group;
  464. int start, end, dir;
  465. int i, j;
  466. struct mthca_db_page *page;
  467. int ret = 0;
  468. u8 status;
  469. mutex_lock(&dev->db_tab->mutex);
  470. switch (type) {
  471. case MTHCA_DB_TYPE_CQ_ARM:
  472. case MTHCA_DB_TYPE_SQ:
  473. group = 0;
  474. start = 0;
  475. end = dev->db_tab->max_group1;
  476. dir = 1;
  477. break;
  478. case MTHCA_DB_TYPE_CQ_SET_CI:
  479. case MTHCA_DB_TYPE_RQ:
  480. case MTHCA_DB_TYPE_SRQ:
  481. group = 1;
  482. start = dev->db_tab->npages - 1;
  483. end = dev->db_tab->min_group2;
  484. dir = -1;
  485. break;
  486. default:
  487. ret = -EINVAL;
  488. goto out;
  489. }
  490. for (i = start; i != end; i += dir)
  491. if (dev->db_tab->page[i].db_rec &&
  492. !bitmap_full(dev->db_tab->page[i].used,
  493. MTHCA_DB_REC_PER_PAGE)) {
  494. page = dev->db_tab->page + i;
  495. goto found;
  496. }
  497. for (i = start; i != end; i += dir)
  498. if (!dev->db_tab->page[i].db_rec) {
  499. page = dev->db_tab->page + i;
  500. goto alloc;
  501. }
  502. if (dev->db_tab->max_group1 >= dev->db_tab->min_group2 - 1) {
  503. ret = -ENOMEM;
  504. goto out;
  505. }
  506. if (group == 0)
  507. ++dev->db_tab->max_group1;
  508. else
  509. --dev->db_tab->min_group2;
  510. page = dev->db_tab->page + end;
  511. alloc:
  512. page->db_rec = dma_alloc_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
  513. &page->mapping, GFP_KERNEL);
  514. if (!page->db_rec) {
  515. ret = -ENOMEM;
  516. goto out;
  517. }
  518. memset(page->db_rec, 0, MTHCA_ICM_PAGE_SIZE);
  519. ret = mthca_MAP_ICM_page(dev, page->mapping,
  520. mthca_uarc_virt(dev, &dev->driver_uar, i), &status);
  521. if (!ret && status)
  522. ret = -EINVAL;
  523. if (ret) {
  524. dma_free_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
  525. page->db_rec, page->mapping);
  526. goto out;
  527. }
  528. bitmap_zero(page->used, MTHCA_DB_REC_PER_PAGE);
  529. found:
  530. j = find_first_zero_bit(page->used, MTHCA_DB_REC_PER_PAGE);
  531. set_bit(j, page->used);
  532. if (group == 1)
  533. j = MTHCA_DB_REC_PER_PAGE - 1 - j;
  534. ret = i * MTHCA_DB_REC_PER_PAGE + j;
  535. page->db_rec[j] = cpu_to_be64((qn << 8) | (type << 5));
  536. *db = (__be32 *) &page->db_rec[j];
  537. out:
  538. mutex_unlock(&dev->db_tab->mutex);
  539. return ret;
  540. }
  541. void mthca_free_db(struct mthca_dev *dev, int type, int db_index)
  542. {
  543. int i, j;
  544. struct mthca_db_page *page;
  545. u8 status;
  546. i = db_index / MTHCA_DB_REC_PER_PAGE;
  547. j = db_index % MTHCA_DB_REC_PER_PAGE;
  548. page = dev->db_tab->page + i;
  549. mutex_lock(&dev->db_tab->mutex);
  550. page->db_rec[j] = 0;
  551. if (i >= dev->db_tab->min_group2)
  552. j = MTHCA_DB_REC_PER_PAGE - 1 - j;
  553. clear_bit(j, page->used);
  554. if (bitmap_empty(page->used, MTHCA_DB_REC_PER_PAGE) &&
  555. i >= dev->db_tab->max_group1 - 1) {
  556. mthca_UNMAP_ICM(dev, mthca_uarc_virt(dev, &dev->driver_uar, i), 1, &status);
  557. dma_free_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
  558. page->db_rec, page->mapping);
  559. page->db_rec = NULL;
  560. if (i == dev->db_tab->max_group1) {
  561. --dev->db_tab->max_group1;
  562. /* XXX may be able to unmap more pages now */
  563. }
  564. if (i == dev->db_tab->min_group2)
  565. ++dev->db_tab->min_group2;
  566. }
  567. mutex_unlock(&dev->db_tab->mutex);
  568. }
  569. int mthca_init_db_tab(struct mthca_dev *dev)
  570. {
  571. int i;
  572. if (!mthca_is_memfree(dev))
  573. return 0;
  574. dev->db_tab = kmalloc(sizeof *dev->db_tab, GFP_KERNEL);
  575. if (!dev->db_tab)
  576. return -ENOMEM;
  577. mutex_init(&dev->db_tab->mutex);
  578. dev->db_tab->npages = dev->uar_table.uarc_size / MTHCA_ICM_PAGE_SIZE;
  579. dev->db_tab->max_group1 = 0;
  580. dev->db_tab->min_group2 = dev->db_tab->npages - 1;
  581. dev->db_tab->page = kmalloc(dev->db_tab->npages *
  582. sizeof *dev->db_tab->page,
  583. GFP_KERNEL);
  584. if (!dev->db_tab->page) {
  585. kfree(dev->db_tab);
  586. return -ENOMEM;
  587. }
  588. for (i = 0; i < dev->db_tab->npages; ++i)
  589. dev->db_tab->page[i].db_rec = NULL;
  590. return 0;
  591. }
  592. void mthca_cleanup_db_tab(struct mthca_dev *dev)
  593. {
  594. int i;
  595. u8 status;
  596. if (!mthca_is_memfree(dev))
  597. return;
  598. /*
  599. * Because we don't always free our UARC pages when they
  600. * become empty to make mthca_free_db() simpler we need to
  601. * make a sweep through the doorbell pages and free any
  602. * leftover pages now.
  603. */
  604. for (i = 0; i < dev->db_tab->npages; ++i) {
  605. if (!dev->db_tab->page[i].db_rec)
  606. continue;
  607. if (!bitmap_empty(dev->db_tab->page[i].used, MTHCA_DB_REC_PER_PAGE))
  608. mthca_warn(dev, "Kernel UARC page %d not empty\n", i);
  609. mthca_UNMAP_ICM(dev, mthca_uarc_virt(dev, &dev->driver_uar, i), 1, &status);
  610. dma_free_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
  611. dev->db_tab->page[i].db_rec,
  612. dev->db_tab->page[i].mapping);
  613. }
  614. kfree(dev->db_tab->page);
  615. kfree(dev->db_tab);
  616. }