mthca_main.c 37 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. *
  34. * $Id: mthca_main.c 1396 2004-12-28 04:10:27Z roland $
  35. */
  36. #include <linux/module.h>
  37. #include <linux/init.h>
  38. #include <linux/errno.h>
  39. #include <linux/pci.h>
  40. #include <linux/interrupt.h>
  41. #include "mthca_dev.h"
  42. #include "mthca_config_reg.h"
  43. #include "mthca_cmd.h"
  44. #include "mthca_profile.h"
  45. #include "mthca_memfree.h"
  46. MODULE_AUTHOR("Roland Dreier");
  47. MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
  48. MODULE_LICENSE("Dual BSD/GPL");
  49. MODULE_VERSION(DRV_VERSION);
  50. #ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
  51. int mthca_debug_level = 0;
  52. module_param_named(debug_level, mthca_debug_level, int, 0644);
  53. MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  54. #endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
  55. #ifdef CONFIG_PCI_MSI
  56. static int msi_x = 1;
  57. module_param(msi_x, int, 0444);
  58. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  59. #else /* CONFIG_PCI_MSI */
  60. #define msi_x (0)
  61. #endif /* CONFIG_PCI_MSI */
  62. static int tune_pci = 0;
  63. module_param(tune_pci, int, 0444);
  64. MODULE_PARM_DESC(tune_pci, "increase PCI burst from the default set by BIOS if nonzero");
  65. DEFINE_MUTEX(mthca_device_mutex);
  66. #define MTHCA_DEFAULT_NUM_QP (1 << 16)
  67. #define MTHCA_DEFAULT_RDB_PER_QP (1 << 2)
  68. #define MTHCA_DEFAULT_NUM_CQ (1 << 16)
  69. #define MTHCA_DEFAULT_NUM_MCG (1 << 13)
  70. #define MTHCA_DEFAULT_NUM_MPT (1 << 17)
  71. #define MTHCA_DEFAULT_NUM_MTT (1 << 20)
  72. #define MTHCA_DEFAULT_NUM_UDAV (1 << 15)
  73. #define MTHCA_DEFAULT_NUM_RESERVED_MTTS (1 << 18)
  74. #define MTHCA_DEFAULT_NUM_UARC_SIZE (1 << 18)
  75. static struct mthca_profile hca_profile = {
  76. .num_qp = MTHCA_DEFAULT_NUM_QP,
  77. .rdb_per_qp = MTHCA_DEFAULT_RDB_PER_QP,
  78. .num_cq = MTHCA_DEFAULT_NUM_CQ,
  79. .num_mcg = MTHCA_DEFAULT_NUM_MCG,
  80. .num_mpt = MTHCA_DEFAULT_NUM_MPT,
  81. .num_mtt = MTHCA_DEFAULT_NUM_MTT,
  82. .num_udav = MTHCA_DEFAULT_NUM_UDAV, /* Tavor only */
  83. .fmr_reserved_mtts = MTHCA_DEFAULT_NUM_RESERVED_MTTS, /* Tavor only */
  84. .uarc_size = MTHCA_DEFAULT_NUM_UARC_SIZE, /* Arbel only */
  85. };
  86. module_param_named(num_qp, hca_profile.num_qp, int, 0444);
  87. MODULE_PARM_DESC(num_qp, "maximum number of QPs per HCA");
  88. module_param_named(rdb_per_qp, hca_profile.rdb_per_qp, int, 0444);
  89. MODULE_PARM_DESC(rdb_per_qp, "number of RDB buffers per QP");
  90. module_param_named(num_cq, hca_profile.num_cq, int, 0444);
  91. MODULE_PARM_DESC(num_cq, "maximum number of CQs per HCA");
  92. module_param_named(num_mcg, hca_profile.num_mcg, int, 0444);
  93. MODULE_PARM_DESC(num_mcg, "maximum number of multicast groups per HCA");
  94. module_param_named(num_mpt, hca_profile.num_mpt, int, 0444);
  95. MODULE_PARM_DESC(num_mpt,
  96. "maximum number of memory protection table entries per HCA");
  97. module_param_named(num_mtt, hca_profile.num_mtt, int, 0444);
  98. MODULE_PARM_DESC(num_mtt,
  99. "maximum number of memory translation table segments per HCA");
  100. module_param_named(num_udav, hca_profile.num_udav, int, 0444);
  101. MODULE_PARM_DESC(num_udav, "maximum number of UD address vectors per HCA");
  102. module_param_named(fmr_reserved_mtts, hca_profile.fmr_reserved_mtts, int, 0444);
  103. MODULE_PARM_DESC(fmr_reserved_mtts,
  104. "number of memory translation table segments reserved for FMR");
  105. static const char mthca_version[] __devinitdata =
  106. DRV_NAME ": Mellanox InfiniBand HCA driver v"
  107. DRV_VERSION " (" DRV_RELDATE ")\n";
  108. static int mthca_tune_pci(struct mthca_dev *mdev)
  109. {
  110. if (!tune_pci)
  111. return 0;
  112. /* First try to max out Read Byte Count */
  113. if (pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX)) {
  114. if (pcix_set_mmrbc(mdev->pdev, pcix_get_max_mmrbc(mdev->pdev))) {
  115. mthca_err(mdev, "Couldn't set PCI-X max read count, "
  116. "aborting.\n");
  117. return -ENODEV;
  118. }
  119. } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
  120. mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
  121. if (pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP)) {
  122. if (pcie_set_readrq(mdev->pdev, 4096)) {
  123. mthca_err(mdev, "Couldn't write PCI Express read request, "
  124. "aborting.\n");
  125. return -ENODEV;
  126. }
  127. } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
  128. mthca_info(mdev, "No PCI Express capability, "
  129. "not setting Max Read Request Size.\n");
  130. return 0;
  131. }
  132. static int mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
  133. {
  134. int err;
  135. u8 status;
  136. err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status);
  137. if (err) {
  138. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  139. return err;
  140. }
  141. if (status) {
  142. mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, "
  143. "aborting.\n", status);
  144. return -EINVAL;
  145. }
  146. if (dev_lim->min_page_sz > PAGE_SIZE) {
  147. mthca_err(mdev, "HCA minimum page size of %d bigger than "
  148. "kernel PAGE_SIZE of %ld, aborting.\n",
  149. dev_lim->min_page_sz, PAGE_SIZE);
  150. return -ENODEV;
  151. }
  152. if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
  153. mthca_err(mdev, "HCA has %d ports, but we only support %d, "
  154. "aborting.\n",
  155. dev_lim->num_ports, MTHCA_MAX_PORTS);
  156. return -ENODEV;
  157. }
  158. if (dev_lim->uar_size > pci_resource_len(mdev->pdev, 2)) {
  159. mthca_err(mdev, "HCA reported UAR size of 0x%x bigger than "
  160. "PCI resource 2 size of 0x%llx, aborting.\n",
  161. dev_lim->uar_size,
  162. (unsigned long long)pci_resource_len(mdev->pdev, 2));
  163. return -ENODEV;
  164. }
  165. mdev->limits.num_ports = dev_lim->num_ports;
  166. mdev->limits.vl_cap = dev_lim->max_vl;
  167. mdev->limits.mtu_cap = dev_lim->max_mtu;
  168. mdev->limits.gid_table_len = dev_lim->max_gids;
  169. mdev->limits.pkey_table_len = dev_lim->max_pkeys;
  170. mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
  171. mdev->limits.max_sg = dev_lim->max_sg;
  172. mdev->limits.max_wqes = dev_lim->max_qp_sz;
  173. mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp;
  174. mdev->limits.reserved_qps = dev_lim->reserved_qps;
  175. mdev->limits.max_srq_wqes = dev_lim->max_srq_sz;
  176. mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
  177. mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
  178. mdev->limits.max_desc_sz = dev_lim->max_desc_sz;
  179. mdev->limits.max_srq_sge = mthca_max_srq_sge(mdev);
  180. /*
  181. * Subtract 1 from the limit because we need to allocate a
  182. * spare CQE so the HCA HW can tell the difference between an
  183. * empty CQ and a full CQ.
  184. */
  185. mdev->limits.max_cqes = dev_lim->max_cq_sz - 1;
  186. mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
  187. mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
  188. mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
  189. mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
  190. mdev->limits.reserved_uars = dev_lim->reserved_uars;
  191. mdev->limits.reserved_pds = dev_lim->reserved_pds;
  192. mdev->limits.port_width_cap = dev_lim->max_port_width;
  193. mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1);
  194. mdev->limits.flags = dev_lim->flags;
  195. /*
  196. * For old FW that doesn't return static rate support, use a
  197. * value of 0x3 (only static rate values of 0 or 1 are handled),
  198. * except on Sinai, where even old FW can handle static rate
  199. * values of 2 and 3.
  200. */
  201. if (dev_lim->stat_rate_support)
  202. mdev->limits.stat_rate_support = dev_lim->stat_rate_support;
  203. else if (mdev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
  204. mdev->limits.stat_rate_support = 0xf;
  205. else
  206. mdev->limits.stat_rate_support = 0x3;
  207. /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
  208. May be doable since hardware supports it for SRQ.
  209. IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
  210. IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
  211. supported by driver. */
  212. mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  213. IB_DEVICE_PORT_ACTIVE_EVENT |
  214. IB_DEVICE_SYS_IMAGE_GUID |
  215. IB_DEVICE_RC_RNR_NAK_GEN;
  216. if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
  217. mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  218. if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
  219. mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  220. if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
  221. mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
  222. if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
  223. mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  224. if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
  225. mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  226. if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
  227. mdev->mthca_flags |= MTHCA_FLAG_SRQ;
  228. return 0;
  229. }
  230. static int mthca_init_tavor(struct mthca_dev *mdev)
  231. {
  232. u8 status;
  233. int err;
  234. struct mthca_dev_lim dev_lim;
  235. struct mthca_profile profile;
  236. struct mthca_init_hca_param init_hca;
  237. err = mthca_SYS_EN(mdev, &status);
  238. if (err) {
  239. mthca_err(mdev, "SYS_EN command failed, aborting.\n");
  240. return err;
  241. }
  242. if (status) {
  243. mthca_err(mdev, "SYS_EN returned status 0x%02x, "
  244. "aborting.\n", status);
  245. return -EINVAL;
  246. }
  247. err = mthca_QUERY_FW(mdev, &status);
  248. if (err) {
  249. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  250. goto err_disable;
  251. }
  252. if (status) {
  253. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  254. "aborting.\n", status);
  255. err = -EINVAL;
  256. goto err_disable;
  257. }
  258. err = mthca_QUERY_DDR(mdev, &status);
  259. if (err) {
  260. mthca_err(mdev, "QUERY_DDR command failed, aborting.\n");
  261. goto err_disable;
  262. }
  263. if (status) {
  264. mthca_err(mdev, "QUERY_DDR returned status 0x%02x, "
  265. "aborting.\n", status);
  266. err = -EINVAL;
  267. goto err_disable;
  268. }
  269. err = mthca_dev_lim(mdev, &dev_lim);
  270. if (err) {
  271. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  272. goto err_disable;
  273. }
  274. profile = hca_profile;
  275. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  276. profile.uarc_size = 0;
  277. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  278. profile.num_srq = dev_lim.max_srqs;
  279. err = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  280. if (err < 0)
  281. goto err_disable;
  282. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  283. if (err) {
  284. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  285. goto err_disable;
  286. }
  287. if (status) {
  288. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  289. "aborting.\n", status);
  290. err = -EINVAL;
  291. goto err_disable;
  292. }
  293. return 0;
  294. err_disable:
  295. mthca_SYS_DIS(mdev, &status);
  296. return err;
  297. }
  298. static int mthca_load_fw(struct mthca_dev *mdev)
  299. {
  300. u8 status;
  301. int err;
  302. /* FIXME: use HCA-attached memory for FW if present */
  303. mdev->fw.arbel.fw_icm =
  304. mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
  305. GFP_HIGHUSER | __GFP_NOWARN, 0);
  306. if (!mdev->fw.arbel.fw_icm) {
  307. mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
  308. return -ENOMEM;
  309. }
  310. err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status);
  311. if (err) {
  312. mthca_err(mdev, "MAP_FA command failed, aborting.\n");
  313. goto err_free;
  314. }
  315. if (status) {
  316. mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status);
  317. err = -EINVAL;
  318. goto err_free;
  319. }
  320. err = mthca_RUN_FW(mdev, &status);
  321. if (err) {
  322. mthca_err(mdev, "RUN_FW command failed, aborting.\n");
  323. goto err_unmap_fa;
  324. }
  325. if (status) {
  326. mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status);
  327. err = -EINVAL;
  328. goto err_unmap_fa;
  329. }
  330. return 0;
  331. err_unmap_fa:
  332. mthca_UNMAP_FA(mdev, &status);
  333. err_free:
  334. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  335. return err;
  336. }
  337. static int mthca_init_icm(struct mthca_dev *mdev,
  338. struct mthca_dev_lim *dev_lim,
  339. struct mthca_init_hca_param *init_hca,
  340. u64 icm_size)
  341. {
  342. u64 aux_pages;
  343. u8 status;
  344. int err;
  345. err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status);
  346. if (err) {
  347. mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n");
  348. return err;
  349. }
  350. if (status) {
  351. mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, "
  352. "aborting.\n", status);
  353. return -EINVAL;
  354. }
  355. mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  356. (unsigned long long) icm_size >> 10,
  357. (unsigned long long) aux_pages << 2);
  358. mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
  359. GFP_HIGHUSER | __GFP_NOWARN, 0);
  360. if (!mdev->fw.arbel.aux_icm) {
  361. mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
  362. return -ENOMEM;
  363. }
  364. err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status);
  365. if (err) {
  366. mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n");
  367. goto err_free_aux;
  368. }
  369. if (status) {
  370. mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status);
  371. err = -EINVAL;
  372. goto err_free_aux;
  373. }
  374. err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
  375. if (err) {
  376. mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
  377. goto err_unmap_aux;
  378. }
  379. /* CPU writes to non-reserved MTTs, while HCA might DMA to reserved mtts */
  380. mdev->limits.reserved_mtts = ALIGN(mdev->limits.reserved_mtts * MTHCA_MTT_SEG_SIZE,
  381. dma_get_cache_alignment()) / MTHCA_MTT_SEG_SIZE;
  382. mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
  383. MTHCA_MTT_SEG_SIZE,
  384. mdev->limits.num_mtt_segs,
  385. mdev->limits.reserved_mtts,
  386. 1, 0);
  387. if (!mdev->mr_table.mtt_table) {
  388. mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
  389. err = -ENOMEM;
  390. goto err_unmap_eq;
  391. }
  392. mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
  393. dev_lim->mpt_entry_sz,
  394. mdev->limits.num_mpts,
  395. mdev->limits.reserved_mrws,
  396. 1, 1);
  397. if (!mdev->mr_table.mpt_table) {
  398. mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
  399. err = -ENOMEM;
  400. goto err_unmap_mtt;
  401. }
  402. mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
  403. dev_lim->qpc_entry_sz,
  404. mdev->limits.num_qps,
  405. mdev->limits.reserved_qps,
  406. 0, 0);
  407. if (!mdev->qp_table.qp_table) {
  408. mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
  409. err = -ENOMEM;
  410. goto err_unmap_mpt;
  411. }
  412. mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
  413. dev_lim->eqpc_entry_sz,
  414. mdev->limits.num_qps,
  415. mdev->limits.reserved_qps,
  416. 0, 0);
  417. if (!mdev->qp_table.eqp_table) {
  418. mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
  419. err = -ENOMEM;
  420. goto err_unmap_qp;
  421. }
  422. mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
  423. MTHCA_RDB_ENTRY_SIZE,
  424. mdev->limits.num_qps <<
  425. mdev->qp_table.rdb_shift, 0,
  426. 0, 0);
  427. if (!mdev->qp_table.rdb_table) {
  428. mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
  429. err = -ENOMEM;
  430. goto err_unmap_eqp;
  431. }
  432. mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
  433. dev_lim->cqc_entry_sz,
  434. mdev->limits.num_cqs,
  435. mdev->limits.reserved_cqs,
  436. 0, 0);
  437. if (!mdev->cq_table.table) {
  438. mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
  439. err = -ENOMEM;
  440. goto err_unmap_rdb;
  441. }
  442. if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
  443. mdev->srq_table.table =
  444. mthca_alloc_icm_table(mdev, init_hca->srqc_base,
  445. dev_lim->srq_entry_sz,
  446. mdev->limits.num_srqs,
  447. mdev->limits.reserved_srqs,
  448. 0, 0);
  449. if (!mdev->srq_table.table) {
  450. mthca_err(mdev, "Failed to map SRQ context memory, "
  451. "aborting.\n");
  452. err = -ENOMEM;
  453. goto err_unmap_cq;
  454. }
  455. }
  456. /*
  457. * It's not strictly required, but for simplicity just map the
  458. * whole multicast group table now. The table isn't very big
  459. * and it's a lot easier than trying to track ref counts.
  460. */
  461. mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
  462. MTHCA_MGM_ENTRY_SIZE,
  463. mdev->limits.num_mgms +
  464. mdev->limits.num_amgms,
  465. mdev->limits.num_mgms +
  466. mdev->limits.num_amgms,
  467. 0, 0);
  468. if (!mdev->mcg_table.table) {
  469. mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
  470. err = -ENOMEM;
  471. goto err_unmap_srq;
  472. }
  473. return 0;
  474. err_unmap_srq:
  475. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  476. mthca_free_icm_table(mdev, mdev->srq_table.table);
  477. err_unmap_cq:
  478. mthca_free_icm_table(mdev, mdev->cq_table.table);
  479. err_unmap_rdb:
  480. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  481. err_unmap_eqp:
  482. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  483. err_unmap_qp:
  484. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  485. err_unmap_mpt:
  486. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  487. err_unmap_mtt:
  488. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  489. err_unmap_eq:
  490. mthca_unmap_eq_icm(mdev);
  491. err_unmap_aux:
  492. mthca_UNMAP_ICM_AUX(mdev, &status);
  493. err_free_aux:
  494. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
  495. return err;
  496. }
  497. static void mthca_free_icms(struct mthca_dev *mdev)
  498. {
  499. u8 status;
  500. mthca_free_icm_table(mdev, mdev->mcg_table.table);
  501. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  502. mthca_free_icm_table(mdev, mdev->srq_table.table);
  503. mthca_free_icm_table(mdev, mdev->cq_table.table);
  504. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  505. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  506. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  507. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  508. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  509. mthca_unmap_eq_icm(mdev);
  510. mthca_UNMAP_ICM_AUX(mdev, &status);
  511. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
  512. }
  513. static int mthca_init_arbel(struct mthca_dev *mdev)
  514. {
  515. struct mthca_dev_lim dev_lim;
  516. struct mthca_profile profile;
  517. struct mthca_init_hca_param init_hca;
  518. u64 icm_size;
  519. u8 status;
  520. int err;
  521. err = mthca_QUERY_FW(mdev, &status);
  522. if (err) {
  523. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  524. return err;
  525. }
  526. if (status) {
  527. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  528. "aborting.\n", status);
  529. return -EINVAL;
  530. }
  531. err = mthca_ENABLE_LAM(mdev, &status);
  532. if (err) {
  533. mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n");
  534. return err;
  535. }
  536. if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) {
  537. mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
  538. mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
  539. } else if (status) {
  540. mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, "
  541. "aborting.\n", status);
  542. return -EINVAL;
  543. }
  544. err = mthca_load_fw(mdev);
  545. if (err) {
  546. mthca_err(mdev, "Failed to start FW, aborting.\n");
  547. goto err_disable;
  548. }
  549. err = mthca_dev_lim(mdev, &dev_lim);
  550. if (err) {
  551. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  552. goto err_stop_fw;
  553. }
  554. profile = hca_profile;
  555. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  556. profile.num_udav = 0;
  557. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  558. profile.num_srq = dev_lim.max_srqs;
  559. icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  560. if ((int) icm_size < 0) {
  561. err = icm_size;
  562. goto err_stop_fw;
  563. }
  564. err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
  565. if (err)
  566. goto err_stop_fw;
  567. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  568. if (err) {
  569. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  570. goto err_free_icm;
  571. }
  572. if (status) {
  573. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  574. "aborting.\n", status);
  575. err = -EINVAL;
  576. goto err_free_icm;
  577. }
  578. return 0;
  579. err_free_icm:
  580. mthca_free_icms(mdev);
  581. err_stop_fw:
  582. mthca_UNMAP_FA(mdev, &status);
  583. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  584. err_disable:
  585. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  586. mthca_DISABLE_LAM(mdev, &status);
  587. return err;
  588. }
  589. static void mthca_close_hca(struct mthca_dev *mdev)
  590. {
  591. u8 status;
  592. mthca_CLOSE_HCA(mdev, 0, &status);
  593. if (mthca_is_memfree(mdev)) {
  594. mthca_free_icms(mdev);
  595. mthca_UNMAP_FA(mdev, &status);
  596. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
  597. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  598. mthca_DISABLE_LAM(mdev, &status);
  599. } else
  600. mthca_SYS_DIS(mdev, &status);
  601. }
  602. static int mthca_init_hca(struct mthca_dev *mdev)
  603. {
  604. u8 status;
  605. int err;
  606. struct mthca_adapter adapter;
  607. if (mthca_is_memfree(mdev))
  608. err = mthca_init_arbel(mdev);
  609. else
  610. err = mthca_init_tavor(mdev);
  611. if (err)
  612. return err;
  613. err = mthca_QUERY_ADAPTER(mdev, &adapter, &status);
  614. if (err) {
  615. mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n");
  616. goto err_close;
  617. }
  618. if (status) {
  619. mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, "
  620. "aborting.\n", status);
  621. err = -EINVAL;
  622. goto err_close;
  623. }
  624. mdev->eq_table.inta_pin = adapter.inta_pin;
  625. mdev->rev_id = adapter.revision_id;
  626. memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
  627. return 0;
  628. err_close:
  629. mthca_close_hca(mdev);
  630. return err;
  631. }
  632. static int mthca_setup_hca(struct mthca_dev *dev)
  633. {
  634. int err;
  635. u8 status;
  636. MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
  637. err = mthca_init_uar_table(dev);
  638. if (err) {
  639. mthca_err(dev, "Failed to initialize "
  640. "user access region table, aborting.\n");
  641. return err;
  642. }
  643. err = mthca_uar_alloc(dev, &dev->driver_uar);
  644. if (err) {
  645. mthca_err(dev, "Failed to allocate driver access region, "
  646. "aborting.\n");
  647. goto err_uar_table_free;
  648. }
  649. dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  650. if (!dev->kar) {
  651. mthca_err(dev, "Couldn't map kernel access region, "
  652. "aborting.\n");
  653. err = -ENOMEM;
  654. goto err_uar_free;
  655. }
  656. err = mthca_init_pd_table(dev);
  657. if (err) {
  658. mthca_err(dev, "Failed to initialize "
  659. "protection domain table, aborting.\n");
  660. goto err_kar_unmap;
  661. }
  662. err = mthca_init_mr_table(dev);
  663. if (err) {
  664. mthca_err(dev, "Failed to initialize "
  665. "memory region table, aborting.\n");
  666. goto err_pd_table_free;
  667. }
  668. err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
  669. if (err) {
  670. mthca_err(dev, "Failed to create driver PD, "
  671. "aborting.\n");
  672. goto err_mr_table_free;
  673. }
  674. err = mthca_init_eq_table(dev);
  675. if (err) {
  676. mthca_err(dev, "Failed to initialize "
  677. "event queue table, aborting.\n");
  678. goto err_pd_free;
  679. }
  680. err = mthca_cmd_use_events(dev);
  681. if (err) {
  682. mthca_err(dev, "Failed to switch to event-driven "
  683. "firmware commands, aborting.\n");
  684. goto err_eq_table_free;
  685. }
  686. err = mthca_NOP(dev, &status);
  687. if (err || status) {
  688. if (dev->mthca_flags & MTHCA_FLAG_MSI_X) {
  689. mthca_warn(dev, "NOP command failed to generate interrupt "
  690. "(IRQ %d).\n",
  691. dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector);
  692. mthca_warn(dev, "Trying again with MSI-X disabled.\n");
  693. } else {
  694. mthca_err(dev, "NOP command failed to generate interrupt "
  695. "(IRQ %d), aborting.\n",
  696. dev->pdev->irq);
  697. mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  698. }
  699. goto err_cmd_poll;
  700. }
  701. mthca_dbg(dev, "NOP command IRQ test passed\n");
  702. err = mthca_init_cq_table(dev);
  703. if (err) {
  704. mthca_err(dev, "Failed to initialize "
  705. "completion queue table, aborting.\n");
  706. goto err_cmd_poll;
  707. }
  708. err = mthca_init_srq_table(dev);
  709. if (err) {
  710. mthca_err(dev, "Failed to initialize "
  711. "shared receive queue table, aborting.\n");
  712. goto err_cq_table_free;
  713. }
  714. err = mthca_init_qp_table(dev);
  715. if (err) {
  716. mthca_err(dev, "Failed to initialize "
  717. "queue pair table, aborting.\n");
  718. goto err_srq_table_free;
  719. }
  720. err = mthca_init_av_table(dev);
  721. if (err) {
  722. mthca_err(dev, "Failed to initialize "
  723. "address vector table, aborting.\n");
  724. goto err_qp_table_free;
  725. }
  726. err = mthca_init_mcg_table(dev);
  727. if (err) {
  728. mthca_err(dev, "Failed to initialize "
  729. "multicast group table, aborting.\n");
  730. goto err_av_table_free;
  731. }
  732. return 0;
  733. err_av_table_free:
  734. mthca_cleanup_av_table(dev);
  735. err_qp_table_free:
  736. mthca_cleanup_qp_table(dev);
  737. err_srq_table_free:
  738. mthca_cleanup_srq_table(dev);
  739. err_cq_table_free:
  740. mthca_cleanup_cq_table(dev);
  741. err_cmd_poll:
  742. mthca_cmd_use_polling(dev);
  743. err_eq_table_free:
  744. mthca_cleanup_eq_table(dev);
  745. err_pd_free:
  746. mthca_pd_free(dev, &dev->driver_pd);
  747. err_mr_table_free:
  748. mthca_cleanup_mr_table(dev);
  749. err_pd_table_free:
  750. mthca_cleanup_pd_table(dev);
  751. err_kar_unmap:
  752. iounmap(dev->kar);
  753. err_uar_free:
  754. mthca_uar_free(dev, &dev->driver_uar);
  755. err_uar_table_free:
  756. mthca_cleanup_uar_table(dev);
  757. return err;
  758. }
  759. static int mthca_request_regions(struct pci_dev *pdev, int ddr_hidden)
  760. {
  761. int err;
  762. /*
  763. * We can't just use pci_request_regions() because the MSI-X
  764. * table is right in the middle of the first BAR. If we did
  765. * pci_request_region and grab all of the first BAR, then
  766. * setting up MSI-X would fail, since the PCI core wants to do
  767. * request_mem_region on the MSI-X vector table.
  768. *
  769. * So just request what we need right now, and request any
  770. * other regions we need when setting up EQs.
  771. */
  772. if (!request_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  773. MTHCA_HCR_SIZE, DRV_NAME))
  774. return -EBUSY;
  775. err = pci_request_region(pdev, 2, DRV_NAME);
  776. if (err)
  777. goto err_bar2_failed;
  778. if (!ddr_hidden) {
  779. err = pci_request_region(pdev, 4, DRV_NAME);
  780. if (err)
  781. goto err_bar4_failed;
  782. }
  783. return 0;
  784. err_bar4_failed:
  785. pci_release_region(pdev, 2);
  786. err_bar2_failed:
  787. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  788. MTHCA_HCR_SIZE);
  789. return err;
  790. }
  791. static void mthca_release_regions(struct pci_dev *pdev,
  792. int ddr_hidden)
  793. {
  794. if (!ddr_hidden)
  795. pci_release_region(pdev, 4);
  796. pci_release_region(pdev, 2);
  797. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  798. MTHCA_HCR_SIZE);
  799. }
  800. static int mthca_enable_msi_x(struct mthca_dev *mdev)
  801. {
  802. struct msix_entry entries[3];
  803. int err;
  804. entries[0].entry = 0;
  805. entries[1].entry = 1;
  806. entries[2].entry = 2;
  807. err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
  808. if (err) {
  809. if (err > 0)
  810. mthca_info(mdev, "Only %d MSI-X vectors available, "
  811. "not using MSI-X\n", err);
  812. return err;
  813. }
  814. mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
  815. mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
  816. mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
  817. return 0;
  818. }
  819. /* Types of supported HCA */
  820. enum {
  821. TAVOR, /* MT23108 */
  822. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  823. ARBEL_NATIVE, /* MT25208 with extended features */
  824. SINAI /* MT25204 */
  825. };
  826. #define MTHCA_FW_VER(major, minor, subminor) \
  827. (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
  828. static struct {
  829. u64 latest_fw;
  830. u32 flags;
  831. } mthca_hca_table[] = {
  832. [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 5, 0),
  833. .flags = 0 },
  834. [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 8, 200),
  835. .flags = MTHCA_FLAG_PCIE },
  836. [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 3, 0),
  837. .flags = MTHCA_FLAG_MEMFREE |
  838. MTHCA_FLAG_PCIE },
  839. [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 2, 0),
  840. .flags = MTHCA_FLAG_MEMFREE |
  841. MTHCA_FLAG_PCIE |
  842. MTHCA_FLAG_SINAI_OPT }
  843. };
  844. static int __mthca_init_one(struct pci_dev *pdev, int hca_type)
  845. {
  846. int ddr_hidden = 0;
  847. int err;
  848. struct mthca_dev *mdev;
  849. printk(KERN_INFO PFX "Initializing %s\n",
  850. pci_name(pdev));
  851. err = pci_enable_device(pdev);
  852. if (err) {
  853. dev_err(&pdev->dev, "Cannot enable PCI device, "
  854. "aborting.\n");
  855. return err;
  856. }
  857. /*
  858. * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
  859. * be present)
  860. */
  861. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  862. pci_resource_len(pdev, 0) != 1 << 20) {
  863. dev_err(&pdev->dev, "Missing DCS, aborting.\n");
  864. err = -ENODEV;
  865. goto err_disable_pdev;
  866. }
  867. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
  868. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  869. err = -ENODEV;
  870. goto err_disable_pdev;
  871. }
  872. if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
  873. ddr_hidden = 1;
  874. err = mthca_request_regions(pdev, ddr_hidden);
  875. if (err) {
  876. dev_err(&pdev->dev, "Cannot obtain PCI resources, "
  877. "aborting.\n");
  878. goto err_disable_pdev;
  879. }
  880. pci_set_master(pdev);
  881. err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  882. if (err) {
  883. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  884. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  885. if (err) {
  886. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  887. goto err_free_res;
  888. }
  889. }
  890. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  891. if (err) {
  892. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  893. "consistent PCI DMA mask.\n");
  894. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  895. if (err) {
  896. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  897. "aborting.\n");
  898. goto err_free_res;
  899. }
  900. }
  901. mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
  902. if (!mdev) {
  903. dev_err(&pdev->dev, "Device struct alloc failed, "
  904. "aborting.\n");
  905. err = -ENOMEM;
  906. goto err_free_res;
  907. }
  908. mdev->pdev = pdev;
  909. mdev->mthca_flags = mthca_hca_table[hca_type].flags;
  910. if (ddr_hidden)
  911. mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
  912. /*
  913. * Now reset the HCA before we touch the PCI capabilities or
  914. * attempt a firmware command, since a boot ROM may have left
  915. * the HCA in an undefined state.
  916. */
  917. err = mthca_reset(mdev);
  918. if (err) {
  919. mthca_err(mdev, "Failed to reset HCA, aborting.\n");
  920. goto err_free_dev;
  921. }
  922. if (mthca_cmd_init(mdev)) {
  923. mthca_err(mdev, "Failed to init command interface, aborting.\n");
  924. goto err_free_dev;
  925. }
  926. err = mthca_tune_pci(mdev);
  927. if (err)
  928. goto err_cmd;
  929. err = mthca_init_hca(mdev);
  930. if (err)
  931. goto err_cmd;
  932. if (mdev->fw_ver < mthca_hca_table[hca_type].latest_fw) {
  933. mthca_warn(mdev, "HCA FW version %d.%d.%03d is old (%d.%d.%03d is current).\n",
  934. (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
  935. (int) (mdev->fw_ver & 0xffff),
  936. (int) (mthca_hca_table[hca_type].latest_fw >> 32),
  937. (int) (mthca_hca_table[hca_type].latest_fw >> 16) & 0xffff,
  938. (int) (mthca_hca_table[hca_type].latest_fw & 0xffff));
  939. mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
  940. }
  941. if (msi_x && !mthca_enable_msi_x(mdev))
  942. mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
  943. err = mthca_setup_hca(mdev);
  944. if (err == -EBUSY && (mdev->mthca_flags & MTHCA_FLAG_MSI_X)) {
  945. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  946. pci_disable_msix(pdev);
  947. mdev->mthca_flags &= ~MTHCA_FLAG_MSI_X;
  948. err = mthca_setup_hca(mdev);
  949. }
  950. if (err)
  951. goto err_close;
  952. err = mthca_register_device(mdev);
  953. if (err)
  954. goto err_cleanup;
  955. err = mthca_create_agents(mdev);
  956. if (err)
  957. goto err_unregister;
  958. pci_set_drvdata(pdev, mdev);
  959. mdev->hca_type = hca_type;
  960. return 0;
  961. err_unregister:
  962. mthca_unregister_device(mdev);
  963. err_cleanup:
  964. mthca_cleanup_mcg_table(mdev);
  965. mthca_cleanup_av_table(mdev);
  966. mthca_cleanup_qp_table(mdev);
  967. mthca_cleanup_srq_table(mdev);
  968. mthca_cleanup_cq_table(mdev);
  969. mthca_cmd_use_polling(mdev);
  970. mthca_cleanup_eq_table(mdev);
  971. mthca_pd_free(mdev, &mdev->driver_pd);
  972. mthca_cleanup_mr_table(mdev);
  973. mthca_cleanup_pd_table(mdev);
  974. mthca_cleanup_uar_table(mdev);
  975. err_close:
  976. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  977. pci_disable_msix(pdev);
  978. mthca_close_hca(mdev);
  979. err_cmd:
  980. mthca_cmd_cleanup(mdev);
  981. err_free_dev:
  982. ib_dealloc_device(&mdev->ib_dev);
  983. err_free_res:
  984. mthca_release_regions(pdev, ddr_hidden);
  985. err_disable_pdev:
  986. pci_disable_device(pdev);
  987. pci_set_drvdata(pdev, NULL);
  988. return err;
  989. }
  990. static void __mthca_remove_one(struct pci_dev *pdev)
  991. {
  992. struct mthca_dev *mdev = pci_get_drvdata(pdev);
  993. u8 status;
  994. int p;
  995. if (mdev) {
  996. mthca_free_agents(mdev);
  997. mthca_unregister_device(mdev);
  998. for (p = 1; p <= mdev->limits.num_ports; ++p)
  999. mthca_CLOSE_IB(mdev, p, &status);
  1000. mthca_cleanup_mcg_table(mdev);
  1001. mthca_cleanup_av_table(mdev);
  1002. mthca_cleanup_qp_table(mdev);
  1003. mthca_cleanup_srq_table(mdev);
  1004. mthca_cleanup_cq_table(mdev);
  1005. mthca_cmd_use_polling(mdev);
  1006. mthca_cleanup_eq_table(mdev);
  1007. mthca_pd_free(mdev, &mdev->driver_pd);
  1008. mthca_cleanup_mr_table(mdev);
  1009. mthca_cleanup_pd_table(mdev);
  1010. iounmap(mdev->kar);
  1011. mthca_uar_free(mdev, &mdev->driver_uar);
  1012. mthca_cleanup_uar_table(mdev);
  1013. mthca_close_hca(mdev);
  1014. mthca_cmd_cleanup(mdev);
  1015. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  1016. pci_disable_msix(pdev);
  1017. ib_dealloc_device(&mdev->ib_dev);
  1018. mthca_release_regions(pdev, mdev->mthca_flags &
  1019. MTHCA_FLAG_DDR_HIDDEN);
  1020. pci_disable_device(pdev);
  1021. pci_set_drvdata(pdev, NULL);
  1022. }
  1023. }
  1024. int __mthca_restart_one(struct pci_dev *pdev)
  1025. {
  1026. struct mthca_dev *mdev;
  1027. int hca_type;
  1028. mdev = pci_get_drvdata(pdev);
  1029. if (!mdev)
  1030. return -ENODEV;
  1031. hca_type = mdev->hca_type;
  1032. __mthca_remove_one(pdev);
  1033. return __mthca_init_one(pdev, hca_type);
  1034. }
  1035. static int __devinit mthca_init_one(struct pci_dev *pdev,
  1036. const struct pci_device_id *id)
  1037. {
  1038. static int mthca_version_printed = 0;
  1039. int ret;
  1040. mutex_lock(&mthca_device_mutex);
  1041. if (!mthca_version_printed) {
  1042. printk(KERN_INFO "%s", mthca_version);
  1043. ++mthca_version_printed;
  1044. }
  1045. if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
  1046. printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
  1047. pci_name(pdev), id->driver_data);
  1048. mutex_unlock(&mthca_device_mutex);
  1049. return -ENODEV;
  1050. }
  1051. ret = __mthca_init_one(pdev, id->driver_data);
  1052. mutex_unlock(&mthca_device_mutex);
  1053. return ret;
  1054. }
  1055. static void __devexit mthca_remove_one(struct pci_dev *pdev)
  1056. {
  1057. mutex_lock(&mthca_device_mutex);
  1058. __mthca_remove_one(pdev);
  1059. mutex_unlock(&mthca_device_mutex);
  1060. }
  1061. static struct pci_device_id mthca_pci_table[] = {
  1062. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1063. .driver_data = TAVOR },
  1064. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
  1065. .driver_data = TAVOR },
  1066. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1067. .driver_data = ARBEL_COMPAT },
  1068. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  1069. .driver_data = ARBEL_COMPAT },
  1070. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1071. .driver_data = ARBEL_NATIVE },
  1072. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
  1073. .driver_data = ARBEL_NATIVE },
  1074. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
  1075. .driver_data = SINAI },
  1076. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
  1077. .driver_data = SINAI },
  1078. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1079. .driver_data = SINAI },
  1080. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1081. .driver_data = SINAI },
  1082. { 0, }
  1083. };
  1084. MODULE_DEVICE_TABLE(pci, mthca_pci_table);
  1085. static struct pci_driver mthca_driver = {
  1086. .name = DRV_NAME,
  1087. .id_table = mthca_pci_table,
  1088. .probe = mthca_init_one,
  1089. .remove = __devexit_p(mthca_remove_one)
  1090. };
  1091. static void __init __mthca_check_profile_val(const char *name, int *pval,
  1092. int pval_default)
  1093. {
  1094. /* value must be positive and power of 2 */
  1095. int old_pval = *pval;
  1096. if (old_pval <= 0)
  1097. *pval = pval_default;
  1098. else
  1099. *pval = roundup_pow_of_two(old_pval);
  1100. if (old_pval != *pval) {
  1101. printk(KERN_WARNING PFX "Invalid value %d for %s in module parameter.\n",
  1102. old_pval, name);
  1103. printk(KERN_WARNING PFX "Corrected %s to %d.\n", name, *pval);
  1104. }
  1105. }
  1106. #define mthca_check_profile_val(name, default) \
  1107. __mthca_check_profile_val(#name, &hca_profile.name, default)
  1108. static void __init mthca_validate_profile(void)
  1109. {
  1110. mthca_check_profile_val(num_qp, MTHCA_DEFAULT_NUM_QP);
  1111. mthca_check_profile_val(rdb_per_qp, MTHCA_DEFAULT_RDB_PER_QP);
  1112. mthca_check_profile_val(num_cq, MTHCA_DEFAULT_NUM_CQ);
  1113. mthca_check_profile_val(num_mcg, MTHCA_DEFAULT_NUM_MCG);
  1114. mthca_check_profile_val(num_mpt, MTHCA_DEFAULT_NUM_MPT);
  1115. mthca_check_profile_val(num_mtt, MTHCA_DEFAULT_NUM_MTT);
  1116. mthca_check_profile_val(num_udav, MTHCA_DEFAULT_NUM_UDAV);
  1117. mthca_check_profile_val(fmr_reserved_mtts, MTHCA_DEFAULT_NUM_RESERVED_MTTS);
  1118. if (hca_profile.fmr_reserved_mtts >= hca_profile.num_mtt) {
  1119. printk(KERN_WARNING PFX "Invalid fmr_reserved_mtts module parameter %d.\n",
  1120. hca_profile.fmr_reserved_mtts);
  1121. printk(KERN_WARNING PFX "(Must be smaller than num_mtt %d)\n",
  1122. hca_profile.num_mtt);
  1123. hca_profile.fmr_reserved_mtts = hca_profile.num_mtt / 2;
  1124. printk(KERN_WARNING PFX "Corrected fmr_reserved_mtts to %d.\n",
  1125. hca_profile.fmr_reserved_mtts);
  1126. }
  1127. }
  1128. static int __init mthca_init(void)
  1129. {
  1130. int ret;
  1131. mthca_validate_profile();
  1132. ret = mthca_catas_init();
  1133. if (ret)
  1134. return ret;
  1135. ret = pci_register_driver(&mthca_driver);
  1136. if (ret < 0) {
  1137. mthca_catas_cleanup();
  1138. return ret;
  1139. }
  1140. return 0;
  1141. }
  1142. static void __exit mthca_cleanup(void)
  1143. {
  1144. pci_unregister_driver(&mthca_driver);
  1145. mthca_catas_cleanup();
  1146. }
  1147. module_init(mthca_init);
  1148. module_exit(mthca_cleanup);