mce_amd_64.c 15 KB

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  1. /*
  2. * (c) 2005, 2006 Advanced Micro Devices, Inc.
  3. * Your use of this code is subject to the terms and conditions of the
  4. * GNU general public license version 2. See "COPYING" or
  5. * http://www.gnu.org/licenses/gpl.html
  6. *
  7. * Written by Jacob Shin - AMD, Inc.
  8. *
  9. * Support : jacob.shin@amd.com
  10. *
  11. * April 2006
  12. * - added support for AMD Family 0x10 processors
  13. *
  14. * All MC4_MISCi registers are shared between multi-cores
  15. */
  16. #include <linux/cpu.h>
  17. #include <linux/errno.h>
  18. #include <linux/init.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/kobject.h>
  21. #include <linux/notifier.h>
  22. #include <linux/sched.h>
  23. #include <linux/smp.h>
  24. #include <linux/sysdev.h>
  25. #include <linux/sysfs.h>
  26. #include <asm/apic.h>
  27. #include <asm/mce.h>
  28. #include <asm/msr.h>
  29. #include <asm/percpu.h>
  30. #include <asm/idle.h>
  31. #define PFX "mce_threshold: "
  32. #define VERSION "version 1.1.1"
  33. #define NR_BANKS 6
  34. #define NR_BLOCKS 9
  35. #define THRESHOLD_MAX 0xFFF
  36. #define INT_TYPE_APIC 0x00020000
  37. #define MASK_VALID_HI 0x80000000
  38. #define MASK_CNTP_HI 0x40000000
  39. #define MASK_LOCKED_HI 0x20000000
  40. #define MASK_LVTOFF_HI 0x00F00000
  41. #define MASK_COUNT_EN_HI 0x00080000
  42. #define MASK_INT_TYPE_HI 0x00060000
  43. #define MASK_OVERFLOW_HI 0x00010000
  44. #define MASK_ERR_COUNT_HI 0x00000FFF
  45. #define MASK_BLKPTR_LO 0xFF000000
  46. #define MCG_XBLK_ADDR 0xC0000400
  47. struct threshold_block {
  48. unsigned int block;
  49. unsigned int bank;
  50. unsigned int cpu;
  51. u32 address;
  52. u16 interrupt_enable;
  53. u16 threshold_limit;
  54. struct kobject kobj;
  55. struct list_head miscj;
  56. };
  57. /* defaults used early on boot */
  58. static struct threshold_block threshold_defaults = {
  59. .interrupt_enable = 0,
  60. .threshold_limit = THRESHOLD_MAX,
  61. };
  62. struct threshold_bank {
  63. struct kobject *kobj;
  64. struct threshold_block *blocks;
  65. cpumask_t cpus;
  66. };
  67. static DEFINE_PER_CPU(struct threshold_bank *, threshold_banks[NR_BANKS]);
  68. #ifdef CONFIG_SMP
  69. static unsigned char shared_bank[NR_BANKS] = {
  70. 0, 0, 0, 0, 1
  71. };
  72. #endif
  73. static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
  74. /*
  75. * CPU Initialization
  76. */
  77. /* must be called with correct cpu affinity */
  78. static void threshold_restart_bank(struct threshold_block *b,
  79. int reset, u16 old_limit)
  80. {
  81. u32 mci_misc_hi, mci_misc_lo;
  82. rdmsr(b->address, mci_misc_lo, mci_misc_hi);
  83. if (b->threshold_limit < (mci_misc_hi & THRESHOLD_MAX))
  84. reset = 1; /* limit cannot be lower than err count */
  85. if (reset) { /* reset err count and overflow bit */
  86. mci_misc_hi =
  87. (mci_misc_hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
  88. (THRESHOLD_MAX - b->threshold_limit);
  89. } else if (old_limit) { /* change limit w/o reset */
  90. int new_count = (mci_misc_hi & THRESHOLD_MAX) +
  91. (old_limit - b->threshold_limit);
  92. mci_misc_hi = (mci_misc_hi & ~MASK_ERR_COUNT_HI) |
  93. (new_count & THRESHOLD_MAX);
  94. }
  95. b->interrupt_enable ?
  96. (mci_misc_hi = (mci_misc_hi & ~MASK_INT_TYPE_HI) | INT_TYPE_APIC) :
  97. (mci_misc_hi &= ~MASK_INT_TYPE_HI);
  98. mci_misc_hi |= MASK_COUNT_EN_HI;
  99. wrmsr(b->address, mci_misc_lo, mci_misc_hi);
  100. }
  101. /* cpu init entry point, called from mce.c with preempt off */
  102. void __cpuinit mce_amd_feature_init(struct cpuinfo_x86 *c)
  103. {
  104. unsigned int bank, block;
  105. unsigned int cpu = smp_processor_id();
  106. u32 low = 0, high = 0, address = 0;
  107. for (bank = 0; bank < NR_BANKS; ++bank) {
  108. for (block = 0; block < NR_BLOCKS; ++block) {
  109. if (block == 0)
  110. address = MSR_IA32_MC0_MISC + bank * 4;
  111. else if (block == 1) {
  112. address = (low & MASK_BLKPTR_LO) >> 21;
  113. if (!address)
  114. break;
  115. address += MCG_XBLK_ADDR;
  116. }
  117. else
  118. ++address;
  119. if (rdmsr_safe(address, &low, &high))
  120. break;
  121. if (!(high & MASK_VALID_HI)) {
  122. if (block)
  123. continue;
  124. else
  125. break;
  126. }
  127. if (!(high & MASK_CNTP_HI) ||
  128. (high & MASK_LOCKED_HI))
  129. continue;
  130. if (!block)
  131. per_cpu(bank_map, cpu) |= (1 << bank);
  132. #ifdef CONFIG_SMP
  133. if (shared_bank[bank] && c->cpu_core_id)
  134. break;
  135. #endif
  136. high &= ~MASK_LVTOFF_HI;
  137. high |= K8_APIC_EXT_LVT_ENTRY_THRESHOLD << 20;
  138. wrmsr(address, low, high);
  139. setup_APIC_extended_lvt(K8_APIC_EXT_LVT_ENTRY_THRESHOLD,
  140. THRESHOLD_APIC_VECTOR,
  141. K8_APIC_EXT_INT_MSG_FIX, 0);
  142. threshold_defaults.address = address;
  143. threshold_restart_bank(&threshold_defaults, 0, 0);
  144. }
  145. }
  146. }
  147. /*
  148. * APIC Interrupt Handler
  149. */
  150. /*
  151. * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
  152. * the interrupt goes off when error_count reaches threshold_limit.
  153. * the handler will simply log mcelog w/ software defined bank number.
  154. */
  155. asmlinkage void mce_threshold_interrupt(void)
  156. {
  157. unsigned int bank, block;
  158. struct mce m;
  159. u32 low = 0, high = 0, address = 0;
  160. ack_APIC_irq();
  161. exit_idle();
  162. irq_enter();
  163. memset(&m, 0, sizeof(m));
  164. rdtscll(m.tsc);
  165. m.cpu = smp_processor_id();
  166. /* assume first bank caused it */
  167. for (bank = 0; bank < NR_BANKS; ++bank) {
  168. if (!(per_cpu(bank_map, m.cpu) & (1 << bank)))
  169. continue;
  170. for (block = 0; block < NR_BLOCKS; ++block) {
  171. if (block == 0)
  172. address = MSR_IA32_MC0_MISC + bank * 4;
  173. else if (block == 1) {
  174. address = (low & MASK_BLKPTR_LO) >> 21;
  175. if (!address)
  176. break;
  177. address += MCG_XBLK_ADDR;
  178. }
  179. else
  180. ++address;
  181. if (rdmsr_safe(address, &low, &high))
  182. break;
  183. if (!(high & MASK_VALID_HI)) {
  184. if (block)
  185. continue;
  186. else
  187. break;
  188. }
  189. if (!(high & MASK_CNTP_HI) ||
  190. (high & MASK_LOCKED_HI))
  191. continue;
  192. /* Log the machine check that caused the threshold
  193. event. */
  194. do_machine_check(NULL, 0);
  195. if (high & MASK_OVERFLOW_HI) {
  196. rdmsrl(address, m.misc);
  197. rdmsrl(MSR_IA32_MC0_STATUS + bank * 4,
  198. m.status);
  199. m.bank = K8_MCE_THRESHOLD_BASE
  200. + bank * NR_BLOCKS
  201. + block;
  202. mce_log(&m);
  203. goto out;
  204. }
  205. }
  206. }
  207. out:
  208. add_pda(irq_threshold_count, 1);
  209. irq_exit();
  210. }
  211. /*
  212. * Sysfs Interface
  213. */
  214. struct threshold_attr {
  215. struct attribute attr;
  216. ssize_t(*show) (struct threshold_block *, char *);
  217. ssize_t(*store) (struct threshold_block *, const char *, size_t count);
  218. };
  219. static cpumask_t affinity_set(unsigned int cpu)
  220. {
  221. cpumask_t oldmask = current->cpus_allowed;
  222. cpumask_t newmask = CPU_MASK_NONE;
  223. cpu_set(cpu, newmask);
  224. set_cpus_allowed(current, newmask);
  225. return oldmask;
  226. }
  227. static void affinity_restore(cpumask_t oldmask)
  228. {
  229. set_cpus_allowed(current, oldmask);
  230. }
  231. #define SHOW_FIELDS(name) \
  232. static ssize_t show_ ## name(struct threshold_block * b, char *buf) \
  233. { \
  234. return sprintf(buf, "%lx\n", (unsigned long) b->name); \
  235. }
  236. SHOW_FIELDS(interrupt_enable)
  237. SHOW_FIELDS(threshold_limit)
  238. static ssize_t store_interrupt_enable(struct threshold_block *b,
  239. const char *buf, size_t count)
  240. {
  241. char *end;
  242. cpumask_t oldmask;
  243. unsigned long new = simple_strtoul(buf, &end, 0);
  244. if (end == buf)
  245. return -EINVAL;
  246. b->interrupt_enable = !!new;
  247. oldmask = affinity_set(b->cpu);
  248. threshold_restart_bank(b, 0, 0);
  249. affinity_restore(oldmask);
  250. return end - buf;
  251. }
  252. static ssize_t store_threshold_limit(struct threshold_block *b,
  253. const char *buf, size_t count)
  254. {
  255. char *end;
  256. cpumask_t oldmask;
  257. u16 old;
  258. unsigned long new = simple_strtoul(buf, &end, 0);
  259. if (end == buf)
  260. return -EINVAL;
  261. if (new > THRESHOLD_MAX)
  262. new = THRESHOLD_MAX;
  263. if (new < 1)
  264. new = 1;
  265. old = b->threshold_limit;
  266. b->threshold_limit = new;
  267. oldmask = affinity_set(b->cpu);
  268. threshold_restart_bank(b, 0, old);
  269. affinity_restore(oldmask);
  270. return end - buf;
  271. }
  272. static ssize_t show_error_count(struct threshold_block *b, char *buf)
  273. {
  274. u32 high, low;
  275. cpumask_t oldmask;
  276. oldmask = affinity_set(b->cpu);
  277. rdmsr(b->address, low, high);
  278. affinity_restore(oldmask);
  279. return sprintf(buf, "%x\n",
  280. (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit));
  281. }
  282. static ssize_t store_error_count(struct threshold_block *b,
  283. const char *buf, size_t count)
  284. {
  285. cpumask_t oldmask;
  286. oldmask = affinity_set(b->cpu);
  287. threshold_restart_bank(b, 1, 0);
  288. affinity_restore(oldmask);
  289. return 1;
  290. }
  291. #define THRESHOLD_ATTR(_name,_mode,_show,_store) { \
  292. .attr = {.name = __stringify(_name), .mode = _mode }, \
  293. .show = _show, \
  294. .store = _store, \
  295. };
  296. #define RW_ATTR(name) \
  297. static struct threshold_attr name = \
  298. THRESHOLD_ATTR(name, 0644, show_## name, store_## name)
  299. RW_ATTR(interrupt_enable);
  300. RW_ATTR(threshold_limit);
  301. RW_ATTR(error_count);
  302. static struct attribute *default_attrs[] = {
  303. &interrupt_enable.attr,
  304. &threshold_limit.attr,
  305. &error_count.attr,
  306. NULL
  307. };
  308. #define to_block(k) container_of(k, struct threshold_block, kobj)
  309. #define to_attr(a) container_of(a, struct threshold_attr, attr)
  310. static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
  311. {
  312. struct threshold_block *b = to_block(kobj);
  313. struct threshold_attr *a = to_attr(attr);
  314. ssize_t ret;
  315. ret = a->show ? a->show(b, buf) : -EIO;
  316. return ret;
  317. }
  318. static ssize_t store(struct kobject *kobj, struct attribute *attr,
  319. const char *buf, size_t count)
  320. {
  321. struct threshold_block *b = to_block(kobj);
  322. struct threshold_attr *a = to_attr(attr);
  323. ssize_t ret;
  324. ret = a->store ? a->store(b, buf, count) : -EIO;
  325. return ret;
  326. }
  327. static struct sysfs_ops threshold_ops = {
  328. .show = show,
  329. .store = store,
  330. };
  331. static struct kobj_type threshold_ktype = {
  332. .sysfs_ops = &threshold_ops,
  333. .default_attrs = default_attrs,
  334. };
  335. static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
  336. unsigned int bank,
  337. unsigned int block,
  338. u32 address)
  339. {
  340. int err;
  341. u32 low, high;
  342. struct threshold_block *b = NULL;
  343. if ((bank >= NR_BANKS) || (block >= NR_BLOCKS))
  344. return 0;
  345. if (rdmsr_safe(address, &low, &high))
  346. return 0;
  347. if (!(high & MASK_VALID_HI)) {
  348. if (block)
  349. goto recurse;
  350. else
  351. return 0;
  352. }
  353. if (!(high & MASK_CNTP_HI) ||
  354. (high & MASK_LOCKED_HI))
  355. goto recurse;
  356. b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
  357. if (!b)
  358. return -ENOMEM;
  359. b->block = block;
  360. b->bank = bank;
  361. b->cpu = cpu;
  362. b->address = address;
  363. b->interrupt_enable = 0;
  364. b->threshold_limit = THRESHOLD_MAX;
  365. INIT_LIST_HEAD(&b->miscj);
  366. if (per_cpu(threshold_banks, cpu)[bank]->blocks)
  367. list_add(&b->miscj,
  368. &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
  369. else
  370. per_cpu(threshold_banks, cpu)[bank]->blocks = b;
  371. err = kobject_init_and_add(&b->kobj, &threshold_ktype,
  372. per_cpu(threshold_banks, cpu)[bank]->kobj,
  373. "misc%i", block);
  374. if (err)
  375. goto out_free;
  376. recurse:
  377. if (!block) {
  378. address = (low & MASK_BLKPTR_LO) >> 21;
  379. if (!address)
  380. return 0;
  381. address += MCG_XBLK_ADDR;
  382. } else
  383. ++address;
  384. err = allocate_threshold_blocks(cpu, bank, ++block, address);
  385. if (err)
  386. goto out_free;
  387. kobject_uevent(&b->kobj, KOBJ_ADD);
  388. return err;
  389. out_free:
  390. if (b) {
  391. kobject_put(&b->kobj);
  392. kfree(b);
  393. }
  394. return err;
  395. }
  396. /* symlinks sibling shared banks to first core. first core owns dir/files. */
  397. static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
  398. {
  399. int i, err = 0;
  400. struct threshold_bank *b = NULL;
  401. cpumask_t oldmask = CPU_MASK_NONE;
  402. char name[32];
  403. sprintf(name, "threshold_bank%i", bank);
  404. #ifdef CONFIG_SMP
  405. if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) { /* symlink */
  406. i = first_cpu(per_cpu(cpu_core_map, cpu));
  407. /* first core not up yet */
  408. if (cpu_data(i).cpu_core_id)
  409. goto out;
  410. /* already linked */
  411. if (per_cpu(threshold_banks, cpu)[bank])
  412. goto out;
  413. b = per_cpu(threshold_banks, i)[bank];
  414. if (!b)
  415. goto out;
  416. err = sysfs_create_link(&per_cpu(device_mce, cpu).kobj,
  417. b->kobj, name);
  418. if (err)
  419. goto out;
  420. b->cpus = per_cpu(cpu_core_map, cpu);
  421. per_cpu(threshold_banks, cpu)[bank] = b;
  422. goto out;
  423. }
  424. #endif
  425. b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
  426. if (!b) {
  427. err = -ENOMEM;
  428. goto out;
  429. }
  430. b->kobj = kobject_create_and_add(name, &per_cpu(device_mce, cpu).kobj);
  431. if (!b->kobj)
  432. goto out_free;
  433. #ifndef CONFIG_SMP
  434. b->cpus = CPU_MASK_ALL;
  435. #else
  436. b->cpus = per_cpu(cpu_core_map, cpu);
  437. #endif
  438. per_cpu(threshold_banks, cpu)[bank] = b;
  439. oldmask = affinity_set(cpu);
  440. err = allocate_threshold_blocks(cpu, bank, 0,
  441. MSR_IA32_MC0_MISC + bank * 4);
  442. affinity_restore(oldmask);
  443. if (err)
  444. goto out_free;
  445. for_each_cpu_mask(i, b->cpus) {
  446. if (i == cpu)
  447. continue;
  448. err = sysfs_create_link(&per_cpu(device_mce, i).kobj,
  449. b->kobj, name);
  450. if (err)
  451. goto out;
  452. per_cpu(threshold_banks, i)[bank] = b;
  453. }
  454. goto out;
  455. out_free:
  456. per_cpu(threshold_banks, cpu)[bank] = NULL;
  457. kfree(b);
  458. out:
  459. return err;
  460. }
  461. /* create dir/files for all valid threshold banks */
  462. static __cpuinit int threshold_create_device(unsigned int cpu)
  463. {
  464. unsigned int bank;
  465. int err = 0;
  466. for (bank = 0; bank < NR_BANKS; ++bank) {
  467. if (!(per_cpu(bank_map, cpu) & 1 << bank))
  468. continue;
  469. err = threshold_create_bank(cpu, bank);
  470. if (err)
  471. goto out;
  472. }
  473. out:
  474. return err;
  475. }
  476. /*
  477. * let's be hotplug friendly.
  478. * in case of multiple core processors, the first core always takes ownership
  479. * of shared sysfs dir/files, and rest of the cores will be symlinked to it.
  480. */
  481. static void deallocate_threshold_block(unsigned int cpu,
  482. unsigned int bank)
  483. {
  484. struct threshold_block *pos = NULL;
  485. struct threshold_block *tmp = NULL;
  486. struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
  487. if (!head)
  488. return;
  489. list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
  490. kobject_put(&pos->kobj);
  491. list_del(&pos->miscj);
  492. kfree(pos);
  493. }
  494. kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
  495. per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
  496. }
  497. static void threshold_remove_bank(unsigned int cpu, int bank)
  498. {
  499. int i = 0;
  500. struct threshold_bank *b;
  501. char name[32];
  502. b = per_cpu(threshold_banks, cpu)[bank];
  503. if (!b)
  504. return;
  505. if (!b->blocks)
  506. goto free_out;
  507. sprintf(name, "threshold_bank%i", bank);
  508. #ifdef CONFIG_SMP
  509. /* sibling symlink */
  510. if (shared_bank[bank] && b->blocks->cpu != cpu) {
  511. sysfs_remove_link(&per_cpu(device_mce, cpu).kobj, name);
  512. per_cpu(threshold_banks, cpu)[bank] = NULL;
  513. return;
  514. }
  515. #endif
  516. /* remove all sibling symlinks before unregistering */
  517. for_each_cpu_mask(i, b->cpus) {
  518. if (i == cpu)
  519. continue;
  520. sysfs_remove_link(&per_cpu(device_mce, i).kobj, name);
  521. per_cpu(threshold_banks, i)[bank] = NULL;
  522. }
  523. deallocate_threshold_block(cpu, bank);
  524. free_out:
  525. kobject_put(b->kobj);
  526. kfree(b);
  527. per_cpu(threshold_banks, cpu)[bank] = NULL;
  528. }
  529. static void threshold_remove_device(unsigned int cpu)
  530. {
  531. unsigned int bank;
  532. for (bank = 0; bank < NR_BANKS; ++bank) {
  533. if (!(per_cpu(bank_map, cpu) & 1 << bank))
  534. continue;
  535. threshold_remove_bank(cpu, bank);
  536. }
  537. }
  538. /* get notified when a cpu comes on/off */
  539. static int threshold_cpu_callback(struct notifier_block *nfb,
  540. unsigned long action, void *hcpu)
  541. {
  542. /* cpu was unsigned int to begin with */
  543. unsigned int cpu = (unsigned long)hcpu;
  544. if (cpu >= NR_CPUS)
  545. goto out;
  546. switch (action) {
  547. case CPU_ONLINE:
  548. case CPU_ONLINE_FROZEN:
  549. threshold_create_device(cpu);
  550. break;
  551. case CPU_DEAD:
  552. case CPU_DEAD_FROZEN:
  553. threshold_remove_device(cpu);
  554. break;
  555. default:
  556. break;
  557. }
  558. out:
  559. return NOTIFY_OK;
  560. }
  561. static struct notifier_block threshold_cpu_notifier = {
  562. .notifier_call = threshold_cpu_callback,
  563. };
  564. static __init int threshold_init_device(void)
  565. {
  566. unsigned lcpu = 0;
  567. /* to hit CPUs online before the notifier is up */
  568. for_each_online_cpu(lcpu) {
  569. int err = threshold_create_device(lcpu);
  570. if (err)
  571. return err;
  572. }
  573. register_hotcpu_notifier(&threshold_cpu_notifier);
  574. return 0;
  575. }
  576. device_initcall(threshold_init_device);