Kconfig 9.2 KB

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  1. #
  2. # Processor families
  3. #
  4. config CPU_SH2
  5. bool
  6. config CPU_SH2A
  7. bool
  8. select CPU_SH2
  9. config CPU_SH3
  10. bool
  11. select CPU_HAS_INTEVT
  12. select CPU_HAS_SR_RB
  13. config CPU_SH4
  14. bool
  15. select CPU_HAS_INTEVT
  16. select CPU_HAS_SR_RB
  17. select CPU_HAS_PTEA if !CPU_SH4A || CPU_SHX2
  18. select CPU_HAS_FPU if !CPU_SH4AL_DSP
  19. config CPU_SH4A
  20. bool
  21. select CPU_SH4
  22. config CPU_SH4AL_DSP
  23. bool
  24. select CPU_SH4A
  25. select CPU_HAS_DSP
  26. config CPU_SHX2
  27. bool
  28. config CPU_SHX3
  29. bool
  30. choice
  31. prompt "Processor sub-type selection"
  32. #
  33. # Processor subtypes
  34. #
  35. # SH-2 Processor Support
  36. config CPU_SUBTYPE_SH7619
  37. bool "Support SH7619 processor"
  38. select CPU_SH2
  39. # SH-2A Processor Support
  40. config CPU_SUBTYPE_SH7206
  41. bool "Support SH7206 processor"
  42. select CPU_SH2A
  43. # SH-3 Processor Support
  44. config CPU_SUBTYPE_SH7705
  45. bool "Support SH7705 processor"
  46. select CPU_SH3
  47. config CPU_SUBTYPE_SH7706
  48. bool "Support SH7706 processor"
  49. select CPU_SH3
  50. help
  51. Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
  52. config CPU_SUBTYPE_SH7707
  53. bool "Support SH7707 processor"
  54. select CPU_SH3
  55. help
  56. Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
  57. config CPU_SUBTYPE_SH7708
  58. bool "Support SH7708 processor"
  59. select CPU_SH3
  60. help
  61. Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or
  62. if you have a 100 Mhz SH-3 HD6417708R CPU.
  63. config CPU_SUBTYPE_SH7709
  64. bool "Support SH7709 processor"
  65. select CPU_SH3
  66. help
  67. Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
  68. config CPU_SUBTYPE_SH7710
  69. bool "Support SH7710 processor"
  70. select CPU_SH3
  71. select CPU_HAS_DSP
  72. help
  73. Select SH7710 if you have a SH3-DSP SH7710 CPU.
  74. config CPU_SUBTYPE_SH7712
  75. bool "Support SH7712 processor"
  76. select CPU_SH3
  77. select CPU_HAS_DSP
  78. help
  79. Select SH7712 if you have a SH3-DSP SH7712 CPU.
  80. config CPU_SUBTYPE_SH7720
  81. bool "Support SH7720 processor"
  82. select CPU_SH3
  83. select CPU_HAS_DSP
  84. help
  85. Select SH7720 if you have a SH3-DSP SH7720 CPU.
  86. # SH-4 Processor Support
  87. config CPU_SUBTYPE_SH7750
  88. bool "Support SH7750 processor"
  89. select CPU_SH4
  90. help
  91. Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
  92. config CPU_SUBTYPE_SH7091
  93. bool "Support SH7091 processor"
  94. select CPU_SH4
  95. help
  96. Select SH7091 if you have an SH-4 based Sega device (such as
  97. the Dreamcast, Naomi, and Naomi 2).
  98. config CPU_SUBTYPE_SH7750R
  99. bool "Support SH7750R processor"
  100. select CPU_SH4
  101. config CPU_SUBTYPE_SH7750S
  102. bool "Support SH7750S processor"
  103. select CPU_SH4
  104. config CPU_SUBTYPE_SH7751
  105. bool "Support SH7751 processor"
  106. select CPU_SH4
  107. help
  108. Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
  109. or if you have a HD6417751R CPU.
  110. config CPU_SUBTYPE_SH7751R
  111. bool "Support SH7751R processor"
  112. select CPU_SH4
  113. config CPU_SUBTYPE_SH7760
  114. bool "Support SH7760 processor"
  115. select CPU_SH4
  116. config CPU_SUBTYPE_SH4_202
  117. bool "Support SH4-202 processor"
  118. select CPU_SH4
  119. # SH-4A Processor Support
  120. config CPU_SUBTYPE_SH7770
  121. bool "Support SH7770 processor"
  122. select CPU_SH4A
  123. config CPU_SUBTYPE_SH7780
  124. bool "Support SH7780 processor"
  125. select CPU_SH4A
  126. config CPU_SUBTYPE_SH7785
  127. bool "Support SH7785 processor"
  128. select CPU_SH4A
  129. select CPU_SHX2
  130. select ARCH_SPARSEMEM_ENABLE
  131. select SYS_SUPPORTS_NUMA
  132. config CPU_SUBTYPE_SHX3
  133. bool "Support SH-X3 processor"
  134. select CPU_SH4A
  135. select CPU_SHX3
  136. select ARCH_SPARSEMEM_ENABLE
  137. select SYS_SUPPORTS_NUMA
  138. select SYS_SUPPORTS_SMP
  139. # SH4AL-DSP Processor Support
  140. config CPU_SUBTYPE_SH7343
  141. bool "Support SH7343 processor"
  142. select CPU_SH4AL_DSP
  143. config CPU_SUBTYPE_SH7722
  144. bool "Support SH7722 processor"
  145. select CPU_SH4AL_DSP
  146. select CPU_SHX2
  147. select ARCH_SPARSEMEM_ENABLE
  148. select SYS_SUPPORTS_NUMA
  149. endchoice
  150. menu "Memory management options"
  151. config QUICKLIST
  152. def_bool y
  153. config MMU
  154. bool "Support for memory management hardware"
  155. depends on !CPU_SH2
  156. default y
  157. help
  158. Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
  159. boot on these systems, this option must not be set.
  160. On other systems (such as the SH-3 and 4) where an MMU exists,
  161. turning this off will boot the kernel on these machines with the
  162. MMU implicitly switched off.
  163. config PAGE_OFFSET
  164. hex
  165. default "0x80000000" if MMU
  166. default "0x00000000"
  167. config MEMORY_START
  168. hex "Physical memory start address"
  169. default "0x08000000"
  170. ---help---
  171. Computers built with Hitachi SuperH processors always
  172. map the ROM starting at address zero. But the processor
  173. does not specify the range that RAM takes.
  174. The physical memory (RAM) start address will be automatically
  175. set to 08000000. Other platforms, such as the Solution Engine
  176. boards typically map RAM at 0C000000.
  177. Tweak this only when porting to a new machine which does not
  178. already have a defconfig. Changing it from the known correct
  179. value on any of the known systems will only lead to disaster.
  180. config MEMORY_SIZE
  181. hex "Physical memory size"
  182. default "0x00400000"
  183. help
  184. This sets the default memory size assumed by your SH kernel. It can
  185. be overridden as normal by the 'mem=' argument on the kernel command
  186. line. If unsure, consult your board specifications or just leave it
  187. as 0x00400000 which was the default value before this became
  188. configurable.
  189. config 32BIT
  190. bool "Support 32-bit physical addressing through PMB"
  191. depends on MMU && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
  192. default y
  193. help
  194. If you say Y here, physical addressing will be extended to
  195. 32-bits through the SH-4A PMB. If this is not set, legacy
  196. 29-bit physical addressing will be used.
  197. config X2TLB
  198. bool "Enable extended TLB mode"
  199. depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL
  200. help
  201. Selecting this option will enable the extended mode of the SH-X2
  202. TLB. For legacy SH-X behaviour and interoperability, say N. For
  203. all of the fun new features and a willingless to submit bug reports,
  204. say Y.
  205. config VSYSCALL
  206. bool "Support vsyscall page"
  207. depends on MMU
  208. default y
  209. help
  210. This will enable support for the kernel mapping a vDSO page
  211. in process space, and subsequently handing down the entry point
  212. to the libc through the ELF auxiliary vector.
  213. From the kernel side this is used for the signal trampoline.
  214. For systems with an MMU that can afford to give up a page,
  215. (the default value) say Y.
  216. config NUMA
  217. bool "Non Uniform Memory Access (NUMA) Support"
  218. depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
  219. default n
  220. help
  221. Some SH systems have many various memories scattered around
  222. the address space, each with varying latencies. This enables
  223. support for these blocks by binding them to nodes and allowing
  224. memory policies to be used for prioritizing and controlling
  225. allocation behaviour.
  226. config NODES_SHIFT
  227. int
  228. default "3" if CPU_SUBTYPE_SHX3
  229. default "1"
  230. depends on NEED_MULTIPLE_NODES
  231. config ARCH_FLATMEM_ENABLE
  232. def_bool y
  233. depends on !NUMA
  234. config ARCH_SPARSEMEM_ENABLE
  235. def_bool y
  236. select SPARSEMEM_STATIC
  237. config ARCH_SPARSEMEM_DEFAULT
  238. def_bool y
  239. config MAX_ACTIVE_REGIONS
  240. int
  241. default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM)
  242. default "2" if SPARSEMEM && (CPU_SUBTYPE_SH7722 || \
  243. CPU_SUBTYPE_SH7785)
  244. default "1"
  245. config ARCH_POPULATES_NODE_MAP
  246. def_bool y
  247. config ARCH_SELECT_MEMORY_MODEL
  248. def_bool y
  249. config ARCH_ENABLE_MEMORY_HOTPLUG
  250. def_bool y
  251. depends on SPARSEMEM
  252. config ARCH_MEMORY_PROBE
  253. def_bool y
  254. depends on MEMORY_HOTPLUG
  255. choice
  256. prompt "Kernel page size"
  257. default PAGE_SIZE_8KB if X2TLB
  258. default PAGE_SIZE_4KB
  259. config PAGE_SIZE_4KB
  260. bool "4kB"
  261. depends on !X2TLB
  262. help
  263. This is the default page size used by all SuperH CPUs.
  264. config PAGE_SIZE_8KB
  265. bool "8kB"
  266. depends on X2TLB
  267. help
  268. This enables 8kB pages as supported by SH-X2 and later MMUs.
  269. config PAGE_SIZE_64KB
  270. bool "64kB"
  271. depends on CPU_SH4
  272. help
  273. This enables support for 64kB pages, possible on all SH-4
  274. CPUs and later.
  275. endchoice
  276. choice
  277. prompt "HugeTLB page size"
  278. depends on HUGETLB_PAGE && CPU_SH4 && MMU
  279. default HUGETLB_PAGE_SIZE_64K
  280. config HUGETLB_PAGE_SIZE_64K
  281. bool "64kB"
  282. config HUGETLB_PAGE_SIZE_256K
  283. bool "256kB"
  284. depends on X2TLB
  285. config HUGETLB_PAGE_SIZE_1MB
  286. bool "1MB"
  287. config HUGETLB_PAGE_SIZE_4MB
  288. bool "4MB"
  289. depends on X2TLB
  290. config HUGETLB_PAGE_SIZE_64MB
  291. bool "64MB"
  292. depends on X2TLB
  293. endchoice
  294. source "mm/Kconfig"
  295. endmenu
  296. menu "Cache configuration"
  297. config SH7705_CACHE_32KB
  298. bool "Enable 32KB cache size for SH7705"
  299. depends on CPU_SUBTYPE_SH7705
  300. default y
  301. config SH_DIRECT_MAPPED
  302. bool "Use direct-mapped caching"
  303. default n
  304. help
  305. Selecting this option will configure the caches to be direct-mapped,
  306. even if the cache supports a 2 or 4-way mode. This is useful primarily
  307. for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
  308. SH4-202, SH4-501, etc.)
  309. Turn this option off for platforms that do not have a direct-mapped
  310. cache, and you have no need to run the caches in such a configuration.
  311. choice
  312. prompt "Cache mode"
  313. default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4
  314. default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
  315. config CACHE_WRITEBACK
  316. bool "Write-back"
  317. depends on CPU_SH2A || CPU_SH3 || CPU_SH4
  318. config CACHE_WRITETHROUGH
  319. bool "Write-through"
  320. help
  321. Selecting this option will configure the caches in write-through
  322. mode, as opposed to the default write-back configuration.
  323. Since there's sill some aliasing issues on SH-4, this option will
  324. unfortunately still require the majority of flushing functions to
  325. be implemented to deal with aliasing.
  326. If unsure, say N.
  327. config CACHE_OFF
  328. bool "Off"
  329. endchoice
  330. endmenu