setup-sh770x.c 6.0 KB

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  1. /*
  2. * SH3 Setup code for SH7706, SH7707, SH7708, SH7709
  3. *
  4. * Copyright (C) 2007 Magnus Damm
  5. *
  6. * Based on setup-sh7709.c
  7. *
  8. * Copyright (C) 2006 Paul Mundt
  9. *
  10. * This file is subject to the terms and conditions of the GNU General Public
  11. * License. See the file "COPYING" in the main directory of this archive
  12. * for more details.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/io.h>
  16. #include <linux/irq.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/serial.h>
  19. #include <asm/sci.h>
  20. enum {
  21. UNUSED = 0,
  22. /* interrupt sources */
  23. IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
  24. PINT07, PINT815,
  25. DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3,
  26. SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
  27. SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
  28. SCI_ERI, SCI_RXI, SCI_TXI, SCI_TEI,
  29. ADC_ADI,
  30. LCDC, PCC0, PCC1,
  31. TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
  32. RTC_ATI, RTC_PRI, RTC_CUI,
  33. WDT,
  34. REF_RCMI, REF_ROVI,
  35. /* interrupt groups */
  36. RTC, REF, TMU2, DMAC, SCI, SCIF2, SCIF0,
  37. };
  38. static struct intc_vect vectors[] __initdata = {
  39. INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
  40. INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
  41. INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
  42. INTC_VECT(RTC_CUI, 0x4c0),
  43. INTC_VECT(SCI_ERI, 0x4e0), INTC_VECT(SCI_RXI, 0x500),
  44. INTC_VECT(SCI_TXI, 0x520), INTC_VECT(SCI_TEI, 0x540),
  45. INTC_VECT(WDT, 0x560),
  46. INTC_VECT(REF_RCMI, 0x580),
  47. INTC_VECT(REF_ROVI, 0x5a0),
  48. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  49. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  50. defined(CONFIG_CPU_SUBTYPE_SH7709)
  51. INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
  52. INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
  53. INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860),
  54. INTC_VECT(ADC_ADI, 0x980),
  55. INTC_VECT(SCIF2_ERI, 0x900), INTC_VECT(SCIF2_RXI, 0x920),
  56. INTC_VECT(SCIF2_BRI, 0x940), INTC_VECT(SCIF2_TXI, 0x960),
  57. #endif
  58. #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  59. defined(CONFIG_CPU_SUBTYPE_SH7709)
  60. INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
  61. INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
  62. INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
  63. #endif
  64. #if defined(CONFIG_CPU_SUBTYPE_SH7707)
  65. INTC_VECT(LCDC, 0x9a0),
  66. INTC_VECT(PCC0, 0x9c0), INTC_VECT(PCC1, 0x9e0),
  67. #endif
  68. };
  69. static struct intc_group groups[] __initdata = {
  70. INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
  71. INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
  72. INTC_GROUP(REF, REF_RCMI, REF_ROVI),
  73. INTC_GROUP(DMAC, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
  74. INTC_GROUP(SCI, SCI_ERI, SCI_RXI, SCI_TXI, SCI_TEI),
  75. INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
  76. INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
  77. };
  78. static struct intc_prio priorities[] __initdata = {
  79. INTC_PRIO(DMAC, 7),
  80. INTC_PRIO(SCI, 3),
  81. INTC_PRIO(SCIF2, 3),
  82. INTC_PRIO(SCIF0, 3),
  83. };
  84. static struct intc_prio_reg prio_registers[] __initdata = {
  85. { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
  86. { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
  87. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  88. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  89. defined(CONFIG_CPU_SUBTYPE_SH7709)
  90. { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
  91. { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
  92. { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },
  93. #endif
  94. #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  95. defined(CONFIG_CPU_SUBTYPE_SH7709)
  96. { 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } },
  97. { 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } },
  98. #endif
  99. #if defined(CONFIG_CPU_SUBTYPE_SH7707)
  100. { 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
  101. #endif
  102. };
  103. static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, groups,
  104. priorities, NULL, prio_registers, NULL);
  105. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  106. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  107. defined(CONFIG_CPU_SUBTYPE_SH7709)
  108. static struct intc_vect vectors_irq[] __initdata = {
  109. INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
  110. INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
  111. };
  112. static DECLARE_INTC_DESC(intc_desc_irq, "sh770x-irq", vectors_irq, NULL,
  113. priorities, NULL, prio_registers, NULL);
  114. #endif
  115. static struct resource rtc_resources[] = {
  116. [0] = {
  117. .start = 0xfffffec0,
  118. .end = 0xfffffec0 + 0x1e,
  119. .flags = IORESOURCE_IO,
  120. },
  121. [1] = {
  122. .start = 20,
  123. .flags = IORESOURCE_IRQ,
  124. },
  125. [2] = {
  126. .start = 21,
  127. .flags = IORESOURCE_IRQ,
  128. },
  129. [3] = {
  130. .start = 22,
  131. .flags = IORESOURCE_IRQ,
  132. },
  133. };
  134. static struct platform_device rtc_device = {
  135. .name = "sh-rtc",
  136. .id = -1,
  137. .num_resources = ARRAY_SIZE(rtc_resources),
  138. .resource = rtc_resources,
  139. };
  140. static struct plat_sci_port sci_platform_data[] = {
  141. {
  142. .mapbase = 0xfffffe80,
  143. .flags = UPF_BOOT_AUTOCONF,
  144. .type = PORT_SCI,
  145. .irqs = { 23, 24, 25, 0 },
  146. },
  147. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  148. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  149. defined(CONFIG_CPU_SUBTYPE_SH7709)
  150. {
  151. .mapbase = 0xa4000150,
  152. .flags = UPF_BOOT_AUTOCONF,
  153. .type = PORT_SCIF,
  154. .irqs = { 56, 57, 59, 58 },
  155. },
  156. #endif
  157. #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  158. defined(CONFIG_CPU_SUBTYPE_SH7709)
  159. {
  160. .mapbase = 0xa4000140,
  161. .flags = UPF_BOOT_AUTOCONF,
  162. .type = PORT_IRDA,
  163. .irqs = { 52, 53, 55, 54 },
  164. },
  165. #endif
  166. {
  167. .flags = 0,
  168. }
  169. };
  170. static struct platform_device sci_device = {
  171. .name = "sh-sci",
  172. .id = -1,
  173. .dev = {
  174. .platform_data = sci_platform_data,
  175. },
  176. };
  177. static struct platform_device *sh770x_devices[] __initdata = {
  178. &sci_device,
  179. &rtc_device,
  180. };
  181. static int __init sh770x_devices_setup(void)
  182. {
  183. return platform_add_devices(sh770x_devices,
  184. ARRAY_SIZE(sh770x_devices));
  185. }
  186. __initcall(sh770x_devices_setup);
  187. #define INTC_ICR1 0xa4000010UL
  188. #define INTC_ICR1_IRQLVL (1<<14)
  189. void __init plat_irq_setup_pins(int mode)
  190. {
  191. if (mode == IRQ_MODE_IRQ) {
  192. #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  193. defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  194. defined(CONFIG_CPU_SUBTYPE_SH7709)
  195. ctrl_outw(ctrl_inw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1);
  196. register_intc_controller(&intc_desc_irq);
  197. return;
  198. #endif
  199. }
  200. BUG();
  201. }
  202. void __init plat_irq_setup(void)
  203. {
  204. register_intc_controller(&intc_desc);
  205. }