io-workarounds.c 6.0 KB

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  1. /*
  2. * Support for Celleb io workarounds
  3. *
  4. * (C) Copyright 2006-2007 TOSHIBA CORPORATION
  5. *
  6. * This file is based to arch/powerpc/platform/cell/io-workarounds.c
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License along
  19. * with this program; if not, write to the Free Software Foundation, Inc.,
  20. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  21. */
  22. #undef DEBUG
  23. #include <linux/of_device.h>
  24. #include <linux/irq.h>
  25. #include <asm/io.h>
  26. #include <asm/prom.h>
  27. #include <asm/machdep.h>
  28. #include <asm/pci-bridge.h>
  29. #include <asm/ppc-pci.h>
  30. #include "pci.h"
  31. #define MAX_CELLEB_PCI_BUS 4
  32. void *celleb_dummy_page_va;
  33. static struct celleb_pci_bus {
  34. struct pci_controller *phb;
  35. void (*dummy_read)(struct pci_controller *);
  36. } celleb_pci_busses[MAX_CELLEB_PCI_BUS];
  37. static int celleb_pci_count = 0;
  38. static struct celleb_pci_bus *celleb_pci_find(unsigned long vaddr,
  39. unsigned long paddr)
  40. {
  41. int i, j;
  42. struct resource *res;
  43. for (i = 0; i < celleb_pci_count; i++) {
  44. struct celleb_pci_bus *bus = &celleb_pci_busses[i];
  45. struct pci_controller *phb = bus->phb;
  46. if (paddr)
  47. for (j = 0; j < 3; j++) {
  48. res = &phb->mem_resources[j];
  49. if (paddr >= res->start && paddr <= res->end)
  50. return bus;
  51. }
  52. res = &phb->io_resource;
  53. if (vaddr && vaddr >= res->start && vaddr <= res->end)
  54. return bus;
  55. }
  56. return NULL;
  57. }
  58. static void celleb_io_flush(const PCI_IO_ADDR addr)
  59. {
  60. struct celleb_pci_bus *bus;
  61. int token;
  62. token = PCI_GET_ADDR_TOKEN(addr);
  63. if (token && token <= celleb_pci_count)
  64. bus = &celleb_pci_busses[token - 1];
  65. else {
  66. unsigned long vaddr, paddr;
  67. pte_t *ptep;
  68. vaddr = (unsigned long)PCI_FIX_ADDR(addr);
  69. if (vaddr < PHB_IO_BASE || vaddr >= PHB_IO_END)
  70. return;
  71. ptep = find_linux_pte(init_mm.pgd, vaddr);
  72. if (ptep == NULL)
  73. paddr = 0;
  74. else
  75. paddr = pte_pfn(*ptep) << PAGE_SHIFT;
  76. bus = celleb_pci_find(vaddr, paddr);
  77. if (bus == NULL)
  78. return;
  79. }
  80. if (bus->dummy_read)
  81. bus->dummy_read(bus->phb);
  82. }
  83. static u8 celleb_readb(const PCI_IO_ADDR addr)
  84. {
  85. u8 val;
  86. val = __do_readb(addr);
  87. celleb_io_flush(addr);
  88. return val;
  89. }
  90. static u16 celleb_readw(const PCI_IO_ADDR addr)
  91. {
  92. u16 val;
  93. val = __do_readw(addr);
  94. celleb_io_flush(addr);
  95. return val;
  96. }
  97. static u32 celleb_readl(const PCI_IO_ADDR addr)
  98. {
  99. u32 val;
  100. val = __do_readl(addr);
  101. celleb_io_flush(addr);
  102. return val;
  103. }
  104. static u64 celleb_readq(const PCI_IO_ADDR addr)
  105. {
  106. u64 val;
  107. val = __do_readq(addr);
  108. celleb_io_flush(addr);
  109. return val;
  110. }
  111. static u16 celleb_readw_be(const PCI_IO_ADDR addr)
  112. {
  113. u16 val;
  114. val = __do_readw_be(addr);
  115. celleb_io_flush(addr);
  116. return val;
  117. }
  118. static u32 celleb_readl_be(const PCI_IO_ADDR addr)
  119. {
  120. u32 val;
  121. val = __do_readl_be(addr);
  122. celleb_io_flush(addr);
  123. return val;
  124. }
  125. static u64 celleb_readq_be(const PCI_IO_ADDR addr)
  126. {
  127. u64 val;
  128. val = __do_readq_be(addr);
  129. celleb_io_flush(addr);
  130. return val;
  131. }
  132. static void celleb_readsb(const PCI_IO_ADDR addr,
  133. void *buf, unsigned long count)
  134. {
  135. __do_readsb(addr, buf, count);
  136. celleb_io_flush(addr);
  137. }
  138. static void celleb_readsw(const PCI_IO_ADDR addr,
  139. void *buf, unsigned long count)
  140. {
  141. __do_readsw(addr, buf, count);
  142. celleb_io_flush(addr);
  143. }
  144. static void celleb_readsl(const PCI_IO_ADDR addr,
  145. void *buf, unsigned long count)
  146. {
  147. __do_readsl(addr, buf, count);
  148. celleb_io_flush(addr);
  149. }
  150. static void celleb_memcpy_fromio(void *dest,
  151. const PCI_IO_ADDR src,
  152. unsigned long n)
  153. {
  154. __do_memcpy_fromio(dest, src, n);
  155. celleb_io_flush(src);
  156. }
  157. static void __iomem *celleb_ioremap(unsigned long addr,
  158. unsigned long size,
  159. unsigned long flags)
  160. {
  161. struct celleb_pci_bus *bus;
  162. void __iomem *res = __ioremap(addr, size, flags);
  163. int busno;
  164. bus = celleb_pci_find(0, addr);
  165. if (bus != NULL) {
  166. busno = bus - celleb_pci_busses;
  167. PCI_SET_ADDR_TOKEN(res, busno + 1);
  168. }
  169. return res;
  170. }
  171. static void celleb_iounmap(volatile void __iomem *addr)
  172. {
  173. return __iounmap(PCI_FIX_ADDR(addr));
  174. }
  175. static struct ppc_pci_io celleb_pci_io __initdata = {
  176. .readb = celleb_readb,
  177. .readw = celleb_readw,
  178. .readl = celleb_readl,
  179. .readq = celleb_readq,
  180. .readw_be = celleb_readw_be,
  181. .readl_be = celleb_readl_be,
  182. .readq_be = celleb_readq_be,
  183. .readsb = celleb_readsb,
  184. .readsw = celleb_readsw,
  185. .readsl = celleb_readsl,
  186. .memcpy_fromio = celleb_memcpy_fromio,
  187. };
  188. void __init celleb_pci_add_one(struct pci_controller *phb,
  189. void (*dummy_read)(struct pci_controller *))
  190. {
  191. struct celleb_pci_bus *bus = &celleb_pci_busses[celleb_pci_count];
  192. struct device_node *np = phb->arch_data;
  193. if (celleb_pci_count >= MAX_CELLEB_PCI_BUS) {
  194. printk(KERN_ERR "Too many pci bridges, workarounds"
  195. " disabled for %s\n", np->full_name);
  196. return;
  197. }
  198. celleb_pci_count++;
  199. bus->phb = phb;
  200. bus->dummy_read = dummy_read;
  201. }
  202. static struct of_device_id celleb_pci_workaround_match[] __initdata = {
  203. {
  204. .name = "pci-pseudo",
  205. .data = fake_pci_workaround_init,
  206. }, {
  207. .name = "epci",
  208. .data = epci_workaround_init,
  209. }, {
  210. },
  211. };
  212. int __init celleb_pci_workaround_init(void)
  213. {
  214. struct pci_controller *phb;
  215. struct device_node *node;
  216. const struct of_device_id *match;
  217. void (*init_func)(struct pci_controller *);
  218. celleb_dummy_page_va = kmalloc(PAGE_SIZE, GFP_KERNEL);
  219. if (!celleb_dummy_page_va) {
  220. printk(KERN_ERR "Celleb: dummy read disabled."
  221. "Alloc celleb_dummy_page_va failed\n");
  222. return 1;
  223. }
  224. list_for_each_entry(phb, &hose_list, list_node) {
  225. node = phb->arch_data;
  226. match = of_match_node(celleb_pci_workaround_match, node);
  227. if (match) {
  228. init_func = match->data;
  229. (*init_func)(phb);
  230. }
  231. }
  232. ppc_pci_io = celleb_pci_io;
  233. ppc_md.ioremap = celleb_ioremap;
  234. ppc_md.iounmap = celleb_iounmap;
  235. return 0;
  236. }