mpc836x_mds.c 4.4 KB

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  1. /*
  2. * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
  3. *
  4. * Author: Li Yang <LeoLi@freescale.com>
  5. * Yin Olivia <Hong-hua.Yin@freescale.com>
  6. *
  7. * Description:
  8. * MPC8360E MDS board specific routines.
  9. *
  10. * Changelog:
  11. * Jun 21, 2006 Initial version
  12. *
  13. * This program is free software; you can redistribute it and/or modify it
  14. * under the terms of the GNU General Public License as published by the
  15. * Free Software Foundation; either version 2 of the License, or (at your
  16. * option) any later version.
  17. */
  18. #include <linux/stddef.h>
  19. #include <linux/kernel.h>
  20. #include <linux/init.h>
  21. #include <linux/errno.h>
  22. #include <linux/reboot.h>
  23. #include <linux/pci.h>
  24. #include <linux/kdev_t.h>
  25. #include <linux/major.h>
  26. #include <linux/console.h>
  27. #include <linux/delay.h>
  28. #include <linux/seq_file.h>
  29. #include <linux/root_dev.h>
  30. #include <linux/initrd.h>
  31. #include <asm/of_device.h>
  32. #include <asm/of_platform.h>
  33. #include <asm/system.h>
  34. #include <asm/atomic.h>
  35. #include <asm/time.h>
  36. #include <asm/io.h>
  37. #include <asm/machdep.h>
  38. #include <asm/ipic.h>
  39. #include <asm/irq.h>
  40. #include <asm/prom.h>
  41. #include <asm/udbg.h>
  42. #include <sysdev/fsl_soc.h>
  43. #include <asm/qe.h>
  44. #include <asm/qe_ic.h>
  45. #include "mpc83xx.h"
  46. #undef DEBUG
  47. #ifdef DEBUG
  48. #define DBG(fmt...) udbg_printf(fmt)
  49. #else
  50. #define DBG(fmt...)
  51. #endif
  52. static u8 *bcsr_regs = NULL;
  53. /* ************************************************************************
  54. *
  55. * Setup the architecture
  56. *
  57. */
  58. static void __init mpc836x_mds_setup_arch(void)
  59. {
  60. struct device_node *np;
  61. if (ppc_md.progress)
  62. ppc_md.progress("mpc836x_mds_setup_arch()", 0);
  63. /* Map BCSR area */
  64. np = of_find_node_by_name(NULL, "bcsr");
  65. if (np != 0) {
  66. struct resource res;
  67. of_address_to_resource(np, 0, &res);
  68. bcsr_regs = ioremap(res.start, res.end - res.start +1);
  69. of_node_put(np);
  70. }
  71. #ifdef CONFIG_PCI
  72. for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
  73. mpc83xx_add_bridge(np);
  74. #endif
  75. #ifdef CONFIG_QUICC_ENGINE
  76. qe_reset();
  77. if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
  78. par_io_init(np);
  79. of_node_put(np);
  80. for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
  81. par_io_of_config(np);
  82. }
  83. if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
  84. != NULL){
  85. uint svid;
  86. /* Reset the Ethernet PHY */
  87. #define BCSR9_GETHRST 0x20
  88. clrbits8(&bcsr_regs[9], BCSR9_GETHRST);
  89. udelay(1000);
  90. setbits8(&bcsr_regs[9], BCSR9_GETHRST);
  91. /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
  92. svid = mfspr(SPRN_SVR);
  93. if (svid == 0x80480021) {
  94. void __iomem *immap;
  95. immap = ioremap(get_immrbase() + 0x14a8, 8);
  96. /*
  97. * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
  98. * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
  99. */
  100. setbits32(immap, 0x0c003000);
  101. /*
  102. * IMMR + 0x14AC[20:27] = 10101010
  103. * (data delay for both UCC's)
  104. */
  105. clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
  106. iounmap(immap);
  107. }
  108. iounmap(bcsr_regs);
  109. of_node_put(np);
  110. }
  111. #endif /* CONFIG_QUICC_ENGINE */
  112. }
  113. static struct of_device_id mpc836x_ids[] = {
  114. { .type = "soc", },
  115. { .compatible = "soc", },
  116. { .type = "qe", },
  117. {},
  118. };
  119. static int __init mpc836x_declare_of_platform_devices(void)
  120. {
  121. if (!machine_is(mpc836x_mds))
  122. return 0;
  123. /* Publish the QE devices */
  124. of_platform_bus_probe(NULL, mpc836x_ids, NULL);
  125. return 0;
  126. }
  127. device_initcall(mpc836x_declare_of_platform_devices);
  128. static void __init mpc836x_mds_init_IRQ(void)
  129. {
  130. struct device_node *np;
  131. np = of_find_node_by_type(NULL, "ipic");
  132. if (!np)
  133. return;
  134. ipic_init(np, 0);
  135. /* Initialize the default interrupt mapping priorities,
  136. * in case the boot rom changed something on us.
  137. */
  138. ipic_set_default_priority();
  139. of_node_put(np);
  140. #ifdef CONFIG_QUICC_ENGINE
  141. np = of_find_node_by_type(NULL, "qeic");
  142. if (!np)
  143. return;
  144. qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
  145. of_node_put(np);
  146. #endif /* CONFIG_QUICC_ENGINE */
  147. }
  148. /*
  149. * Called very early, MMU is off, device-tree isn't unflattened
  150. */
  151. static int __init mpc836x_mds_probe(void)
  152. {
  153. unsigned long root = of_get_flat_dt_root();
  154. return of_flat_dt_is_compatible(root, "MPC836xMDS");
  155. }
  156. define_machine(mpc836x_mds) {
  157. .name = "MPC836x MDS",
  158. .probe = mpc836x_mds_probe,
  159. .setup_arch = mpc836x_mds_setup_arch,
  160. .init_IRQ = mpc836x_mds_init_IRQ,
  161. .get_irq = ipic_get_irq,
  162. .restart = mpc83xx_restart,
  163. .time_init = mpc83xx_time_init,
  164. .calibrate_decr = generic_calibrate_decr,
  165. .progress = udbg_progress,
  166. };